]> Git Repo - linux.git/blame - drivers/char/rocket.c
projects / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
riscom8: Prepare for BKL pushdown
[linux.git] / drivers / char / rocket.c
CommitLineData
1da177e4
LT		 1/*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42/****** Defines ******/
1da177e4
LT		 43#define ROCKET_PARANOIA_CHECK
44#define ROCKET_DISABLE_SIMUSAGE
45
46#undef ROCKET_SOFT_FLOW
47#undef ROCKET_DEBUG_OPEN
48#undef ROCKET_DEBUG_INTR
49#undef ROCKET_DEBUG_WRITE
50#undef ROCKET_DEBUG_FLOW
51#undef ROCKET_DEBUG_THROTTLE
52#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53#undef ROCKET_DEBUG_RECEIVE
54#undef ROCKET_DEBUG_HANGUP
55#undef REV_PCI_ORDER
56#undef ROCKET_DEBUG_IO
57
58#define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
59
60/****** Kernel includes ******/
61
1da177e4
LT		 62#include <linux/module.h>
63#include <linux/errno.h>
64#include <linux/major.h>
65#include <linux/kernel.h>
66#include <linux/signal.h>
67#include <linux/slab.h>
68#include <linux/mm.h>
69#include <linux/sched.h>
70#include <linux/timer.h>
71#include <linux/interrupt.h>
72#include <linux/tty.h>
73#include <linux/tty_driver.h>
74#include <linux/tty_flip.h>
75#include <linux/string.h>
76#include <linux/fcntl.h>
77#include <linux/ptrace.h>
69f545ea 78#include <linux/mutex.h>
1da177e4
LT		 79#include <linux/ioport.h>
80#include <linux/delay.h>
8cf5a8c5 81#include <linux/completion.h>
1da177e4
LT		 82#include <linux/wait.h>
83#include <linux/pci.h>
84#include <asm/uaccess.h>
85#include <asm/atomic.h>
457fb605 86#include <asm/unaligned.h>
1da177e4
LT		 87#include <linux/bitops.h>
88#include <linux/spinlock.h>
1da177e4
LT		 89#include <linux/init.h>
90
91/****** RocketPort includes ******/
92
93#include "rocket_int.h"
94#include "rocket.h"
95
96#define ROCKET_VERSION "2.09"
97#define ROCKET_DATE "12-June-2003"
98
99/****** RocketPort Local Variables ******/
100
40565f19
JS		 101static void rp_do_poll(unsigned long dummy);
102
1da177e4
LT		 103static struct tty_driver *rocket_driver;
104
105static struct rocket_version driver_version = {
106 ROCKET_VERSION, ROCKET_DATE
107};
108
109static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
110static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
111 /* eg. Bit 0 indicates port 0 has xmit data, ... */
112static atomic_t rp_num_ports_open; /* Number of serial ports open */
40565f19 113static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
1da177e4
LT		 114
115static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
116static unsigned long board2;
117static unsigned long board3;
118static unsigned long board4;
119static unsigned long controller;
120static int support_low_speed;
121static unsigned long modem1;
122static unsigned long modem2;
123static unsigned long modem3;
124static unsigned long modem4;
125static unsigned long pc104_1[8];
126static unsigned long pc104_2[8];
127static unsigned long pc104_3[8];
128static unsigned long pc104_4[8];
129static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
130
131static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
132static unsigned long rcktpt_io_addr[NUM_BOARDS];
133static int rcktpt_type[NUM_BOARDS];
134static int is_PCI[NUM_BOARDS];
135static rocketModel_t rocketModel[NUM_BOARDS];
136static int max_board;
137
138/*
139 * The following arrays define the interrupt bits corresponding to each AIOP.
140 * These bits are different between the ISA and regular PCI boards and the
141 * Universal PCI boards.
142 */
143
144static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
145 AIOP_INTR_BIT_0,
146 AIOP_INTR_BIT_1,
147 AIOP_INTR_BIT_2,
148 AIOP_INTR_BIT_3
149};
150
151static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
152 UPCI_AIOP_INTR_BIT_0,
153 UPCI_AIOP_INTR_BIT_1,
154 UPCI_AIOP_INTR_BIT_2,
155 UPCI_AIOP_INTR_BIT_3
156};
157
f15313bf
AB		 158static Byte_t RData[RDATASIZE] = {
159 0x00, 0x09, 0xf6, 0x82,
160 0x02, 0x09, 0x86, 0xfb,
161 0x04, 0x09, 0x00, 0x0a,
162 0x06, 0x09, 0x01, 0x0a,
163 0x08, 0x09, 0x8a, 0x13,
164 0x0a, 0x09, 0xc5, 0x11,
165 0x0c, 0x09, 0x86, 0x85,
166 0x0e, 0x09, 0x20, 0x0a,
167 0x10, 0x09, 0x21, 0x0a,
168 0x12, 0x09, 0x41, 0xff,
169 0x14, 0x09, 0x82, 0x00,
170 0x16, 0x09, 0x82, 0x7b,
171 0x18, 0x09, 0x8a, 0x7d,
172 0x1a, 0x09, 0x88, 0x81,
173 0x1c, 0x09, 0x86, 0x7a,
174 0x1e, 0x09, 0x84, 0x81,
175 0x20, 0x09, 0x82, 0x7c,
176 0x22, 0x09, 0x0a, 0x0a
177};
178
179static Byte_t RRegData[RREGDATASIZE] = {
180 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
181 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
182 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
183 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
184 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
185 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
186 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
187 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
188 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
189 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
190 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
191 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
192 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
193};
194
195static CONTROLLER_T sController[CTL_SIZE] = {
196 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
197 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
204};
205
206static Byte_t sBitMapClrTbl[8] = {
207 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
208};
209
210static Byte_t sBitMapSetTbl[8] = {
211 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
212};
213
214static int sClockPrescale = 0x14;
215
1da177e4
LT		 216/*
217 * Line number is the ttySIx number (x), the Minor number. We
218 * assign them sequentially, starting at zero. The following
219 * array keeps track of the line number assigned to a given board/aiop/channel.
220 */
221static unsigned char lineNumbers[MAX_RP_PORTS];
222static unsigned long nextLineNumber;
223
224/***** RocketPort Static Prototypes *********/
225static int __init init_ISA(int i);
226static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
227static void rp_flush_buffer(struct tty_struct *tty);
228static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
229static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
230static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
231static void rp_start(struct tty_struct *tty);
f15313bf
AB		 232static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
233 int ChanNum);
234static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
235static void sFlushRxFIFO(CHANNEL_T * ChP);
236static void sFlushTxFIFO(CHANNEL_T * ChP);
237static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
238static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
239static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
240static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
241static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
242static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
243 ByteIO_t * AiopIOList, int AiopIOListSize,
244 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
245 int PeriodicOnly, int altChanRingIndicator,
246 int UPCIRingInd);
247static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
248 ByteIO_t * AiopIOList, int AiopIOListSize,
249 int IRQNum, Byte_t Frequency, int PeriodicOnly);
250static int sReadAiopID(ByteIO_t io);
251static int sReadAiopNumChan(WordIO_t io);
1da177e4 252
1da177e4
LT		 253MODULE_AUTHOR("Theodore Ts'o");
254MODULE_DESCRIPTION("Comtrol RocketPort driver");
255module_param(board1, ulong, 0);
256MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
257module_param(board2, ulong, 0);
258MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
259module_param(board3, ulong, 0);
260MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
261module_param(board4, ulong, 0);
262MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
263module_param(controller, ulong, 0);
264MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
265module_param(support_low_speed, bool, 0);
266MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
267module_param(modem1, ulong, 0);
268MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
269module_param(modem2, ulong, 0);
270MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
271module_param(modem3, ulong, 0);
272MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
273module_param(modem4, ulong, 0);
274MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
275module_param_array(pc104_1, ulong, NULL, 0);
276MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
277module_param_array(pc104_2, ulong, NULL, 0);
278MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
279module_param_array(pc104_3, ulong, NULL, 0);
280MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
281module_param_array(pc104_4, ulong, NULL, 0);
282MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
283
d269cdd0 284static int rp_init(void);
1da177e4
LT		 285static void rp_cleanup_module(void);
286
287module_init(rp_init);
288module_exit(rp_cleanup_module);
289
1da177e4 290
1da177e4 291MODULE_LICENSE("Dual BSD/GPL");
1da177e4
LT		 292
293/*************************************************************************/
294/* Module code starts here */
295
296static inline int rocket_paranoia_check(struct r_port *info,
297 const char *routine)
298{
299#ifdef ROCKET_PARANOIA_CHECK
300 if (!info)
301 return 1;
302 if (info->magic != RPORT_MAGIC) {
68562b79
JS		 303 printk(KERN_WARNING "Warning: bad magic number for rocketport "
304 "struct in %s\n", routine);
1da177e4
LT		 305 return 1;
306 }
307#endif
308 return 0;
309}
310
311
312/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
313 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
314 * tty layer.
315 */
316static void rp_do_receive(struct r_port *info,
317 struct tty_struct *tty,
318 CHANNEL_t * cp, unsigned int ChanStatus)
319{
320 unsigned int CharNStat;
cc44a817
PF		 321 int ToRecv, wRecv, space;
322 unsigned char *cbuf;
1da177e4
LT		 323
324 ToRecv = sGetRxCnt(cp);
1da177e4 325#ifdef ROCKET_DEBUG_INTR
68562b79 326 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
1da177e4 327#endif
cc44a817
PF		 328 if (ToRecv == 0)
329 return;
33f0f88f 330
1da177e4
LT		 331 /*
332 * if status indicates there are errored characters in the
333 * FIFO, then enter status mode (a word in FIFO holds
334 * character and status).
335 */
336 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
337 if (!(ChanStatus & STATMODE)) {
338#ifdef ROCKET_DEBUG_RECEIVE
68562b79 339 printk(KERN_INFO "Entering STATMODE...\n");
1da177e4
LT		 340#endif
341 ChanStatus |= STATMODE;
342 sEnRxStatusMode(cp);
343 }
344 }
345
346 /*
347 * if we previously entered status mode, then read down the
348 * FIFO one word at a time, pulling apart the character and
349 * the status. Update error counters depending on status
350 */
351 if (ChanStatus & STATMODE) {
352#ifdef ROCKET_DEBUG_RECEIVE
68562b79
JS		 353 printk(KERN_INFO "Ignore %x, read %x...\n",
354 info->ignore_status_mask, info->read_status_mask);
1da177e4
LT		 355#endif
356 while (ToRecv) {
cc44a817
PF		 357 char flag;
358
1da177e4
LT		 359 CharNStat = sInW(sGetTxRxDataIO(cp));
360#ifdef ROCKET_DEBUG_RECEIVE
68562b79 361 printk(KERN_INFO "%x...\n", CharNStat);
1da177e4
LT		 362#endif
363 if (CharNStat & STMBREAKH)
364 CharNStat &= ~(STMFRAMEH | STMPARITYH);
365 if (CharNStat & info->ignore_status_mask) {
366 ToRecv--;
367 continue;
368 }
369 CharNStat &= info->read_status_mask;
370 if (CharNStat & STMBREAKH)
cc44a817 371 flag = TTY_BREAK;
1da177e4 372 else if (CharNStat & STMPARITYH)
cc44a817 373 flag = TTY_PARITY;
1da177e4 374 else if (CharNStat & STMFRAMEH)
cc44a817 375 flag = TTY_FRAME;
1da177e4 376 else if (CharNStat & STMRCVROVRH)
cc44a817 377 flag = TTY_OVERRUN;
1da177e4 378 else
cc44a817
PF		 379 flag = TTY_NORMAL;
380 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
1da177e4
LT		 381 ToRecv--;
382 }
383
384 /*
385 * after we've emptied the FIFO in status mode, turn
386 * status mode back off
387 */
388 if (sGetRxCnt(cp) == 0) {
389#ifdef ROCKET_DEBUG_RECEIVE
390 printk(KERN_INFO "Status mode off.\n");
391#endif
392 sDisRxStatusMode(cp);
393 }
394 } else {
395 /*
396 * we aren't in status mode, so read down the FIFO two
397 * characters at time by doing repeated word IO
398 * transfer.
399 */
cc44a817
PF		 400 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
401 if (space < ToRecv) {
402#ifdef ROCKET_DEBUG_RECEIVE
403 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
404#endif
405 if (space <= 0)
406 return;
407 ToRecv = space;
408 }
1da177e4
LT		 409 wRecv = ToRecv >> 1;
410 if (wRecv)
411 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
412 if (ToRecv & 1)
413 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
1da177e4
LT		 414 }
415 /* Push the data up to the tty layer */
cc44a817 416 tty_flip_buffer_push(tty);
1da177e4
LT		 417}
418
419/*
420 * Serial port transmit data function. Called from the timer polling loop as a
421 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
422 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
423 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
424 */
425static void rp_do_transmit(struct r_port *info)
426{
427 int c;
428 CHANNEL_t *cp = &info->channel;
429 struct tty_struct *tty;
430 unsigned long flags;
431
432#ifdef ROCKET_DEBUG_INTR
68562b79 433 printk(KERN_DEBUG "%s\n", __func__);
1da177e4
LT		 434#endif
435 if (!info)
436 return;
437 if (!info->tty) {
68562b79
JS		 438 printk(KERN_WARNING "rp: WARNING %s called with "
439 "info->tty==NULL\n", __func__);
1da177e4
LT		 440 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
441 return;
442 }
443
444 spin_lock_irqsave(&info->slock, flags);
445 tty = info->tty;
446 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
447
448 /* Loop sending data to FIFO until done or FIFO full */
449 while (1) {
450 if (tty->stopped || tty->hw_stopped)
451 break;
452 c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
453 if (c <= 0 || info->xmit_fifo_room <= 0)
454 break;
455 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
456 if (c & 1)
457 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
458 info->xmit_tail += c;
459 info->xmit_tail &= XMIT_BUF_SIZE - 1;
460 info->xmit_cnt -= c;
461 info->xmit_fifo_room -= c;
462#ifdef ROCKET_DEBUG_INTR
68562b79 463 printk(KERN_INFO "tx %d chars...\n", c);
1da177e4
LT		 464#endif
465 }
466
467 if (info->xmit_cnt == 0)
468 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
469
470 if (info->xmit_cnt < WAKEUP_CHARS) {
471 tty_wakeup(tty);
1da177e4
LT		 472#ifdef ROCKETPORT_HAVE_POLL_WAIT
473 wake_up_interruptible(&tty->poll_wait);
474#endif
475 }
476
477 spin_unlock_irqrestore(&info->slock, flags);
478
479#ifdef ROCKET_DEBUG_INTR
68562b79 480 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
1da177e4
LT		 481 info->xmit_tail, info->xmit_fifo_room);
482#endif
483}
484
485/*
486 * Called when a serial port signals it has read data in it's RX FIFO.
487 * It checks what interrupts are pending and services them, including
488 * receiving serial data.
489 */
490static void rp_handle_port(struct r_port *info)
491{
492 CHANNEL_t *cp;
493 struct tty_struct *tty;
494 unsigned int IntMask, ChanStatus;
495
496 if (!info)
497 return;
498
499 if ((info->flags & ROCKET_INITIALIZED) == 0) {
68562b79
JS		 500 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
501 "info->flags & NOT_INIT\n");
1da177e4
LT		 502 return;
503 }
504 if (!info->tty) {
68562b79
JS		 505 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
506 "info->tty==NULL\n");
1da177e4
LT		 507 return;
508 }
509 cp = &info->channel;
510 tty = info->tty;
511
512 IntMask = sGetChanIntID(cp) & info->intmask;
513#ifdef ROCKET_DEBUG_INTR
68562b79 514 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
1da177e4
LT		 515#endif
516 ChanStatus = sGetChanStatus(cp);
517 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
518 rp_do_receive(info, tty, cp, ChanStatus);
519 }
520 if (IntMask & DELTA_CD) { /* CD change */
521#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
68562b79 522 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
1da177e4
LT		 523 (ChanStatus & CD_ACT) ? "on" : "off");
524#endif
525 if (!(ChanStatus & CD_ACT) && info->cd_status) {
526#ifdef ROCKET_DEBUG_HANGUP
527 printk(KERN_INFO "CD drop, calling hangup.\n");
528#endif
529 tty_hangup(tty);
530 }
531 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
532 wake_up_interruptible(&info->open_wait);
533 }
534#ifdef ROCKET_DEBUG_INTR
535 if (IntMask & DELTA_CTS) { /* CTS change */
536 printk(KERN_INFO "CTS change...\n");
537 }
538 if (IntMask & DELTA_DSR) { /* DSR change */
539 printk(KERN_INFO "DSR change...\n");
540 }
541#endif
542}
543
544/*
545 * The top level polling routine. Repeats every 1/100 HZ (10ms).
546 */
547static void rp_do_poll(unsigned long dummy)
548{
549 CONTROLLER_t *ctlp;
6c0286b1
JS		 550 int ctrl, aiop, ch, line;
551 unsigned int xmitmask, i;
1da177e4
LT		 552 unsigned int CtlMask;
553 unsigned char AiopMask;
554 Word_t bit;
555
556 /* Walk through all the boards (ctrl's) */
557 for (ctrl = 0; ctrl < max_board; ctrl++) {
558 if (rcktpt_io_addr[ctrl] <= 0)
559 continue;
560
561 /* Get a ptr to the board's control struct */
562 ctlp = sCtlNumToCtlPtr(ctrl);
563
3a4fa0a2 564 /* Get the interrupt status from the board */
1da177e4
LT		 565#ifdef CONFIG_PCI
566 if (ctlp->BusType == isPCI)
567 CtlMask = sPCIGetControllerIntStatus(ctlp);
568 else
569#endif
570 CtlMask = sGetControllerIntStatus(ctlp);
571
572 /* Check if any AIOP read bits are set */
573 for (aiop = 0; CtlMask; aiop++) {
574 bit = ctlp->AiopIntrBits[aiop];
575 if (CtlMask & bit) {
576 CtlMask &= ~bit;
577 AiopMask = sGetAiopIntStatus(ctlp, aiop);
578
579 /* Check if any port read bits are set */
580 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
581 if (AiopMask & 1) {
582
583 /* Get the line number (/dev/ttyRx number). */
584 /* Read the data from the port. */
585 line = GetLineNumber(ctrl, aiop, ch);
586 rp_handle_port(rp_table[line]);
587 }
588 }
589 }
590 }
591
592 xmitmask = xmit_flags[ctrl];
593
594 /*
595 * xmit_flags contains bit-significant flags, indicating there is data
596 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
597 * 1, ... (32 total possible). The variable i has the aiop and ch
598 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
599 */
600 if (xmitmask) {
601 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
602 if (xmitmask & (1 << i)) {
603 aiop = (i & 0x18) >> 3;
604 ch = i & 0x07;
605 line = GetLineNumber(ctrl, aiop, ch);
606 rp_do_transmit(rp_table[line]);
607 }
608 }
609 }
610 }
611
612 /*
613 * Reset the timer so we get called at the next clock tick (10ms).
614 */
615 if (atomic_read(&rp_num_ports_open))
616 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
617}
618
619/*
620 * Initializes the r_port structure for a port, as well as enabling the port on
621 * the board.
622 * Inputs: board, aiop, chan numbers
623 */
624static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
625{
626 unsigned rocketMode;
627 struct r_port *info;
628 int line;
629 CONTROLLER_T *ctlp;
630
631 /* Get the next available line number */
632 line = SetLineNumber(board, aiop, chan);
633
634 ctlp = sCtlNumToCtlPtr(board);
635
636 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
dd00cc48 637 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
1da177e4 638 if (!info) {
68562b79
JS		 639 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
640 line);
1da177e4
LT		 641 return;
642 }
1da177e4
LT		 643
644 info->magic = RPORT_MAGIC;
645 info->line = line;
646 info->ctlp = ctlp;
647 info->board = board;
648 info->aiop = aiop;
649 info->chan = chan;
650 info->closing_wait = 3000;
651 info->close_delay = 50;
652 init_waitqueue_head(&info->open_wait);
8cf5a8c5 653 init_completion(&info->close_wait);
1da177e4
LT		 654 info->flags &= ~ROCKET_MODE_MASK;
655 switch (pc104[board][line]) {
656 case 422:
657 info->flags |= ROCKET_MODE_RS422;
658 break;
659 case 485:
660 info->flags |= ROCKET_MODE_RS485;
661 break;
662 case 232:
663 default:
664 info->flags |= ROCKET_MODE_RS232;
665 break;
666 }
667
668 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
669 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
68562b79
JS		 670 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
671 board, aiop, chan);
1da177e4
LT		 672 kfree(info);
673 return;
674 }
675
676 rocketMode = info->flags & ROCKET_MODE_MASK;
677
678 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
679 sEnRTSToggle(&info->channel);
680 else
681 sDisRTSToggle(&info->channel);
682
683 if (ctlp->boardType == ROCKET_TYPE_PC104) {
684 switch (rocketMode) {
685 case ROCKET_MODE_RS485:
686 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
687 break;
688 case ROCKET_MODE_RS422:
689 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
690 break;
691 case ROCKET_MODE_RS232:
692 default:
693 if (info->flags & ROCKET_RTS_TOGGLE)
694 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
695 else
696 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
697 break;
698 }
699 }
700 spin_lock_init(&info->slock);
69f545ea 701 mutex_init(&info->write_mtx);
1da177e4 702 rp_table[line] = info;
ac6aec2f
JS		 703 tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
704 NULL);
1da177e4
LT		 705}
706
707/*
708 * Configures a rocketport port according to its termio settings. Called from
709 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
710 */
711static void configure_r_port(struct r_port *info,
606d099c 712 struct ktermios *old_termios)
1da177e4
LT		 713{
714 unsigned cflag;
715 unsigned long flags;
716 unsigned rocketMode;
717 int bits, baud, divisor;
718 CHANNEL_t *cp;
6df3526b 719 struct ktermios *t = info->tty->termios;
1da177e4 720
1da177e4 721 cp = &info->channel;
6df3526b 722 cflag = t->c_cflag;
1da177e4
LT		 723
724 /* Byte size and parity */
725 if ((cflag & CSIZE) == CS8) {
726 sSetData8(cp);
727 bits = 10;
728 } else {
729 sSetData7(cp);
730 bits = 9;
731 }
732 if (cflag & CSTOPB) {
733 sSetStop2(cp);
734 bits++;
735 } else {
736 sSetStop1(cp);
737 }
738
739 if (cflag & PARENB) {
740 sEnParity(cp);
741 bits++;
742 if (cflag & PARODD) {
743 sSetOddParity(cp);
744 } else {
745 sSetEvenParity(cp);
746 }
747 } else {
748 sDisParity(cp);
749 }
750
751 /* baud rate */
752 baud = tty_get_baud_rate(info->tty);
753 if (!baud)
754 baud = 9600;
755 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
756 if ((divisor >= 8192 || divisor < 0) && old_termios) {
6df3526b 757 baud = tty_termios_baud_rate(old_termios);
1da177e4
LT		 758 if (!baud)
759 baud = 9600;
760 divisor = (rp_baud_base[info->board] / baud) - 1;
761 }
762 if (divisor >= 8192 || divisor < 0) {
763 baud = 9600;
764 divisor = (rp_baud_base[info->board] / baud) - 1;
765 }
766 info->cps = baud / bits;
767 sSetBaud(cp, divisor);
768
6df3526b
AC		 769 /* FIXME: Should really back compute a baud rate from the divisor */
770 tty_encode_baud_rate(info->tty, baud, baud);
771
1da177e4
LT		 772 if (cflag & CRTSCTS) {
773 info->intmask |= DELTA_CTS;
774 sEnCTSFlowCtl(cp);
775 } else {
776 info->intmask &= ~DELTA_CTS;
777 sDisCTSFlowCtl(cp);
778 }
779 if (cflag & CLOCAL) {
780 info->intmask &= ~DELTA_CD;
781 } else {
782 spin_lock_irqsave(&info->slock, flags);
783 if (sGetChanStatus(cp) & CD_ACT)
784 info->cd_status = 1;
785 else
786 info->cd_status = 0;
787 info->intmask |= DELTA_CD;
788 spin_unlock_irqrestore(&info->slock, flags);
789 }
790
791 /*
792 * Handle software flow control in the board
793 */
794#ifdef ROCKET_SOFT_FLOW
795 if (I_IXON(info->tty)) {
796 sEnTxSoftFlowCtl(cp);
797 if (I_IXANY(info->tty)) {
798 sEnIXANY(cp);
799 } else {
800 sDisIXANY(cp);
801 }
802 sSetTxXONChar(cp, START_CHAR(info->tty));
803 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
804 } else {
805 sDisTxSoftFlowCtl(cp);
806 sDisIXANY(cp);
807 sClrTxXOFF(cp);
808 }
809#endif
810
811 /*
812 * Set up ignore/read mask words
813 */
814 info->read_status_mask = STMRCVROVRH | 0xFF;
815 if (I_INPCK(info->tty))
816 info->read_status_mask |= STMFRAMEH | STMPARITYH;
817 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
818 info->read_status_mask |= STMBREAKH;
819
820 /*
821 * Characters to ignore
822 */
823 info->ignore_status_mask = 0;
824 if (I_IGNPAR(info->tty))
825 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
826 if (I_IGNBRK(info->tty)) {
827 info->ignore_status_mask |= STMBREAKH;
828 /*
829 * If we're ignoring parity and break indicators,
830 * ignore overruns too. (For real raw support).
831 */
832 if (I_IGNPAR(info->tty))
833 info->ignore_status_mask |= STMRCVROVRH;
834 }
835
836 rocketMode = info->flags & ROCKET_MODE_MASK;
837
838 if ((info->flags & ROCKET_RTS_TOGGLE)
839 || (rocketMode == ROCKET_MODE_RS485))
840 sEnRTSToggle(cp);
841 else
842 sDisRTSToggle(cp);
843
844 sSetRTS(&info->channel);
845
846 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
847 switch (rocketMode) {
848 case ROCKET_MODE_RS485:
849 sSetInterfaceMode(cp, InterfaceModeRS485);
850 break;
851 case ROCKET_MODE_RS422:
852 sSetInterfaceMode(cp, InterfaceModeRS422);
853 break;
854 case ROCKET_MODE_RS232:
855 default:
856 if (info->flags & ROCKET_RTS_TOGGLE)
857 sSetInterfaceMode(cp, InterfaceModeRS232T);
858 else
859 sSetInterfaceMode(cp, InterfaceModeRS232);
860 break;
861 }
862 }
863}
864
865/* info->count is considered critical, protected by spinlocks. */
866static int block_til_ready(struct tty_struct *tty, struct file *filp,
867 struct r_port *info)
868{
869 DECLARE_WAITQUEUE(wait, current);
870 int retval;
871 int do_clocal = 0, extra_count = 0;
872 unsigned long flags;
873
874 /*
875 * If the device is in the middle of being closed, then block
876 * until it's done, and then try again.
877 */
878 if (tty_hung_up_p(filp))
879 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
880 if (info->flags & ROCKET_CLOSING) {
8cf5a8c5
JS		 881 if (wait_for_completion_interruptible(&info->close_wait))
882 return -ERESTARTSYS;
1da177e4
LT		 883 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
884 }
885
886 /*
887 * If non-blocking mode is set, or the port is not enabled,
888 * then make the check up front and then exit.
889 */
890 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
891 info->flags |= ROCKET_NORMAL_ACTIVE;
892 return 0;
893 }
894 if (tty->termios->c_cflag & CLOCAL)
895 do_clocal = 1;
896
897 /*
898 * Block waiting for the carrier detect and the line to become free. While we are in
899 * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
900 * We restore it upon exit, either normal or abnormal.
901 */
902 retval = 0;
903 add_wait_queue(&info->open_wait, &wait);
904#ifdef ROCKET_DEBUG_OPEN
905 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
906#endif
907 spin_lock_irqsave(&info->slock, flags);
908
909#ifdef ROCKET_DISABLE_SIMUSAGE
910 info->flags |= ROCKET_NORMAL_ACTIVE;
911#else
912 if (!tty_hung_up_p(filp)) {
913 extra_count = 1;
914 info->count--;
915 }
916#endif
917 info->blocked_open++;
918
919 spin_unlock_irqrestore(&info->slock, flags);
920
921 while (1) {
922 if (tty->termios->c_cflag & CBAUD) {
923 sSetDTR(&info->channel);
924 sSetRTS(&info->channel);
925 }
926 set_current_state(TASK_INTERRUPTIBLE);
927 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
928 if (info->flags & ROCKET_HUP_NOTIFY)
929 retval = -EAGAIN;
930 else
931 retval = -ERESTARTSYS;
932 break;
933 }
934 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
935 break;
936 if (signal_pending(current)) {
937 retval = -ERESTARTSYS;
938 break;
939 }
940#ifdef ROCKET_DEBUG_OPEN
941 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
942 info->line, info->count, info->flags);
943#endif
944 schedule(); /* Don't hold spinlock here, will hang PC */
945 }
cc0a8fbb 946 __set_current_state(TASK_RUNNING);
1da177e4
LT		 947 remove_wait_queue(&info->open_wait, &wait);
948
949 spin_lock_irqsave(&info->slock, flags);
950
951 if (extra_count)
952 info->count++;
953 info->blocked_open--;
954
955 spin_unlock_irqrestore(&info->slock, flags);
956
957#ifdef ROCKET_DEBUG_OPEN
958 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
959 info->line, info->count);
960#endif
961 if (retval)
962 return retval;
963 info->flags |= ROCKET_NORMAL_ACTIVE;
964 return 0;
965}
966
967/*
968 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
969 * port's r_port struct. Initializes the port hardware.
970 */
971static int rp_open(struct tty_struct *tty, struct file *filp)
972{
973 struct r_port *info;
974 int line = 0, retval;
975 CHANNEL_t *cp;
976 unsigned long page;
977
f6de0c98 978 line = tty->index;
1da177e4
LT		 979 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
980 return -ENXIO;
981
982 page = __get_free_page(GFP_KERNEL);
983 if (!page)
984 return -ENOMEM;
985
986 if (info->flags & ROCKET_CLOSING) {
8cf5a8c5 987 retval = wait_for_completion_interruptible(&info->close_wait);
1da177e4 988 free_page(page);
8cf5a8c5
JS		 989 if (retval)
990 return retval;
1da177e4
LT		 991 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
992 }
993
994 /*
995 * We must not sleep from here until the port is marked fully in use.
996 */
997 if (info->xmit_buf)
998 free_page(page);
999 else
1000 info->xmit_buf = (unsigned char *) page;
1001
1002 tty->driver_data = info;
1003 info->tty = tty;
1004
1005 if (info->count++ == 0) {
1006 atomic_inc(&rp_num_ports_open);
1007
1008#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 1009 printk(KERN_INFO "rocket mod++ = %d...\n",
1010 atomic_read(&rp_num_ports_open));
1da177e4
LT		 1011#endif
1012 }
1013#ifdef ROCKET_DEBUG_OPEN
1014 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
1015#endif
1016
1017 /*
1018 * Info->count is now 1; so it's safe to sleep now.
1019 */
1da177e4
LT		 1020 if ((info->flags & ROCKET_INITIALIZED) == 0) {
1021 cp = &info->channel;
1022 sSetRxTrigger(cp, TRIG_1);
1023 if (sGetChanStatus(cp) & CD_ACT)
1024 info->cd_status = 1;
1025 else
1026 info->cd_status = 0;
1027 sDisRxStatusMode(cp);
1028 sFlushRxFIFO(cp);
1029 sFlushTxFIFO(cp);
1030
1031 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1032 sSetRxTrigger(cp, TRIG_1);
1033
1034 sGetChanStatus(cp);
1035 sDisRxStatusMode(cp);
1036 sClrTxXOFF(cp);
1037
1038 sDisCTSFlowCtl(cp);
1039 sDisTxSoftFlowCtl(cp);
1040
1041 sEnRxFIFO(cp);
1042 sEnTransmit(cp);
1043
1044 info->flags |= ROCKET_INITIALIZED;
1045
1046 /*
1047 * Set up the tty->alt_speed kludge
1048 */
1049 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1050 info->tty->alt_speed = 57600;
1051 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1052 info->tty->alt_speed = 115200;
1053 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1054 info->tty->alt_speed = 230400;
1055 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1056 info->tty->alt_speed = 460800;
1057
1058 configure_r_port(info, NULL);
1059 if (tty->termios->c_cflag & CBAUD) {
1060 sSetDTR(cp);
1061 sSetRTS(cp);
1062 }
1063 }
1064 /* Starts (or resets) the maint polling loop */
1065 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1066
1067 retval = block_til_ready(tty, filp, info);
1068 if (retval) {
1069#ifdef ROCKET_DEBUG_OPEN
1070 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1071#endif
1072 return retval;
1073 }
1074 return 0;
1075}
1076
1077/*
1078 * Exception handler that closes a serial port. info->count is considered critical.
1079 */
1080static void rp_close(struct tty_struct *tty, struct file *filp)
1081{
1082 struct r_port *info = (struct r_port *) tty->driver_data;
1083 unsigned long flags;
1084 int timeout;
1085 CHANNEL_t *cp;
1086
1087 if (rocket_paranoia_check(info, "rp_close"))
1088 return;
1089
1090#ifdef ROCKET_DEBUG_OPEN
1091 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1092#endif
1093
1094 if (tty_hung_up_p(filp))
1095 return;
1096 spin_lock_irqsave(&info->slock, flags);
1097
1098 if ((tty->count == 1) && (info->count != 1)) {
1099 /*
1100 * Uh, oh. tty->count is 1, which means that the tty
1101 * structure will be freed. Info->count should always
1102 * be one in these conditions. If it's greater than
1103 * one, we've got real problems, since it means the
1104 * serial port won't be shutdown.
1105 */
68562b79
JS		 1106 printk(KERN_WARNING "rp_close: bad serial port count; "
1107 "tty->count is 1, info->count is %d\n", info->count);
1da177e4
LT		 1108 info->count = 1;
1109 }
1110 if (--info->count < 0) {
68562b79
JS		 1111 printk(KERN_WARNING "rp_close: bad serial port count for "
1112 "ttyR%d: %d\n", info->line, info->count);
1da177e4
LT		 1113 info->count = 0;
1114 }
1115 if (info->count) {
1116 spin_unlock_irqrestore(&info->slock, flags);
1117 return;
1118 }
1119 info->flags |= ROCKET_CLOSING;
1120 spin_unlock_irqrestore(&info->slock, flags);
1121
1122 cp = &info->channel;
1123
1124 /*
1125 * Notify the line discpline to only process XON/XOFF characters
1126 */
1127 tty->closing = 1;
1128
1129 /*
1130 * If transmission was throttled by the application request,
1131 * just flush the xmit buffer.
1132 */
1133 if (tty->flow_stopped)
1134 rp_flush_buffer(tty);
1135
1136 /*
1137 * Wait for the transmit buffer to clear
1138 */
1139 if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1140 tty_wait_until_sent(tty, info->closing_wait);
1141 /*
1142 * Before we drop DTR, make sure the UART transmitter
1143 * has completely drained; this is especially
1144 * important if there is a transmit FIFO!
1145 */
1146 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1147 if (timeout == 0)
1148 timeout = 1;
1149 rp_wait_until_sent(tty, timeout);
1150 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1151
1152 sDisTransmit(cp);
1153 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1154 sDisCTSFlowCtl(cp);
1155 sDisTxSoftFlowCtl(cp);
1156 sClrTxXOFF(cp);
1157 sFlushRxFIFO(cp);
1158 sFlushTxFIFO(cp);
1159 sClrRTS(cp);
1160 if (C_HUPCL(tty))
1161 sClrDTR(cp);
1162
f6de0c98 1163 rp_flush_buffer(tty);
1da177e4
LT		 1164
1165 tty_ldisc_flush(tty);
1166
1167 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1168
1169 if (info->blocked_open) {
1170 if (info->close_delay) {
1171 msleep_interruptible(jiffies_to_msecs(info->close_delay));
1172 }
1173 wake_up_interruptible(&info->open_wait);
1174 } else {
1175 if (info->xmit_buf) {
1176 free_page((unsigned long) info->xmit_buf);
1177 info->xmit_buf = NULL;
1178 }
1179 }
1180 info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1181 tty->closing = 0;
8cf5a8c5 1182 complete_all(&info->close_wait);
1da177e4
LT		 1183 atomic_dec(&rp_num_ports_open);
1184
1185#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 1186 printk(KERN_INFO "rocket mod-- = %d...\n",
1187 atomic_read(&rp_num_ports_open));
1da177e4
LT		 1188 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1189#endif
1190
1191}
1192
1193static void rp_set_termios(struct tty_struct *tty,
606d099c 1194 struct ktermios *old_termios)
1da177e4
LT		 1195{
1196 struct r_port *info = (struct r_port *) tty->driver_data;
1197 CHANNEL_t *cp;
1198 unsigned cflag;
1199
1200 if (rocket_paranoia_check(info, "rp_set_termios"))
1201 return;
1202
1203 cflag = tty->termios->c_cflag;
1204
1da177e4
LT		 1205 /*
1206 * This driver doesn't support CS5 or CS6
1207 */
1208 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1209 tty->termios->c_cflag =
1210 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
6df3526b
AC		 1211 /* Or CMSPAR */
1212 tty->termios->c_cflag &= ~CMSPAR;
1da177e4
LT		 1213
1214 configure_r_port(info, old_termios);
1215
1216 cp = &info->channel;
1217
1218 /* Handle transition to B0 status */
1219 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1220 sClrDTR(cp);
1221 sClrRTS(cp);
1222 }
1223
1224 /* Handle transition away from B0 status */
1225 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1226 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1227 sSetRTS(cp);
1228 sSetDTR(cp);
1229 }
1230
1231 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1232 tty->hw_stopped = 0;
1233 rp_start(tty);
1234 }
1235}
1236
1237static void rp_break(struct tty_struct *tty, int break_state)
1238{
1239 struct r_port *info = (struct r_port *) tty->driver_data;
1240 unsigned long flags;
1241
1242 if (rocket_paranoia_check(info, "rp_break"))
1243 return;
1244
1245 spin_lock_irqsave(&info->slock, flags);
1246 if (break_state == -1)
1247 sSendBreak(&info->channel);
1248 else
1249 sClrBreak(&info->channel);
1250 spin_unlock_irqrestore(&info->slock, flags);
1251}
1252
1253/*
1254 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1255 * the UPCI boards was added, it was decided to make this a function because
1256 * the macro was getting too complicated. All cases except the first one
1257 * (UPCIRingInd) are taken directly from the original macro.
1258 */
1259static int sGetChanRI(CHANNEL_T * ChP)
1260{
1261 CONTROLLER_t *CtlP = ChP->CtlP;
1262 int ChanNum = ChP->ChanNum;
1263 int RingInd = 0;
1264
1265 if (CtlP->UPCIRingInd)
1266 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1267 else if (CtlP->AltChanRingIndicator)
1268 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1269 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1270 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1271
1272 return RingInd;
1273}
1274
1275/********************************************************************************************/
1276/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1277
1278/*
1279 * Returns the state of the serial modem control lines. These next 2 functions
1280 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1281 */
1282static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1283{
1284 struct r_port *info = (struct r_port *)tty->driver_data;
1285 unsigned int control, result, ChanStatus;
1286
1287 ChanStatus = sGetChanStatusLo(&info->channel);
1288 control = info->channel.TxControl[3];
1289 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1290 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1291 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1292 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1293 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1294 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1295
1296 return result;
1297}
1298
1299/*
1300 * Sets the modem control lines
1301 */
1302static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1303 unsigned int set, unsigned int clear)
1304{
1305 struct r_port *info = (struct r_port *)tty->driver_data;
1306
1307 if (set & TIOCM_RTS)
1308 info->channel.TxControl[3] |= SET_RTS;
1309 if (set & TIOCM_DTR)
1310 info->channel.TxControl[3] |= SET_DTR;
1311 if (clear & TIOCM_RTS)
1312 info->channel.TxControl[3] &= ~SET_RTS;
1313 if (clear & TIOCM_DTR)
1314 info->channel.TxControl[3] &= ~SET_DTR;
1315
457fb605 1316 out32(info->channel.IndexAddr, info->channel.TxControl);
1da177e4
LT		 1317 return 0;
1318}
1319
1320static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1321{
1322 struct rocket_config tmp;
1323
1324 if (!retinfo)
1325 return -EFAULT;
1326 memset(&tmp, 0, sizeof (tmp));
1327 tmp.line = info->line;
1328 tmp.flags = info->flags;
1329 tmp.close_delay = info->close_delay;
1330 tmp.closing_wait = info->closing_wait;
1331 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1332
1333 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1334 return -EFAULT;
1335 return 0;
1336}
1337
1338static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1339{
1340 struct rocket_config new_serial;
1341
1342 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1343 return -EFAULT;
1344
1345 if (!capable(CAP_SYS_ADMIN))
1346 {
1347 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1348 return -EPERM;
1349 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1350 configure_r_port(info, NULL);
1351 return 0;
1352 }
1353
1354 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1355 info->close_delay = new_serial.close_delay;
1356 info->closing_wait = new_serial.closing_wait;
1357
1358 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1359 info->tty->alt_speed = 57600;
1360 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1361 info->tty->alt_speed = 115200;
1362 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1363 info->tty->alt_speed = 230400;
1364 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1365 info->tty->alt_speed = 460800;
1366
1367 configure_r_port(info, NULL);
1368 return 0;
1369}
1370
1371/*
1372 * This function fills in a rocket_ports struct with information
1373 * about what boards/ports are in the system. This info is passed
1374 * to user space. See setrocket.c where the info is used to create
1375 * the /dev/ttyRx ports.
1376 */
1377static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1378{
1379 struct rocket_ports tmp;
1380 int board;
1381
1382 if (!retports)
1383 return -EFAULT;
1384 memset(&tmp, 0, sizeof (tmp));
1385 tmp.tty_major = rocket_driver->major;
1386
1387 for (board = 0; board < 4; board++) {
1388 tmp.rocketModel[board].model = rocketModel[board].model;
1389 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1390 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1391 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1392 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1393 }
1394 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1395 return -EFAULT;
1396 return 0;
1397}
1398
1399static int reset_rm2(struct r_port *info, void __user *arg)
1400{
1401 int reset;
1402
4129a645
AC		 1403 if (!capable(CAP_SYS_ADMIN))
1404 return -EPERM;
1405
1da177e4
LT		 1406 if (copy_from_user(&reset, arg, sizeof (int)))
1407 return -EFAULT;
1408 if (reset)
1409 reset = 1;
1410
1411 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1412 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1413 return -EINVAL;
1414
1415 if (info->ctlp->BusType == isISA)
1416 sModemReset(info->ctlp, info->chan, reset);
1417 else
1418 sPCIModemReset(info->ctlp, info->chan, reset);
1419
1420 return 0;
1421}
1422
1423static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1424{
1425 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1426 return -EFAULT;
1427 return 0;
1428}
1429
1430/* IOCTL call handler into the driver */
1431static int rp_ioctl(struct tty_struct *tty, struct file *file,
1432 unsigned int cmd, unsigned long arg)
1433{
1434 struct r_port *info = (struct r_port *) tty->driver_data;
1435 void __user *argp = (void __user *)arg;
1436
1437 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1438 return -ENXIO;
1439
1440 switch (cmd) {
1441 case RCKP_GET_STRUCT:
1442 if (copy_to_user(argp, info, sizeof (struct r_port)))
1443 return -EFAULT;
1444 return 0;
1445 case RCKP_GET_CONFIG:
1446 return get_config(info, argp);
1447 case RCKP_SET_CONFIG:
1448 return set_config(info, argp);
1449 case RCKP_GET_PORTS:
1450 return get_ports(info, argp);
1451 case RCKP_RESET_RM2:
1452 return reset_rm2(info, argp);
1453 case RCKP_GET_VERSION:
1454 return get_version(info, argp);
1455 default:
1456 return -ENOIOCTLCMD;
1457 }
1458 return 0;
1459}
1460
1461static void rp_send_xchar(struct tty_struct *tty, char ch)
1462{
1463 struct r_port *info = (struct r_port *) tty->driver_data;
1464 CHANNEL_t *cp;
1465
1466 if (rocket_paranoia_check(info, "rp_send_xchar"))
1467 return;
1468
1469 cp = &info->channel;
1470 if (sGetTxCnt(cp))
1471 sWriteTxPrioByte(cp, ch);
1472 else
1473 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1474}
1475
1476static void rp_throttle(struct tty_struct *tty)
1477{
1478 struct r_port *info = (struct r_port *) tty->driver_data;
1479 CHANNEL_t *cp;
1480
1481#ifdef ROCKET_DEBUG_THROTTLE
1482 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1483 tty->ldisc.chars_in_buffer(tty));
1484#endif
1485
1486 if (rocket_paranoia_check(info, "rp_throttle"))
1487 return;
1488
1489 cp = &info->channel;
1490 if (I_IXOFF(tty))
1491 rp_send_xchar(tty, STOP_CHAR(tty));
1492
1493 sClrRTS(&info->channel);
1494}
1495
1496static void rp_unthrottle(struct tty_struct *tty)
1497{
1498 struct r_port *info = (struct r_port *) tty->driver_data;
1499 CHANNEL_t *cp;
1500#ifdef ROCKET_DEBUG_THROTTLE
1501 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1502 tty->ldisc.chars_in_buffer(tty));
1503#endif
1504
1505 if (rocket_paranoia_check(info, "rp_throttle"))
1506 return;
1507
1508 cp = &info->channel;
1509 if (I_IXOFF(tty))
1510 rp_send_xchar(tty, START_CHAR(tty));
1511
1512 sSetRTS(&info->channel);
1513}
1514
1515/*
1516 * ------------------------------------------------------------
1517 * rp_stop() and rp_start()
1518 *
1519 * This routines are called before setting or resetting tty->stopped.
1520 * They enable or disable transmitter interrupts, as necessary.
1521 * ------------------------------------------------------------
1522 */
1523static void rp_stop(struct tty_struct *tty)
1524{
1525 struct r_port *info = (struct r_port *) tty->driver_data;
1526
1527#ifdef ROCKET_DEBUG_FLOW
1528 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1529 info->xmit_cnt, info->xmit_fifo_room);
1530#endif
1531
1532 if (rocket_paranoia_check(info, "rp_stop"))
1533 return;
1534
1535 if (sGetTxCnt(&info->channel))
1536 sDisTransmit(&info->channel);
1537}
1538
1539static void rp_start(struct tty_struct *tty)
1540{
1541 struct r_port *info = (struct r_port *) tty->driver_data;
1542
1543#ifdef ROCKET_DEBUG_FLOW
1544 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1545 info->xmit_cnt, info->xmit_fifo_room);
1546#endif
1547
1548 if (rocket_paranoia_check(info, "rp_stop"))
1549 return;
1550
1551 sEnTransmit(&info->channel);
1552 set_bit((info->aiop * 8) + info->chan,
1553 (void *) &xmit_flags[info->board]);
1554}
1555
1556/*
1557 * rp_wait_until_sent() --- wait until the transmitter is empty
1558 */
1559static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1560{
1561 struct r_port *info = (struct r_port *) tty->driver_data;
1562 CHANNEL_t *cp;
1563 unsigned long orig_jiffies;
1564 int check_time, exit_time;
1565 int txcnt;
1566
1567 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1568 return;
1569
1570 cp = &info->channel;
1571
1572 orig_jiffies = jiffies;
1573#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79 1574 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1da177e4 1575 jiffies);
68562b79 1576 printk(KERN_INFO "cps=%d...\n", info->cps);
1da177e4
LT		 1577#endif
1578 while (1) {
1579 txcnt = sGetTxCnt(cp);
1580 if (!txcnt) {
1581 if (sGetChanStatusLo(cp) & TXSHRMT)
1582 break;
1583 check_time = (HZ / info->cps) / 5;
1584 } else {
1585 check_time = HZ * txcnt / info->cps;
1586 }
1587 if (timeout) {
1588 exit_time = orig_jiffies + timeout - jiffies;
1589 if (exit_time <= 0)
1590 break;
1591 if (exit_time < check_time)
1592 check_time = exit_time;
1593 }
1594 if (check_time == 0)
1595 check_time = 1;
1596#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79
JS		 1597 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1598 jiffies, check_time);
1da177e4
LT		 1599#endif
1600 msleep_interruptible(jiffies_to_msecs(check_time));
1601 if (signal_pending(current))
1602 break;
1603 }
cc0a8fbb 1604 __set_current_state(TASK_RUNNING);
1da177e4
LT		 1605#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1606 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1607#endif
1608}
1609
1610/*
1611 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1612 */
1613static void rp_hangup(struct tty_struct *tty)
1614{
1615 CHANNEL_t *cp;
1616 struct r_port *info = (struct r_port *) tty->driver_data;
1617
1618 if (rocket_paranoia_check(info, "rp_hangup"))
1619 return;
1620
1621#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
68562b79 1622 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1da177e4
LT		 1623#endif
1624 rp_flush_buffer(tty);
1625 if (info->flags & ROCKET_CLOSING)
1626 return;
1627 if (info->count)
1628 atomic_dec(&rp_num_ports_open);
1629 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1630
1631 info->count = 0;
1632 info->flags &= ~ROCKET_NORMAL_ACTIVE;
1633 info->tty = NULL;
1634
1635 cp = &info->channel;
1636 sDisRxFIFO(cp);
1637 sDisTransmit(cp);
1638 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1639 sDisCTSFlowCtl(cp);
1640 sDisTxSoftFlowCtl(cp);
1641 sClrTxXOFF(cp);
1642 info->flags &= ~ROCKET_INITIALIZED;
1643
1644 wake_up_interruptible(&info->open_wait);
1645}
1646
1647/*
1648 * Exception handler - write char routine. The RocketPort driver uses a
1649 * double-buffering strategy, with the twist that if the in-memory CPU
1650 * buffer is empty, and there's space in the transmit FIFO, the
1651 * writing routines will write directly to transmit FIFO.
1652 * Write buffer and counters protected by spinlocks
1653 */
1654static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1655{
1656 struct r_port *info = (struct r_port *) tty->driver_data;
1657 CHANNEL_t *cp;
1658 unsigned long flags;
1659
1660 if (rocket_paranoia_check(info, "rp_put_char"))
1661 return;
1662
69f545ea
MK		 1663 /*
1664 * Grab the port write mutex, locking out other processes that try to
1665 * write to this port
1666 */
1667 mutex_lock(&info->write_mtx);
1da177e4
LT		 1668
1669#ifdef ROCKET_DEBUG_WRITE
68562b79 1670 printk(KERN_INFO "rp_put_char %c...\n", ch);
1da177e4
LT		 1671#endif
1672
1673 spin_lock_irqsave(&info->slock, flags);
1674 cp = &info->channel;
1675
1676 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1677 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1678
1679 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1680 info->xmit_buf[info->xmit_head++] = ch;
1681 info->xmit_head &= XMIT_BUF_SIZE - 1;
1682 info->xmit_cnt++;
1683 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1684 } else {
1685 sOutB(sGetTxRxDataIO(cp), ch);
1686 info->xmit_fifo_room--;
1687 }
1688 spin_unlock_irqrestore(&info->slock, flags);
69f545ea 1689 mutex_unlock(&info->write_mtx);
1da177e4
LT		 1690}
1691
1692/*
1693 * Exception handler - write routine, called when user app writes to the device.
69f545ea 1694 * A per port write mutex is used to protect from another process writing to
1da177e4
LT		 1695 * this port at the same time. This other process could be running on the other CPU
1696 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1697 * Spinlocks protect the info xmit members.
1698 */
1699static int rp_write(struct tty_struct *tty,
1700 const unsigned char *buf, int count)
1701{
1702 struct r_port *info = (struct r_port *) tty->driver_data;
1703 CHANNEL_t *cp;
1704 const unsigned char *b;
1705 int c, retval = 0;
1706 unsigned long flags;
1707
1708 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1709 return 0;
1710
1e3e8d91
SS		 1711 if (mutex_lock_interruptible(&info->write_mtx))
1712 return -ERESTARTSYS;
1da177e4
LT		 1713
1714#ifdef ROCKET_DEBUG_WRITE
68562b79 1715 printk(KERN_INFO "rp_write %d chars...\n", count);
1da177e4
LT		 1716#endif
1717 cp = &info->channel;
1718
1719 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1720 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1721
1722 /*
1723 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1724 * into FIFO. Use the write queue for temp storage.
1725 */
1726 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1727 c = min(count, info->xmit_fifo_room);
1728 b = buf;
1729
1730 /* Push data into FIFO, 2 bytes at a time */
1731 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1732
1733 /* If there is a byte remaining, write it */
1734 if (c & 1)
1735 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1736
1737 retval += c;
1738 buf += c;
1739 count -= c;
1740
1741 spin_lock_irqsave(&info->slock, flags);
1742 info->xmit_fifo_room -= c;
1743 spin_unlock_irqrestore(&info->slock, flags);
1744 }
1745
1746 /* If count is zero, we wrote it all and are done */
1747 if (!count)
1748 goto end;
1749
1750 /* Write remaining data into the port's xmit_buf */
1751 while (1) {
457fb605 1752 if (!info->tty) /* Seemingly obligatory check... */
1da177e4
LT		 1753 goto end;
1754
1755 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
1756 if (c <= 0)
1757 break;
1758
1759 b = buf;
1760 memcpy(info->xmit_buf + info->xmit_head, b, c);
1761
1762 spin_lock_irqsave(&info->slock, flags);
1763 info->xmit_head =
1764 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1765 info->xmit_cnt += c;
1766 spin_unlock_irqrestore(&info->slock, flags);
1767
1768 buf += c;
1769 count -= c;
1770 retval += c;
1771 }
1772
1773 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1774 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1775
1776end:
1777 if (info->xmit_cnt < WAKEUP_CHARS) {
1778 tty_wakeup(tty);
1da177e4
LT		 1779#ifdef ROCKETPORT_HAVE_POLL_WAIT
1780 wake_up_interruptible(&tty->poll_wait);
1781#endif
1782 }
69f545ea 1783 mutex_unlock(&info->write_mtx);
1da177e4
LT		 1784 return retval;
1785}
1786
1787/*
1788 * Return the number of characters that can be sent. We estimate
1789 * only using the in-memory transmit buffer only, and ignore the
1790 * potential space in the transmit FIFO.
1791 */
1792static int rp_write_room(struct tty_struct *tty)
1793{
1794 struct r_port *info = (struct r_port *) tty->driver_data;
1795 int ret;
1796
1797 if (rocket_paranoia_check(info, "rp_write_room"))
1798 return 0;
1799
1800 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1801 if (ret < 0)
1802 ret = 0;
1803#ifdef ROCKET_DEBUG_WRITE
68562b79 1804 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1da177e4
LT		 1805#endif
1806 return ret;
1807}
1808
1809/*
1810 * Return the number of characters in the buffer. Again, this only
1811 * counts those characters in the in-memory transmit buffer.
1812 */
1813static int rp_chars_in_buffer(struct tty_struct *tty)
1814{
1815 struct r_port *info = (struct r_port *) tty->driver_data;
1816 CHANNEL_t *cp;
1817
1818 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1819 return 0;
1820
1821 cp = &info->channel;
1822
1823#ifdef ROCKET_DEBUG_WRITE
68562b79 1824 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1da177e4
LT		 1825#endif
1826 return info->xmit_cnt;
1827}
1828
1829/*
1830 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1831 * r_port struct for the port. Note that spinlock are used to protect info members,
1832 * do not call this function if the spinlock is already held.
1833 */
1834static void rp_flush_buffer(struct tty_struct *tty)
1835{
1836 struct r_port *info = (struct r_port *) tty->driver_data;
1837 CHANNEL_t *cp;
1838 unsigned long flags;
1839
1840 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1841 return;
1842
1843 spin_lock_irqsave(&info->slock, flags);
1844 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1845 spin_unlock_irqrestore(&info->slock, flags);
1846
1da177e4
LT		 1847#ifdef ROCKETPORT_HAVE_POLL_WAIT
1848 wake_up_interruptible(&tty->poll_wait);
1849#endif
1850 tty_wakeup(tty);
1851
1852 cp = &info->channel;
1853 sFlushTxFIFO(cp);
1854}
1855
1856#ifdef CONFIG_PCI
1857
8d5916d3
JS		 1858static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1859 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1860 { }
1861};
1862MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1863
1da177e4
LT		 1864/*
1865 * Called when a PCI card is found. Retrieves and stores model information,
1866 * init's aiopic and serial port hardware.
1867 * Inputs: i is the board number (0-n)
1868 */
f15313bf 1869static __init int register_PCI(int i, struct pci_dev *dev)
1da177e4
LT		 1870{
1871 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1872 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1873 char *str, *board_type;
1874 CONTROLLER_t *ctlp;
1875
1876 int fast_clock = 0;
1877 int altChanRingIndicator = 0;
1878 int ports_per_aiop = 8;
1da177e4
LT		 1879 WordIO_t ConfigIO = 0;
1880 ByteIO_t UPCIRingInd = 0;
1881
1882 if (!dev || pci_enable_device(dev))
1883 return 0;
1884
1885 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1da177e4
LT		 1886
1887 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1888 rocketModel[i].loadrm2 = 0;
1889 rocketModel[i].startingPortNumber = nextLineNumber;
1890
1891 /* Depending on the model, set up some config variables */
1892 switch (dev->device) {
1893 case PCI_DEVICE_ID_RP4QUAD:
1894 str = "Quadcable";
1895 max_num_aiops = 1;
1896 ports_per_aiop = 4;
1897 rocketModel[i].model = MODEL_RP4QUAD;
1898 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1899 rocketModel[i].numPorts = 4;
1900 break;
1901 case PCI_DEVICE_ID_RP8OCTA:
1902 str = "Octacable";
1903 max_num_aiops = 1;
1904 rocketModel[i].model = MODEL_RP8OCTA;
1905 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1906 rocketModel[i].numPorts = 8;
1907 break;
1908 case PCI_DEVICE_ID_URP8OCTA:
1909 str = "Octacable";
1910 max_num_aiops = 1;
1911 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1912 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1913 rocketModel[i].numPorts = 8;
1914 break;
1915 case PCI_DEVICE_ID_RP8INTF:
1916 str = "8";
1917 max_num_aiops = 1;
1918 rocketModel[i].model = MODEL_RP8INTF;
1919 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1920 rocketModel[i].numPorts = 8;
1921 break;
1922 case PCI_DEVICE_ID_URP8INTF:
1923 str = "8";
1924 max_num_aiops = 1;
1925 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1926 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1927 rocketModel[i].numPorts = 8;
1928 break;
1929 case PCI_DEVICE_ID_RP8J:
1930 str = "8J";
1931 max_num_aiops = 1;
1932 rocketModel[i].model = MODEL_RP8J;
1933 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1934 rocketModel[i].numPorts = 8;
1935 break;
1936 case PCI_DEVICE_ID_RP4J:
1937 str = "4J";
1938 max_num_aiops = 1;
1939 ports_per_aiop = 4;
1940 rocketModel[i].model = MODEL_RP4J;
1941 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1942 rocketModel[i].numPorts = 4;
1943 break;
1944 case PCI_DEVICE_ID_RP8SNI:
1945 str = "8 (DB78 Custom)";
1946 max_num_aiops = 1;
1947 rocketModel[i].model = MODEL_RP8SNI;
1948 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1949 rocketModel[i].numPorts = 8;
1950 break;
1951 case PCI_DEVICE_ID_RP16SNI:
1952 str = "16 (DB78 Custom)";
1953 max_num_aiops = 2;
1954 rocketModel[i].model = MODEL_RP16SNI;
1955 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1956 rocketModel[i].numPorts = 16;
1957 break;
1958 case PCI_DEVICE_ID_RP16INTF:
1959 str = "16";
1960 max_num_aiops = 2;
1961 rocketModel[i].model = MODEL_RP16INTF;
1962 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1963 rocketModel[i].numPorts = 16;
1964 break;
1965 case PCI_DEVICE_ID_URP16INTF:
1966 str = "16";
1967 max_num_aiops = 2;
1968 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1969 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1970 rocketModel[i].numPorts = 16;
1971 break;
1972 case PCI_DEVICE_ID_CRP16INTF:
1973 str = "16";
1974 max_num_aiops = 2;
1975 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1976 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1977 rocketModel[i].numPorts = 16;
1978 break;
1979 case PCI_DEVICE_ID_RP32INTF:
1980 str = "32";
1981 max_num_aiops = 4;
1982 rocketModel[i].model = MODEL_RP32INTF;
1983 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1984 rocketModel[i].numPorts = 32;
1985 break;
1986 case PCI_DEVICE_ID_URP32INTF:
1987 str = "32";
1988 max_num_aiops = 4;
1989 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1990 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1991 rocketModel[i].numPorts = 32;
1992 break;
1993 case PCI_DEVICE_ID_RPP4:
1994 str = "Plus Quadcable";
1995 max_num_aiops = 1;
1996 ports_per_aiop = 4;
1997 altChanRingIndicator++;
1998 fast_clock++;
1999 rocketModel[i].model = MODEL_RPP4;
2000 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2001 rocketModel[i].numPorts = 4;
2002 break;
2003 case PCI_DEVICE_ID_RPP8:
2004 str = "Plus Octacable";
2005 max_num_aiops = 2;
2006 ports_per_aiop = 4;
2007 altChanRingIndicator++;
2008 fast_clock++;
2009 rocketModel[i].model = MODEL_RPP8;
2010 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2011 rocketModel[i].numPorts = 8;
2012 break;
2013 case PCI_DEVICE_ID_RP2_232:
2014 str = "Plus 2 (RS-232)";
2015 max_num_aiops = 1;
2016 ports_per_aiop = 2;
2017 altChanRingIndicator++;
2018 fast_clock++;
2019 rocketModel[i].model = MODEL_RP2_232;
2020 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2021 rocketModel[i].numPorts = 2;
2022 break;
2023 case PCI_DEVICE_ID_RP2_422:
2024 str = "Plus 2 (RS-422)";
2025 max_num_aiops = 1;
2026 ports_per_aiop = 2;
2027 altChanRingIndicator++;
2028 fast_clock++;
2029 rocketModel[i].model = MODEL_RP2_422;
2030 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2031 rocketModel[i].numPorts = 2;
2032 break;
2033 case PCI_DEVICE_ID_RP6M:
2034
2035 max_num_aiops = 1;
2036 ports_per_aiop = 6;
2037 str = "6-port";
2038
57fedc7a
JS		 2039 /* If revision is 1, the rocketmodem flash must be loaded.
2040 * If it is 2 it is a "socketed" version. */
2041 if (dev->revision == 1) {
1da177e4
LT		 2042 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2043 rocketModel[i].loadrm2 = 1;
2044 } else {
2045 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2046 }
2047
2048 rocketModel[i].model = MODEL_RP6M;
2049 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2050 rocketModel[i].numPorts = 6;
2051 break;
2052 case PCI_DEVICE_ID_RP4M:
2053 max_num_aiops = 1;
2054 ports_per_aiop = 4;
2055 str = "4-port";
57fedc7a 2056 if (dev->revision == 1) {
1da177e4
LT		 2057 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2058 rocketModel[i].loadrm2 = 1;
2059 } else {
2060 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2061 }
2062
2063 rocketModel[i].model = MODEL_RP4M;
2064 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2065 rocketModel[i].numPorts = 4;
2066 break;
2067 default:
2068 str = "(unknown/unsupported)";
2069 max_num_aiops = 0;
2070 break;
2071 }
2072
2073 /*
2074 * Check for UPCI boards.
2075 */
2076
2077 switch (dev->device) {
2078 case PCI_DEVICE_ID_URP32INTF:
2079 case PCI_DEVICE_ID_URP8INTF:
2080 case PCI_DEVICE_ID_URP16INTF:
2081 case PCI_DEVICE_ID_CRP16INTF:
2082 case PCI_DEVICE_ID_URP8OCTA:
2083 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2084 ConfigIO = pci_resource_start(dev, 1);
2085 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2086 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2087
2088 /*
2089 * Check for octa or quad cable.
2090 */
2091 if (!
2092 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2093 PCI_GPIO_CTRL_8PORT)) {
2094 str = "Quadcable";
2095 ports_per_aiop = 4;
2096 rocketModel[i].numPorts = 4;
2097 }
2098 }
2099 break;
2100 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2101 str = "8 ports";
2102 max_num_aiops = 1;
2103 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2104 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2105 rocketModel[i].numPorts = 8;
2106 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2107 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2108 ConfigIO = pci_resource_start(dev, 1);
2109 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2110 break;
2111 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2112 str = "4 ports";
2113 max_num_aiops = 1;
2114 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2115 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2116 rocketModel[i].numPorts = 4;
2117 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2118 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2119 ConfigIO = pci_resource_start(dev, 1);
2120 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2121 break;
2122 default:
2123 break;
2124 }
2125
2126 switch (rcktpt_type[i]) {
2127 case ROCKET_TYPE_MODEM:
2128 board_type = "RocketModem";
2129 break;
2130 case ROCKET_TYPE_MODEMII:
2131 board_type = "RocketModem II";
2132 break;
2133 case ROCKET_TYPE_MODEMIII:
2134 board_type = "RocketModem III";
2135 break;
2136 default:
2137 board_type = "RocketPort";
2138 break;
2139 }
2140
2141 if (fast_clock) {
2142 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2143 rp_baud_base[i] = 921600;
2144 } else {
2145 /*
2146 * If support_low_speed is set, use the slow clock
2147 * prescale, which supports 50 bps
2148 */
2149 if (support_low_speed) {
2150 /* mod 9 (divide by 10) prescale */
2151 sClockPrescale = 0x19;
2152 rp_baud_base[i] = 230400;
2153 } else {
2154 /* mod 4 (devide by 5) prescale */
2155 sClockPrescale = 0x14;
2156 rp_baud_base[i] = 460800;
2157 }
2158 }
2159
2160 for (aiop = 0; aiop < max_num_aiops; aiop++)
2161 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2162 ctlp = sCtlNumToCtlPtr(i);
2163 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2164 for (aiop = 0; aiop < max_num_aiops; aiop++)
2165 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2166
68562b79
JS		 2167 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2168 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2169 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2170 rocketModel[i].startingPortNumber,
2171 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
1da177e4
LT		 2172
2173 if (num_aiops <= 0) {
2174 rcktpt_io_addr[i] = 0;
2175 return (0);
2176 }
2177 is_PCI[i] = 1;
2178
2179 /* Reset the AIOPIC, init the serial ports */
2180 for (aiop = 0; aiop < num_aiops; aiop++) {
2181 sResetAiopByNum(ctlp, aiop);
2182 num_chan = ports_per_aiop;
2183 for (chan = 0; chan < num_chan; chan++)
2184 init_r_port(i, aiop, chan, dev);
2185 }
2186
2187 /* Rocket modems must be reset */
2188 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2189 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2190 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2191 num_chan = ports_per_aiop;
2192 for (chan = 0; chan < num_chan; chan++)
2193 sPCIModemReset(ctlp, chan, 1);
48a67f5d 2194 msleep(500);
1da177e4
LT		 2195 for (chan = 0; chan < num_chan; chan++)
2196 sPCIModemReset(ctlp, chan, 0);
48a67f5d 2197 msleep(500);
1da177e4
LT		 2198 rmSpeakerReset(ctlp, rocketModel[i].model);
2199 }
2200 return (1);
2201}
2202
2203/*
2204 * Probes for PCI cards, inits them if found
2205 * Input: board_found = number of ISA boards already found, or the
2206 * starting board number
2207 * Returns: Number of PCI boards found
2208 */
2209static int __init init_PCI(int boards_found)
2210{
2211 struct pci_dev *dev = NULL;
2212 int count = 0;
2213
2214 /* Work through the PCI device list, pulling out ours */
606d099c 2215 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
1da177e4
LT		 2216 if (register_PCI(count + boards_found, dev))
2217 count++;
2218 }
2219 return (count);
2220}
2221
2222#endif /* CONFIG_PCI */
2223
2224/*
2225 * Probes for ISA cards
2226 * Input: i = the board number to look for
2227 * Returns: 1 if board found, 0 else
2228 */
2229static int __init init_ISA(int i)
2230{
2231 int num_aiops, num_chan = 0, total_num_chan = 0;
2232 int aiop, chan;
2233 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2234 CONTROLLER_t *ctlp;
2235 char *type_string;
2236
2237 /* If io_addr is zero, no board configured */
2238 if (rcktpt_io_addr[i] == 0)
2239 return (0);
2240
2241 /* Reserve the IO region */
2242 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
68562b79
JS		 2243 printk(KERN_ERR "Unable to reserve IO region for configured "
2244 "ISA RocketPort at address 0x%lx, board not "
2245 "installed...\n", rcktpt_io_addr[i]);
1da177e4
LT		 2246 rcktpt_io_addr[i] = 0;
2247 return (0);
2248 }
2249
2250 ctlp = sCtlNumToCtlPtr(i);
2251
2252 ctlp->boardType = rcktpt_type[i];
2253
2254 switch (rcktpt_type[i]) {
2255 case ROCKET_TYPE_PC104:
2256 type_string = "(PC104)";
2257 break;
2258 case ROCKET_TYPE_MODEM:
2259 type_string = "(RocketModem)";
2260 break;
2261 case ROCKET_TYPE_MODEMII:
2262 type_string = "(RocketModem II)";
2263 break;
2264 default:
2265 type_string = "";
2266 break;
2267 }
2268
2269 /*
2270 * If support_low_speed is set, use the slow clock prescale,
2271 * which supports 50 bps
2272 */
2273 if (support_low_speed) {
2274 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2275 rp_baud_base[i] = 230400;
2276 } else {
2277 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2278 rp_baud_base[i] = 460800;
2279 }
2280
2281 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2282 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2283
2284 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2285
2286 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2287 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2288 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2289 }
2290
2291 /* If something went wrong initing the AIOP's release the ISA IO memory */
2292 if (num_aiops <= 0) {
2293 release_region(rcktpt_io_addr[i], 64);
2294 rcktpt_io_addr[i] = 0;
2295 return (0);
2296 }
2297
2298 rocketModel[i].startingPortNumber = nextLineNumber;
2299
2300 for (aiop = 0; aiop < num_aiops; aiop++) {
2301 sResetAiopByNum(ctlp, aiop);
2302 sEnAiop(ctlp, aiop);
2303 num_chan = sGetAiopNumChan(ctlp, aiop);
2304 total_num_chan += num_chan;
2305 for (chan = 0; chan < num_chan; chan++)
2306 init_r_port(i, aiop, chan, NULL);
2307 }
2308 is_PCI[i] = 0;
2309 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2310 num_chan = sGetAiopNumChan(ctlp, 0);
2311 total_num_chan = num_chan;
2312 for (chan = 0; chan < num_chan; chan++)
2313 sModemReset(ctlp, chan, 1);
48a67f5d 2314 msleep(500);
1da177e4
LT		 2315 for (chan = 0; chan < num_chan; chan++)
2316 sModemReset(ctlp, chan, 0);
48a67f5d 2317 msleep(500);
1da177e4
LT		 2318 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2319 } else {
2320 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2321 }
2322 rocketModel[i].numPorts = total_num_chan;
2323 rocketModel[i].model = MODEL_ISA;
2324
2325 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2326 i, rcktpt_io_addr[i], num_aiops, type_string);
2327
2328 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2329 rocketModel[i].modelString,
2330 rocketModel[i].startingPortNumber,
2331 rocketModel[i].startingPortNumber +
2332 rocketModel[i].numPorts - 1);
2333
2334 return (1);
2335}
2336
b68e31d0 2337static const struct tty_operations rocket_ops = {
1da177e4
LT		 2338 .open = rp_open,
2339 .close = rp_close,
2340 .write = rp_write,
2341 .put_char = rp_put_char,
2342 .write_room = rp_write_room,
2343 .chars_in_buffer = rp_chars_in_buffer,
2344 .flush_buffer = rp_flush_buffer,
2345 .ioctl = rp_ioctl,
2346 .throttle = rp_throttle,
2347 .unthrottle = rp_unthrottle,
2348 .set_termios = rp_set_termios,
2349 .stop = rp_stop,
2350 .start = rp_start,
2351 .hangup = rp_hangup,
2352 .break_ctl = rp_break,
2353 .send_xchar = rp_send_xchar,
2354 .wait_until_sent = rp_wait_until_sent,
2355 .tiocmget = rp_tiocmget,
2356 .tiocmset = rp_tiocmset,
2357};
2358
2359/*
2360 * The module "startup" routine; it's run when the module is loaded.
2361 */
d269cdd0 2362static int __init rp_init(void)
1da177e4 2363{
4384a3fa 2364 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
1da177e4
LT		 2365
2366 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2367 ROCKET_VERSION, ROCKET_DATE);
2368
2369 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2370 if (!rocket_driver)
4384a3fa 2371 goto err;
1da177e4 2372
1da177e4
LT		 2373 /*
2374 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2375 * zero, use the default controller IO address of board1 + 0x40.
2376 */
2377 if (board1) {
2378 if (controller == 0)
2379 controller = board1 + 0x40;
2380 } else {
2381 controller = 0; /* Used as a flag, meaning no ISA boards */
2382 }
2383
2384 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2385 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
4384a3fa
JS		 2386 printk(KERN_ERR "Unable to reserve IO region for first "
2387 "configured ISA RocketPort controller 0x%lx. "
2388 "Driver exiting\n", controller);
2389 ret = -EBUSY;
2390 goto err_tty;
1da177e4
LT		 2391 }
2392
2393 /* Store ISA variable retrieved from command line or .conf file. */
2394 rcktpt_io_addr[0] = board1;
2395 rcktpt_io_addr[1] = board2;
2396 rcktpt_io_addr[2] = board3;
2397 rcktpt_io_addr[3] = board4;
2398
2399 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2400 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2401 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2402 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2403 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2404 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2405 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2406 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2407
2408 /*
2409 * Set up the tty driver structure and then register this
2410 * driver with the tty layer.
2411 */
2412
2413 rocket_driver->owner = THIS_MODULE;
331b8319 2414 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 2415 rocket_driver->name = "ttyR";
2416 rocket_driver->driver_name = "Comtrol RocketPort";
2417 rocket_driver->major = TTY_ROCKET_MAJOR;
2418 rocket_driver->minor_start = 0;
2419 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2420 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2421 rocket_driver->init_termios = tty_std_termios;
2422 rocket_driver->init_termios.c_cflag =
2423 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 2424 rocket_driver->init_termios.c_ispeed = 9600;
2425 rocket_driver->init_termios.c_ospeed = 9600;
1da177e4 2426#ifdef ROCKET_SOFT_FLOW
ac6aec2f 2427 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
1da177e4
LT		 2428#endif
2429 tty_set_operations(rocket_driver, &rocket_ops);
2430
4384a3fa
JS		 2431 ret = tty_register_driver(rocket_driver);
2432 if (ret < 0) {
2433 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2434 goto err_tty;
1da177e4
LT		 2435 }
2436
2437#ifdef ROCKET_DEBUG_OPEN
2438 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2439#endif
2440
2441 /*
2442 * OK, let's probe each of the controllers looking for boards. Any boards found
2443 * will be initialized here.
2444 */
2445 isa_boards_found = 0;
2446 pci_boards_found = 0;
2447
2448 for (i = 0; i < NUM_BOARDS; i++) {
2449 if (init_ISA(i))
2450 isa_boards_found++;
2451 }
2452
2453#ifdef CONFIG_PCI
2454 if (isa_boards_found < NUM_BOARDS)
2455 pci_boards_found = init_PCI(isa_boards_found);
2456#endif
2457
2458 max_board = pci_boards_found + isa_boards_found;
2459
2460 if (max_board == 0) {
4384a3fa
JS		 2461 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2462 ret = -ENXIO;
2463 goto err_ttyu;
1da177e4
LT		 2464 }
2465
2466 return 0;
4384a3fa
JS		 2467err_ttyu:
2468 tty_unregister_driver(rocket_driver);
2469err_tty:
2470 put_tty_driver(rocket_driver);
2471err:
2472 return ret;
1da177e4
LT		 2473}
2474
1da177e4
LT		 2475
2476static void rp_cleanup_module(void)
2477{
2478 int retval;
2479 int i;
2480
2481 del_timer_sync(&rocket_timer);
2482
2483 retval = tty_unregister_driver(rocket_driver);
2484 if (retval)
68562b79 2485 printk(KERN_ERR "Error %d while trying to unregister "
1da177e4 2486 "rocketport driver\n", -retval);
1da177e4 2487
735d5661 2488 for (i = 0; i < MAX_RP_PORTS; i++)
ac6aec2f
JS		 2489 if (rp_table[i]) {
2490 tty_unregister_device(rocket_driver, i);
2491 kfree(rp_table[i]);
2492 }
2493
2494 put_tty_driver(rocket_driver);
1da177e4
LT		 2495
2496 for (i = 0; i < NUM_BOARDS; i++) {
2497 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2498 continue;
2499 release_region(rcktpt_io_addr[i], 64);
2500 }
2501 if (controller)
2502 release_region(controller, 4);
2503}
1da177e4 2504
1da177e4
LT		 2505/***************************************************************************
2506Function: sInitController
2507Purpose: Initialization of controller global registers and controller
2508 structure.
2509Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2510 IRQNum,Frequency,PeriodicOnly)
2511 CONTROLLER_T *CtlP; Ptr to controller structure
2512 int CtlNum; Controller number
2513 ByteIO_t MudbacIO; Mudbac base I/O address.
2514 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2515 This list must be in the order the AIOPs will be found on the
2516 controller. Once an AIOP in the list is not found, it is
2517 assumed that there are no more AIOPs on the controller.
2518 int AiopIOListSize; Number of addresses in AiopIOList
2519 int IRQNum; Interrupt Request number. Can be any of the following:
2520 0: Disable global interrupts
2521 3: IRQ 3
2522 4: IRQ 4
2523 5: IRQ 5
2524 9: IRQ 9
2525 10: IRQ 10
2526 11: IRQ 11
2527 12: IRQ 12
2528 15: IRQ 15
2529 Byte_t Frequency: A flag identifying the frequency
2530 of the periodic interrupt, can be any one of the following:
2531 FREQ_DIS - periodic interrupt disabled
2532 FREQ_137HZ - 137 Hertz
2533 FREQ_69HZ - 69 Hertz
2534 FREQ_34HZ - 34 Hertz
2535 FREQ_17HZ - 17 Hertz
2536 FREQ_9HZ - 9 Hertz
2537 FREQ_4HZ - 4 Hertz
2538 If IRQNum is set to 0 the Frequency parameter is
2539 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2540 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2541 interrupt are to be blocked.
f15313bf 2542 0 is both the periodic interrupt and
1da177e4
LT		 2543 other channel interrupts are allowed.
2544 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2545 overidden, it is forced to a value of 0.
1da177e4
LT		 2546Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2547 initialization failed.
2548
2549Comments:
2550 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2551 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2552
2553 If interrupts are to be completely disabled set IRQNum to 0.
2554
f15313bf 2555 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2556 invalid combination.
2557
2558 This function performs initialization of global interrupt modes,
2559 but it does not actually enable global interrupts. To enable
2560 and disable global interrupts use functions sEnGlobalInt() and
2561 sDisGlobalInt(). Enabling of global interrupts is normally not
2562 done until all other initializations are complete.
2563
2564 Even if interrupts are globally enabled, they must also be
2565 individually enabled for each channel that is to generate
2566 interrupts.
2567
2568Warnings: No range checking on any of the parameters is done.
2569
2570 No context switches are allowed while executing this function.
2571
2572 After this function all AIOPs on the controller are disabled,
2573 they can be enabled with sEnAiop().
2574*/
f15313bf
AB		 2575static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2576 ByteIO_t * AiopIOList, int AiopIOListSize,
2577 int IRQNum, Byte_t Frequency, int PeriodicOnly)
1da177e4
LT		 2578{
2579 int i;
2580 ByteIO_t io;
2581 int done;
2582
2583 CtlP->AiopIntrBits = aiop_intr_bits;
2584 CtlP->AltChanRingIndicator = 0;
2585 CtlP->CtlNum = CtlNum;
2586 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2587 CtlP->BusType = isISA;
2588 CtlP->MBaseIO = MudbacIO;
2589 CtlP->MReg1IO = MudbacIO + 1;
2590 CtlP->MReg2IO = MudbacIO + 2;
2591 CtlP->MReg3IO = MudbacIO + 3;
2592#if 1
2593 CtlP->MReg2 = 0; /* interrupt disable */
2594 CtlP->MReg3 = 0; /* no periodic interrupts */
2595#else
2596 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2597 CtlP->MReg2 = 0; /* interrupt disable */
2598 CtlP->MReg3 = 0; /* no periodic interrupts */
2599 } else {
2600 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2601 CtlP->MReg3 = Frequency; /* set frequency */
2602 if (PeriodicOnly) { /* periodic interrupt only */
2603 CtlP->MReg3 |= PERIODIC_ONLY;
2604 }
2605 }
2606#endif
2607 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2608 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2609 sControllerEOI(CtlP); /* clear EOI if warm init */
2610 /* Init AIOPs */
2611 CtlP->NumAiop = 0;
2612 for (i = done = 0; i < AiopIOListSize; i++) {
2613 io = AiopIOList[i];
2614 CtlP->AiopIO[i] = (WordIO_t) io;
2615 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2616 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2617 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2618 if (done)
2619 continue;
2620 sEnAiop(CtlP, i); /* enable the AIOP */
2621 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2622 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2623 done = 1; /* done looking for AIOPs */
2624 else {
2625 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2626 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2627 sOutB(io + _INDX_DATA, sClockPrescale);
2628 CtlP->NumAiop++; /* bump count of AIOPs */
2629 }
2630 sDisAiop(CtlP, i); /* disable AIOP */
2631 }
2632
2633 if (CtlP->NumAiop == 0)
2634 return (-1);
2635 else
2636 return (CtlP->NumAiop);
2637}
2638
2639/***************************************************************************
2640Function: sPCIInitController
2641Purpose: Initialization of controller global registers and controller
2642 structure.
2643Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2644 IRQNum,Frequency,PeriodicOnly)
2645 CONTROLLER_T *CtlP; Ptr to controller structure
2646 int CtlNum; Controller number
2647 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2648 This list must be in the order the AIOPs will be found on the
2649 controller. Once an AIOP in the list is not found, it is
2650 assumed that there are no more AIOPs on the controller.
2651 int AiopIOListSize; Number of addresses in AiopIOList
2652 int IRQNum; Interrupt Request number. Can be any of the following:
2653 0: Disable global interrupts
2654 3: IRQ 3
2655 4: IRQ 4
2656 5: IRQ 5
2657 9: IRQ 9
2658 10: IRQ 10
2659 11: IRQ 11
2660 12: IRQ 12
2661 15: IRQ 15
2662 Byte_t Frequency: A flag identifying the frequency
2663 of the periodic interrupt, can be any one of the following:
2664 FREQ_DIS - periodic interrupt disabled
2665 FREQ_137HZ - 137 Hertz
2666 FREQ_69HZ - 69 Hertz
2667 FREQ_34HZ - 34 Hertz
2668 FREQ_17HZ - 17 Hertz
2669 FREQ_9HZ - 9 Hertz
2670 FREQ_4HZ - 4 Hertz
2671 If IRQNum is set to 0 the Frequency parameter is
2672 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2673 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2674 interrupt are to be blocked.
f15313bf 2675 0 is both the periodic interrupt and
1da177e4
LT		 2676 other channel interrupts are allowed.
2677 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2678 overidden, it is forced to a value of 0.
1da177e4
LT		 2679Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2680 initialization failed.
2681
2682Comments:
2683 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2684 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2685
2686 If interrupts are to be completely disabled set IRQNum to 0.
2687
f15313bf 2688 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2689 invalid combination.
2690
2691 This function performs initialization of global interrupt modes,
2692 but it does not actually enable global interrupts. To enable
2693 and disable global interrupts use functions sEnGlobalInt() and
2694 sDisGlobalInt(). Enabling of global interrupts is normally not
2695 done until all other initializations are complete.
2696
2697 Even if interrupts are globally enabled, they must also be
2698 individually enabled for each channel that is to generate
2699 interrupts.
2700
2701Warnings: No range checking on any of the parameters is done.
2702
2703 No context switches are allowed while executing this function.
2704
2705 After this function all AIOPs on the controller are disabled,
2706 they can be enabled with sEnAiop().
2707*/
f15313bf
AB		 2708static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2709 ByteIO_t * AiopIOList, int AiopIOListSize,
2710 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2711 int PeriodicOnly, int altChanRingIndicator,
2712 int UPCIRingInd)
1da177e4
LT		 2713{
2714 int i;
2715 ByteIO_t io;
2716
2717 CtlP->AltChanRingIndicator = altChanRingIndicator;
2718 CtlP->UPCIRingInd = UPCIRingInd;
2719 CtlP->CtlNum = CtlNum;
2720 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2721 CtlP->BusType = isPCI; /* controller release 1 */
2722
2723 if (ConfigIO) {
2724 CtlP->isUPCI = 1;
2725 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2726 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2727 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2728 } else {
2729 CtlP->isUPCI = 0;
2730 CtlP->PCIIO =
2731 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2732 CtlP->AiopIntrBits = aiop_intr_bits;
2733 }
2734
2735 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2736 /* Init AIOPs */
2737 CtlP->NumAiop = 0;
2738 for (i = 0; i < AiopIOListSize; i++) {
2739 io = AiopIOList[i];
2740 CtlP->AiopIO[i] = (WordIO_t) io;
2741 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2742
2743 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2744 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2745 break; /* done looking for AIOPs */
2746
2747 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2748 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2749 sOutB(io + _INDX_DATA, sClockPrescale);
2750 CtlP->NumAiop++; /* bump count of AIOPs */
2751 }
2752
2753 if (CtlP->NumAiop == 0)
2754 return (-1);
2755 else
2756 return (CtlP->NumAiop);
2757}
2758
2759/***************************************************************************
2760Function: sReadAiopID
2761Purpose: Read the AIOP idenfication number directly from an AIOP.
2762Call: sReadAiopID(io)
2763 ByteIO_t io: AIOP base I/O address
2764Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2765 is replace by an identifying number.
2766 Flag AIOPID_NULL if no valid AIOP is found
2767Warnings: No context switches are allowed while executing this function.
2768
2769*/
f15313bf 2770static int sReadAiopID(ByteIO_t io)
1da177e4
LT		 2771{
2772 Byte_t AiopID; /* ID byte from AIOP */
2773
2774 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2775 sOutB(io + _CMD_REG, 0x0);
2776 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2777 if (AiopID == 0x06)
2778 return (1);
2779 else /* AIOP does not exist */
2780 return (-1);
2781}
2782
2783/***************************************************************************
2784Function: sReadAiopNumChan
2785Purpose: Read the number of channels available in an AIOP directly from
2786 an AIOP.
2787Call: sReadAiopNumChan(io)
2788 WordIO_t io: AIOP base I/O address
2789Return: int: The number of channels available
2790Comments: The number of channels is determined by write/reads from identical
2791 offsets within the SRAM address spaces for channels 0 and 4.
2792 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2793 AIOP, otherwise it is an 8 channel.
2794Warnings: No context switches are allowed while executing this function.
2795*/
f15313bf 2796static int sReadAiopNumChan(WordIO_t io)
1da177e4
LT		 2797{
2798 Word_t x;
2799 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2800
2801 /* write to chan 0 SRAM */
457fb605 2802 out32((DWordIO_t) io + _INDX_ADDR, R);
1da177e4
LT		 2803 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2804 x = sInW(io + _INDX_DATA);
2805 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2806 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2807 return (8);
2808 else
2809 return (4);
2810}
2811
2812/***************************************************************************
2813Function: sInitChan
2814Purpose: Initialization of a channel and channel structure
2815Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2816 CONTROLLER_T *CtlP; Ptr to controller structure
2817 CHANNEL_T *ChP; Ptr to channel structure
2818 int AiopNum; AIOP number within controller
2819 int ChanNum; Channel number within AIOP
f15313bf 2820Return: int: 1 if initialization succeeded, 0 if it fails because channel
1da177e4
LT		 2821 number exceeds number of channels available in AIOP.
2822Comments: This function must be called before a channel can be used.
2823Warnings: No range checking on any of the parameters is done.
2824
2825 No context switches are allowed while executing this function.
2826*/
f15313bf
AB		 2827static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2828 int ChanNum)
1da177e4
LT		 2829{
2830 int i;
2831 WordIO_t AiopIO;
2832 WordIO_t ChIOOff;
2833 Byte_t *ChR;
2834 Word_t ChOff;
2835 static Byte_t R[4];
2836 int brd9600;
2837
2838 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
f15313bf 2839 return 0; /* exceeds num chans in AIOP */
1da177e4
LT		 2840
2841 /* Channel, AIOP, and controller identifiers */
2842 ChP->CtlP = CtlP;
2843 ChP->ChanID = CtlP->AiopID[AiopNum];
2844 ChP->AiopNum = AiopNum;
2845 ChP->ChanNum = ChanNum;
2846
2847 /* Global direct addresses */
2848 AiopIO = CtlP->AiopIO[AiopNum];
2849 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2850 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2851 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2852 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2853 ChP->IndexData = AiopIO + _INDX_DATA;
2854
2855 /* Channel direct addresses */
2856 ChIOOff = AiopIO + ChP->ChanNum * 2;
2857 ChP->TxRxData = ChIOOff + _TD0;
2858 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2859 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2860 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2861
2862 /* Initialize the channel from the RData array */
2863 for (i = 0; i < RDATASIZE; i += 4) {
2864 R[0] = RData[i];
2865 R[1] = RData[i + 1] + 0x10 * ChanNum;
2866 R[2] = RData[i + 2];
2867 R[3] = RData[i + 3];
457fb605 2868 out32(ChP->IndexAddr, R);
1da177e4
LT		 2869 }
2870
2871 ChR = ChP->R;
2872 for (i = 0; i < RREGDATASIZE; i += 4) {
2873 ChR[i] = RRegData[i];
2874 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2875 ChR[i + 2] = RRegData[i + 2];
2876 ChR[i + 3] = RRegData[i + 3];
2877 }
2878
2879 /* Indexed registers */
2880 ChOff = (Word_t) ChanNum *0x1000;
2881
2882 if (sClockPrescale == 0x14)
2883 brd9600 = 47;
2884 else
2885 brd9600 = 23;
2886
2887 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2888 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2889 ChP->BaudDiv[2] = (Byte_t) brd9600;
2890 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
457fb605 2891 out32(ChP->IndexAddr, ChP->BaudDiv);
1da177e4
LT		 2892
2893 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2894 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2895 ChP->TxControl[2] = 0;
2896 ChP->TxControl[3] = 0;
457fb605 2897 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 2898
2899 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2900 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2901 ChP->RxControl[2] = 0;
2902 ChP->RxControl[3] = 0;
457fb605 2903 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 2904
2905 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2906 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2907 ChP->TxEnables[2] = 0;
2908 ChP->TxEnables[3] = 0;
457fb605 2909 out32(ChP->IndexAddr, ChP->TxEnables);
1da177e4
LT		 2910
2911 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2912 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2913 ChP->TxCompare[2] = 0;
2914 ChP->TxCompare[3] = 0;
457fb605 2915 out32(ChP->IndexAddr, ChP->TxCompare);
1da177e4
LT		 2916
2917 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2918 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2919 ChP->TxReplace1[2] = 0;
2920 ChP->TxReplace1[3] = 0;
457fb605 2921 out32(ChP->IndexAddr, ChP->TxReplace1);
1da177e4
LT		 2922
2923 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2924 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2925 ChP->TxReplace2[2] = 0;
2926 ChP->TxReplace2[3] = 0;
457fb605 2927 out32(ChP->IndexAddr, ChP->TxReplace2);
1da177e4
LT		 2928
2929 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2930 ChP->TxFIFO = ChOff + _TX_FIFO;
2931
2932 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2933 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2934 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2935 sOutW(ChP->IndexData, 0);
2936 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2937 ChP->RxFIFO = ChOff + _RX_FIFO;
2938
2939 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2940 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2941 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2942 sOutW(ChP->IndexData, 0);
2943 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2944 sOutW(ChP->IndexData, 0);
2945 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2946 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2947 sOutB(ChP->IndexData, 0);
2948 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2949 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2950 sOutB(ChP->IndexData, 0);
2951 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2952 sEnRxProcessor(ChP); /* start the Rx processor */
2953
f15313bf 2954 return 1;
1da177e4
LT		 2955}
2956
2957/***************************************************************************
2958Function: sStopRxProcessor
2959Purpose: Stop the receive processor from processing a channel.
2960Call: sStopRxProcessor(ChP)
2961 CHANNEL_T *ChP; Ptr to channel structure
2962
2963Comments: The receive processor can be started again with sStartRxProcessor().
2964 This function causes the receive processor to skip over the
2965 stopped channel. It does not stop it from processing other channels.
2966
2967Warnings: No context switches are allowed while executing this function.
2968
2969 Do not leave the receive processor stopped for more than one
2970 character time.
2971
2972 After calling this function a delay of 4 uS is required to ensure
2973 that the receive processor is no longer processing this channel.
2974*/
f15313bf 2975static void sStopRxProcessor(CHANNEL_T * ChP)
1da177e4
LT		 2976{
2977 Byte_t R[4];
2978
2979 R[0] = ChP->R[0];
2980 R[1] = ChP->R[1];
2981 R[2] = 0x0a;
2982 R[3] = ChP->R[3];
457fb605 2983 out32(ChP->IndexAddr, R);
1da177e4
LT		 2984}
2985
2986/***************************************************************************
2987Function: sFlushRxFIFO
2988Purpose: Flush the Rx FIFO
2989Call: sFlushRxFIFO(ChP)
2990 CHANNEL_T *ChP; Ptr to channel structure
2991Return: void
2992Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2993 while it is being flushed the receive processor is stopped
2994 and the transmitter is disabled. After these operations a
2995 4 uS delay is done before clearing the pointers to allow
2996 the receive processor to stop. These items are handled inside
2997 this function.
2998Warnings: No context switches are allowed while executing this function.
2999*/
f15313bf 3000static void sFlushRxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 3001{
3002 int i;
3003 Byte_t Ch; /* channel number within AIOP */
f15313bf 3004 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
1da177e4
LT		 3005
3006 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3007 return; /* don't need to flush */
3008
f15313bf 3009 RxFIFOEnabled = 0;
1da177e4 3010 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
f15313bf 3011 RxFIFOEnabled = 1;
1da177e4
LT		 3012 sDisRxFIFO(ChP); /* disable it */
3013 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3014 sInB(ChP->IntChan); /* depends on bus i/o timing */
3015 }
3016 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3017 Ch = (Byte_t) sGetChanNum(ChP);
3018 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3019 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3020 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3021 sOutW(ChP->IndexData, 0);
3022 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3023 sOutW(ChP->IndexData, 0);
3024 if (RxFIFOEnabled)
3025 sEnRxFIFO(ChP); /* enable Rx FIFO */
3026}
3027
3028/***************************************************************************
3029Function: sFlushTxFIFO
3030Purpose: Flush the Tx FIFO
3031Call: sFlushTxFIFO(ChP)
3032 CHANNEL_T *ChP; Ptr to channel structure
3033Return: void
3034Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3035 while it is being flushed the receive processor is stopped
3036 and the transmitter is disabled. After these operations a
3037 4 uS delay is done before clearing the pointers to allow
3038 the receive processor to stop. These items are handled inside
3039 this function.
3040Warnings: No context switches are allowed while executing this function.
3041*/
f15313bf 3042static void sFlushTxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 3043{
3044 int i;
3045 Byte_t Ch; /* channel number within AIOP */
f15313bf 3046 int TxEnabled; /* 1 if transmitter enabled */
1da177e4
LT		 3047
3048 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3049 return; /* don't need to flush */
3050
f15313bf 3051 TxEnabled = 0;
1da177e4 3052 if (ChP->TxControl[3] & TX_ENABLE) {
f15313bf 3053 TxEnabled = 1;
1da177e4
LT		 3054 sDisTransmit(ChP); /* disable transmitter */
3055 }
3056 sStopRxProcessor(ChP); /* stop Rx processor */
3057 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3058 sInB(ChP->IntChan); /* depends on bus i/o timing */
3059 Ch = (Byte_t) sGetChanNum(ChP);
3060 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3061 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3062 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3063 sOutW(ChP->IndexData, 0);
3064 if (TxEnabled)
3065 sEnTransmit(ChP); /* enable transmitter */
3066 sStartRxProcessor(ChP); /* restart Rx processor */
3067}
3068
3069/***************************************************************************
3070Function: sWriteTxPrioByte
3071Purpose: Write a byte of priority transmit data to a channel
3072Call: sWriteTxPrioByte(ChP,Data)
3073 CHANNEL_T *ChP; Ptr to channel structure
3074 Byte_t Data; The transmit data byte
3075
3076Return: int: 1 if the bytes is successfully written, otherwise 0.
3077
3078Comments: The priority byte is transmitted before any data in the Tx FIFO.
3079
3080Warnings: No context switches are allowed while executing this function.
3081*/
f15313bf 3082static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
1da177e4
LT		 3083{
3084 Byte_t DWBuf[4]; /* buffer for double word writes */
3085 Word_t *WordPtr; /* must be far because Win SS != DS */
3086 register DWordIO_t IndexAddr;
3087
3088 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3089 IndexAddr = ChP->IndexAddr;
3090 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3091 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3092 return (0); /* nothing sent */
3093
3094 WordPtr = (Word_t *) (&DWBuf[0]);
3095 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3096
3097 DWBuf[2] = Data; /* data byte value */
457fb605 3098 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 3099
3100 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3101
3102 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3103 DWBuf[3] = 0; /* priority buffer pointer */
457fb605 3104 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 3105 } else { /* write it to Tx FIFO */
3106
3107 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3108 }
3109 return (1); /* 1 byte sent */
3110}
3111
3112/***************************************************************************
3113Function: sEnInterrupts
3114Purpose: Enable one or more interrupts for a channel
3115Call: sEnInterrupts(ChP,Flags)
3116 CHANNEL_T *ChP; Ptr to channel structure
3117 Word_t Flags: Interrupt enable flags, can be any combination
3118 of the following flags:
3119 TXINT_EN: Interrupt on Tx FIFO empty
3120 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3121 sSetRxTrigger())
3122 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3123 MCINT_EN: Interrupt on modem input change
3124 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3125 Interrupt Channel Register.
3126Return: void
3127Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3128 enabled. If an interrupt enable flag is not set in Flags, that
3129 interrupt will not be changed. Interrupts can be disabled with
3130 function sDisInterrupts().
3131
3132 This function sets the appropriate bit for the channel in the AIOP's
3133 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3134 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3135
3136 Interrupts must also be globally enabled before channel interrupts
3137 will be passed on to the host. This is done with function
3138 sEnGlobalInt().
3139
3140 In some cases it may be desirable to disable interrupts globally but
3141 enable channel interrupts. This would allow the global interrupt
3142 status register to be used to determine which AIOPs need service.
3143*/
f15313bf 3144static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3145{
3146 Byte_t Mask; /* Interrupt Mask Register */
3147
3148 ChP->RxControl[2] |=
3149 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3150
457fb605 3151 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 3152
3153 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3154
457fb605 3155 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3156
3157 if (Flags & CHANINT_EN) {
3158 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3159 sOutB(ChP->IntMask, Mask);
3160 }
3161}
3162
3163/***************************************************************************
3164Function: sDisInterrupts
3165Purpose: Disable one or more interrupts for a channel
3166Call: sDisInterrupts(ChP,Flags)
3167 CHANNEL_T *ChP; Ptr to channel structure
3168 Word_t Flags: Interrupt flags, can be any combination
3169 of the following flags:
3170 TXINT_EN: Interrupt on Tx FIFO empty
3171 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3172 sSetRxTrigger())
3173 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3174 MCINT_EN: Interrupt on modem input change
3175 CHANINT_EN: Disable channel interrupt signal to the
3176 AIOP's Interrupt Channel Register.
3177Return: void
3178Comments: If an interrupt flag is set in Flags, that interrupt will be
3179 disabled. If an interrupt flag is not set in Flags, that
3180 interrupt will not be changed. Interrupts can be enabled with
3181 function sEnInterrupts().
3182
3183 This function clears the appropriate bit for the channel in the AIOP's
3184 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3185 this channel's bit from being set in the AIOP's Interrupt Channel
3186 Register.
3187*/
f15313bf 3188static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3189{
3190 Byte_t Mask; /* Interrupt Mask Register */
3191
3192 ChP->RxControl[2] &=
3193 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
457fb605 3194 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4 3195 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
457fb605 3196 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3197
3198 if (Flags & CHANINT_EN) {
3199 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3200 sOutB(ChP->IntMask, Mask);
3201 }
3202}
3203
f15313bf 3204static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
1da177e4
LT		 3205{
3206 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3207}
3208
3209/*
3210 * Not an official SSCI function, but how to reset RocketModems.
3211 * ISA bus version
3212 */
f15313bf 3213static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3214{
3215 ByteIO_t addr;
3216 Byte_t val;
3217
3218 addr = CtlP->AiopIO[0] + 0x400;
3219 val = sInB(CtlP->MReg3IO);
3220 /* if AIOP[1] is not enabled, enable it */
3221 if ((val & 2) == 0) {
3222 val = sInB(CtlP->MReg2IO);
3223 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3224 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3225 }
3226
3227 sEnAiop(CtlP, 1);
3228 if (!on)
3229 addr += 8;
3230 sOutB(addr + chan, 0); /* apply or remove reset */
3231 sDisAiop(CtlP, 1);
3232}
3233
3234/*
3235 * Not an official SSCI function, but how to reset RocketModems.
3236 * PCI bus version
3237 */
f15313bf 3238static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3239{
3240 ByteIO_t addr;
3241
3242 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3243 if (!on)
3244 addr += 8;
3245 sOutB(addr + chan, 0); /* apply or remove reset */
3246}
3247
3248/* Resets the speaker controller on RocketModem II and III devices */
3249static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3250{
3251 ByteIO_t addr;
3252
3253 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3254 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3255 addr = CtlP->AiopIO[0] + 0x4F;
3256 sOutB(addr, 0);
3257 }
3258
3259 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3260 if ((model == MODEL_UPCI_RM3_8PORT)
3261 || (model == MODEL_UPCI_RM3_4PORT)) {
3262 addr = CtlP->AiopIO[0] + 0x88;
3263 sOutB(addr, 0);
3264 }
3265}
3266
3267/* Returns the line number given the controller (board), aiop and channel number */
3268static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3269{
3270 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3271}
3272
3273/*
3274 * Stores the line number associated with a given controller (board), aiop
3275 * and channel number.
3276 * Returns: The line number assigned
3277 */
3278static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3279{
3280 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3281 return (nextLineNumber - 1);
3282}
Empty description
This page took 0.856199 seconds and 4 git commands to generate.