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move die notifier handling to common code
[linux.git] / drivers / char / rocket.c
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1da177e4
LT		 1/*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42/****** Defines ******/
43#ifdef PCI_NUM_RESOURCES
44#define PCI_BASE_ADDRESS(dev, r) ((dev)->resource[r].start)
45#else
46#define PCI_BASE_ADDRESS(dev, r) ((dev)->base_address[r])
47#endif
48
49#define ROCKET_PARANOIA_CHECK
50#define ROCKET_DISABLE_SIMUSAGE
51
52#undef ROCKET_SOFT_FLOW
53#undef ROCKET_DEBUG_OPEN
54#undef ROCKET_DEBUG_INTR
55#undef ROCKET_DEBUG_WRITE
56#undef ROCKET_DEBUG_FLOW
57#undef ROCKET_DEBUG_THROTTLE
58#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
59#undef ROCKET_DEBUG_RECEIVE
60#undef ROCKET_DEBUG_HANGUP
61#undef REV_PCI_ORDER
62#undef ROCKET_DEBUG_IO
63
64#define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
65
66/****** Kernel includes ******/
67
1da177e4
LT		 68#include <linux/module.h>
69#include <linux/errno.h>
70#include <linux/major.h>
71#include <linux/kernel.h>
72#include <linux/signal.h>
73#include <linux/slab.h>
74#include <linux/mm.h>
75#include <linux/sched.h>
76#include <linux/timer.h>
77#include <linux/interrupt.h>
78#include <linux/tty.h>
79#include <linux/tty_driver.h>
80#include <linux/tty_flip.h>
81#include <linux/string.h>
82#include <linux/fcntl.h>
83#include <linux/ptrace.h>
84#include <linux/ioport.h>
85#include <linux/delay.h>
86#include <linux/wait.h>
87#include <linux/pci.h>
88#include <asm/uaccess.h>
89#include <asm/atomic.h>
90#include <linux/bitops.h>
91#include <linux/spinlock.h>
92#include <asm/semaphore.h>
93#include <linux/init.h>
94
95/****** RocketPort includes ******/
96
97#include "rocket_int.h"
98#include "rocket.h"
99
100#define ROCKET_VERSION "2.09"
101#define ROCKET_DATE "12-June-2003"
102
103/****** RocketPort Local Variables ******/
104
40565f19
JS		 105static void rp_do_poll(unsigned long dummy);
106
1da177e4
LT		 107static struct tty_driver *rocket_driver;
108
109static struct rocket_version driver_version = {
110 ROCKET_VERSION, ROCKET_DATE
111};
112
113static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
114static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
115 /* eg. Bit 0 indicates port 0 has xmit data, ... */
116static atomic_t rp_num_ports_open; /* Number of serial ports open */
40565f19 117static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
1da177e4
LT		 118
119static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
120static unsigned long board2;
121static unsigned long board3;
122static unsigned long board4;
123static unsigned long controller;
124static int support_low_speed;
125static unsigned long modem1;
126static unsigned long modem2;
127static unsigned long modem3;
128static unsigned long modem4;
129static unsigned long pc104_1[8];
130static unsigned long pc104_2[8];
131static unsigned long pc104_3[8];
132static unsigned long pc104_4[8];
133static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
134
135static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
136static unsigned long rcktpt_io_addr[NUM_BOARDS];
137static int rcktpt_type[NUM_BOARDS];
138static int is_PCI[NUM_BOARDS];
139static rocketModel_t rocketModel[NUM_BOARDS];
140static int max_board;
141
142/*
143 * The following arrays define the interrupt bits corresponding to each AIOP.
144 * These bits are different between the ISA and regular PCI boards and the
145 * Universal PCI boards.
146 */
147
148static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
149 AIOP_INTR_BIT_0,
150 AIOP_INTR_BIT_1,
151 AIOP_INTR_BIT_2,
152 AIOP_INTR_BIT_3
153};
154
155static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
156 UPCI_AIOP_INTR_BIT_0,
157 UPCI_AIOP_INTR_BIT_1,
158 UPCI_AIOP_INTR_BIT_2,
159 UPCI_AIOP_INTR_BIT_3
160};
161
f15313bf
AB		 162static Byte_t RData[RDATASIZE] = {
163 0x00, 0x09, 0xf6, 0x82,
164 0x02, 0x09, 0x86, 0xfb,
165 0x04, 0x09, 0x00, 0x0a,
166 0x06, 0x09, 0x01, 0x0a,
167 0x08, 0x09, 0x8a, 0x13,
168 0x0a, 0x09, 0xc5, 0x11,
169 0x0c, 0x09, 0x86, 0x85,
170 0x0e, 0x09, 0x20, 0x0a,
171 0x10, 0x09, 0x21, 0x0a,
172 0x12, 0x09, 0x41, 0xff,
173 0x14, 0x09, 0x82, 0x00,
174 0x16, 0x09, 0x82, 0x7b,
175 0x18, 0x09, 0x8a, 0x7d,
176 0x1a, 0x09, 0x88, 0x81,
177 0x1c, 0x09, 0x86, 0x7a,
178 0x1e, 0x09, 0x84, 0x81,
179 0x20, 0x09, 0x82, 0x7c,
180 0x22, 0x09, 0x0a, 0x0a
181};
182
183static Byte_t RRegData[RREGDATASIZE] = {
184 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
185 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
186 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
187 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
188 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
189 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
190 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
191 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
192 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
193 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
194 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
195 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
196 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
197};
198
199static CONTROLLER_T sController[CTL_SIZE] = {
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208};
209
210static Byte_t sBitMapClrTbl[8] = {
211 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212};
213
214static Byte_t sBitMapSetTbl[8] = {
215 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216};
217
218static int sClockPrescale = 0x14;
219
1da177e4
LT		 220/*
221 * Line number is the ttySIx number (x), the Minor number. We
222 * assign them sequentially, starting at zero. The following
223 * array keeps track of the line number assigned to a given board/aiop/channel.
224 */
225static unsigned char lineNumbers[MAX_RP_PORTS];
226static unsigned long nextLineNumber;
227
228/***** RocketPort Static Prototypes *********/
229static int __init init_ISA(int i);
230static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
231static void rp_flush_buffer(struct tty_struct *tty);
232static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
233static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
234static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
235static void rp_start(struct tty_struct *tty);
f15313bf
AB		 236static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
237 int ChanNum);
238static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
239static void sFlushRxFIFO(CHANNEL_T * ChP);
240static void sFlushTxFIFO(CHANNEL_T * ChP);
241static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
242static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
243static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
244static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
245static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
246static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
247 ByteIO_t * AiopIOList, int AiopIOListSize,
248 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
249 int PeriodicOnly, int altChanRingIndicator,
250 int UPCIRingInd);
251static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
252 ByteIO_t * AiopIOList, int AiopIOListSize,
253 int IRQNum, Byte_t Frequency, int PeriodicOnly);
254static int sReadAiopID(ByteIO_t io);
255static int sReadAiopNumChan(WordIO_t io);
1da177e4 256
1da177e4
LT		 257MODULE_AUTHOR("Theodore Ts'o");
258MODULE_DESCRIPTION("Comtrol RocketPort driver");
259module_param(board1, ulong, 0);
260MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
261module_param(board2, ulong, 0);
262MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
263module_param(board3, ulong, 0);
264MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
265module_param(board4, ulong, 0);
266MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
267module_param(controller, ulong, 0);
268MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
269module_param(support_low_speed, bool, 0);
270MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
271module_param(modem1, ulong, 0);
272MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
273module_param(modem2, ulong, 0);
274MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
275module_param(modem3, ulong, 0);
276MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
277module_param(modem4, ulong, 0);
278MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
279module_param_array(pc104_1, ulong, NULL, 0);
280MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
281module_param_array(pc104_2, ulong, NULL, 0);
282MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
283module_param_array(pc104_3, ulong, NULL, 0);
284MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
285module_param_array(pc104_4, ulong, NULL, 0);
286MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
287
d269cdd0 288static int rp_init(void);
1da177e4
LT		 289static void rp_cleanup_module(void);
290
291module_init(rp_init);
292module_exit(rp_cleanup_module);
293
1da177e4 294
1da177e4 295MODULE_LICENSE("Dual BSD/GPL");
1da177e4
LT		 296
297/*************************************************************************/
298/* Module code starts here */
299
300static inline int rocket_paranoia_check(struct r_port *info,
301 const char *routine)
302{
303#ifdef ROCKET_PARANOIA_CHECK
304 if (!info)
305 return 1;
306 if (info->magic != RPORT_MAGIC) {
307 printk(KERN_INFO "Warning: bad magic number for rocketport struct in %s\n",
308 routine);
309 return 1;
310 }
311#endif
312 return 0;
313}
314
315
316/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
317 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
318 * tty layer.
319 */
320static void rp_do_receive(struct r_port *info,
321 struct tty_struct *tty,
322 CHANNEL_t * cp, unsigned int ChanStatus)
323{
324 unsigned int CharNStat;
cc44a817
PF		 325 int ToRecv, wRecv, space;
326 unsigned char *cbuf;
1da177e4
LT		 327
328 ToRecv = sGetRxCnt(cp);
1da177e4 329#ifdef ROCKET_DEBUG_INTR
cc44a817 330 printk(KERN_INFO "rp_do_receive(%d)...", ToRecv);
1da177e4 331#endif
cc44a817
PF		 332 if (ToRecv == 0)
333 return;
33f0f88f 334
1da177e4
LT		 335 /*
336 * if status indicates there are errored characters in the
337 * FIFO, then enter status mode (a word in FIFO holds
338 * character and status).
339 */
340 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
341 if (!(ChanStatus & STATMODE)) {
342#ifdef ROCKET_DEBUG_RECEIVE
343 printk(KERN_INFO "Entering STATMODE...");
344#endif
345 ChanStatus |= STATMODE;
346 sEnRxStatusMode(cp);
347 }
348 }
349
350 /*
351 * if we previously entered status mode, then read down the
352 * FIFO one word at a time, pulling apart the character and
353 * the status. Update error counters depending on status
354 */
355 if (ChanStatus & STATMODE) {
356#ifdef ROCKET_DEBUG_RECEIVE
357 printk(KERN_INFO "Ignore %x, read %x...", info->ignore_status_mask,
358 info->read_status_mask);
359#endif
360 while (ToRecv) {
cc44a817
PF		 361 char flag;
362
1da177e4
LT		 363 CharNStat = sInW(sGetTxRxDataIO(cp));
364#ifdef ROCKET_DEBUG_RECEIVE
365 printk(KERN_INFO "%x...", CharNStat);
366#endif
367 if (CharNStat & STMBREAKH)
368 CharNStat &= ~(STMFRAMEH | STMPARITYH);
369 if (CharNStat & info->ignore_status_mask) {
370 ToRecv--;
371 continue;
372 }
373 CharNStat &= info->read_status_mask;
374 if (CharNStat & STMBREAKH)
cc44a817 375 flag = TTY_BREAK;
1da177e4 376 else if (CharNStat & STMPARITYH)
cc44a817 377 flag = TTY_PARITY;
1da177e4 378 else if (CharNStat & STMFRAMEH)
cc44a817 379 flag = TTY_FRAME;
1da177e4 380 else if (CharNStat & STMRCVROVRH)
cc44a817 381 flag = TTY_OVERRUN;
1da177e4 382 else
cc44a817
PF		 383 flag = TTY_NORMAL;
384 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
1da177e4
LT		 385 ToRecv--;
386 }
387
388 /*
389 * after we've emptied the FIFO in status mode, turn
390 * status mode back off
391 */
392 if (sGetRxCnt(cp) == 0) {
393#ifdef ROCKET_DEBUG_RECEIVE
394 printk(KERN_INFO "Status mode off.\n");
395#endif
396 sDisRxStatusMode(cp);
397 }
398 } else {
399 /*
400 * we aren't in status mode, so read down the FIFO two
401 * characters at time by doing repeated word IO
402 * transfer.
403 */
cc44a817
PF		 404 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
405 if (space < ToRecv) {
406#ifdef ROCKET_DEBUG_RECEIVE
407 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
408#endif
409 if (space <= 0)
410 return;
411 ToRecv = space;
412 }
1da177e4
LT		 413 wRecv = ToRecv >> 1;
414 if (wRecv)
415 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
416 if (ToRecv & 1)
417 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
1da177e4
LT		 418 }
419 /* Push the data up to the tty layer */
cc44a817 420 tty_flip_buffer_push(tty);
1da177e4
LT		 421}
422
423/*
424 * Serial port transmit data function. Called from the timer polling loop as a
425 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
426 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
427 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
428 */
429static void rp_do_transmit(struct r_port *info)
430{
431 int c;
432 CHANNEL_t *cp = &info->channel;
433 struct tty_struct *tty;
434 unsigned long flags;
435
436#ifdef ROCKET_DEBUG_INTR
437 printk(KERN_INFO "rp_do_transmit ");
438#endif
439 if (!info)
440 return;
441 if (!info->tty) {
442 printk(KERN_INFO "rp: WARNING rp_do_transmit called with info->tty==NULL\n");
443 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
444 return;
445 }
446
447 spin_lock_irqsave(&info->slock, flags);
448 tty = info->tty;
449 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
450
451 /* Loop sending data to FIFO until done or FIFO full */
452 while (1) {
453 if (tty->stopped || tty->hw_stopped)
454 break;
455 c = min(info->xmit_fifo_room, min(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
456 if (c <= 0 || info->xmit_fifo_room <= 0)
457 break;
458 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
459 if (c & 1)
460 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
461 info->xmit_tail += c;
462 info->xmit_tail &= XMIT_BUF_SIZE - 1;
463 info->xmit_cnt -= c;
464 info->xmit_fifo_room -= c;
465#ifdef ROCKET_DEBUG_INTR
466 printk(KERN_INFO "tx %d chars...", c);
467#endif
468 }
469
470 if (info->xmit_cnt == 0)
471 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
472
473 if (info->xmit_cnt < WAKEUP_CHARS) {
474 tty_wakeup(tty);
1da177e4
LT		 475#ifdef ROCKETPORT_HAVE_POLL_WAIT
476 wake_up_interruptible(&tty->poll_wait);
477#endif
478 }
479
480 spin_unlock_irqrestore(&info->slock, flags);
481
482#ifdef ROCKET_DEBUG_INTR
483 printk(KERN_INFO "(%d,%d,%d,%d)...", info->xmit_cnt, info->xmit_head,
484 info->xmit_tail, info->xmit_fifo_room);
485#endif
486}
487
488/*
489 * Called when a serial port signals it has read data in it's RX FIFO.
490 * It checks what interrupts are pending and services them, including
491 * receiving serial data.
492 */
493static void rp_handle_port(struct r_port *info)
494{
495 CHANNEL_t *cp;
496 struct tty_struct *tty;
497 unsigned int IntMask, ChanStatus;
498
499 if (!info)
500 return;
501
502 if ((info->flags & ROCKET_INITIALIZED) == 0) {
503 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->flags & NOT_INIT\n");
504 return;
505 }
506 if (!info->tty) {
507 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->tty==NULL\n");
508 return;
509 }
510 cp = &info->channel;
511 tty = info->tty;
512
513 IntMask = sGetChanIntID(cp) & info->intmask;
514#ifdef ROCKET_DEBUG_INTR
515 printk(KERN_INFO "rp_interrupt %02x...", IntMask);
516#endif
517 ChanStatus = sGetChanStatus(cp);
518 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
519 rp_do_receive(info, tty, cp, ChanStatus);
520 }
521 if (IntMask & DELTA_CD) { /* CD change */
522#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
523 printk(KERN_INFO "ttyR%d CD now %s...", info->line,
524 (ChanStatus & CD_ACT) ? "on" : "off");
525#endif
526 if (!(ChanStatus & CD_ACT) && info->cd_status) {
527#ifdef ROCKET_DEBUG_HANGUP
528 printk(KERN_INFO "CD drop, calling hangup.\n");
529#endif
530 tty_hangup(tty);
531 }
532 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
533 wake_up_interruptible(&info->open_wait);
534 }
535#ifdef ROCKET_DEBUG_INTR
536 if (IntMask & DELTA_CTS) { /* CTS change */
537 printk(KERN_INFO "CTS change...\n");
538 }
539 if (IntMask & DELTA_DSR) { /* DSR change */
540 printk(KERN_INFO "DSR change...\n");
541 }
542#endif
543}
544
545/*
546 * The top level polling routine. Repeats every 1/100 HZ (10ms).
547 */
548static void rp_do_poll(unsigned long dummy)
549{
550 CONTROLLER_t *ctlp;
551 int ctrl, aiop, ch, line, i;
552 unsigned int xmitmask;
553 unsigned int CtlMask;
554 unsigned char AiopMask;
555 Word_t bit;
556
557 /* Walk through all the boards (ctrl's) */
558 for (ctrl = 0; ctrl < max_board; ctrl++) {
559 if (rcktpt_io_addr[ctrl] <= 0)
560 continue;
561
562 /* Get a ptr to the board's control struct */
563 ctlp = sCtlNumToCtlPtr(ctrl);
564
565 /* Get the interupt status from the board */
566#ifdef CONFIG_PCI
567 if (ctlp->BusType == isPCI)
568 CtlMask = sPCIGetControllerIntStatus(ctlp);
569 else
570#endif
571 CtlMask = sGetControllerIntStatus(ctlp);
572
573 /* Check if any AIOP read bits are set */
574 for (aiop = 0; CtlMask; aiop++) {
575 bit = ctlp->AiopIntrBits[aiop];
576 if (CtlMask & bit) {
577 CtlMask &= ~bit;
578 AiopMask = sGetAiopIntStatus(ctlp, aiop);
579
580 /* Check if any port read bits are set */
581 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
582 if (AiopMask & 1) {
583
584 /* Get the line number (/dev/ttyRx number). */
585 /* Read the data from the port. */
586 line = GetLineNumber(ctrl, aiop, ch);
587 rp_handle_port(rp_table[line]);
588 }
589 }
590 }
591 }
592
593 xmitmask = xmit_flags[ctrl];
594
595 /*
596 * xmit_flags contains bit-significant flags, indicating there is data
597 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
598 * 1, ... (32 total possible). The variable i has the aiop and ch
599 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
600 */
601 if (xmitmask) {
602 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
603 if (xmitmask & (1 << i)) {
604 aiop = (i & 0x18) >> 3;
605 ch = i & 0x07;
606 line = GetLineNumber(ctrl, aiop, ch);
607 rp_do_transmit(rp_table[line]);
608 }
609 }
610 }
611 }
612
613 /*
614 * Reset the timer so we get called at the next clock tick (10ms).
615 */
616 if (atomic_read(&rp_num_ports_open))
617 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
618}
619
620/*
621 * Initializes the r_port structure for a port, as well as enabling the port on
622 * the board.
623 * Inputs: board, aiop, chan numbers
624 */
625static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
626{
627 unsigned rocketMode;
628 struct r_port *info;
629 int line;
630 CONTROLLER_T *ctlp;
631
632 /* Get the next available line number */
633 line = SetLineNumber(board, aiop, chan);
634
635 ctlp = sCtlNumToCtlPtr(board);
636
637 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
638 info = kmalloc(sizeof (struct r_port), GFP_KERNEL);
639 if (!info) {
640 printk(KERN_INFO "Couldn't allocate info struct for line #%d\n", line);
641 return;
642 }
643 memset(info, 0, sizeof (struct r_port));
644
645 info->magic = RPORT_MAGIC;
646 info->line = line;
647 info->ctlp = ctlp;
648 info->board = board;
649 info->aiop = aiop;
650 info->chan = chan;
651 info->closing_wait = 3000;
652 info->close_delay = 50;
653 init_waitqueue_head(&info->open_wait);
654 init_waitqueue_head(&info->close_wait);
655 info->flags &= ~ROCKET_MODE_MASK;
656 switch (pc104[board][line]) {
657 case 422:
658 info->flags |= ROCKET_MODE_RS422;
659 break;
660 case 485:
661 info->flags |= ROCKET_MODE_RS485;
662 break;
663 case 232:
664 default:
665 info->flags |= ROCKET_MODE_RS232;
666 break;
667 }
668
669 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
670 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
671 printk(KERN_INFO "RocketPort sInitChan(%d, %d, %d) failed!\n", board, aiop, chan);
672 kfree(info);
673 return;
674 }
675
676 rocketMode = info->flags & ROCKET_MODE_MASK;
677
678 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
679 sEnRTSToggle(&info->channel);
680 else
681 sDisRTSToggle(&info->channel);
682
683 if (ctlp->boardType == ROCKET_TYPE_PC104) {
684 switch (rocketMode) {
685 case ROCKET_MODE_RS485:
686 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
687 break;
688 case ROCKET_MODE_RS422:
689 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
690 break;
691 case ROCKET_MODE_RS232:
692 default:
693 if (info->flags & ROCKET_RTS_TOGGLE)
694 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
695 else
696 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
697 break;
698 }
699 }
700 spin_lock_init(&info->slock);
701 sema_init(&info->write_sem, 1);
702 rp_table[line] = info;
703 if (pci_dev)
704 tty_register_device(rocket_driver, line, &pci_dev->dev);
705}
706
707/*
708 * Configures a rocketport port according to its termio settings. Called from
709 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
710 */
711static void configure_r_port(struct r_port *info,
606d099c 712 struct ktermios *old_termios)
1da177e4
LT		 713{
714 unsigned cflag;
715 unsigned long flags;
716 unsigned rocketMode;
717 int bits, baud, divisor;
718 CHANNEL_t *cp;
719
720 if (!info->tty || !info->tty->termios)
721 return;
722 cp = &info->channel;
723 cflag = info->tty->termios->c_cflag;
724
725 /* Byte size and parity */
726 if ((cflag & CSIZE) == CS8) {
727 sSetData8(cp);
728 bits = 10;
729 } else {
730 sSetData7(cp);
731 bits = 9;
732 }
733 if (cflag & CSTOPB) {
734 sSetStop2(cp);
735 bits++;
736 } else {
737 sSetStop1(cp);
738 }
739
740 if (cflag & PARENB) {
741 sEnParity(cp);
742 bits++;
743 if (cflag & PARODD) {
744 sSetOddParity(cp);
745 } else {
746 sSetEvenParity(cp);
747 }
748 } else {
749 sDisParity(cp);
750 }
751
752 /* baud rate */
753 baud = tty_get_baud_rate(info->tty);
754 if (!baud)
755 baud = 9600;
756 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
757 if ((divisor >= 8192 || divisor < 0) && old_termios) {
758 info->tty->termios->c_cflag &= ~CBAUD;
759 info->tty->termios->c_cflag |=
760 (old_termios->c_cflag & CBAUD);
761 baud = tty_get_baud_rate(info->tty);
762 if (!baud)
763 baud = 9600;
764 divisor = (rp_baud_base[info->board] / baud) - 1;
765 }
766 if (divisor >= 8192 || divisor < 0) {
767 baud = 9600;
768 divisor = (rp_baud_base[info->board] / baud) - 1;
769 }
770 info->cps = baud / bits;
771 sSetBaud(cp, divisor);
772
773 if (cflag & CRTSCTS) {
774 info->intmask |= DELTA_CTS;
775 sEnCTSFlowCtl(cp);
776 } else {
777 info->intmask &= ~DELTA_CTS;
778 sDisCTSFlowCtl(cp);
779 }
780 if (cflag & CLOCAL) {
781 info->intmask &= ~DELTA_CD;
782 } else {
783 spin_lock_irqsave(&info->slock, flags);
784 if (sGetChanStatus(cp) & CD_ACT)
785 info->cd_status = 1;
786 else
787 info->cd_status = 0;
788 info->intmask |= DELTA_CD;
789 spin_unlock_irqrestore(&info->slock, flags);
790 }
791
792 /*
793 * Handle software flow control in the board
794 */
795#ifdef ROCKET_SOFT_FLOW
796 if (I_IXON(info->tty)) {
797 sEnTxSoftFlowCtl(cp);
798 if (I_IXANY(info->tty)) {
799 sEnIXANY(cp);
800 } else {
801 sDisIXANY(cp);
802 }
803 sSetTxXONChar(cp, START_CHAR(info->tty));
804 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
805 } else {
806 sDisTxSoftFlowCtl(cp);
807 sDisIXANY(cp);
808 sClrTxXOFF(cp);
809 }
810#endif
811
812 /*
813 * Set up ignore/read mask words
814 */
815 info->read_status_mask = STMRCVROVRH | 0xFF;
816 if (I_INPCK(info->tty))
817 info->read_status_mask |= STMFRAMEH | STMPARITYH;
818 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
819 info->read_status_mask |= STMBREAKH;
820
821 /*
822 * Characters to ignore
823 */
824 info->ignore_status_mask = 0;
825 if (I_IGNPAR(info->tty))
826 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
827 if (I_IGNBRK(info->tty)) {
828 info->ignore_status_mask |= STMBREAKH;
829 /*
830 * If we're ignoring parity and break indicators,
831 * ignore overruns too. (For real raw support).
832 */
833 if (I_IGNPAR(info->tty))
834 info->ignore_status_mask |= STMRCVROVRH;
835 }
836
837 rocketMode = info->flags & ROCKET_MODE_MASK;
838
839 if ((info->flags & ROCKET_RTS_TOGGLE)
840 || (rocketMode == ROCKET_MODE_RS485))
841 sEnRTSToggle(cp);
842 else
843 sDisRTSToggle(cp);
844
845 sSetRTS(&info->channel);
846
847 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
848 switch (rocketMode) {
849 case ROCKET_MODE_RS485:
850 sSetInterfaceMode(cp, InterfaceModeRS485);
851 break;
852 case ROCKET_MODE_RS422:
853 sSetInterfaceMode(cp, InterfaceModeRS422);
854 break;
855 case ROCKET_MODE_RS232:
856 default:
857 if (info->flags & ROCKET_RTS_TOGGLE)
858 sSetInterfaceMode(cp, InterfaceModeRS232T);
859 else
860 sSetInterfaceMode(cp, InterfaceModeRS232);
861 break;
862 }
863 }
864}
865
866/* info->count is considered critical, protected by spinlocks. */
867static int block_til_ready(struct tty_struct *tty, struct file *filp,
868 struct r_port *info)
869{
870 DECLARE_WAITQUEUE(wait, current);
871 int retval;
872 int do_clocal = 0, extra_count = 0;
873 unsigned long flags;
874
875 /*
876 * If the device is in the middle of being closed, then block
877 * until it's done, and then try again.
878 */
879 if (tty_hung_up_p(filp))
880 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
881 if (info->flags & ROCKET_CLOSING) {
882 interruptible_sleep_on(&info->close_wait);
883 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
884 }
885
886 /*
887 * If non-blocking mode is set, or the port is not enabled,
888 * then make the check up front and then exit.
889 */
890 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
891 info->flags |= ROCKET_NORMAL_ACTIVE;
892 return 0;
893 }
894 if (tty->termios->c_cflag & CLOCAL)
895 do_clocal = 1;
896
897 /*
898 * Block waiting for the carrier detect and the line to become free. While we are in
899 * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
900 * We restore it upon exit, either normal or abnormal.
901 */
902 retval = 0;
903 add_wait_queue(&info->open_wait, &wait);
904#ifdef ROCKET_DEBUG_OPEN
905 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
906#endif
907 spin_lock_irqsave(&info->slock, flags);
908
909#ifdef ROCKET_DISABLE_SIMUSAGE
910 info->flags |= ROCKET_NORMAL_ACTIVE;
911#else
912 if (!tty_hung_up_p(filp)) {
913 extra_count = 1;
914 info->count--;
915 }
916#endif
917 info->blocked_open++;
918
919 spin_unlock_irqrestore(&info->slock, flags);
920
921 while (1) {
922 if (tty->termios->c_cflag & CBAUD) {
923 sSetDTR(&info->channel);
924 sSetRTS(&info->channel);
925 }
926 set_current_state(TASK_INTERRUPTIBLE);
927 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
928 if (info->flags & ROCKET_HUP_NOTIFY)
929 retval = -EAGAIN;
930 else
931 retval = -ERESTARTSYS;
932 break;
933 }
934 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
935 break;
936 if (signal_pending(current)) {
937 retval = -ERESTARTSYS;
938 break;
939 }
940#ifdef ROCKET_DEBUG_OPEN
941 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
942 info->line, info->count, info->flags);
943#endif
944 schedule(); /* Don't hold spinlock here, will hang PC */
945 }
946 current->state = TASK_RUNNING;
947 remove_wait_queue(&info->open_wait, &wait);
948
949 spin_lock_irqsave(&info->slock, flags);
950
951 if (extra_count)
952 info->count++;
953 info->blocked_open--;
954
955 spin_unlock_irqrestore(&info->slock, flags);
956
957#ifdef ROCKET_DEBUG_OPEN
958 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
959 info->line, info->count);
960#endif
961 if (retval)
962 return retval;
963 info->flags |= ROCKET_NORMAL_ACTIVE;
964 return 0;
965}
966
967/*
968 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
969 * port's r_port struct. Initializes the port hardware.
970 */
971static int rp_open(struct tty_struct *tty, struct file *filp)
972{
973 struct r_port *info;
974 int line = 0, retval;
975 CHANNEL_t *cp;
976 unsigned long page;
977
978 line = TTY_GET_LINE(tty);
979 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
980 return -ENXIO;
981
982 page = __get_free_page(GFP_KERNEL);
983 if (!page)
984 return -ENOMEM;
985
986 if (info->flags & ROCKET_CLOSING) {
987 interruptible_sleep_on(&info->close_wait);
988 free_page(page);
989 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
990 }
991
992 /*
993 * We must not sleep from here until the port is marked fully in use.
994 */
995 if (info->xmit_buf)
996 free_page(page);
997 else
998 info->xmit_buf = (unsigned char *) page;
999
1000 tty->driver_data = info;
1001 info->tty = tty;
1002
1003 if (info->count++ == 0) {
1004 atomic_inc(&rp_num_ports_open);
1005
1006#ifdef ROCKET_DEBUG_OPEN
1007 printk(KERN_INFO "rocket mod++ = %d...", atomic_read(&rp_num_ports_open));
1008#endif
1009 }
1010#ifdef ROCKET_DEBUG_OPEN
1011 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
1012#endif
1013
1014 /*
1015 * Info->count is now 1; so it's safe to sleep now.
1016 */
937949d9 1017 info->session = process_session(current);
1da177e4
LT		 1018 info->pgrp = process_group(current);
1019
1020 if ((info->flags & ROCKET_INITIALIZED) == 0) {
1021 cp = &info->channel;
1022 sSetRxTrigger(cp, TRIG_1);
1023 if (sGetChanStatus(cp) & CD_ACT)
1024 info->cd_status = 1;
1025 else
1026 info->cd_status = 0;
1027 sDisRxStatusMode(cp);
1028 sFlushRxFIFO(cp);
1029 sFlushTxFIFO(cp);
1030
1031 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1032 sSetRxTrigger(cp, TRIG_1);
1033
1034 sGetChanStatus(cp);
1035 sDisRxStatusMode(cp);
1036 sClrTxXOFF(cp);
1037
1038 sDisCTSFlowCtl(cp);
1039 sDisTxSoftFlowCtl(cp);
1040
1041 sEnRxFIFO(cp);
1042 sEnTransmit(cp);
1043
1044 info->flags |= ROCKET_INITIALIZED;
1045
1046 /*
1047 * Set up the tty->alt_speed kludge
1048 */
1049 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1050 info->tty->alt_speed = 57600;
1051 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1052 info->tty->alt_speed = 115200;
1053 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1054 info->tty->alt_speed = 230400;
1055 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1056 info->tty->alt_speed = 460800;
1057
1058 configure_r_port(info, NULL);
1059 if (tty->termios->c_cflag & CBAUD) {
1060 sSetDTR(cp);
1061 sSetRTS(cp);
1062 }
1063 }
1064 /* Starts (or resets) the maint polling loop */
1065 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1066
1067 retval = block_til_ready(tty, filp, info);
1068 if (retval) {
1069#ifdef ROCKET_DEBUG_OPEN
1070 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1071#endif
1072 return retval;
1073 }
1074 return 0;
1075}
1076
1077/*
1078 * Exception handler that closes a serial port. info->count is considered critical.
1079 */
1080static void rp_close(struct tty_struct *tty, struct file *filp)
1081{
1082 struct r_port *info = (struct r_port *) tty->driver_data;
1083 unsigned long flags;
1084 int timeout;
1085 CHANNEL_t *cp;
1086
1087 if (rocket_paranoia_check(info, "rp_close"))
1088 return;
1089
1090#ifdef ROCKET_DEBUG_OPEN
1091 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1092#endif
1093
1094 if (tty_hung_up_p(filp))
1095 return;
1096 spin_lock_irqsave(&info->slock, flags);
1097
1098 if ((tty->count == 1) && (info->count != 1)) {
1099 /*
1100 * Uh, oh. tty->count is 1, which means that the tty
1101 * structure will be freed. Info->count should always
1102 * be one in these conditions. If it's greater than
1103 * one, we've got real problems, since it means the
1104 * serial port won't be shutdown.
1105 */
1106 printk(KERN_INFO "rp_close: bad serial port count; tty->count is 1, "
1107 "info->count is %d\n", info->count);
1108 info->count = 1;
1109 }
1110 if (--info->count < 0) {
1111 printk(KERN_INFO "rp_close: bad serial port count for ttyR%d: %d\n",
1112 info->line, info->count);
1113 info->count = 0;
1114 }
1115 if (info->count) {
1116 spin_unlock_irqrestore(&info->slock, flags);
1117 return;
1118 }
1119 info->flags |= ROCKET_CLOSING;
1120 spin_unlock_irqrestore(&info->slock, flags);
1121
1122 cp = &info->channel;
1123
1124 /*
1125 * Notify the line discpline to only process XON/XOFF characters
1126 */
1127 tty->closing = 1;
1128
1129 /*
1130 * If transmission was throttled by the application request,
1131 * just flush the xmit buffer.
1132 */
1133 if (tty->flow_stopped)
1134 rp_flush_buffer(tty);
1135
1136 /*
1137 * Wait for the transmit buffer to clear
1138 */
1139 if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1140 tty_wait_until_sent(tty, info->closing_wait);
1141 /*
1142 * Before we drop DTR, make sure the UART transmitter
1143 * has completely drained; this is especially
1144 * important if there is a transmit FIFO!
1145 */
1146 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1147 if (timeout == 0)
1148 timeout = 1;
1149 rp_wait_until_sent(tty, timeout);
1150 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1151
1152 sDisTransmit(cp);
1153 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1154 sDisCTSFlowCtl(cp);
1155 sDisTxSoftFlowCtl(cp);
1156 sClrTxXOFF(cp);
1157 sFlushRxFIFO(cp);
1158 sFlushTxFIFO(cp);
1159 sClrRTS(cp);
1160 if (C_HUPCL(tty))
1161 sClrDTR(cp);
1162
1163 if (TTY_DRIVER_FLUSH_BUFFER_EXISTS(tty))
1164 TTY_DRIVER_FLUSH_BUFFER(tty);
1165
1166 tty_ldisc_flush(tty);
1167
1168 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1169
1170 if (info->blocked_open) {
1171 if (info->close_delay) {
1172 msleep_interruptible(jiffies_to_msecs(info->close_delay));
1173 }
1174 wake_up_interruptible(&info->open_wait);
1175 } else {
1176 if (info->xmit_buf) {
1177 free_page((unsigned long) info->xmit_buf);
1178 info->xmit_buf = NULL;
1179 }
1180 }
1181 info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1182 tty->closing = 0;
1183 wake_up_interruptible(&info->close_wait);
1184 atomic_dec(&rp_num_ports_open);
1185
1186#ifdef ROCKET_DEBUG_OPEN
1187 printk(KERN_INFO "rocket mod-- = %d...", atomic_read(&rp_num_ports_open));
1188 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1189#endif
1190
1191}
1192
1193static void rp_set_termios(struct tty_struct *tty,
606d099c 1194 struct ktermios *old_termios)
1da177e4
LT		 1195{
1196 struct r_port *info = (struct r_port *) tty->driver_data;
1197 CHANNEL_t *cp;
1198 unsigned cflag;
1199
1200 if (rocket_paranoia_check(info, "rp_set_termios"))
1201 return;
1202
1203 cflag = tty->termios->c_cflag;
1204
1205 if (cflag == old_termios->c_cflag)
1206 return;
1207
1208 /*
1209 * This driver doesn't support CS5 or CS6
1210 */
1211 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1212 tty->termios->c_cflag =
1213 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1214
1215 configure_r_port(info, old_termios);
1216
1217 cp = &info->channel;
1218
1219 /* Handle transition to B0 status */
1220 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1221 sClrDTR(cp);
1222 sClrRTS(cp);
1223 }
1224
1225 /* Handle transition away from B0 status */
1226 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1227 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1228 sSetRTS(cp);
1229 sSetDTR(cp);
1230 }
1231
1232 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1233 tty->hw_stopped = 0;
1234 rp_start(tty);
1235 }
1236}
1237
1238static void rp_break(struct tty_struct *tty, int break_state)
1239{
1240 struct r_port *info = (struct r_port *) tty->driver_data;
1241 unsigned long flags;
1242
1243 if (rocket_paranoia_check(info, "rp_break"))
1244 return;
1245
1246 spin_lock_irqsave(&info->slock, flags);
1247 if (break_state == -1)
1248 sSendBreak(&info->channel);
1249 else
1250 sClrBreak(&info->channel);
1251 spin_unlock_irqrestore(&info->slock, flags);
1252}
1253
1254/*
1255 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1256 * the UPCI boards was added, it was decided to make this a function because
1257 * the macro was getting too complicated. All cases except the first one
1258 * (UPCIRingInd) are taken directly from the original macro.
1259 */
1260static int sGetChanRI(CHANNEL_T * ChP)
1261{
1262 CONTROLLER_t *CtlP = ChP->CtlP;
1263 int ChanNum = ChP->ChanNum;
1264 int RingInd = 0;
1265
1266 if (CtlP->UPCIRingInd)
1267 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1268 else if (CtlP->AltChanRingIndicator)
1269 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1270 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1271 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1272
1273 return RingInd;
1274}
1275
1276/********************************************************************************************/
1277/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1278
1279/*
1280 * Returns the state of the serial modem control lines. These next 2 functions
1281 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1282 */
1283static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1284{
1285 struct r_port *info = (struct r_port *)tty->driver_data;
1286 unsigned int control, result, ChanStatus;
1287
1288 ChanStatus = sGetChanStatusLo(&info->channel);
1289 control = info->channel.TxControl[3];
1290 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1291 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1292 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1293 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1294 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1295 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1296
1297 return result;
1298}
1299
1300/*
1301 * Sets the modem control lines
1302 */
1303static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1304 unsigned int set, unsigned int clear)
1305{
1306 struct r_port *info = (struct r_port *)tty->driver_data;
1307
1308 if (set & TIOCM_RTS)
1309 info->channel.TxControl[3] |= SET_RTS;
1310 if (set & TIOCM_DTR)
1311 info->channel.TxControl[3] |= SET_DTR;
1312 if (clear & TIOCM_RTS)
1313 info->channel.TxControl[3] &= ~SET_RTS;
1314 if (clear & TIOCM_DTR)
1315 info->channel.TxControl[3] &= ~SET_DTR;
1316
1317 sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0]));
1318 return 0;
1319}
1320
1321static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1322{
1323 struct rocket_config tmp;
1324
1325 if (!retinfo)
1326 return -EFAULT;
1327 memset(&tmp, 0, sizeof (tmp));
1328 tmp.line = info->line;
1329 tmp.flags = info->flags;
1330 tmp.close_delay = info->close_delay;
1331 tmp.closing_wait = info->closing_wait;
1332 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1333
1334 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1335 return -EFAULT;
1336 return 0;
1337}
1338
1339static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1340{
1341 struct rocket_config new_serial;
1342
1343 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1344 return -EFAULT;
1345
1346 if (!capable(CAP_SYS_ADMIN))
1347 {
1348 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1349 return -EPERM;
1350 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1351 configure_r_port(info, NULL);
1352 return 0;
1353 }
1354
1355 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1356 info->close_delay = new_serial.close_delay;
1357 info->closing_wait = new_serial.closing_wait;
1358
1359 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1360 info->tty->alt_speed = 57600;
1361 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1362 info->tty->alt_speed = 115200;
1363 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1364 info->tty->alt_speed = 230400;
1365 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1366 info->tty->alt_speed = 460800;
1367
1368 configure_r_port(info, NULL);
1369 return 0;
1370}
1371
1372/*
1373 * This function fills in a rocket_ports struct with information
1374 * about what boards/ports are in the system. This info is passed
1375 * to user space. See setrocket.c where the info is used to create
1376 * the /dev/ttyRx ports.
1377 */
1378static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1379{
1380 struct rocket_ports tmp;
1381 int board;
1382
1383 if (!retports)
1384 return -EFAULT;
1385 memset(&tmp, 0, sizeof (tmp));
1386 tmp.tty_major = rocket_driver->major;
1387
1388 for (board = 0; board < 4; board++) {
1389 tmp.rocketModel[board].model = rocketModel[board].model;
1390 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1391 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1392 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1393 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1394 }
1395 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1396 return -EFAULT;
1397 return 0;
1398}
1399
1400static int reset_rm2(struct r_port *info, void __user *arg)
1401{
1402 int reset;
1403
1404 if (copy_from_user(&reset, arg, sizeof (int)))
1405 return -EFAULT;
1406 if (reset)
1407 reset = 1;
1408
1409 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1410 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1411 return -EINVAL;
1412
1413 if (info->ctlp->BusType == isISA)
1414 sModemReset(info->ctlp, info->chan, reset);
1415 else
1416 sPCIModemReset(info->ctlp, info->chan, reset);
1417
1418 return 0;
1419}
1420
1421static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1422{
1423 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1424 return -EFAULT;
1425 return 0;
1426}
1427
1428/* IOCTL call handler into the driver */
1429static int rp_ioctl(struct tty_struct *tty, struct file *file,
1430 unsigned int cmd, unsigned long arg)
1431{
1432 struct r_port *info = (struct r_port *) tty->driver_data;
1433 void __user *argp = (void __user *)arg;
1434
1435 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1436 return -ENXIO;
1437
1438 switch (cmd) {
1439 case RCKP_GET_STRUCT:
1440 if (copy_to_user(argp, info, sizeof (struct r_port)))
1441 return -EFAULT;
1442 return 0;
1443 case RCKP_GET_CONFIG:
1444 return get_config(info, argp);
1445 case RCKP_SET_CONFIG:
1446 return set_config(info, argp);
1447 case RCKP_GET_PORTS:
1448 return get_ports(info, argp);
1449 case RCKP_RESET_RM2:
1450 return reset_rm2(info, argp);
1451 case RCKP_GET_VERSION:
1452 return get_version(info, argp);
1453 default:
1454 return -ENOIOCTLCMD;
1455 }
1456 return 0;
1457}
1458
1459static void rp_send_xchar(struct tty_struct *tty, char ch)
1460{
1461 struct r_port *info = (struct r_port *) tty->driver_data;
1462 CHANNEL_t *cp;
1463
1464 if (rocket_paranoia_check(info, "rp_send_xchar"))
1465 return;
1466
1467 cp = &info->channel;
1468 if (sGetTxCnt(cp))
1469 sWriteTxPrioByte(cp, ch);
1470 else
1471 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1472}
1473
1474static void rp_throttle(struct tty_struct *tty)
1475{
1476 struct r_port *info = (struct r_port *) tty->driver_data;
1477 CHANNEL_t *cp;
1478
1479#ifdef ROCKET_DEBUG_THROTTLE
1480 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1481 tty->ldisc.chars_in_buffer(tty));
1482#endif
1483
1484 if (rocket_paranoia_check(info, "rp_throttle"))
1485 return;
1486
1487 cp = &info->channel;
1488 if (I_IXOFF(tty))
1489 rp_send_xchar(tty, STOP_CHAR(tty));
1490
1491 sClrRTS(&info->channel);
1492}
1493
1494static void rp_unthrottle(struct tty_struct *tty)
1495{
1496 struct r_port *info = (struct r_port *) tty->driver_data;
1497 CHANNEL_t *cp;
1498#ifdef ROCKET_DEBUG_THROTTLE
1499 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1500 tty->ldisc.chars_in_buffer(tty));
1501#endif
1502
1503 if (rocket_paranoia_check(info, "rp_throttle"))
1504 return;
1505
1506 cp = &info->channel;
1507 if (I_IXOFF(tty))
1508 rp_send_xchar(tty, START_CHAR(tty));
1509
1510 sSetRTS(&info->channel);
1511}
1512
1513/*
1514 * ------------------------------------------------------------
1515 * rp_stop() and rp_start()
1516 *
1517 * This routines are called before setting or resetting tty->stopped.
1518 * They enable or disable transmitter interrupts, as necessary.
1519 * ------------------------------------------------------------
1520 */
1521static void rp_stop(struct tty_struct *tty)
1522{
1523 struct r_port *info = (struct r_port *) tty->driver_data;
1524
1525#ifdef ROCKET_DEBUG_FLOW
1526 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1527 info->xmit_cnt, info->xmit_fifo_room);
1528#endif
1529
1530 if (rocket_paranoia_check(info, "rp_stop"))
1531 return;
1532
1533 if (sGetTxCnt(&info->channel))
1534 sDisTransmit(&info->channel);
1535}
1536
1537static void rp_start(struct tty_struct *tty)
1538{
1539 struct r_port *info = (struct r_port *) tty->driver_data;
1540
1541#ifdef ROCKET_DEBUG_FLOW
1542 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1543 info->xmit_cnt, info->xmit_fifo_room);
1544#endif
1545
1546 if (rocket_paranoia_check(info, "rp_stop"))
1547 return;
1548
1549 sEnTransmit(&info->channel);
1550 set_bit((info->aiop * 8) + info->chan,
1551 (void *) &xmit_flags[info->board]);
1552}
1553
1554/*
1555 * rp_wait_until_sent() --- wait until the transmitter is empty
1556 */
1557static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1558{
1559 struct r_port *info = (struct r_port *) tty->driver_data;
1560 CHANNEL_t *cp;
1561 unsigned long orig_jiffies;
1562 int check_time, exit_time;
1563 int txcnt;
1564
1565 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1566 return;
1567
1568 cp = &info->channel;
1569
1570 orig_jiffies = jiffies;
1571#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1572 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...", timeout,
1573 jiffies);
1574 printk(KERN_INFO "cps=%d...", info->cps);
1575#endif
1576 while (1) {
1577 txcnt = sGetTxCnt(cp);
1578 if (!txcnt) {
1579 if (sGetChanStatusLo(cp) & TXSHRMT)
1580 break;
1581 check_time = (HZ / info->cps) / 5;
1582 } else {
1583 check_time = HZ * txcnt / info->cps;
1584 }
1585 if (timeout) {
1586 exit_time = orig_jiffies + timeout - jiffies;
1587 if (exit_time <= 0)
1588 break;
1589 if (exit_time < check_time)
1590 check_time = exit_time;
1591 }
1592 if (check_time == 0)
1593 check_time = 1;
1594#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1595 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...", txcnt, jiffies, check_time);
1596#endif
1597 msleep_interruptible(jiffies_to_msecs(check_time));
1598 if (signal_pending(current))
1599 break;
1600 }
1601 current->state = TASK_RUNNING;
1602#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1603 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1604#endif
1605}
1606
1607/*
1608 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1609 */
1610static void rp_hangup(struct tty_struct *tty)
1611{
1612 CHANNEL_t *cp;
1613 struct r_port *info = (struct r_port *) tty->driver_data;
1614
1615 if (rocket_paranoia_check(info, "rp_hangup"))
1616 return;
1617
1618#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1619 printk(KERN_INFO "rp_hangup of ttyR%d...", info->line);
1620#endif
1621 rp_flush_buffer(tty);
1622 if (info->flags & ROCKET_CLOSING)
1623 return;
1624 if (info->count)
1625 atomic_dec(&rp_num_ports_open);
1626 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1627
1628 info->count = 0;
1629 info->flags &= ~ROCKET_NORMAL_ACTIVE;
1630 info->tty = NULL;
1631
1632 cp = &info->channel;
1633 sDisRxFIFO(cp);
1634 sDisTransmit(cp);
1635 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1636 sDisCTSFlowCtl(cp);
1637 sDisTxSoftFlowCtl(cp);
1638 sClrTxXOFF(cp);
1639 info->flags &= ~ROCKET_INITIALIZED;
1640
1641 wake_up_interruptible(&info->open_wait);
1642}
1643
1644/*
1645 * Exception handler - write char routine. The RocketPort driver uses a
1646 * double-buffering strategy, with the twist that if the in-memory CPU
1647 * buffer is empty, and there's space in the transmit FIFO, the
1648 * writing routines will write directly to transmit FIFO.
1649 * Write buffer and counters protected by spinlocks
1650 */
1651static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1652{
1653 struct r_port *info = (struct r_port *) tty->driver_data;
1654 CHANNEL_t *cp;
1655 unsigned long flags;
1656
1657 if (rocket_paranoia_check(info, "rp_put_char"))
1658 return;
1659
1660 /* Grab the port write semaphore, locking out other processes that try to write to this port */
1661 down(&info->write_sem);
1662
1663#ifdef ROCKET_DEBUG_WRITE
1664 printk(KERN_INFO "rp_put_char %c...", ch);
1665#endif
1666
1667 spin_lock_irqsave(&info->slock, flags);
1668 cp = &info->channel;
1669
1670 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1671 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1672
1673 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1674 info->xmit_buf[info->xmit_head++] = ch;
1675 info->xmit_head &= XMIT_BUF_SIZE - 1;
1676 info->xmit_cnt++;
1677 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1678 } else {
1679 sOutB(sGetTxRxDataIO(cp), ch);
1680 info->xmit_fifo_room--;
1681 }
1682 spin_unlock_irqrestore(&info->slock, flags);
1683 up(&info->write_sem);
1684}
1685
1686/*
1687 * Exception handler - write routine, called when user app writes to the device.
1688 * A per port write semaphore is used to protect from another process writing to
1689 * this port at the same time. This other process could be running on the other CPU
1690 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1691 * Spinlocks protect the info xmit members.
1692 */
1693static int rp_write(struct tty_struct *tty,
1694 const unsigned char *buf, int count)
1695{
1696 struct r_port *info = (struct r_port *) tty->driver_data;
1697 CHANNEL_t *cp;
1698 const unsigned char *b;
1699 int c, retval = 0;
1700 unsigned long flags;
1701
1702 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1703 return 0;
1704
1705 down_interruptible(&info->write_sem);
1706
1707#ifdef ROCKET_DEBUG_WRITE
1708 printk(KERN_INFO "rp_write %d chars...", count);
1709#endif
1710 cp = &info->channel;
1711
1712 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1713 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1714
1715 /*
1716 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1717 * into FIFO. Use the write queue for temp storage.
1718 */
1719 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1720 c = min(count, info->xmit_fifo_room);
1721 b = buf;
1722
1723 /* Push data into FIFO, 2 bytes at a time */
1724 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1725
1726 /* If there is a byte remaining, write it */
1727 if (c & 1)
1728 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1729
1730 retval += c;
1731 buf += c;
1732 count -= c;
1733
1734 spin_lock_irqsave(&info->slock, flags);
1735 info->xmit_fifo_room -= c;
1736 spin_unlock_irqrestore(&info->slock, flags);
1737 }
1738
1739 /* If count is zero, we wrote it all and are done */
1740 if (!count)
1741 goto end;
1742
1743 /* Write remaining data into the port's xmit_buf */
1744 while (1) {
1745 if (info->tty == 0) /* Seemingly obligatory check... */
1746 goto end;
1747
1748 c = min(count, min(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
1749 if (c <= 0)
1750 break;
1751
1752 b = buf;
1753 memcpy(info->xmit_buf + info->xmit_head, b, c);
1754
1755 spin_lock_irqsave(&info->slock, flags);
1756 info->xmit_head =
1757 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1758 info->xmit_cnt += c;
1759 spin_unlock_irqrestore(&info->slock, flags);
1760
1761 buf += c;
1762 count -= c;
1763 retval += c;
1764 }
1765
1766 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1767 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1768
1769end:
1770 if (info->xmit_cnt < WAKEUP_CHARS) {
1771 tty_wakeup(tty);
1da177e4
LT		 1772#ifdef ROCKETPORT_HAVE_POLL_WAIT
1773 wake_up_interruptible(&tty->poll_wait);
1774#endif
1775 }
1776 up(&info->write_sem);
1777 return retval;
1778}
1779
1780/*
1781 * Return the number of characters that can be sent. We estimate
1782 * only using the in-memory transmit buffer only, and ignore the
1783 * potential space in the transmit FIFO.
1784 */
1785static int rp_write_room(struct tty_struct *tty)
1786{
1787 struct r_port *info = (struct r_port *) tty->driver_data;
1788 int ret;
1789
1790 if (rocket_paranoia_check(info, "rp_write_room"))
1791 return 0;
1792
1793 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1794 if (ret < 0)
1795 ret = 0;
1796#ifdef ROCKET_DEBUG_WRITE
1797 printk(KERN_INFO "rp_write_room returns %d...", ret);
1798#endif
1799 return ret;
1800}
1801
1802/*
1803 * Return the number of characters in the buffer. Again, this only
1804 * counts those characters in the in-memory transmit buffer.
1805 */
1806static int rp_chars_in_buffer(struct tty_struct *tty)
1807{
1808 struct r_port *info = (struct r_port *) tty->driver_data;
1809 CHANNEL_t *cp;
1810
1811 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1812 return 0;
1813
1814 cp = &info->channel;
1815
1816#ifdef ROCKET_DEBUG_WRITE
1817 printk(KERN_INFO "rp_chars_in_buffer returns %d...", info->xmit_cnt);
1818#endif
1819 return info->xmit_cnt;
1820}
1821
1822/*
1823 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1824 * r_port struct for the port. Note that spinlock are used to protect info members,
1825 * do not call this function if the spinlock is already held.
1826 */
1827static void rp_flush_buffer(struct tty_struct *tty)
1828{
1829 struct r_port *info = (struct r_port *) tty->driver_data;
1830 CHANNEL_t *cp;
1831 unsigned long flags;
1832
1833 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1834 return;
1835
1836 spin_lock_irqsave(&info->slock, flags);
1837 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1838 spin_unlock_irqrestore(&info->slock, flags);
1839
1da177e4
LT		 1840#ifdef ROCKETPORT_HAVE_POLL_WAIT
1841 wake_up_interruptible(&tty->poll_wait);
1842#endif
1843 tty_wakeup(tty);
1844
1845 cp = &info->channel;
1846 sFlushTxFIFO(cp);
1847}
1848
1849#ifdef CONFIG_PCI
1850
1851/*
1852 * Called when a PCI card is found. Retrieves and stores model information,
1853 * init's aiopic and serial port hardware.
1854 * Inputs: i is the board number (0-n)
1855 */
f15313bf 1856static __init int register_PCI(int i, struct pci_dev *dev)
1da177e4
LT		 1857{
1858 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1859 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1860 char *str, *board_type;
1861 CONTROLLER_t *ctlp;
1862
1863 int fast_clock = 0;
1864 int altChanRingIndicator = 0;
1865 int ports_per_aiop = 8;
1866 int ret;
1867 unsigned int class_rev;
1868 WordIO_t ConfigIO = 0;
1869 ByteIO_t UPCIRingInd = 0;
1870
1871 if (!dev || pci_enable_device(dev))
1872 return 0;
1873
1874 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1875 ret = pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1876
1877 if (ret) {
1878 printk(KERN_INFO " Error during register_PCI(), unable to read config dword \n");
1879 return 0;
1880 }
1881
1882 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1883 rocketModel[i].loadrm2 = 0;
1884 rocketModel[i].startingPortNumber = nextLineNumber;
1885
1886 /* Depending on the model, set up some config variables */
1887 switch (dev->device) {
1888 case PCI_DEVICE_ID_RP4QUAD:
1889 str = "Quadcable";
1890 max_num_aiops = 1;
1891 ports_per_aiop = 4;
1892 rocketModel[i].model = MODEL_RP4QUAD;
1893 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1894 rocketModel[i].numPorts = 4;
1895 break;
1896 case PCI_DEVICE_ID_RP8OCTA:
1897 str = "Octacable";
1898 max_num_aiops = 1;
1899 rocketModel[i].model = MODEL_RP8OCTA;
1900 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1901 rocketModel[i].numPorts = 8;
1902 break;
1903 case PCI_DEVICE_ID_URP8OCTA:
1904 str = "Octacable";
1905 max_num_aiops = 1;
1906 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1907 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1908 rocketModel[i].numPorts = 8;
1909 break;
1910 case PCI_DEVICE_ID_RP8INTF:
1911 str = "8";
1912 max_num_aiops = 1;
1913 rocketModel[i].model = MODEL_RP8INTF;
1914 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1915 rocketModel[i].numPorts = 8;
1916 break;
1917 case PCI_DEVICE_ID_URP8INTF:
1918 str = "8";
1919 max_num_aiops = 1;
1920 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1921 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1922 rocketModel[i].numPorts = 8;
1923 break;
1924 case PCI_DEVICE_ID_RP8J:
1925 str = "8J";
1926 max_num_aiops = 1;
1927 rocketModel[i].model = MODEL_RP8J;
1928 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1929 rocketModel[i].numPorts = 8;
1930 break;
1931 case PCI_DEVICE_ID_RP4J:
1932 str = "4J";
1933 max_num_aiops = 1;
1934 ports_per_aiop = 4;
1935 rocketModel[i].model = MODEL_RP4J;
1936 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1937 rocketModel[i].numPorts = 4;
1938 break;
1939 case PCI_DEVICE_ID_RP8SNI:
1940 str = "8 (DB78 Custom)";
1941 max_num_aiops = 1;
1942 rocketModel[i].model = MODEL_RP8SNI;
1943 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1944 rocketModel[i].numPorts = 8;
1945 break;
1946 case PCI_DEVICE_ID_RP16SNI:
1947 str = "16 (DB78 Custom)";
1948 max_num_aiops = 2;
1949 rocketModel[i].model = MODEL_RP16SNI;
1950 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1951 rocketModel[i].numPorts = 16;
1952 break;
1953 case PCI_DEVICE_ID_RP16INTF:
1954 str = "16";
1955 max_num_aiops = 2;
1956 rocketModel[i].model = MODEL_RP16INTF;
1957 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1958 rocketModel[i].numPorts = 16;
1959 break;
1960 case PCI_DEVICE_ID_URP16INTF:
1961 str = "16";
1962 max_num_aiops = 2;
1963 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1964 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1965 rocketModel[i].numPorts = 16;
1966 break;
1967 case PCI_DEVICE_ID_CRP16INTF:
1968 str = "16";
1969 max_num_aiops = 2;
1970 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1971 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1972 rocketModel[i].numPorts = 16;
1973 break;
1974 case PCI_DEVICE_ID_RP32INTF:
1975 str = "32";
1976 max_num_aiops = 4;
1977 rocketModel[i].model = MODEL_RP32INTF;
1978 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1979 rocketModel[i].numPorts = 32;
1980 break;
1981 case PCI_DEVICE_ID_URP32INTF:
1982 str = "32";
1983 max_num_aiops = 4;
1984 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1985 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1986 rocketModel[i].numPorts = 32;
1987 break;
1988 case PCI_DEVICE_ID_RPP4:
1989 str = "Plus Quadcable";
1990 max_num_aiops = 1;
1991 ports_per_aiop = 4;
1992 altChanRingIndicator++;
1993 fast_clock++;
1994 rocketModel[i].model = MODEL_RPP4;
1995 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1996 rocketModel[i].numPorts = 4;
1997 break;
1998 case PCI_DEVICE_ID_RPP8:
1999 str = "Plus Octacable";
2000 max_num_aiops = 2;
2001 ports_per_aiop = 4;
2002 altChanRingIndicator++;
2003 fast_clock++;
2004 rocketModel[i].model = MODEL_RPP8;
2005 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2006 rocketModel[i].numPorts = 8;
2007 break;
2008 case PCI_DEVICE_ID_RP2_232:
2009 str = "Plus 2 (RS-232)";
2010 max_num_aiops = 1;
2011 ports_per_aiop = 2;
2012 altChanRingIndicator++;
2013 fast_clock++;
2014 rocketModel[i].model = MODEL_RP2_232;
2015 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2016 rocketModel[i].numPorts = 2;
2017 break;
2018 case PCI_DEVICE_ID_RP2_422:
2019 str = "Plus 2 (RS-422)";
2020 max_num_aiops = 1;
2021 ports_per_aiop = 2;
2022 altChanRingIndicator++;
2023 fast_clock++;
2024 rocketModel[i].model = MODEL_RP2_422;
2025 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2026 rocketModel[i].numPorts = 2;
2027 break;
2028 case PCI_DEVICE_ID_RP6M:
2029
2030 max_num_aiops = 1;
2031 ports_per_aiop = 6;
2032 str = "6-port";
2033
2034 /* If class_rev is 1, the rocketmodem flash must be loaded. If it is 2 it is a "socketed" version. */
2035 if ((class_rev & 0xFF) == 1) {
2036 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2037 rocketModel[i].loadrm2 = 1;
2038 } else {
2039 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2040 }
2041
2042 rocketModel[i].model = MODEL_RP6M;
2043 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2044 rocketModel[i].numPorts = 6;
2045 break;
2046 case PCI_DEVICE_ID_RP4M:
2047 max_num_aiops = 1;
2048 ports_per_aiop = 4;
2049 str = "4-port";
2050 if ((class_rev & 0xFF) == 1) {
2051 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2052 rocketModel[i].loadrm2 = 1;
2053 } else {
2054 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2055 }
2056
2057 rocketModel[i].model = MODEL_RP4M;
2058 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2059 rocketModel[i].numPorts = 4;
2060 break;
2061 default:
2062 str = "(unknown/unsupported)";
2063 max_num_aiops = 0;
2064 break;
2065 }
2066
2067 /*
2068 * Check for UPCI boards.
2069 */
2070
2071 switch (dev->device) {
2072 case PCI_DEVICE_ID_URP32INTF:
2073 case PCI_DEVICE_ID_URP8INTF:
2074 case PCI_DEVICE_ID_URP16INTF:
2075 case PCI_DEVICE_ID_CRP16INTF:
2076 case PCI_DEVICE_ID_URP8OCTA:
2077 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2078 ConfigIO = pci_resource_start(dev, 1);
2079 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2080 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2081
2082 /*
2083 * Check for octa or quad cable.
2084 */
2085 if (!
2086 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2087 PCI_GPIO_CTRL_8PORT)) {
2088 str = "Quadcable";
2089 ports_per_aiop = 4;
2090 rocketModel[i].numPorts = 4;
2091 }
2092 }
2093 break;
2094 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2095 str = "8 ports";
2096 max_num_aiops = 1;
2097 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2098 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2099 rocketModel[i].numPorts = 8;
2100 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2101 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2102 ConfigIO = pci_resource_start(dev, 1);
2103 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2104 break;
2105 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2106 str = "4 ports";
2107 max_num_aiops = 1;
2108 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2109 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2110 rocketModel[i].numPorts = 4;
2111 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2112 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2113 ConfigIO = pci_resource_start(dev, 1);
2114 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2115 break;
2116 default:
2117 break;
2118 }
2119
2120 switch (rcktpt_type[i]) {
2121 case ROCKET_TYPE_MODEM:
2122 board_type = "RocketModem";
2123 break;
2124 case ROCKET_TYPE_MODEMII:
2125 board_type = "RocketModem II";
2126 break;
2127 case ROCKET_TYPE_MODEMIII:
2128 board_type = "RocketModem III";
2129 break;
2130 default:
2131 board_type = "RocketPort";
2132 break;
2133 }
2134
2135 if (fast_clock) {
2136 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2137 rp_baud_base[i] = 921600;
2138 } else {
2139 /*
2140 * If support_low_speed is set, use the slow clock
2141 * prescale, which supports 50 bps
2142 */
2143 if (support_low_speed) {
2144 /* mod 9 (divide by 10) prescale */
2145 sClockPrescale = 0x19;
2146 rp_baud_base[i] = 230400;
2147 } else {
2148 /* mod 4 (devide by 5) prescale */
2149 sClockPrescale = 0x14;
2150 rp_baud_base[i] = 460800;
2151 }
2152 }
2153
2154 for (aiop = 0; aiop < max_num_aiops; aiop++)
2155 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2156 ctlp = sCtlNumToCtlPtr(i);
2157 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2158 for (aiop = 0; aiop < max_num_aiops; aiop++)
2159 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2160
2161 printk("Comtrol PCI controller #%d ID 0x%x found in bus:slot:fn %s at address %04lx, "
2162 "%d AIOP(s) (%s)\n", i, dev->device, pci_name(dev),
2163 rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString);
2164 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2165 rocketModel[i].modelString,
2166 rocketModel[i].startingPortNumber,
2167 rocketModel[i].startingPortNumber +
2168 rocketModel[i].numPorts - 1);
2169
2170 if (num_aiops <= 0) {
2171 rcktpt_io_addr[i] = 0;
2172 return (0);
2173 }
2174 is_PCI[i] = 1;
2175
2176 /* Reset the AIOPIC, init the serial ports */
2177 for (aiop = 0; aiop < num_aiops; aiop++) {
2178 sResetAiopByNum(ctlp, aiop);
2179 num_chan = ports_per_aiop;
2180 for (chan = 0; chan < num_chan; chan++)
2181 init_r_port(i, aiop, chan, dev);
2182 }
2183
2184 /* Rocket modems must be reset */
2185 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2186 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2187 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2188 num_chan = ports_per_aiop;
2189 for (chan = 0; chan < num_chan; chan++)
2190 sPCIModemReset(ctlp, chan, 1);
2191 mdelay(500);
2192 for (chan = 0; chan < num_chan; chan++)
2193 sPCIModemReset(ctlp, chan, 0);
2194 mdelay(500);
2195 rmSpeakerReset(ctlp, rocketModel[i].model);
2196 }
2197 return (1);
2198}
2199
2200/*
2201 * Probes for PCI cards, inits them if found
2202 * Input: board_found = number of ISA boards already found, or the
2203 * starting board number
2204 * Returns: Number of PCI boards found
2205 */
2206static int __init init_PCI(int boards_found)
2207{
2208 struct pci_dev *dev = NULL;
2209 int count = 0;
2210
2211 /* Work through the PCI device list, pulling out ours */
606d099c 2212 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
1da177e4
LT		 2213 if (register_PCI(count + boards_found, dev))
2214 count++;
2215 }
2216 return (count);
2217}
2218
2219#endif /* CONFIG_PCI */
2220
2221/*
2222 * Probes for ISA cards
2223 * Input: i = the board number to look for
2224 * Returns: 1 if board found, 0 else
2225 */
2226static int __init init_ISA(int i)
2227{
2228 int num_aiops, num_chan = 0, total_num_chan = 0;
2229 int aiop, chan;
2230 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2231 CONTROLLER_t *ctlp;
2232 char *type_string;
2233
2234 /* If io_addr is zero, no board configured */
2235 if (rcktpt_io_addr[i] == 0)
2236 return (0);
2237
2238 /* Reserve the IO region */
2239 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2240 printk(KERN_INFO "Unable to reserve IO region for configured ISA RocketPort at address 0x%lx, board not installed...\n", rcktpt_io_addr[i]);
2241 rcktpt_io_addr[i] = 0;
2242 return (0);
2243 }
2244
2245 ctlp = sCtlNumToCtlPtr(i);
2246
2247 ctlp->boardType = rcktpt_type[i];
2248
2249 switch (rcktpt_type[i]) {
2250 case ROCKET_TYPE_PC104:
2251 type_string = "(PC104)";
2252 break;
2253 case ROCKET_TYPE_MODEM:
2254 type_string = "(RocketModem)";
2255 break;
2256 case ROCKET_TYPE_MODEMII:
2257 type_string = "(RocketModem II)";
2258 break;
2259 default:
2260 type_string = "";
2261 break;
2262 }
2263
2264 /*
2265 * If support_low_speed is set, use the slow clock prescale,
2266 * which supports 50 bps
2267 */
2268 if (support_low_speed) {
2269 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2270 rp_baud_base[i] = 230400;
2271 } else {
2272 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2273 rp_baud_base[i] = 460800;
2274 }
2275
2276 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2277 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2278
2279 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2280
2281 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2282 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2283 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2284 }
2285
2286 /* If something went wrong initing the AIOP's release the ISA IO memory */
2287 if (num_aiops <= 0) {
2288 release_region(rcktpt_io_addr[i], 64);
2289 rcktpt_io_addr[i] = 0;
2290 return (0);
2291 }
2292
2293 rocketModel[i].startingPortNumber = nextLineNumber;
2294
2295 for (aiop = 0; aiop < num_aiops; aiop++) {
2296 sResetAiopByNum(ctlp, aiop);
2297 sEnAiop(ctlp, aiop);
2298 num_chan = sGetAiopNumChan(ctlp, aiop);
2299 total_num_chan += num_chan;
2300 for (chan = 0; chan < num_chan; chan++)
2301 init_r_port(i, aiop, chan, NULL);
2302 }
2303 is_PCI[i] = 0;
2304 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2305 num_chan = sGetAiopNumChan(ctlp, 0);
2306 total_num_chan = num_chan;
2307 for (chan = 0; chan < num_chan; chan++)
2308 sModemReset(ctlp, chan, 1);
2309 mdelay(500);
2310 for (chan = 0; chan < num_chan; chan++)
2311 sModemReset(ctlp, chan, 0);
2312 mdelay(500);
2313 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2314 } else {
2315 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2316 }
2317 rocketModel[i].numPorts = total_num_chan;
2318 rocketModel[i].model = MODEL_ISA;
2319
2320 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2321 i, rcktpt_io_addr[i], num_aiops, type_string);
2322
2323 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2324 rocketModel[i].modelString,
2325 rocketModel[i].startingPortNumber,
2326 rocketModel[i].startingPortNumber +
2327 rocketModel[i].numPorts - 1);
2328
2329 return (1);
2330}
2331
b68e31d0 2332static const struct tty_operations rocket_ops = {
1da177e4
LT		 2333 .open = rp_open,
2334 .close = rp_close,
2335 .write = rp_write,
2336 .put_char = rp_put_char,
2337 .write_room = rp_write_room,
2338 .chars_in_buffer = rp_chars_in_buffer,
2339 .flush_buffer = rp_flush_buffer,
2340 .ioctl = rp_ioctl,
2341 .throttle = rp_throttle,
2342 .unthrottle = rp_unthrottle,
2343 .set_termios = rp_set_termios,
2344 .stop = rp_stop,
2345 .start = rp_start,
2346 .hangup = rp_hangup,
2347 .break_ctl = rp_break,
2348 .send_xchar = rp_send_xchar,
2349 .wait_until_sent = rp_wait_until_sent,
2350 .tiocmget = rp_tiocmget,
2351 .tiocmset = rp_tiocmset,
2352};
2353
2354/*
2355 * The module "startup" routine; it's run when the module is loaded.
2356 */
d269cdd0 2357static int __init rp_init(void)
1da177e4
LT		 2358{
2359 int retval, pci_boards_found, isa_boards_found, i;
2360
2361 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2362 ROCKET_VERSION, ROCKET_DATE);
2363
2364 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2365 if (!rocket_driver)
2366 return -ENOMEM;
2367
1da177e4
LT		 2368 /*
2369 * Initialize the array of pointers to our own internal state
2370 * structures.
2371 */
2372 memset(rp_table, 0, sizeof (rp_table));
2373 memset(xmit_flags, 0, sizeof (xmit_flags));
2374
2375 for (i = 0; i < MAX_RP_PORTS; i++)
2376 lineNumbers[i] = 0;
2377 nextLineNumber = 0;
2378 memset(rocketModel, 0, sizeof (rocketModel));
2379
2380 /*
2381 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2382 * zero, use the default controller IO address of board1 + 0x40.
2383 */
2384 if (board1) {
2385 if (controller == 0)
2386 controller = board1 + 0x40;
2387 } else {
2388 controller = 0; /* Used as a flag, meaning no ISA boards */
2389 }
2390
2391 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2392 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2393 printk(KERN_INFO "Unable to reserve IO region for first configured ISA RocketPort controller 0x%lx. Driver exiting \n", controller);
2394 return -EBUSY;
2395 }
2396
2397 /* Store ISA variable retrieved from command line or .conf file. */
2398 rcktpt_io_addr[0] = board1;
2399 rcktpt_io_addr[1] = board2;
2400 rcktpt_io_addr[2] = board3;
2401 rcktpt_io_addr[3] = board4;
2402
2403 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2404 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2405 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2406 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2407 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2408 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2409 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2410 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2411
2412 /*
2413 * Set up the tty driver structure and then register this
2414 * driver with the tty layer.
2415 */
2416
2417 rocket_driver->owner = THIS_MODULE;
331b8319 2418 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 2419 rocket_driver->name = "ttyR";
2420 rocket_driver->driver_name = "Comtrol RocketPort";
2421 rocket_driver->major = TTY_ROCKET_MAJOR;
2422 rocket_driver->minor_start = 0;
2423 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2424 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2425 rocket_driver->init_termios = tty_std_termios;
2426 rocket_driver->init_termios.c_cflag =
2427 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 2428 rocket_driver->init_termios.c_ispeed = 9600;
2429 rocket_driver->init_termios.c_ospeed = 9600;
1da177e4 2430#ifdef ROCKET_SOFT_FLOW
331b8319 2431 rocket_driver->flags |= TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 2432#endif
2433 tty_set_operations(rocket_driver, &rocket_ops);
2434
2435 retval = tty_register_driver(rocket_driver);
2436 if (retval < 0) {
2437 printk(KERN_INFO "Couldn't install tty RocketPort driver (error %d)\n", -retval);
2438 put_tty_driver(rocket_driver);
2439 return -1;
2440 }
2441
2442#ifdef ROCKET_DEBUG_OPEN
2443 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2444#endif
2445
2446 /*
2447 * OK, let's probe each of the controllers looking for boards. Any boards found
2448 * will be initialized here.
2449 */
2450 isa_boards_found = 0;
2451 pci_boards_found = 0;
2452
2453 for (i = 0; i < NUM_BOARDS; i++) {
2454 if (init_ISA(i))
2455 isa_boards_found++;
2456 }
2457
2458#ifdef CONFIG_PCI
2459 if (isa_boards_found < NUM_BOARDS)
2460 pci_boards_found = init_PCI(isa_boards_found);
2461#endif
2462
2463 max_board = pci_boards_found + isa_boards_found;
2464
2465 if (max_board == 0) {
2466 printk(KERN_INFO "No rocketport ports found; unloading driver.\n");
2467 del_timer_sync(&rocket_timer);
2468 tty_unregister_driver(rocket_driver);
2469 put_tty_driver(rocket_driver);
2470 return -ENXIO;
2471 }
2472
2473 return 0;
2474}
2475
1da177e4
LT		 2476
2477static void rp_cleanup_module(void)
2478{
2479 int retval;
2480 int i;
2481
2482 del_timer_sync(&rocket_timer);
2483
2484 retval = tty_unregister_driver(rocket_driver);
2485 if (retval)
2486 printk(KERN_INFO "Error %d while trying to unregister "
2487 "rocketport driver\n", -retval);
2488 put_tty_driver(rocket_driver);
2489
735d5661
JJ		 2490 for (i = 0; i < MAX_RP_PORTS; i++)
2491 kfree(rp_table[i]);
1da177e4
LT		 2492
2493 for (i = 0; i < NUM_BOARDS; i++) {
2494 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2495 continue;
2496 release_region(rcktpt_io_addr[i], 64);
2497 }
2498 if (controller)
2499 release_region(controller, 4);
2500}
1da177e4 2501
1da177e4
LT		 2502/***************************************************************************
2503Function: sInitController
2504Purpose: Initialization of controller global registers and controller
2505 structure.
2506Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2507 IRQNum,Frequency,PeriodicOnly)
2508 CONTROLLER_T *CtlP; Ptr to controller structure
2509 int CtlNum; Controller number
2510 ByteIO_t MudbacIO; Mudbac base I/O address.
2511 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2512 This list must be in the order the AIOPs will be found on the
2513 controller. Once an AIOP in the list is not found, it is
2514 assumed that there are no more AIOPs on the controller.
2515 int AiopIOListSize; Number of addresses in AiopIOList
2516 int IRQNum; Interrupt Request number. Can be any of the following:
2517 0: Disable global interrupts
2518 3: IRQ 3
2519 4: IRQ 4
2520 5: IRQ 5
2521 9: IRQ 9
2522 10: IRQ 10
2523 11: IRQ 11
2524 12: IRQ 12
2525 15: IRQ 15
2526 Byte_t Frequency: A flag identifying the frequency
2527 of the periodic interrupt, can be any one of the following:
2528 FREQ_DIS - periodic interrupt disabled
2529 FREQ_137HZ - 137 Hertz
2530 FREQ_69HZ - 69 Hertz
2531 FREQ_34HZ - 34 Hertz
2532 FREQ_17HZ - 17 Hertz
2533 FREQ_9HZ - 9 Hertz
2534 FREQ_4HZ - 4 Hertz
2535 If IRQNum is set to 0 the Frequency parameter is
2536 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2537 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2538 interrupt are to be blocked.
f15313bf 2539 0 is both the periodic interrupt and
1da177e4
LT		 2540 other channel interrupts are allowed.
2541 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2542 overidden, it is forced to a value of 0.
1da177e4
LT		 2543Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2544 initialization failed.
2545
2546Comments:
2547 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2548 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2549
2550 If interrupts are to be completely disabled set IRQNum to 0.
2551
f15313bf 2552 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2553 invalid combination.
2554
2555 This function performs initialization of global interrupt modes,
2556 but it does not actually enable global interrupts. To enable
2557 and disable global interrupts use functions sEnGlobalInt() and
2558 sDisGlobalInt(). Enabling of global interrupts is normally not
2559 done until all other initializations are complete.
2560
2561 Even if interrupts are globally enabled, they must also be
2562 individually enabled for each channel that is to generate
2563 interrupts.
2564
2565Warnings: No range checking on any of the parameters is done.
2566
2567 No context switches are allowed while executing this function.
2568
2569 After this function all AIOPs on the controller are disabled,
2570 they can be enabled with sEnAiop().
2571*/
f15313bf
AB		 2572static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2573 ByteIO_t * AiopIOList, int AiopIOListSize,
2574 int IRQNum, Byte_t Frequency, int PeriodicOnly)
1da177e4
LT		 2575{
2576 int i;
2577 ByteIO_t io;
2578 int done;
2579
2580 CtlP->AiopIntrBits = aiop_intr_bits;
2581 CtlP->AltChanRingIndicator = 0;
2582 CtlP->CtlNum = CtlNum;
2583 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2584 CtlP->BusType = isISA;
2585 CtlP->MBaseIO = MudbacIO;
2586 CtlP->MReg1IO = MudbacIO + 1;
2587 CtlP->MReg2IO = MudbacIO + 2;
2588 CtlP->MReg3IO = MudbacIO + 3;
2589#if 1
2590 CtlP->MReg2 = 0; /* interrupt disable */
2591 CtlP->MReg3 = 0; /* no periodic interrupts */
2592#else
2593 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2594 CtlP->MReg2 = 0; /* interrupt disable */
2595 CtlP->MReg3 = 0; /* no periodic interrupts */
2596 } else {
2597 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2598 CtlP->MReg3 = Frequency; /* set frequency */
2599 if (PeriodicOnly) { /* periodic interrupt only */
2600 CtlP->MReg3 |= PERIODIC_ONLY;
2601 }
2602 }
2603#endif
2604 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2605 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2606 sControllerEOI(CtlP); /* clear EOI if warm init */
2607 /* Init AIOPs */
2608 CtlP->NumAiop = 0;
2609 for (i = done = 0; i < AiopIOListSize; i++) {
2610 io = AiopIOList[i];
2611 CtlP->AiopIO[i] = (WordIO_t) io;
2612 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2613 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2614 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2615 if (done)
2616 continue;
2617 sEnAiop(CtlP, i); /* enable the AIOP */
2618 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2619 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2620 done = 1; /* done looking for AIOPs */
2621 else {
2622 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2623 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2624 sOutB(io + _INDX_DATA, sClockPrescale);
2625 CtlP->NumAiop++; /* bump count of AIOPs */
2626 }
2627 sDisAiop(CtlP, i); /* disable AIOP */
2628 }
2629
2630 if (CtlP->NumAiop == 0)
2631 return (-1);
2632 else
2633 return (CtlP->NumAiop);
2634}
2635
2636/***************************************************************************
2637Function: sPCIInitController
2638Purpose: Initialization of controller global registers and controller
2639 structure.
2640Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2641 IRQNum,Frequency,PeriodicOnly)
2642 CONTROLLER_T *CtlP; Ptr to controller structure
2643 int CtlNum; Controller number
2644 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2645 This list must be in the order the AIOPs will be found on the
2646 controller. Once an AIOP in the list is not found, it is
2647 assumed that there are no more AIOPs on the controller.
2648 int AiopIOListSize; Number of addresses in AiopIOList
2649 int IRQNum; Interrupt Request number. Can be any of the following:
2650 0: Disable global interrupts
2651 3: IRQ 3
2652 4: IRQ 4
2653 5: IRQ 5
2654 9: IRQ 9
2655 10: IRQ 10
2656 11: IRQ 11
2657 12: IRQ 12
2658 15: IRQ 15
2659 Byte_t Frequency: A flag identifying the frequency
2660 of the periodic interrupt, can be any one of the following:
2661 FREQ_DIS - periodic interrupt disabled
2662 FREQ_137HZ - 137 Hertz
2663 FREQ_69HZ - 69 Hertz
2664 FREQ_34HZ - 34 Hertz
2665 FREQ_17HZ - 17 Hertz
2666 FREQ_9HZ - 9 Hertz
2667 FREQ_4HZ - 4 Hertz
2668 If IRQNum is set to 0 the Frequency parameter is
2669 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2670 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2671 interrupt are to be blocked.
f15313bf 2672 0 is both the periodic interrupt and
1da177e4
LT		 2673 other channel interrupts are allowed.
2674 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2675 overidden, it is forced to a value of 0.
1da177e4
LT		 2676Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2677 initialization failed.
2678
2679Comments:
2680 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2681 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2682
2683 If interrupts are to be completely disabled set IRQNum to 0.
2684
f15313bf 2685 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2686 invalid combination.
2687
2688 This function performs initialization of global interrupt modes,
2689 but it does not actually enable global interrupts. To enable
2690 and disable global interrupts use functions sEnGlobalInt() and
2691 sDisGlobalInt(). Enabling of global interrupts is normally not
2692 done until all other initializations are complete.
2693
2694 Even if interrupts are globally enabled, they must also be
2695 individually enabled for each channel that is to generate
2696 interrupts.
2697
2698Warnings: No range checking on any of the parameters is done.
2699
2700 No context switches are allowed while executing this function.
2701
2702 After this function all AIOPs on the controller are disabled,
2703 they can be enabled with sEnAiop().
2704*/
f15313bf
AB		 2705static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2706 ByteIO_t * AiopIOList, int AiopIOListSize,
2707 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2708 int PeriodicOnly, int altChanRingIndicator,
2709 int UPCIRingInd)
1da177e4
LT		 2710{
2711 int i;
2712 ByteIO_t io;
2713
2714 CtlP->AltChanRingIndicator = altChanRingIndicator;
2715 CtlP->UPCIRingInd = UPCIRingInd;
2716 CtlP->CtlNum = CtlNum;
2717 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2718 CtlP->BusType = isPCI; /* controller release 1 */
2719
2720 if (ConfigIO) {
2721 CtlP->isUPCI = 1;
2722 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2723 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2724 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2725 } else {
2726 CtlP->isUPCI = 0;
2727 CtlP->PCIIO =
2728 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2729 CtlP->AiopIntrBits = aiop_intr_bits;
2730 }
2731
2732 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2733 /* Init AIOPs */
2734 CtlP->NumAiop = 0;
2735 for (i = 0; i < AiopIOListSize; i++) {
2736 io = AiopIOList[i];
2737 CtlP->AiopIO[i] = (WordIO_t) io;
2738 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2739
2740 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2741 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2742 break; /* done looking for AIOPs */
2743
2744 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2745 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2746 sOutB(io + _INDX_DATA, sClockPrescale);
2747 CtlP->NumAiop++; /* bump count of AIOPs */
2748 }
2749
2750 if (CtlP->NumAiop == 0)
2751 return (-1);
2752 else
2753 return (CtlP->NumAiop);
2754}
2755
2756/***************************************************************************
2757Function: sReadAiopID
2758Purpose: Read the AIOP idenfication number directly from an AIOP.
2759Call: sReadAiopID(io)
2760 ByteIO_t io: AIOP base I/O address
2761Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2762 is replace by an identifying number.
2763 Flag AIOPID_NULL if no valid AIOP is found
2764Warnings: No context switches are allowed while executing this function.
2765
2766*/
f15313bf 2767static int sReadAiopID(ByteIO_t io)
1da177e4
LT		 2768{
2769 Byte_t AiopID; /* ID byte from AIOP */
2770
2771 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2772 sOutB(io + _CMD_REG, 0x0);
2773 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2774 if (AiopID == 0x06)
2775 return (1);
2776 else /* AIOP does not exist */
2777 return (-1);
2778}
2779
2780/***************************************************************************
2781Function: sReadAiopNumChan
2782Purpose: Read the number of channels available in an AIOP directly from
2783 an AIOP.
2784Call: sReadAiopNumChan(io)
2785 WordIO_t io: AIOP base I/O address
2786Return: int: The number of channels available
2787Comments: The number of channels is determined by write/reads from identical
2788 offsets within the SRAM address spaces for channels 0 and 4.
2789 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2790 AIOP, otherwise it is an 8 channel.
2791Warnings: No context switches are allowed while executing this function.
2792*/
f15313bf 2793static int sReadAiopNumChan(WordIO_t io)
1da177e4
LT		 2794{
2795 Word_t x;
2796 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2797
2798 /* write to chan 0 SRAM */
2799 sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0]));
2800 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2801 x = sInW(io + _INDX_DATA);
2802 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2803 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2804 return (8);
2805 else
2806 return (4);
2807}
2808
2809/***************************************************************************
2810Function: sInitChan
2811Purpose: Initialization of a channel and channel structure
2812Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2813 CONTROLLER_T *CtlP; Ptr to controller structure
2814 CHANNEL_T *ChP; Ptr to channel structure
2815 int AiopNum; AIOP number within controller
2816 int ChanNum; Channel number within AIOP
f15313bf 2817Return: int: 1 if initialization succeeded, 0 if it fails because channel
1da177e4
LT		 2818 number exceeds number of channels available in AIOP.
2819Comments: This function must be called before a channel can be used.
2820Warnings: No range checking on any of the parameters is done.
2821
2822 No context switches are allowed while executing this function.
2823*/
f15313bf
AB		 2824static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2825 int ChanNum)
1da177e4
LT		 2826{
2827 int i;
2828 WordIO_t AiopIO;
2829 WordIO_t ChIOOff;
2830 Byte_t *ChR;
2831 Word_t ChOff;
2832 static Byte_t R[4];
2833 int brd9600;
2834
2835 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
f15313bf 2836 return 0; /* exceeds num chans in AIOP */
1da177e4
LT		 2837
2838 /* Channel, AIOP, and controller identifiers */
2839 ChP->CtlP = CtlP;
2840 ChP->ChanID = CtlP->AiopID[AiopNum];
2841 ChP->AiopNum = AiopNum;
2842 ChP->ChanNum = ChanNum;
2843
2844 /* Global direct addresses */
2845 AiopIO = CtlP->AiopIO[AiopNum];
2846 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2847 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2848 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2849 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2850 ChP->IndexData = AiopIO + _INDX_DATA;
2851
2852 /* Channel direct addresses */
2853 ChIOOff = AiopIO + ChP->ChanNum * 2;
2854 ChP->TxRxData = ChIOOff + _TD0;
2855 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2856 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2857 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2858
2859 /* Initialize the channel from the RData array */
2860 for (i = 0; i < RDATASIZE; i += 4) {
2861 R[0] = RData[i];
2862 R[1] = RData[i + 1] + 0x10 * ChanNum;
2863 R[2] = RData[i + 2];
2864 R[3] = RData[i + 3];
2865 sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0]));
2866 }
2867
2868 ChR = ChP->R;
2869 for (i = 0; i < RREGDATASIZE; i += 4) {
2870 ChR[i] = RRegData[i];
2871 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2872 ChR[i + 2] = RRegData[i + 2];
2873 ChR[i + 3] = RRegData[i + 3];
2874 }
2875
2876 /* Indexed registers */
2877 ChOff = (Word_t) ChanNum *0x1000;
2878
2879 if (sClockPrescale == 0x14)
2880 brd9600 = 47;
2881 else
2882 brd9600 = 23;
2883
2884 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2885 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2886 ChP->BaudDiv[2] = (Byte_t) brd9600;
2887 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2888 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]);
2889
2890 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2891 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2892 ChP->TxControl[2] = 0;
2893 ChP->TxControl[3] = 0;
2894 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
2895
2896 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2897 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2898 ChP->RxControl[2] = 0;
2899 ChP->RxControl[3] = 0;
2900 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
2901
2902 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2903 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2904 ChP->TxEnables[2] = 0;
2905 ChP->TxEnables[3] = 0;
2906 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]);
2907
2908 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2909 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2910 ChP->TxCompare[2] = 0;
2911 ChP->TxCompare[3] = 0;
2912 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]);
2913
2914 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2915 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2916 ChP->TxReplace1[2] = 0;
2917 ChP->TxReplace1[3] = 0;
2918 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]);
2919
2920 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2921 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2922 ChP->TxReplace2[2] = 0;
2923 ChP->TxReplace2[3] = 0;
2924 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]);
2925
2926 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2927 ChP->TxFIFO = ChOff + _TX_FIFO;
2928
2929 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2930 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2931 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2932 sOutW(ChP->IndexData, 0);
2933 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2934 ChP->RxFIFO = ChOff + _RX_FIFO;
2935
2936 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2937 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2938 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2939 sOutW(ChP->IndexData, 0);
2940 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2941 sOutW(ChP->IndexData, 0);
2942 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2943 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2944 sOutB(ChP->IndexData, 0);
2945 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2946 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2947 sOutB(ChP->IndexData, 0);
2948 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2949 sEnRxProcessor(ChP); /* start the Rx processor */
2950
f15313bf 2951 return 1;
1da177e4
LT		 2952}
2953
2954/***************************************************************************
2955Function: sStopRxProcessor
2956Purpose: Stop the receive processor from processing a channel.
2957Call: sStopRxProcessor(ChP)
2958 CHANNEL_T *ChP; Ptr to channel structure
2959
2960Comments: The receive processor can be started again with sStartRxProcessor().
2961 This function causes the receive processor to skip over the
2962 stopped channel. It does not stop it from processing other channels.
2963
2964Warnings: No context switches are allowed while executing this function.
2965
2966 Do not leave the receive processor stopped for more than one
2967 character time.
2968
2969 After calling this function a delay of 4 uS is required to ensure
2970 that the receive processor is no longer processing this channel.
2971*/
f15313bf 2972static void sStopRxProcessor(CHANNEL_T * ChP)
1da177e4
LT		 2973{
2974 Byte_t R[4];
2975
2976 R[0] = ChP->R[0];
2977 R[1] = ChP->R[1];
2978 R[2] = 0x0a;
2979 R[3] = ChP->R[3];
2980 sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]);
2981}
2982
2983/***************************************************************************
2984Function: sFlushRxFIFO
2985Purpose: Flush the Rx FIFO
2986Call: sFlushRxFIFO(ChP)
2987 CHANNEL_T *ChP; Ptr to channel structure
2988Return: void
2989Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2990 while it is being flushed the receive processor is stopped
2991 and the transmitter is disabled. After these operations a
2992 4 uS delay is done before clearing the pointers to allow
2993 the receive processor to stop. These items are handled inside
2994 this function.
2995Warnings: No context switches are allowed while executing this function.
2996*/
f15313bf 2997static void sFlushRxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2998{
2999 int i;
3000 Byte_t Ch; /* channel number within AIOP */
f15313bf 3001 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
1da177e4
LT		 3002
3003 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3004 return; /* don't need to flush */
3005
f15313bf 3006 RxFIFOEnabled = 0;
1da177e4 3007 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
f15313bf 3008 RxFIFOEnabled = 1;
1da177e4
LT		 3009 sDisRxFIFO(ChP); /* disable it */
3010 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3011 sInB(ChP->IntChan); /* depends on bus i/o timing */
3012 }
3013 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3014 Ch = (Byte_t) sGetChanNum(ChP);
3015 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3016 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3017 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3018 sOutW(ChP->IndexData, 0);
3019 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3020 sOutW(ChP->IndexData, 0);
3021 if (RxFIFOEnabled)
3022 sEnRxFIFO(ChP); /* enable Rx FIFO */
3023}
3024
3025/***************************************************************************
3026Function: sFlushTxFIFO
3027Purpose: Flush the Tx FIFO
3028Call: sFlushTxFIFO(ChP)
3029 CHANNEL_T *ChP; Ptr to channel structure
3030Return: void
3031Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3032 while it is being flushed the receive processor is stopped
3033 and the transmitter is disabled. After these operations a
3034 4 uS delay is done before clearing the pointers to allow
3035 the receive processor to stop. These items are handled inside
3036 this function.
3037Warnings: No context switches are allowed while executing this function.
3038*/
f15313bf 3039static void sFlushTxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 3040{
3041 int i;
3042 Byte_t Ch; /* channel number within AIOP */
f15313bf 3043 int TxEnabled; /* 1 if transmitter enabled */
1da177e4
LT		 3044
3045 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3046 return; /* don't need to flush */
3047
f15313bf 3048 TxEnabled = 0;
1da177e4 3049 if (ChP->TxControl[3] & TX_ENABLE) {
f15313bf 3050 TxEnabled = 1;
1da177e4
LT		 3051 sDisTransmit(ChP); /* disable transmitter */
3052 }
3053 sStopRxProcessor(ChP); /* stop Rx processor */
3054 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3055 sInB(ChP->IntChan); /* depends on bus i/o timing */
3056 Ch = (Byte_t) sGetChanNum(ChP);
3057 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3058 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3059 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3060 sOutW(ChP->IndexData, 0);
3061 if (TxEnabled)
3062 sEnTransmit(ChP); /* enable transmitter */
3063 sStartRxProcessor(ChP); /* restart Rx processor */
3064}
3065
3066/***************************************************************************
3067Function: sWriteTxPrioByte
3068Purpose: Write a byte of priority transmit data to a channel
3069Call: sWriteTxPrioByte(ChP,Data)
3070 CHANNEL_T *ChP; Ptr to channel structure
3071 Byte_t Data; The transmit data byte
3072
3073Return: int: 1 if the bytes is successfully written, otherwise 0.
3074
3075Comments: The priority byte is transmitted before any data in the Tx FIFO.
3076
3077Warnings: No context switches are allowed while executing this function.
3078*/
f15313bf 3079static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
1da177e4
LT		 3080{
3081 Byte_t DWBuf[4]; /* buffer for double word writes */
3082 Word_t *WordPtr; /* must be far because Win SS != DS */
3083 register DWordIO_t IndexAddr;
3084
3085 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3086 IndexAddr = ChP->IndexAddr;
3087 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3088 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3089 return (0); /* nothing sent */
3090
3091 WordPtr = (Word_t *) (&DWBuf[0]);
3092 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3093
3094 DWBuf[2] = Data; /* data byte value */
3095 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
3096
3097 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3098
3099 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3100 DWBuf[3] = 0; /* priority buffer pointer */
3101 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
3102 } else { /* write it to Tx FIFO */
3103
3104 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3105 }
3106 return (1); /* 1 byte sent */
3107}
3108
3109/***************************************************************************
3110Function: sEnInterrupts
3111Purpose: Enable one or more interrupts for a channel
3112Call: sEnInterrupts(ChP,Flags)
3113 CHANNEL_T *ChP; Ptr to channel structure
3114 Word_t Flags: Interrupt enable flags, can be any combination
3115 of the following flags:
3116 TXINT_EN: Interrupt on Tx FIFO empty
3117 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3118 sSetRxTrigger())
3119 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3120 MCINT_EN: Interrupt on modem input change
3121 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3122 Interrupt Channel Register.
3123Return: void
3124Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3125 enabled. If an interrupt enable flag is not set in Flags, that
3126 interrupt will not be changed. Interrupts can be disabled with
3127 function sDisInterrupts().
3128
3129 This function sets the appropriate bit for the channel in the AIOP's
3130 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3131 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3132
3133 Interrupts must also be globally enabled before channel interrupts
3134 will be passed on to the host. This is done with function
3135 sEnGlobalInt().
3136
3137 In some cases it may be desirable to disable interrupts globally but
3138 enable channel interrupts. This would allow the global interrupt
3139 status register to be used to determine which AIOPs need service.
3140*/
f15313bf 3141static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3142{
3143 Byte_t Mask; /* Interrupt Mask Register */
3144
3145 ChP->RxControl[2] |=
3146 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3147
3148 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3149
3150 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3151
3152 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3153
3154 if (Flags & CHANINT_EN) {
3155 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3156 sOutB(ChP->IntMask, Mask);
3157 }
3158}
3159
3160/***************************************************************************
3161Function: sDisInterrupts
3162Purpose: Disable one or more interrupts for a channel
3163Call: sDisInterrupts(ChP,Flags)
3164 CHANNEL_T *ChP; Ptr to channel structure
3165 Word_t Flags: Interrupt flags, can be any combination
3166 of the following flags:
3167 TXINT_EN: Interrupt on Tx FIFO empty
3168 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3169 sSetRxTrigger())
3170 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3171 MCINT_EN: Interrupt on modem input change
3172 CHANINT_EN: Disable channel interrupt signal to the
3173 AIOP's Interrupt Channel Register.
3174Return: void
3175Comments: If an interrupt flag is set in Flags, that interrupt will be
3176 disabled. If an interrupt flag is not set in Flags, that
3177 interrupt will not be changed. Interrupts can be enabled with
3178 function sEnInterrupts().
3179
3180 This function clears the appropriate bit for the channel in the AIOP's
3181 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3182 this channel's bit from being set in the AIOP's Interrupt Channel
3183 Register.
3184*/
f15313bf 3185static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3186{
3187 Byte_t Mask; /* Interrupt Mask Register */
3188
3189 ChP->RxControl[2] &=
3190 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3191 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3192 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3193 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3194
3195 if (Flags & CHANINT_EN) {
3196 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3197 sOutB(ChP->IntMask, Mask);
3198 }
3199}
3200
f15313bf 3201static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
1da177e4
LT		 3202{
3203 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3204}
3205
3206/*
3207 * Not an official SSCI function, but how to reset RocketModems.
3208 * ISA bus version
3209 */
f15313bf 3210static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3211{
3212 ByteIO_t addr;
3213 Byte_t val;
3214
3215 addr = CtlP->AiopIO[0] + 0x400;
3216 val = sInB(CtlP->MReg3IO);
3217 /* if AIOP[1] is not enabled, enable it */
3218 if ((val & 2) == 0) {
3219 val = sInB(CtlP->MReg2IO);
3220 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3221 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3222 }
3223
3224 sEnAiop(CtlP, 1);
3225 if (!on)
3226 addr += 8;
3227 sOutB(addr + chan, 0); /* apply or remove reset */
3228 sDisAiop(CtlP, 1);
3229}
3230
3231/*
3232 * Not an official SSCI function, but how to reset RocketModems.
3233 * PCI bus version
3234 */
f15313bf 3235static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3236{
3237 ByteIO_t addr;
3238
3239 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3240 if (!on)
3241 addr += 8;
3242 sOutB(addr + chan, 0); /* apply or remove reset */
3243}
3244
3245/* Resets the speaker controller on RocketModem II and III devices */
3246static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3247{
3248 ByteIO_t addr;
3249
3250 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3251 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3252 addr = CtlP->AiopIO[0] + 0x4F;
3253 sOutB(addr, 0);
3254 }
3255
3256 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3257 if ((model == MODEL_UPCI_RM3_8PORT)
3258 || (model == MODEL_UPCI_RM3_4PORT)) {
3259 addr = CtlP->AiopIO[0] + 0x88;
3260 sOutB(addr, 0);
3261 }
3262}
3263
3264/* Returns the line number given the controller (board), aiop and channel number */
3265static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3266{
3267 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3268}
3269
3270/*
3271 * Stores the line number associated with a given controller (board), aiop
3272 * and channel number.
3273 * Returns: The line number assigned
3274 */
3275static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3276{
3277 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3278 return (nextLineNumber - 1);
3279}
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