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[binutils.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus ([email protected]).
3e73aa7c 25 x86_64 support by Jan Hubicka ([email protected])
0f10071e 26 VIA PadLock support by Michal Ludvig ([email protected])
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
6305a203
L		 117/* 386 opcode byte to code indirect addressing. */
118typedef struct
119{
120 unsigned base;
121 unsigned index;
122 unsigned scale;
123}
124sib_byte;
125
6305a203
L		 126/* x86 arch names, types and features */
127typedef struct
128{
129 const char *name; /* arch name */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132}
133arch_entry;
134
e3bb37b5
L		 135static void set_code_flag (int);
136static void set_16bit_gcc_code_flag (int);
137static void set_intel_syntax (int);
1efbbeb4 138static void set_intel_mnemonic (int);
db51cc60 139static void set_allow_index_reg (int);
cb19c032 140static void set_sse_check (int);
e3bb37b5 141static void set_cpu_arch (int);
6482c264 142#ifdef TE_PE
e3bb37b5 143static void pe_directive_secrel (int);
6482c264 144#endif
e3bb37b5
L		 145static void signed_cons (int);
146static char *output_invalid (int c);
ee86248c
JB		 147static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
148 const char *);
149static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
150 const char *);
a7619375 151static int i386_att_operand (char *);
e3bb37b5 152static int i386_intel_operand (char *, int);
ee86248c
JB		 153static int i386_intel_simplify (expressionS *);
154static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 155static const reg_entry *parse_register (char *, char **);
156static char *parse_insn (char *, char *);
157static char *parse_operands (char *, const char *);
158static void swap_operands (void);
4d456e3d 159static void swap_2_operands (int, int);
e3bb37b5
L		 160static void optimize_imm (void);
161static void optimize_disp (void);
fa99fab2 162static const template *match_template (void);
e3bb37b5
L		 163static int check_string (void);
164static int process_suffix (void);
165static int check_byte_reg (void);
166static int check_long_reg (void);
167static int check_qword_reg (void);
168static int check_word_reg (void);
169static int finalize_imm (void);
170static int process_operands (void);
171static const seg_entry *build_modrm_byte (void);
172static void output_insn (void);
173static void output_imm (fragS *, offsetT);
174static void output_disp (fragS *, offsetT);
29b0f896 175#ifndef I386COFF
e3bb37b5 176static void s_bss (int);
252b5132 177#endif
17d4e2a2
L		 178#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179static void handle_large_common (int small ATTRIBUTE_UNUSED);
180#endif
252b5132 181
a847613f 182static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 183
c0f3af97
L		 184/* VEX prefix. */
185typedef struct
186{
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes[3];
189 unsigned int length;
190 /* Destination or source register specifier. */
191 const reg_entry *register_specifier;
192} vex_prefix;
193
252b5132 194/* 'md_assemble ()' gathers together information and puts it into a
47926f60 195 i386_insn. */
252b5132 196
520dc8e8
AM		 197union i386_op
198 {
199 expressionS *disps;
200 expressionS *imms;
201 const reg_entry *regs;
202 };
203
252b5132
RH		 204struct _i386_insn
205 {
47926f60 206 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 207 template tm;
208
7d5e4556
L		 209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
252b5132
RH		 211 char suffix;
212
47926f60 213 /* OPERANDS gives the number of given operands. */
252b5132
RH		 214 unsigned int operands;
215
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
47926f60 218 operands. */
252b5132
RH		 219 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
220
221 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 222 use OP[i] for the corresponding operand. */
40fb9820 223 i386_operand_type types[MAX_OPERANDS];
252b5132 224
520dc8e8
AM		 225 /* Displacement expression, immediate expression, or register for each
226 operand. */
227 union i386_op op[MAX_OPERANDS];
252b5132 228
3e73aa7c
JH		 229 /* Flags for operands. */
230 unsigned int flags[MAX_OPERANDS];
231#define Operand_PCrel 1
232
252b5132 233 /* Relocation type for operand */
f86103b7 234 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 235
252b5132
RH		 236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry *base_reg;
239 const reg_entry *index_reg;
240 unsigned int log2_scale_factor;
241
242 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 243 explicit segment overrides are given. */
ce8a8b2f 244 const seg_entry *seg[2];
252b5132
RH		 245
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes;
249 unsigned char prefix[MAX_PREFIXES];
250
251 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 252 addressing modes of this insn are encoded. */
252b5132 253 modrm_byte rm;
3e73aa7c 254 rex_byte rex;
252b5132 255 sib_byte sib;
c0f3af97 256 vex_prefix vex;
b6169b20
L		 257
258 /* Swap operand in encoding. */
259 unsigned int swap_operand : 1;
252b5132
RH		 260 };
261
262typedef struct _i386_insn i386_insn;
263
264/* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
32137342 266const char extra_symbol_chars[] = "*%-(["
252b5132 267#ifdef LEX_AT
32137342
NC		 268 "@"
269#endif
270#ifdef LEX_QM
271 "?"
252b5132 272#endif
32137342 273 ;
252b5132 274
29b0f896
AM		 275#if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 277 && !defined (TE_GNU) \
29b0f896 278 && !defined (TE_LINUX) \
32137342 279 && !defined (TE_NETWARE) \
29b0f896
AM		 280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
252b5132 282/* This array holds the chars that always start a comment. If the
b3b91714
AM		 283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285const char *i386_comment_chars = "#/";
286#define SVR4_COMMENT_CHARS 1
252b5132 287#define PREFIX_SEPARATOR '\\'
252b5132 288
b3b91714
AM		 289#else
290const char *i386_comment_chars = "#";
291#define PREFIX_SEPARATOR '/'
292#endif
293
252b5132
RH		 294/* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 298 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
252b5132 301 '/' isn't otherwise defined. */
b3b91714 302const char line_comment_chars[] = "#/";
252b5132 303
63a0b638 304const char line_separator_chars[] = ";";
252b5132 305
ce8a8b2f
AM		 306/* Chars that can be used to separate mant from exp in floating point
307 nums. */
252b5132
RH		 308const char EXP_CHARS[] = "eE";
309
ce8a8b2f
AM		 310/* Chars that mean this number is a floating point constant
311 As in 0f12.456
312 or 0d1.2345e12. */
252b5132
RH		 313const char FLT_CHARS[] = "fFdDxX";
314
ce8a8b2f 315/* Tables for lexical analysis. */
252b5132
RH		 316static char mnemonic_chars[256];
317static char register_chars[256];
318static char operand_chars[256];
319static char identifier_chars[256];
320static char digit_chars[256];
321
ce8a8b2f 322/* Lexical macros. */
252b5132
RH		 323#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324#define is_operand_char(x) (operand_chars[(unsigned char) x])
325#define is_register_char(x) (register_chars[(unsigned char) x])
326#define is_space_char(x) ((x) == ' ')
327#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328#define is_digit_char(x) (digit_chars[(unsigned char) x])
329
0234cb7c 330/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 331static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
332
333/* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
47926f60 336 assembler instruction). */
252b5132 337static char save_stack[32];
ce8a8b2f 338static char *save_stack_p;
252b5132
RH		 339#define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341#define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
343
47926f60 344/* The instruction we're assembling. */
252b5132
RH		 345static i386_insn i;
346
347/* Possible templates for current insn. */
348static const templates *current_templates;
349
31b2323c
L		 350/* Per instruction expressionS buffers: max displacements & immediates. */
351static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
352static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 353
47926f60 354/* Current operand we are working on. */
ee86248c 355static int this_operand = -1;
252b5132 356
3e73aa7c
JH		 357/* We support four different modes. FLAG_CODE variable is used to distinguish
358 these. */
359
360enum flag_code {
361 CODE_32BIT,
362 CODE_16BIT,
363 CODE_64BIT };
364
365static enum flag_code flag_code;
4fa24527 366static unsigned int object_64bit;
3e73aa7c
JH		 367static int use_rela_relocations = 0;
368
369/* The names used to print error messages. */
b77a7acd 370static const char *flag_code_names[] =
3e73aa7c
JH		 371 {
372 "32",
373 "16",
374 "64"
375 };
252b5132 376
47926f60
KH		 377/* 1 for intel syntax,
378 0 if att syntax. */
379static int intel_syntax = 0;
252b5132 380
1efbbeb4
L		 381/* 1 for intel mnemonic,
382 0 if att mnemonic. */
383static int intel_mnemonic = !SYSV386_COMPAT;
384
5209009a 385/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 386static int old_gcc = OLDGCC_COMPAT;
387
a60de03c
JB		 388/* 1 if pseudo registers are permitted. */
389static int allow_pseudo_reg = 0;
390
47926f60
KH		 391/* 1 if register prefix % not required. */
392static int allow_naked_reg = 0;
252b5132 393
ba104c83 394/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 395static int allow_index_reg = 0;
396
daf50ae7
L		 397static enum
398 {
399 sse_check_none = 0,
400 sse_check_warning,
401 sse_check_error
402 }
403sse_check;
404
2ca3ace5
L		 405/* Register prefix used for error message. */
406static const char *register_prefix = "%";
407
47926f60
KH		 408/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411static char stackop_size = '\0';
eecb386c 412
12b55ccc
L		 413/* Non-zero to optimize code alignment. */
414int optimize_align_code = 1;
415
47926f60
KH		 416/* Non-zero to quieten some warnings. */
417static int quiet_warnings = 0;
a38cf1db 418
47926f60
KH		 419/* CPU name. */
420static const char *cpu_arch_name = NULL;
6305a203 421static char *cpu_sub_arch_name = NULL;
a38cf1db 422
47926f60 423/* CPU feature flags. */
40fb9820
L		 424static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
425
ccc9c027
L		 426/* If we have selected a cpu we are generating instructions for. */
427static int cpu_arch_tune_set = 0;
428
9103f4f4 429/* Cpu we are generating instructions for. */
fbf3f584 430enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 431
432/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 433static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 434
ccc9c027 435/* CPU instruction set architecture used. */
fbf3f584 436enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 437
9103f4f4 438/* CPU feature flags of instruction set architecture used. */
fbf3f584 439i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 440
fddf5b5b
AM		 441/* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443static unsigned int no_cond_jump_promotion = 0;
444
c0f3af97
L		 445/* Encode SSE instructions with VEX prefix. */
446static unsigned int sse2avx;
447
29b0f896 448/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 449static symbolS *GOT_symbol;
29b0f896 450
a4447b93
RH		 451/* The dwarf2 return column, adjusted for 32 or 64 bit. */
452unsigned int x86_dwarf2_return_column;
453
454/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455int x86_cie_data_alignment;
456
252b5132 457/* Interface to relax_segment.
fddf5b5b
AM		 458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
252b5132 461
47926f60 462/* Types. */
93c2a809
AM		 463#define UNCOND_JUMP 0
464#define COND_JUMP 1
465#define COND_JUMP86 2
fddf5b5b 466
47926f60 467/* Sizes. */
252b5132
RH		 468#define CODE16 1
469#define SMALL 0
29b0f896 470#define SMALL16 (SMALL | CODE16)
252b5132 471#define BIG 2
29b0f896 472#define BIG16 (BIG | CODE16)
252b5132
RH		 473
474#ifndef INLINE
475#ifdef __GNUC__
476#define INLINE __inline__
477#else
478#define INLINE
479#endif
480#endif
481
fddf5b5b
AM		 482#define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484#define TYPE_FROM_RELAX_STATE(s) \
485 ((s) >> 2)
486#define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 488
489/* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
496
497const relax_typeS md_relax_table[] =
498{
24eab124
AM		 499 /* The fields are:
500 1) most positive reach of this state,
501 2) most negative reach of this state,
93c2a809 502 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 503 4) which index into the table to try if we can't fit into this one. */
252b5132 504
fddf5b5b 505 /* UNCOND_JUMP states. */
93c2a809
AM		 506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
252b5132 510 {0, 0, 4, 0},
93c2a809
AM		 511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 513 {0, 0, 2, 0},
514
93c2a809
AM		 515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
520 {0, 0, 5, 0},
fddf5b5b 521 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 522 1 extra opcode byte, 2 displacement bytes. */
523 {0, 0, 3, 0},
524
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
530 {0, 0, 5, 0},
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
533 {0, 0, 4, 0}
252b5132
RH		 534};
535
9103f4f4
L		 536static const arch_entry cpu_arch[] =
537{
6305a203
L		 538 { "generic32", PROCESSOR_GENERIC32,
539 CPU_GENERIC32_FLAGS },
540 { "generic64", PROCESSOR_GENERIC64,
541 CPU_GENERIC64_FLAGS },
542 { "i8086", PROCESSOR_UNKNOWN,
543 CPU_NONE_FLAGS },
544 { "i186", PROCESSOR_UNKNOWN,
545 CPU_I186_FLAGS },
546 { "i286", PROCESSOR_UNKNOWN,
547 CPU_I286_FLAGS },
548 { "i386", PROCESSOR_I386,
549 CPU_I386_FLAGS },
550 { "i486", PROCESSOR_I486,
551 CPU_I486_FLAGS },
552 { "i586", PROCESSOR_PENTIUM,
553 CPU_I586_FLAGS },
554 { "i686", PROCESSOR_PENTIUMPRO,
555 CPU_I686_FLAGS },
556 { "pentium", PROCESSOR_PENTIUM,
557 CPU_I586_FLAGS },
558 { "pentiumpro", PROCESSOR_PENTIUMPRO,
559 CPU_I686_FLAGS },
560 { "pentiumii", PROCESSOR_PENTIUMPRO,
561 CPU_P2_FLAGS },
562 { "pentiumiii",PROCESSOR_PENTIUMPRO,
563 CPU_P3_FLAGS },
564 { "pentium4", PROCESSOR_PENTIUM4,
565 CPU_P4_FLAGS },
566 { "prescott", PROCESSOR_NOCONA,
567 CPU_CORE_FLAGS },
568 { "nocona", PROCESSOR_NOCONA,
569 CPU_NOCONA_FLAGS },
570 { "yonah", PROCESSOR_CORE,
571 CPU_CORE_FLAGS },
572 { "core", PROCESSOR_CORE,
573 CPU_CORE_FLAGS },
574 { "merom", PROCESSOR_CORE2,
575 CPU_CORE2_FLAGS },
576 { "core2", PROCESSOR_CORE2,
577 CPU_CORE2_FLAGS },
bd5295b2
L		 578 { "corei7", PROCESSOR_COREI7,
579 CPU_COREI7_FLAGS },
6305a203
L		 580 { "k6", PROCESSOR_K6,
581 CPU_K6_FLAGS },
582 { "k6_2", PROCESSOR_K6,
583 CPU_K6_2_FLAGS },
584 { "athlon", PROCESSOR_ATHLON,
585 CPU_ATHLON_FLAGS },
586 { "sledgehammer", PROCESSOR_K8,
587 CPU_K8_FLAGS },
588 { "opteron", PROCESSOR_K8,
589 CPU_K8_FLAGS },
590 { "k8", PROCESSOR_K8,
591 CPU_K8_FLAGS },
592 { "amdfam10", PROCESSOR_AMDFAM10,
593 CPU_AMDFAM10_FLAGS },
309d3373
JB		 594 { ".8087", PROCESSOR_UNKNOWN,
595 CPU_8087_FLAGS },
596 { ".287", PROCESSOR_UNKNOWN,
597 CPU_287_FLAGS },
598 { ".387", PROCESSOR_UNKNOWN,
599 CPU_387_FLAGS },
600 { ".no87", PROCESSOR_UNKNOWN,
601 CPU_ANY87_FLAGS },
6305a203
L		 602 { ".mmx", PROCESSOR_UNKNOWN,
603 CPU_MMX_FLAGS },
309d3373
JB		 604 { ".nommx", PROCESSOR_UNKNOWN,
605 CPU_3DNOWA_FLAGS },
6305a203
L		 606 { ".sse", PROCESSOR_UNKNOWN,
607 CPU_SSE_FLAGS },
608 { ".sse2", PROCESSOR_UNKNOWN,
609 CPU_SSE2_FLAGS },
610 { ".sse3", PROCESSOR_UNKNOWN,
611 CPU_SSE3_FLAGS },
612 { ".ssse3", PROCESSOR_UNKNOWN,
613 CPU_SSSE3_FLAGS },
614 { ".sse4.1", PROCESSOR_UNKNOWN,
615 CPU_SSE4_1_FLAGS },
616 { ".sse4.2", PROCESSOR_UNKNOWN,
617 CPU_SSE4_2_FLAGS },
618 { ".sse4", PROCESSOR_UNKNOWN,
619 CPU_SSE4_2_FLAGS },
309d3373
JB		 620 { ".nosse", PROCESSOR_UNKNOWN,
621 CPU_ANY_SSE_FLAGS },
c0f3af97
L		 622 { ".avx", PROCESSOR_UNKNOWN,
623 CPU_AVX_FLAGS },
309d3373
JB		 624 { ".noavx", PROCESSOR_UNKNOWN,
625 CPU_ANY_AVX_FLAGS },
6305a203
L		 626 { ".vmx", PROCESSOR_UNKNOWN,
627 CPU_VMX_FLAGS },
628 { ".smx", PROCESSOR_UNKNOWN,
629 CPU_SMX_FLAGS },
f03fe4c1
L		 630 { ".xsave", PROCESSOR_UNKNOWN,
631 CPU_XSAVE_FLAGS },
c0f3af97
L		 632 { ".aes", PROCESSOR_UNKNOWN,
633 CPU_AES_FLAGS },
594ab6a3
L		 634 { ".pclmul", PROCESSOR_UNKNOWN,
635 CPU_PCLMUL_FLAGS },
c0f3af97 636 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 637 CPU_PCLMUL_FLAGS },
c0f3af97
L		 638 { ".fma", PROCESSOR_UNKNOWN,
639 CPU_FMA_FLAGS },
922d8de8
DR		 640 { ".fma4", PROCESSOR_UNKNOWN,
641 CPU_FMA4_FLAGS },
f1f8f695
L		 642 { ".movbe", PROCESSOR_UNKNOWN,
643 CPU_MOVBE_FLAGS },
644 { ".ept", PROCESSOR_UNKNOWN,
645 CPU_EPT_FLAGS },
bd5295b2
L		 646 { ".clflush", PROCESSOR_UNKNOWN,
647 CPU_CLFLUSH_FLAGS },
648 { ".syscall", PROCESSOR_UNKNOWN,
649 CPU_SYSCALL_FLAGS },
1b7f3fb0
L		 650 { ".rdtscp", PROCESSOR_UNKNOWN,
651 CPU_RDTSCP_FLAGS },
6305a203
L		 652 { ".3dnow", PROCESSOR_UNKNOWN,
653 CPU_3DNOW_FLAGS },
654 { ".3dnowa", PROCESSOR_UNKNOWN,
655 CPU_3DNOWA_FLAGS },
656 { ".padlock", PROCESSOR_UNKNOWN,
657 CPU_PADLOCK_FLAGS },
658 { ".pacifica", PROCESSOR_UNKNOWN,
659 CPU_SVME_FLAGS },
660 { ".svme", PROCESSOR_UNKNOWN,
661 CPU_SVME_FLAGS },
662 { ".sse4a", PROCESSOR_UNKNOWN,
663 CPU_SSE4A_FLAGS },
664 { ".abm", PROCESSOR_UNKNOWN,
665 CPU_ABM_FLAGS },
e413e4e9
AM		 666};
667
704209c0 668#ifdef I386COFF
a6c24e68
NC		 669/* Like s_lcomm_internal in gas/read.c but the alignment string
670 is allowed to be optional. */
671
672static symbolS *
673pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
674{
675 addressT align = 0;
676
677 SKIP_WHITESPACE ();
678
7ab9ffdd 679 if (needs_align
a6c24e68
NC		 680 && *input_line_pointer == ',')
681 {
682 align = parse_align (needs_align - 1);
7ab9ffdd 683
a6c24e68
NC		 684 if (align == (addressT) -1)
685 return NULL;
686 }
687 else
688 {
689 if (size >= 8)
690 align = 3;
691 else if (size >= 4)
692 align = 2;
693 else if (size >= 2)
694 align = 1;
695 else
696 align = 0;
697 }
698
699 bss_alloc (symbolP, size, align);
700 return symbolP;
701}
702
704209c0 703static void
a6c24e68
NC		 704pe_lcomm (int needs_align)
705{
706 s_comm_internal (needs_align * 2, pe_lcomm_internal);
707}
704209c0 708#endif
a6c24e68 709
29b0f896
AM		 710const pseudo_typeS md_pseudo_table[] =
711{
712#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
713 {"align", s_align_bytes, 0},
714#else
715 {"align", s_align_ptwo, 0},
716#endif
717 {"arch", set_cpu_arch, 0},
718#ifndef I386COFF
719 {"bss", s_bss, 0},
a6c24e68
NC		 720#else
721 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 722#endif
723 {"ffloat", float_cons, 'f'},
724 {"dfloat", float_cons, 'd'},
725 {"tfloat", float_cons, 'x'},
726 {"value", cons, 2},
d182319b 727 {"slong", signed_cons, 4},
29b0f896
AM		 728 {"noopt", s_ignore, 0},
729 {"optim", s_ignore, 0},
730 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
731 {"code16", set_code_flag, CODE_16BIT},
732 {"code32", set_code_flag, CODE_32BIT},
733 {"code64", set_code_flag, CODE_64BIT},
734 {"intel_syntax", set_intel_syntax, 1},
735 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 736 {"intel_mnemonic", set_intel_mnemonic, 1},
737 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 738 {"allow_index_reg", set_allow_index_reg, 1},
739 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 740 {"sse_check", set_sse_check, 0},
3b22753a
L		 741#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
742 {"largecomm", handle_large_common, 0},
07a53e5c 743#else
e3bb37b5 744 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 745 {"loc", dwarf2_directive_loc, 0},
746 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 747#endif
6482c264
NC		 748#ifdef TE_PE
749 {"secrel32", pe_directive_secrel, 0},
750#endif
29b0f896
AM		 751 {0, 0, 0}
752};
753
754/* For interface with expression (). */
755extern char *input_line_pointer;
756
757/* Hash table for instruction mnemonic lookup. */
758static struct hash_control *op_hash;
759
760/* Hash table for register lookup. */
761static struct hash_control *reg_hash;
762\f
252b5132 763void
e3bb37b5 764i386_align_code (fragS *fragP, int count)
252b5132 765{
ce8a8b2f
AM		 766 /* Various efficient no-op patterns for aligning code labels.
767 Note: Don't try to assemble the instructions in the comments.
768 0L and 0w are not legal. */
252b5132
RH		 769 static const char f32_1[] =
770 {0x90}; /* nop */
771 static const char f32_2[] =
ccc9c027 772 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 773 static const char f32_3[] =
774 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
775 static const char f32_4[] =
776 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
777 static const char f32_5[] =
778 {0x90, /* nop */
779 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
780 static const char f32_6[] =
781 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
782 static const char f32_7[] =
783 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
784 static const char f32_8[] =
785 {0x90, /* nop */
786 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
787 static const char f32_9[] =
788 {0x89,0xf6, /* movl %esi,%esi */
789 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
790 static const char f32_10[] =
791 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
792 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
793 static const char f32_11[] =
794 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
795 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
796 static const char f32_12[] =
797 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
798 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
799 static const char f32_13[] =
800 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
801 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
802 static const char f32_14[] =
803 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 805 static const char f16_3[] =
806 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 807 static const char f16_4[] =
808 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
809 static const char f16_5[] =
810 {0x90, /* nop */
811 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
812 static const char f16_6[] =
813 {0x89,0xf6, /* mov %si,%si */
814 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
815 static const char f16_7[] =
816 {0x8d,0x74,0x00, /* lea 0(%si),%si */
817 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
818 static const char f16_8[] =
819 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
820 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 821 static const char jump_31[] =
822 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
823 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
824 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
825 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 826 static const char *const f32_patt[] = {
827 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 828 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 829 };
830 static const char *const f16_patt[] = {
76bc74dc 831 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 832 };
ccc9c027
L		 833 /* nopl (%[re]ax) */
834 static const char alt_3[] =
835 {0x0f,0x1f,0x00};
836 /* nopl 0(%[re]ax) */
837 static const char alt_4[] =
838 {0x0f,0x1f,0x40,0x00};
839 /* nopl 0(%[re]ax,%[re]ax,1) */
840 static const char alt_5[] =
841 {0x0f,0x1f,0x44,0x00,0x00};
842 /* nopw 0(%[re]ax,%[re]ax,1) */
843 static const char alt_6[] =
844 {0x66,0x0f,0x1f,0x44,0x00,0x00};
845 /* nopl 0L(%[re]ax) */
846 static const char alt_7[] =
847 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
848 /* nopl 0L(%[re]ax,%[re]ax,1) */
849 static const char alt_8[] =
850 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
851 /* nopw 0L(%[re]ax,%[re]ax,1) */
852 static const char alt_9[] =
853 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
854 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
855 static const char alt_10[] =
856 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
857 /* data16
858 nopw %cs:0L(%[re]ax,%[re]ax,1) */
859 static const char alt_long_11[] =
860 {0x66,
861 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* data16
863 data16
864 nopw %cs:0L(%[re]ax,%[re]ax,1) */
865 static const char alt_long_12[] =
866 {0x66,
867 0x66,
868 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 /* data16
870 data16
871 data16
872 nopw %cs:0L(%[re]ax,%[re]ax,1) */
873 static const char alt_long_13[] =
874 {0x66,
875 0x66,
876 0x66,
877 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
878 /* data16
879 data16
880 data16
881 data16
882 nopw %cs:0L(%[re]ax,%[re]ax,1) */
883 static const char alt_long_14[] =
884 {0x66,
885 0x66,
886 0x66,
887 0x66,
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 /* data16
890 data16
891 data16
892 data16
893 data16
894 nopw %cs:0L(%[re]ax,%[re]ax,1) */
895 static const char alt_long_15[] =
896 {0x66,
897 0x66,
898 0x66,
899 0x66,
900 0x66,
901 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
902 /* nopl 0(%[re]ax,%[re]ax,1)
903 nopw 0(%[re]ax,%[re]ax,1) */
904 static const char alt_short_11[] =
905 {0x0f,0x1f,0x44,0x00,0x00,
906 0x66,0x0f,0x1f,0x44,0x00,0x00};
907 /* nopw 0(%[re]ax,%[re]ax,1)
908 nopw 0(%[re]ax,%[re]ax,1) */
909 static const char alt_short_12[] =
910 {0x66,0x0f,0x1f,0x44,0x00,0x00,
911 0x66,0x0f,0x1f,0x44,0x00,0x00};
912 /* nopw 0(%[re]ax,%[re]ax,1)
913 nopl 0L(%[re]ax) */
914 static const char alt_short_13[] =
915 {0x66,0x0f,0x1f,0x44,0x00,0x00,
916 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
917 /* nopl 0L(%[re]ax)
918 nopl 0L(%[re]ax) */
919 static const char alt_short_14[] =
920 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
921 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
922 /* nopl 0L(%[re]ax)
923 nopl 0L(%[re]ax,%[re]ax,1) */
924 static const char alt_short_15[] =
925 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
926 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
927 static const char *const alt_short_patt[] = {
928 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
929 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
930 alt_short_14, alt_short_15
931 };
932 static const char *const alt_long_patt[] = {
933 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
934 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
935 alt_long_14, alt_long_15
936 };
252b5132 937
76bc74dc
L		 938 /* Only align for at least a positive non-zero boundary. */
939 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 940 return;
3e73aa7c 941
ccc9c027
L		 942 /* We need to decide which NOP sequence to use for 32bit and
943 64bit. When -mtune= is used:
4eed87de 944
76bc74dc
L		 945 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
946 PROCESSOR_GENERIC32, f32_patt will be used.
947 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 948 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
949 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 950 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
951 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 952
76bc74dc
L		 953 When -mtune= isn't used, alt_long_patt will be used if
954 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
955 be used.
ccc9c027
L		 956
957 When -march= or .arch is used, we can't use anything beyond
958 cpu_arch_isa_flags. */
959
960 if (flag_code == CODE_16BIT)
961 {
ccc9c027 962 if (count > 8)
33fef721 963 {
76bc74dc
L		 964 memcpy (fragP->fr_literal + fragP->fr_fix,
965 jump_31, count);
966 /* Adjust jump offset. */
967 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 968 }
76bc74dc
L		 969 else
970 memcpy (fragP->fr_literal + fragP->fr_fix,
971 f16_patt[count - 1], count);
252b5132 972 }
33fef721 973 else
ccc9c027
L		 974 {
975 const char *const *patt = NULL;
976
fbf3f584 977 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 978 {
979 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
980 switch (cpu_arch_tune)
981 {
982 case PROCESSOR_UNKNOWN:
983 /* We use cpu_arch_isa_flags to check if we SHOULD
984 optimize for Cpu686. */
fbf3f584 985 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 986 patt = alt_long_patt;
ccc9c027
L		 987 else
988 patt = f32_patt;
989 break;
ccc9c027
L		 990 case PROCESSOR_PENTIUMPRO:
991 case PROCESSOR_PENTIUM4:
992 case PROCESSOR_NOCONA:
ef05d495 993 case PROCESSOR_CORE:
76bc74dc 994 case PROCESSOR_CORE2:
bd5295b2 995 case PROCESSOR_COREI7:
76bc74dc
L		 996 case PROCESSOR_GENERIC64:
997 patt = alt_long_patt;
998 break;
ccc9c027
L		 999 case PROCESSOR_K6:
1000 case PROCESSOR_ATHLON:
1001 case PROCESSOR_K8:
4eed87de 1002 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1003 patt = alt_short_patt;
1004 break;
76bc74dc 1005 case PROCESSOR_I386:
ccc9c027
L		 1006 case PROCESSOR_I486:
1007 case PROCESSOR_PENTIUM:
1008 case PROCESSOR_GENERIC32:
1009 patt = f32_patt;
1010 break;
4eed87de 1011 }
ccc9c027
L		 1012 }
1013 else
1014 {
fbf3f584 1015 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1016 {
1017 case PROCESSOR_UNKNOWN:
e6a14101 1018 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1019 PROCESSOR_UNKNOWN. */
1020 abort ();
1021 break;
1022
76bc74dc 1023 case PROCESSOR_I386:
ccc9c027
L		 1024 case PROCESSOR_I486:
1025 case PROCESSOR_PENTIUM:
ccc9c027
L		 1026 case PROCESSOR_K6:
1027 case PROCESSOR_ATHLON:
1028 case PROCESSOR_K8:
4eed87de 1029 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1030 case PROCESSOR_GENERIC32:
1031 /* We use cpu_arch_isa_flags to check if we CAN optimize
1032 for Cpu686. */
fbf3f584 1033 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1034 patt = alt_short_patt;
1035 else
1036 patt = f32_patt;
1037 break;
76bc74dc
L		 1038 case PROCESSOR_PENTIUMPRO:
1039 case PROCESSOR_PENTIUM4:
1040 case PROCESSOR_NOCONA:
1041 case PROCESSOR_CORE:
ef05d495 1042 case PROCESSOR_CORE2:
bd5295b2 1043 case PROCESSOR_COREI7:
fbf3f584 1044 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1045 patt = alt_long_patt;
1046 else
1047 patt = f32_patt;
1048 break;
1049 case PROCESSOR_GENERIC64:
76bc74dc 1050 patt = alt_long_patt;
ccc9c027 1051 break;
4eed87de 1052 }
ccc9c027
L		 1053 }
1054
76bc74dc
L		 1055 if (patt == f32_patt)
1056 {
1057 /* If the padding is less than 15 bytes, we use the normal
1058 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1059 its offset. */
1060 int limit;
1061
1062 /* For 64bit, the limit is 3 bytes. */
1063 if (flag_code == CODE_64BIT
1064 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1065 limit = 3;
1066 else
1067 limit = 15;
1068 if (count < limit)
76bc74dc
L		 1069 memcpy (fragP->fr_literal + fragP->fr_fix,
1070 patt[count - 1], count);
1071 else
1072 {
1073 memcpy (fragP->fr_literal + fragP->fr_fix,
1074 jump_31, count);
1075 /* Adjust jump offset. */
1076 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1077 }
1078 }
1079 else
1080 {
1081 /* Maximum length of an instruction is 15 byte. If the
1082 padding is greater than 15 bytes and we don't use jump,
1083 we have to break it into smaller pieces. */
1084 int padding = count;
1085 while (padding > 15)
1086 {
1087 padding -= 15;
1088 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1089 patt [14], 15);
1090 }
1091
1092 if (padding)
1093 memcpy (fragP->fr_literal + fragP->fr_fix,
1094 patt [padding - 1], padding);
1095 }
ccc9c027 1096 }
33fef721 1097 fragP->fr_var = count;
252b5132
RH		 1098}
1099
c6fb90c8 1100static INLINE int
0dfbf9d7 1101operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1102{
0dfbf9d7 1103 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1104 {
1105 case 3:
0dfbf9d7 1106 if (x->array[2])
c6fb90c8
L		 1107 return 0;
1108 case 2:
0dfbf9d7 1109 if (x->array[1])
c6fb90c8
L		 1110 return 0;
1111 case 1:
0dfbf9d7 1112 return !x->array[0];
c6fb90c8
L		 1113 default:
1114 abort ();
1115 }
40fb9820
L		 1116}
1117
c6fb90c8 1118static INLINE void
0dfbf9d7 1119operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1120{
0dfbf9d7 1121 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1122 {
1123 case 3:
0dfbf9d7 1124 x->array[2] = v;
c6fb90c8 1125 case 2:
0dfbf9d7 1126 x->array[1] = v;
c6fb90c8 1127 case 1:
0dfbf9d7 1128 x->array[0] = v;
c6fb90c8
L		 1129 break;
1130 default:
1131 abort ();
1132 }
1133}
40fb9820 1134
c6fb90c8 1135static INLINE int
0dfbf9d7
L		 1136operand_type_equal (const union i386_operand_type *x,
1137 const union i386_operand_type *y)
c6fb90c8 1138{
0dfbf9d7 1139 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1140 {
1141 case 3:
0dfbf9d7 1142 if (x->array[2] != y->array[2])
c6fb90c8
L		 1143 return 0;
1144 case 2:
0dfbf9d7 1145 if (x->array[1] != y->array[1])
c6fb90c8
L		 1146 return 0;
1147 case 1:
0dfbf9d7 1148 return x->array[0] == y->array[0];
c6fb90c8
L		 1149 break;
1150 default:
1151 abort ();
1152 }
1153}
40fb9820 1154
0dfbf9d7
L		 1155static INLINE int
1156cpu_flags_all_zero (const union i386_cpu_flags *x)
1157{
1158 switch (ARRAY_SIZE(x->array))
1159 {
1160 case 3:
1161 if (x->array[2])
1162 return 0;
1163 case 2:
1164 if (x->array[1])
1165 return 0;
1166 case 1:
1167 return !x->array[0];
1168 default:
1169 abort ();
1170 }
1171}
1172
1173static INLINE void
1174cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1175{
1176 switch (ARRAY_SIZE(x->array))
1177 {
1178 case 3:
1179 x->array[2] = v;
1180 case 2:
1181 x->array[1] = v;
1182 case 1:
1183 x->array[0] = v;
1184 break;
1185 default:
1186 abort ();
1187 }
1188}
1189
1190static INLINE int
1191cpu_flags_equal (const union i386_cpu_flags *x,
1192 const union i386_cpu_flags *y)
1193{
1194 switch (ARRAY_SIZE(x->array))
1195 {
1196 case 3:
1197 if (x->array[2] != y->array[2])
1198 return 0;
1199 case 2:
1200 if (x->array[1] != y->array[1])
1201 return 0;
1202 case 1:
1203 return x->array[0] == y->array[0];
1204 break;
1205 default:
1206 abort ();
1207 }
1208}
c6fb90c8
L		 1209
1210static INLINE int
1211cpu_flags_check_cpu64 (i386_cpu_flags f)
1212{
1213 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1214 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1215}
1216
c6fb90c8
L		 1217static INLINE i386_cpu_flags
1218cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1219{
c6fb90c8
L		 1220 switch (ARRAY_SIZE (x.array))
1221 {
1222 case 3:
1223 x.array [2] &= y.array [2];
1224 case 2:
1225 x.array [1] &= y.array [1];
1226 case 1:
1227 x.array [0] &= y.array [0];
1228 break;
1229 default:
1230 abort ();
1231 }
1232 return x;
1233}
40fb9820 1234
c6fb90c8
L		 1235static INLINE i386_cpu_flags
1236cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1237{
c6fb90c8 1238 switch (ARRAY_SIZE (x.array))
40fb9820 1239 {
c6fb90c8
L		 1240 case 3:
1241 x.array [2] |= y.array [2];
1242 case 2:
1243 x.array [1] |= y.array [1];
1244 case 1:
1245 x.array [0] |= y.array [0];
40fb9820
L		 1246 break;
1247 default:
1248 abort ();
1249 }
40fb9820
L		 1250 return x;
1251}
1252
309d3373
JB		 1253static INLINE i386_cpu_flags
1254cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1255{
1256 switch (ARRAY_SIZE (x.array))
1257 {
1258 case 3:
1259 x.array [2] &= ~y.array [2];
1260 case 2:
1261 x.array [1] &= ~y.array [1];
1262 case 1:
1263 x.array [0] &= ~y.array [0];
1264 break;
1265 default:
1266 abort ();
1267 }
1268 return x;
1269}
1270
c0f3af97
L		 1271#define CPU_FLAGS_ARCH_MATCH 0x1
1272#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1273#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1274#define CPU_FLAGS_PCLMUL_MATCH 0x8
1275#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1276
a5ff0eb2 1277#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1278 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1279 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1280#define CPU_FLAGS_PERFECT_MATCH \
1281 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1282
1283/* Return CPU flags match bits. */
3629bb00 1284
40fb9820 1285static int
c0f3af97 1286cpu_flags_match (const template *t)
40fb9820 1287{
c0f3af97
L		 1288 i386_cpu_flags x = t->cpu_flags;
1289 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1290
1291 x.bitfield.cpu64 = 0;
1292 x.bitfield.cpuno64 = 0;
1293
0dfbf9d7 1294 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1295 {
1296 /* This instruction is available on all archs. */
1297 match |= CPU_FLAGS_32BIT_MATCH;
1298 }
3629bb00
L		 1299 else
1300 {
c0f3af97 1301 /* This instruction is available only on some archs. */
3629bb00
L		 1302 i386_cpu_flags cpu = cpu_arch_flags;
1303
1304 cpu.bitfield.cpu64 = 0;
1305 cpu.bitfield.cpuno64 = 0;
1306 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1307 if (!cpu_flags_all_zero (&cpu))
1308 {
a5ff0eb2
L		 1309 if (x.bitfield.cpuavx)
1310 {
ce2f5b3c 1311 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1312 if (cpu.bitfield.cpuavx)
1313 {
1314 /* Check SSE2AVX. */
1315 if (!t->opcode_modifier.sse2avx|| sse2avx)
1316 {
1317 match |= (CPU_FLAGS_ARCH_MATCH
1318 | CPU_FLAGS_AVX_MATCH);
1319 /* Check AES. */
1320 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1321 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1322 /* Check PCLMUL. */
1323 if (!x.bitfield.cpupclmul
1324 || cpu.bitfield.cpupclmul)
1325 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1326 }
1327 }
1328 else
1329 match |= CPU_FLAGS_ARCH_MATCH;
1330 }
1331 else
c0f3af97
L		 1332 match |= CPU_FLAGS_32BIT_MATCH;
1333 }
3629bb00 1334 }
c0f3af97 1335 return match;
40fb9820
L		 1336}
1337
c6fb90c8
L		 1338static INLINE i386_operand_type
1339operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1340{
c6fb90c8
L		 1341 switch (ARRAY_SIZE (x.array))
1342 {
1343 case 3:
1344 x.array [2] &= y.array [2];
1345 case 2:
1346 x.array [1] &= y.array [1];
1347 case 1:
1348 x.array [0] &= y.array [0];
1349 break;
1350 default:
1351 abort ();
1352 }
1353 return x;
40fb9820
L		 1354}
1355
c6fb90c8
L		 1356static INLINE i386_operand_type
1357operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1358{
c6fb90c8 1359 switch (ARRAY_SIZE (x.array))
40fb9820 1360 {
c6fb90c8
L		 1361 case 3:
1362 x.array [2] |= y.array [2];
1363 case 2:
1364 x.array [1] |= y.array [1];
1365 case 1:
1366 x.array [0] |= y.array [0];
40fb9820
L		 1367 break;
1368 default:
1369 abort ();
1370 }
c6fb90c8
L		 1371 return x;
1372}
40fb9820 1373
c6fb90c8
L		 1374static INLINE i386_operand_type
1375operand_type_xor (i386_operand_type x, i386_operand_type y)
1376{
1377 switch (ARRAY_SIZE (x.array))
1378 {
1379 case 3:
1380 x.array [2] ^= y.array [2];
1381 case 2:
1382 x.array [1] ^= y.array [1];
1383 case 1:
1384 x.array [0] ^= y.array [0];
1385 break;
1386 default:
1387 abort ();
1388 }
40fb9820
L		 1389 return x;
1390}
1391
1392static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1393static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1394static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1395static const i386_operand_type inoutportreg
1396 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1397static const i386_operand_type reg16_inoutportreg
1398 = OPERAND_TYPE_REG16_INOUTPORTREG;
1399static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1400static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1401static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1402static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1403static const i386_operand_type anydisp
1404 = OPERAND_TYPE_ANYDISP;
40fb9820 1405static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1406static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1407static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1408static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1409static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1410static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1411static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1412static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1413static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1414static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1415static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1416
1417enum operand_type
1418{
1419 reg,
40fb9820
L		 1420 imm,
1421 disp,
1422 anymem
1423};
1424
c6fb90c8 1425static INLINE int
40fb9820
L		 1426operand_type_check (i386_operand_type t, enum operand_type c)
1427{
1428 switch (c)
1429 {
1430 case reg:
1431 return (t.bitfield.reg8
1432 || t.bitfield.reg16
1433 || t.bitfield.reg32
1434 || t.bitfield.reg64);
1435
40fb9820
L		 1436 case imm:
1437 return (t.bitfield.imm8
1438 || t.bitfield.imm8s
1439 || t.bitfield.imm16
1440 || t.bitfield.imm32
1441 || t.bitfield.imm32s
1442 || t.bitfield.imm64);
1443
1444 case disp:
1445 return (t.bitfield.disp8
1446 || t.bitfield.disp16
1447 || t.bitfield.disp32
1448 || t.bitfield.disp32s
1449 || t.bitfield.disp64);
1450
1451 case anymem:
1452 return (t.bitfield.disp8
1453 || t.bitfield.disp16
1454 || t.bitfield.disp32
1455 || t.bitfield.disp32s
1456 || t.bitfield.disp64
1457 || t.bitfield.baseindex);
1458
1459 default:
1460 abort ();
1461 }
2cfe26b6
AM		 1462
1463 return 0;
40fb9820
L		 1464}
1465
5c07affc
L		 1466/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1467 operand J for instruction template T. */
1468
1469static INLINE int
1470match_reg_size (const template *t, unsigned int j)
1471{
1472 return !((i.types[j].bitfield.byte
1473 && !t->operand_types[j].bitfield.byte)
1474 || (i.types[j].bitfield.word
1475 && !t->operand_types[j].bitfield.word)
1476 || (i.types[j].bitfield.dword
1477 && !t->operand_types[j].bitfield.dword)
1478 || (i.types[j].bitfield.qword
1479 && !t->operand_types[j].bitfield.qword));
1480}
1481
1482/* Return 1 if there is no conflict in any size on operand J for
1483 instruction template T. */
1484
1485static INLINE int
1486match_mem_size (const template *t, unsigned int j)
1487{
1488 return (match_reg_size (t, j)
1489 && !((i.types[j].bitfield.unspecified
1490 && !t->operand_types[j].bitfield.unspecified)
1491 || (i.types[j].bitfield.fword
1492 && !t->operand_types[j].bitfield.fword)
1493 || (i.types[j].bitfield.tbyte
1494 && !t->operand_types[j].bitfield.tbyte)
1495 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1496 && !t->operand_types[j].bitfield.xmmword)
1497 || (i.types[j].bitfield.ymmword
1498 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1499}
1500
1501/* Return 1 if there is no size conflict on any operands for
1502 instruction template T. */
1503
1504static INLINE int
1505operand_size_match (const template *t)
1506{
1507 unsigned int j;
1508 int match = 1;
1509
1510 /* Don't check jump instructions. */
1511 if (t->opcode_modifier.jump
1512 || t->opcode_modifier.jumpbyte
1513 || t->opcode_modifier.jumpdword
1514 || t->opcode_modifier.jumpintersegment)
1515 return match;
1516
1517 /* Check memory and accumulator operand size. */
1518 for (j = 0; j < i.operands; j++)
1519 {
1520 if (t->operand_types[j].bitfield.anysize)
1521 continue;
1522
1523 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1524 {
1525 match = 0;
1526 break;
1527 }
1528
1529 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1530 {
1531 match = 0;
1532 break;
1533 }
1534 }
1535
1536 if (match
1537 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1538 return match;
1539
1540 /* Check reverse. */
9c2799c2 1541 gas_assert (i.operands == 2);
5c07affc
L		 1542
1543 match = 1;
1544 for (j = 0; j < 2; j++)
1545 {
1546 if (t->operand_types[j].bitfield.acc
1547 && !match_reg_size (t, j ? 0 : 1))
1548 {
1549 match = 0;
1550 break;
1551 }
1552
1553 if (i.types[j].bitfield.mem
1554 && !match_mem_size (t, j ? 0 : 1))
1555 {
1556 match = 0;
1557 break;
1558 }
1559 }
1560
1561 return match;
1562}
1563
c6fb90c8 1564static INLINE int
40fb9820
L		 1565operand_type_match (i386_operand_type overlap,
1566 i386_operand_type given)
1567{
1568 i386_operand_type temp = overlap;
1569
1570 temp.bitfield.jumpabsolute = 0;
7d5e4556 1571 temp.bitfield.unspecified = 0;
5c07affc
L		 1572 temp.bitfield.byte = 0;
1573 temp.bitfield.word = 0;
1574 temp.bitfield.dword = 0;
1575 temp.bitfield.fword = 0;
1576 temp.bitfield.qword = 0;
1577 temp.bitfield.tbyte = 0;
1578 temp.bitfield.xmmword = 0;
c0f3af97 1579 temp.bitfield.ymmword = 0;
0dfbf9d7 1580 if (operand_type_all_zero (&temp))
40fb9820
L		 1581 return 0;
1582
1583 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1584 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1585}
1586
7d5e4556 1587/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1588 unless the expected operand type register overlap is null.
1589 Note that Acc in a template matches every size of reg. */
1590
c6fb90c8 1591static INLINE int
40fb9820
L		 1592operand_type_register_match (i386_operand_type m0,
1593 i386_operand_type g0,
1594 i386_operand_type t0,
1595 i386_operand_type m1,
1596 i386_operand_type g1,
1597 i386_operand_type t1)
1598{
1599 if (!operand_type_check (g0, reg))
1600 return 1;
1601
1602 if (!operand_type_check (g1, reg))
1603 return 1;
1604
1605 if (g0.bitfield.reg8 == g1.bitfield.reg8
1606 && g0.bitfield.reg16 == g1.bitfield.reg16
1607 && g0.bitfield.reg32 == g1.bitfield.reg32
1608 && g0.bitfield.reg64 == g1.bitfield.reg64)
1609 return 1;
1610
1611 if (m0.bitfield.acc)
1612 {
1613 t0.bitfield.reg8 = 1;
1614 t0.bitfield.reg16 = 1;
1615 t0.bitfield.reg32 = 1;
1616 t0.bitfield.reg64 = 1;
1617 }
1618
1619 if (m1.bitfield.acc)
1620 {
1621 t1.bitfield.reg8 = 1;
1622 t1.bitfield.reg16 = 1;
1623 t1.bitfield.reg32 = 1;
1624 t1.bitfield.reg64 = 1;
1625 }
1626
1627 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1628 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1629 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1630 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1631}
1632
252b5132 1633static INLINE unsigned int
40fb9820 1634mode_from_disp_size (i386_operand_type t)
252b5132 1635{
40fb9820
L		 1636 if (t.bitfield.disp8)
1637 return 1;
1638 else if (t.bitfield.disp16
1639 || t.bitfield.disp32
1640 || t.bitfield.disp32s)
1641 return 2;
1642 else
1643 return 0;
252b5132
RH		 1644}
1645
1646static INLINE int
e3bb37b5 1647fits_in_signed_byte (offsetT num)
252b5132
RH		 1648{
1649 return (num >= -128) && (num <= 127);
47926f60 1650}
252b5132
RH		 1651
1652static INLINE int
e3bb37b5 1653fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1654{
1655 return (num & 0xff) == num;
47926f60 1656}
252b5132
RH		 1657
1658static INLINE int
e3bb37b5 1659fits_in_unsigned_word (offsetT num)
252b5132
RH		 1660{
1661 return (num & 0xffff) == num;
47926f60 1662}
252b5132
RH		 1663
1664static INLINE int
e3bb37b5 1665fits_in_signed_word (offsetT num)
252b5132
RH		 1666{
1667 return (-32768 <= num) && (num <= 32767);
47926f60 1668}
2a962e6d 1669
3e73aa7c 1670static INLINE int
e3bb37b5 1671fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1672{
1673#ifndef BFD64
1674 return 1;
1675#else
1676 return (!(((offsetT) -1 << 31) & num)
1677 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1678#endif
1679} /* fits_in_signed_long() */
2a962e6d 1680
3e73aa7c 1681static INLINE int
e3bb37b5 1682fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1683{
1684#ifndef BFD64
1685 return 1;
1686#else
1687 return (num & (((offsetT) 2 << 31) - 1)) == num;
1688#endif
1689} /* fits_in_unsigned_long() */
252b5132 1690
40fb9820 1691static i386_operand_type
e3bb37b5 1692smallest_imm_type (offsetT num)
252b5132 1693{
40fb9820 1694 i386_operand_type t;
7ab9ffdd 1695
0dfbf9d7 1696 operand_type_set (&t, 0);
40fb9820
L		 1697 t.bitfield.imm64 = 1;
1698
1699 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1700 {
1701 /* This code is disabled on the 486 because all the Imm1 forms
1702 in the opcode table are slower on the i486. They're the
1703 versions with the implicitly specified single-position
1704 displacement, which has another syntax if you really want to
1705 use that form. */
40fb9820
L		 1706 t.bitfield.imm1 = 1;
1707 t.bitfield.imm8 = 1;
1708 t.bitfield.imm8s = 1;
1709 t.bitfield.imm16 = 1;
1710 t.bitfield.imm32 = 1;
1711 t.bitfield.imm32s = 1;
1712 }
1713 else if (fits_in_signed_byte (num))
1714 {
1715 t.bitfield.imm8 = 1;
1716 t.bitfield.imm8s = 1;
1717 t.bitfield.imm16 = 1;
1718 t.bitfield.imm32 = 1;
1719 t.bitfield.imm32s = 1;
1720 }
1721 else if (fits_in_unsigned_byte (num))
1722 {
1723 t.bitfield.imm8 = 1;
1724 t.bitfield.imm16 = 1;
1725 t.bitfield.imm32 = 1;
1726 t.bitfield.imm32s = 1;
1727 }
1728 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1729 {
1730 t.bitfield.imm16 = 1;
1731 t.bitfield.imm32 = 1;
1732 t.bitfield.imm32s = 1;
1733 }
1734 else if (fits_in_signed_long (num))
1735 {
1736 t.bitfield.imm32 = 1;
1737 t.bitfield.imm32s = 1;
1738 }
1739 else if (fits_in_unsigned_long (num))
1740 t.bitfield.imm32 = 1;
1741
1742 return t;
47926f60 1743}
252b5132 1744
847f7ad4 1745static offsetT
e3bb37b5 1746offset_in_range (offsetT val, int size)
847f7ad4 1747{
508866be 1748 addressT mask;
ba2adb93 1749
847f7ad4
AM		 1750 switch (size)
1751 {
508866be
L		 1752 case 1: mask = ((addressT) 1 << 8) - 1; break;
1753 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1754 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1755#ifdef BFD64
1756 case 8: mask = ((addressT) 2 << 63) - 1; break;
1757#endif
47926f60 1758 default: abort ();
847f7ad4
AM		 1759 }
1760
ba2adb93 1761 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1762 if (!use_rela_relocations)
1763 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1764 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1765
47926f60 1766 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1767 {
1768 char buf1[40], buf2[40];
1769
1770 sprint_value (buf1, val);
1771 sprint_value (buf2, val & mask);
1772 as_warn (_("%s shortened to %s"), buf1, buf2);
1773 }
1774 return val & mask;
1775}
1776
252b5132
RH		 1777/* Returns 0 if attempting to add a prefix where one from the same
1778 class already exists, 1 if non rep/repne added, 2 if rep/repne
1779 added. */
1780static int
e3bb37b5 1781add_prefix (unsigned int prefix)
252b5132
RH		 1782{
1783 int ret = 1;
b1905489 1784 unsigned int q;
252b5132 1785
29b0f896
AM		 1786 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1787 && flag_code == CODE_64BIT)
b1905489 1788 {
161a04f6
L		 1789 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1790 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1791 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1792 ret = 0;
1793 q = REX_PREFIX;
1794 }
3e73aa7c 1795 else
b1905489
JB		 1796 {
1797 switch (prefix)
1798 {
1799 default:
1800 abort ();
1801
1802 case CS_PREFIX_OPCODE:
1803 case DS_PREFIX_OPCODE:
1804 case ES_PREFIX_OPCODE:
1805 case FS_PREFIX_OPCODE:
1806 case GS_PREFIX_OPCODE:
1807 case SS_PREFIX_OPCODE:
1808 q = SEG_PREFIX;
1809 break;
1810
1811 case REPNE_PREFIX_OPCODE:
1812 case REPE_PREFIX_OPCODE:
1813 ret = 2;
1814 /* fall thru */
1815 case LOCK_PREFIX_OPCODE:
1816 q = LOCKREP_PREFIX;
1817 break;
1818
1819 case FWAIT_OPCODE:
1820 q = WAIT_PREFIX;
1821 break;
1822
1823 case ADDR_PREFIX_OPCODE:
1824 q = ADDR_PREFIX;
1825 break;
1826
1827 case DATA_PREFIX_OPCODE:
1828 q = DATA_PREFIX;
1829 break;
1830 }
1831 if (i.prefix[q] != 0)
1832 ret = 0;
1833 }
252b5132 1834
b1905489 1835 if (ret)
252b5132 1836 {
b1905489
JB		 1837 if (!i.prefix[q])
1838 ++i.prefixes;
1839 i.prefix[q] |= prefix;
252b5132 1840 }
b1905489
JB		 1841 else
1842 as_bad (_("same type of prefix used twice"));
252b5132 1843
252b5132
RH		 1844 return ret;
1845}
1846
1847static void
e3bb37b5 1848set_code_flag (int value)
eecb386c 1849{
3e73aa7c 1850 flag_code = value;
40fb9820
L		 1851 if (flag_code == CODE_64BIT)
1852 {
1853 cpu_arch_flags.bitfield.cpu64 = 1;
1854 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1855 }
1856 else
1857 {
1858 cpu_arch_flags.bitfield.cpu64 = 0;
1859 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1860 }
1861 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1862 {
1863 as_bad (_("64bit mode not supported on this CPU."));
1864 }
40fb9820 1865 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1866 {
1867 as_bad (_("32bit mode not supported on this CPU."));
1868 }
eecb386c
AM		 1869 stackop_size = '\0';
1870}
1871
1872static void
e3bb37b5 1873set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1874{
3e73aa7c 1875 flag_code = new_code_flag;
40fb9820
L		 1876 if (flag_code != CODE_16BIT)
1877 abort ();
1878 cpu_arch_flags.bitfield.cpu64 = 0;
1879 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1880 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1881}
1882
1883static void
e3bb37b5 1884set_intel_syntax (int syntax_flag)
252b5132
RH		 1885{
1886 /* Find out if register prefixing is specified. */
1887 int ask_naked_reg = 0;
1888
1889 SKIP_WHITESPACE ();
29b0f896 1890 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1891 {
1892 char *string = input_line_pointer;
1893 int e = get_symbol_end ();
1894
47926f60 1895 if (strcmp (string, "prefix") == 0)
252b5132 1896 ask_naked_reg = 1;
47926f60 1897 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1898 ask_naked_reg = -1;
1899 else
d0b47220 1900 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1901 *input_line_pointer = e;
1902 }
1903 demand_empty_rest_of_line ();
c3332e24 1904
252b5132
RH		 1905 intel_syntax = syntax_flag;
1906
1907 if (ask_naked_reg == 0)
f86103b7
AM		 1908 allow_naked_reg = (intel_syntax
1909 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1910 else
1911 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1912
ee86248c 1913 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1914
e4a3b5a4 1915 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1916 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1917 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1918}
1919
1efbbeb4
L		 1920static void
1921set_intel_mnemonic (int mnemonic_flag)
1922{
e1d4d893 1923 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1924}
1925
db51cc60
L		 1926static void
1927set_allow_index_reg (int flag)
1928{
1929 allow_index_reg = flag;
1930}
1931
cb19c032
L		 1932static void
1933set_sse_check (int dummy ATTRIBUTE_UNUSED)
1934{
1935 SKIP_WHITESPACE ();
1936
1937 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1938 {
1939 char *string = input_line_pointer;
1940 int e = get_symbol_end ();
1941
1942 if (strcmp (string, "none") == 0)
1943 sse_check = sse_check_none;
1944 else if (strcmp (string, "warning") == 0)
1945 sse_check = sse_check_warning;
1946 else if (strcmp (string, "error") == 0)
1947 sse_check = sse_check_error;
1948 else
1949 as_bad (_("bad argument to sse_check directive."));
1950 *input_line_pointer = e;
1951 }
1952 else
1953 as_bad (_("missing argument for sse_check directive"));
1954
1955 demand_empty_rest_of_line ();
1956}
1957
e413e4e9 1958static void
e3bb37b5 1959set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1960{
47926f60 1961 SKIP_WHITESPACE ();
e413e4e9 1962
29b0f896 1963 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1964 {
1965 char *string = input_line_pointer;
1966 int e = get_symbol_end ();
9103f4f4 1967 unsigned int i;
40fb9820 1968 i386_cpu_flags flags;
e413e4e9 1969
9103f4f4 1970 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1971 {
1972 if (strcmp (string, cpu_arch[i].name) == 0)
1973 {
5c6af06e
JB		 1974 if (*string != '.')
1975 {
1976 cpu_arch_name = cpu_arch[i].name;
1977 cpu_sub_arch_name = NULL;
40fb9820
L		 1978 cpu_arch_flags = cpu_arch[i].flags;
1979 if (flag_code == CODE_64BIT)
1980 {
1981 cpu_arch_flags.bitfield.cpu64 = 1;
1982 cpu_arch_flags.bitfield.cpuno64 = 0;
1983 }
1984 else
1985 {
1986 cpu_arch_flags.bitfield.cpu64 = 0;
1987 cpu_arch_flags.bitfield.cpuno64 = 1;
1988 }
ccc9c027 1989 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1990 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1991 if (!cpu_arch_tune_set)
1992 {
1993 cpu_arch_tune = cpu_arch_isa;
1994 cpu_arch_tune_flags = cpu_arch_isa_flags;
1995 }
5c6af06e
JB		 1996 break;
1997 }
40fb9820 1998
309d3373
JB		 1999 if (strncmp (string + 1, "no", 2))
2000 flags = cpu_flags_or (cpu_arch_flags,
2001 cpu_arch[i].flags);
2002 else
2003 flags = cpu_flags_and_not (cpu_arch_flags,
2004 cpu_arch[i].flags);
0dfbf9d7 2005 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2006 {
6305a203
L		 2007 if (cpu_sub_arch_name)
2008 {
2009 char *name = cpu_sub_arch_name;
2010 cpu_sub_arch_name = concat (name,
2011 cpu_arch[i].name,
1bf57e9f 2012 (const char *) NULL);
6305a203
L		 2013 free (name);
2014 }
2015 else
2016 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 2017 cpu_arch_flags = flags;
5c6af06e
JB		 2018 }
2019 *input_line_pointer = e;
2020 demand_empty_rest_of_line ();
2021 return;
e413e4e9
AM		 2022 }
2023 }
9103f4f4 2024 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2025 as_bad (_("no such architecture: `%s'"), string);
2026
2027 *input_line_pointer = e;
2028 }
2029 else
2030 as_bad (_("missing cpu architecture"));
2031
fddf5b5b
AM		 2032 no_cond_jump_promotion = 0;
2033 if (*input_line_pointer == ','
29b0f896 2034 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2035 {
2036 char *string = ++input_line_pointer;
2037 int e = get_symbol_end ();
2038
2039 if (strcmp (string, "nojumps") == 0)
2040 no_cond_jump_promotion = 1;
2041 else if (strcmp (string, "jumps") == 0)
2042 ;
2043 else
2044 as_bad (_("no such architecture modifier: `%s'"), string);
2045
2046 *input_line_pointer = e;
2047 }
2048
e413e4e9
AM		 2049 demand_empty_rest_of_line ();
2050}
2051
b9d79e03
JH		 2052unsigned long
2053i386_mach ()
2054{
2055 if (!strcmp (default_arch, "x86_64"))
2056 return bfd_mach_x86_64;
2057 else if (!strcmp (default_arch, "i386"))
2058 return bfd_mach_i386_i386;
2059 else
2060 as_fatal (_("Unknown architecture"));
2061}
b9d79e03 2062\f
252b5132
RH		 2063void
2064md_begin ()
2065{
2066 const char *hash_err;
2067
47926f60 2068 /* Initialize op_hash hash table. */
252b5132
RH		 2069 op_hash = hash_new ();
2070
2071 {
29b0f896
AM		 2072 const template *optab;
2073 templates *core_optab;
252b5132 2074
47926f60
KH		 2075 /* Setup for loop. */
2076 optab = i386_optab;
252b5132
RH		 2077 core_optab = (templates *) xmalloc (sizeof (templates));
2078 core_optab->start = optab;
2079
2080 while (1)
2081 {
2082 ++optab;
2083 if (optab->name == NULL
2084 || strcmp (optab->name, (optab - 1)->name) != 0)
2085 {
2086 /* different name --> ship out current template list;
47926f60 2087 add to hash table; & begin anew. */
252b5132
RH		 2088 core_optab->end = optab;
2089 hash_err = hash_insert (op_hash,
2090 (optab - 1)->name,
5a49b8ac 2091 (void *) core_optab);
252b5132
RH		 2092 if (hash_err)
2093 {
252b5132
RH		 2094 as_fatal (_("Internal Error: Can't hash %s: %s"),
2095 (optab - 1)->name,
2096 hash_err);
2097 }
2098 if (optab->name == NULL)
2099 break;
2100 core_optab = (templates *) xmalloc (sizeof (templates));
2101 core_optab->start = optab;
2102 }
2103 }
2104 }
2105
47926f60 2106 /* Initialize reg_hash hash table. */
252b5132
RH		 2107 reg_hash = hash_new ();
2108 {
29b0f896 2109 const reg_entry *regtab;
c3fe08fa 2110 unsigned int regtab_size = i386_regtab_size;
252b5132 2111
c3fe08fa 2112 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2113 {
5a49b8ac 2114 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2115 if (hash_err)
3e73aa7c
JH		 2116 as_fatal (_("Internal Error: Can't hash %s: %s"),
2117 regtab->reg_name,
2118 hash_err);
252b5132
RH		 2119 }
2120 }
2121
47926f60 2122 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2123 {
29b0f896
AM		 2124 int c;
2125 char *p;
252b5132
RH		 2126
2127 for (c = 0; c < 256; c++)
2128 {
3882b010 2129 if (ISDIGIT (c))
252b5132
RH		 2130 {
2131 digit_chars[c] = c;
2132 mnemonic_chars[c] = c;
2133 register_chars[c] = c;
2134 operand_chars[c] = c;
2135 }
3882b010 2136 else if (ISLOWER (c))
252b5132
RH		 2137 {
2138 mnemonic_chars[c] = c;
2139 register_chars[c] = c;
2140 operand_chars[c] = c;
2141 }
3882b010 2142 else if (ISUPPER (c))
252b5132 2143 {
3882b010 2144 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2145 register_chars[c] = mnemonic_chars[c];
2146 operand_chars[c] = c;
2147 }
2148
3882b010 2149 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2150 identifier_chars[c] = c;
2151 else if (c >= 128)
2152 {
2153 identifier_chars[c] = c;
2154 operand_chars[c] = c;
2155 }
2156 }
2157
2158#ifdef LEX_AT
2159 identifier_chars['@'] = '@';
32137342
NC		 2160#endif
2161#ifdef LEX_QM
2162 identifier_chars['?'] = '?';
2163 operand_chars['?'] = '?';
252b5132 2164#endif
252b5132 2165 digit_chars['-'] = '-';
c0f3af97 2166 mnemonic_chars['_'] = '_';
791fe849 2167 mnemonic_chars['-'] = '-';
0003779b 2168 mnemonic_chars['.'] = '.';
252b5132
RH		 2169 identifier_chars['_'] = '_';
2170 identifier_chars['.'] = '.';
2171
2172 for (p = operand_special_chars; *p != '\0'; p++)
2173 operand_chars[(unsigned char) *p] = *p;
2174 }
2175
2176#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2177 if (IS_ELF)
252b5132
RH		 2178 {
2179 record_alignment (text_section, 2);
2180 record_alignment (data_section, 2);
2181 record_alignment (bss_section, 2);
2182 }
2183#endif
a4447b93
RH		 2184
2185 if (flag_code == CODE_64BIT)
2186 {
2187 x86_dwarf2_return_column = 16;
2188 x86_cie_data_alignment = -8;
2189 }
2190 else
2191 {
2192 x86_dwarf2_return_column = 8;
2193 x86_cie_data_alignment = -4;
2194 }
252b5132
RH		 2195}
2196
2197void
e3bb37b5 2198i386_print_statistics (FILE *file)
252b5132
RH		 2199{
2200 hash_print_statistics (file, "i386 opcode", op_hash);
2201 hash_print_statistics (file, "i386 register", reg_hash);
2202}
2203\f
252b5132
RH		 2204#ifdef DEBUG386
2205
ce8a8b2f 2206/* Debugging routines for md_assemble. */
e3bb37b5 2207static void pte (template *);
40fb9820 2208static void pt (i386_operand_type);
e3bb37b5
L		 2209static void pe (expressionS *);
2210static void ps (symbolS *);
252b5132
RH		 2211
2212static void
e3bb37b5 2213pi (char *line, i386_insn *x)
252b5132 2214{
09f131f2 2215 unsigned int i;
252b5132
RH		 2216
2217 fprintf (stdout, "%s: template ", line);
2218 pte (&x->tm);
09f131f2
JH		 2219 fprintf (stdout, " address: base %s index %s scale %x\n",
2220 x->base_reg ? x->base_reg->reg_name : "none",
2221 x->index_reg ? x->index_reg->reg_name : "none",
2222 x->log2_scale_factor);
2223 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2224 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2225 fprintf (stdout, " sib: base %x index %x scale %x\n",
2226 x->sib.base, x->sib.index, x->sib.scale);
2227 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2228 (x->rex & REX_W) != 0,
2229 (x->rex & REX_R) != 0,
2230 (x->rex & REX_X) != 0,
2231 (x->rex & REX_B) != 0);
252b5132
RH		 2232 for (i = 0; i < x->operands; i++)
2233 {
2234 fprintf (stdout, " #%d: ", i + 1);
2235 pt (x->types[i]);
2236 fprintf (stdout, "\n");
40fb9820
L		 2237 if (x->types[i].bitfield.reg8
2238 || x->types[i].bitfield.reg16
2239 || x->types[i].bitfield.reg32
2240 || x->types[i].bitfield.reg64
2241 || x->types[i].bitfield.regmmx
2242 || x->types[i].bitfield.regxmm
c0f3af97 2243 || x->types[i].bitfield.regymm
40fb9820
L		 2244 || x->types[i].bitfield.sreg2
2245 || x->types[i].bitfield.sreg3
2246 || x->types[i].bitfield.control
2247 || x->types[i].bitfield.debug
2248 || x->types[i].bitfield.test)
520dc8e8 2249 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2250 if (operand_type_check (x->types[i], imm))
520dc8e8 2251 pe (x->op[i].imms);
40fb9820 2252 if (operand_type_check (x->types[i], disp))
520dc8e8 2253 pe (x->op[i].disps);
252b5132
RH		 2254 }
2255}
2256
2257static void
e3bb37b5 2258pte (template *t)
252b5132 2259{
09f131f2 2260 unsigned int i;
252b5132 2261 fprintf (stdout, " %d operands ", t->operands);
47926f60 2262 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2263 if (t->extension_opcode != None)
2264 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2265 if (t->opcode_modifier.d)
252b5132 2266 fprintf (stdout, "D");
40fb9820 2267 if (t->opcode_modifier.w)
252b5132
RH		 2268 fprintf (stdout, "W");
2269 fprintf (stdout, "\n");
2270 for (i = 0; i < t->operands; i++)
2271 {
2272 fprintf (stdout, " #%d type ", i + 1);
2273 pt (t->operand_types[i]);
2274 fprintf (stdout, "\n");
2275 }
2276}
2277
2278static void
e3bb37b5 2279pe (expressionS *e)
252b5132 2280{
24eab124 2281 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2282 fprintf (stdout, " add_number %ld (%lx)\n",
2283 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2284 if (e->X_add_symbol)
2285 {
2286 fprintf (stdout, " add_symbol ");
2287 ps (e->X_add_symbol);
2288 fprintf (stdout, "\n");
2289 }
2290 if (e->X_op_symbol)
2291 {
2292 fprintf (stdout, " op_symbol ");
2293 ps (e->X_op_symbol);
2294 fprintf (stdout, "\n");
2295 }
2296}
2297
2298static void
e3bb37b5 2299ps (symbolS *s)
252b5132
RH		 2300{
2301 fprintf (stdout, "%s type %s%s",
2302 S_GET_NAME (s),
2303 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2304 segment_name (S_GET_SEGMENT (s)));
2305}
2306
7b81dfbb 2307static struct type_name
252b5132 2308 {
40fb9820
L		 2309 i386_operand_type mask;
2310 const char *name;
252b5132 2311 }
7b81dfbb 2312const type_names[] =
252b5132 2313{
40fb9820
L		 2314 { OPERAND_TYPE_REG8, "r8" },
2315 { OPERAND_TYPE_REG16, "r16" },
2316 { OPERAND_TYPE_REG32, "r32" },
2317 { OPERAND_TYPE_REG64, "r64" },
2318 { OPERAND_TYPE_IMM8, "i8" },
2319 { OPERAND_TYPE_IMM8, "i8s" },
2320 { OPERAND_TYPE_IMM16, "i16" },
2321 { OPERAND_TYPE_IMM32, "i32" },
2322 { OPERAND_TYPE_IMM32S, "i32s" },
2323 { OPERAND_TYPE_IMM64, "i64" },
2324 { OPERAND_TYPE_IMM1, "i1" },
2325 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2326 { OPERAND_TYPE_DISP8, "d8" },
2327 { OPERAND_TYPE_DISP16, "d16" },
2328 { OPERAND_TYPE_DISP32, "d32" },
2329 { OPERAND_TYPE_DISP32S, "d32s" },
2330 { OPERAND_TYPE_DISP64, "d64" },
2331 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2332 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2333 { OPERAND_TYPE_CONTROL, "control reg" },
2334 { OPERAND_TYPE_TEST, "test reg" },
2335 { OPERAND_TYPE_DEBUG, "debug reg" },
2336 { OPERAND_TYPE_FLOATREG, "FReg" },
2337 { OPERAND_TYPE_FLOATACC, "FAcc" },
2338 { OPERAND_TYPE_SREG2, "SReg2" },
2339 { OPERAND_TYPE_SREG3, "SReg3" },
2340 { OPERAND_TYPE_ACC, "Acc" },
2341 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2342 { OPERAND_TYPE_REGMMX, "rMMX" },
2343 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2344 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2345 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2346};
2347
2348static void
40fb9820 2349pt (i386_operand_type t)
252b5132 2350{
40fb9820 2351 unsigned int j;
c6fb90c8 2352 i386_operand_type a;
252b5132 2353
40fb9820 2354 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2355 {
2356 a = operand_type_and (t, type_names[j].mask);
0349dc08 2357 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2358 fprintf (stdout, "%s, ", type_names[j].name);
2359 }
252b5132
RH		 2360 fflush (stdout);
2361}
2362
2363#endif /* DEBUG386 */
2364\f
252b5132 2365static bfd_reloc_code_real_type
3956db08 2366reloc (unsigned int size,
64e74474
AM		 2367 int pcrel,
2368 int sign,
2369 bfd_reloc_code_real_type other)
252b5132 2370{
47926f60 2371 if (other != NO_RELOC)
3956db08
JB		 2372 {
2373 reloc_howto_type *reloc;
2374
2375 if (size == 8)
2376 switch (other)
2377 {
64e74474
AM		 2378 case BFD_RELOC_X86_64_GOT32:
2379 return BFD_RELOC_X86_64_GOT64;
2380 break;
2381 case BFD_RELOC_X86_64_PLTOFF64:
2382 return BFD_RELOC_X86_64_PLTOFF64;
2383 break;
2384 case BFD_RELOC_X86_64_GOTPC32:
2385 other = BFD_RELOC_X86_64_GOTPC64;
2386 break;
2387 case BFD_RELOC_X86_64_GOTPCREL:
2388 other = BFD_RELOC_X86_64_GOTPCREL64;
2389 break;
2390 case BFD_RELOC_X86_64_TPOFF32:
2391 other = BFD_RELOC_X86_64_TPOFF64;
2392 break;
2393 case BFD_RELOC_X86_64_DTPOFF32:
2394 other = BFD_RELOC_X86_64_DTPOFF64;
2395 break;
2396 default:
2397 break;
3956db08 2398 }
e05278af
JB		 2399
2400 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2401 if (size == 4 && flag_code != CODE_64BIT)
2402 sign = -1;
2403
3956db08
JB		 2404 reloc = bfd_reloc_type_lookup (stdoutput, other);
2405 if (!reloc)
2406 as_bad (_("unknown relocation (%u)"), other);
2407 else if (size != bfd_get_reloc_size (reloc))
2408 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2409 bfd_get_reloc_size (reloc),
2410 size);
2411 else if (pcrel && !reloc->pc_relative)
2412 as_bad (_("non-pc-relative relocation for pc-relative field"));
2413 else if ((reloc->complain_on_overflow == complain_overflow_signed
2414 && !sign)
2415 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2416 && sign > 0))
3956db08
JB		 2417 as_bad (_("relocated field and relocation type differ in signedness"));
2418 else
2419 return other;
2420 return NO_RELOC;
2421 }
252b5132
RH		 2422
2423 if (pcrel)
2424 {
3e73aa7c 2425 if (!sign)
3956db08 2426 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2427 switch (size)
2428 {
2429 case 1: return BFD_RELOC_8_PCREL;
2430 case 2: return BFD_RELOC_16_PCREL;
2431 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2432 case 8: return BFD_RELOC_64_PCREL;
252b5132 2433 }
3956db08 2434 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2435 }
2436 else
2437 {
3956db08 2438 if (sign > 0)
e5cb08ac 2439 switch (size)
3e73aa7c
JH		 2440 {
2441 case 4: return BFD_RELOC_X86_64_32S;
2442 }
2443 else
2444 switch (size)
2445 {
2446 case 1: return BFD_RELOC_8;
2447 case 2: return BFD_RELOC_16;
2448 case 4: return BFD_RELOC_32;
2449 case 8: return BFD_RELOC_64;
2450 }
3956db08
JB		 2451 as_bad (_("cannot do %s %u byte relocation"),
2452 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2453 }
2454
0cc9e1d3 2455 return NO_RELOC;
252b5132
RH		 2456}
2457
47926f60
KH		 2458/* Here we decide which fixups can be adjusted to make them relative to
2459 the beginning of the section instead of the symbol. Basically we need
2460 to make sure that the dynamic relocations are done correctly, so in
2461 some cases we force the original symbol to be used. */
2462
252b5132 2463int
e3bb37b5 2464tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2465{
6d249963 2466#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2467 if (!IS_ELF)
31312f95
AM		 2468 return 1;
2469
a161fe53
AM		 2470 /* Don't adjust pc-relative references to merge sections in 64-bit
2471 mode. */
2472 if (use_rela_relocations
2473 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2474 && fixP->fx_pcrel)
252b5132 2475 return 0;
31312f95 2476
8d01d9a9
AJ		 2477 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2478 and changed later by validate_fix. */
2479 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2480 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2481 return 0;
2482
ce8a8b2f 2483 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2484 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2485 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2486 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2487 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2488 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2489 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2490 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2491 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2492 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2493 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2494 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2495 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2496 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2497 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2498 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2499 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2500 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2501 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2502 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2503 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2504 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2505 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2506 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2507 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2508 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2509 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2510 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2511 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2512 return 0;
d8045f23
NC		 2513
2514 if (fixP->fx_addsy != NULL
2515 && symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_GNU_INDIRECT_FUNCTION)
2516 return 0;
31312f95 2517#endif
252b5132
RH		 2518 return 1;
2519}
252b5132 2520
b4cac588 2521static int
e3bb37b5 2522intel_float_operand (const char *mnemonic)
252b5132 2523{
9306ca4a
JB		 2524 /* Note that the value returned is meaningful only for opcodes with (memory)
2525 operands, hence the code here is free to improperly handle opcodes that
2526 have no operands (for better performance and smaller code). */
2527
2528 if (mnemonic[0] != 'f')
2529 return 0; /* non-math */
2530
2531 switch (mnemonic[1])
2532 {
2533 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2534 the fs segment override prefix not currently handled because no
2535 call path can make opcodes without operands get here */
2536 case 'i':
2537 return 2 /* integer op */;
2538 case 'l':
2539 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2540 return 3; /* fldcw/fldenv */
2541 break;
2542 case 'n':
2543 if (mnemonic[2] != 'o' /* fnop */)
2544 return 3; /* non-waiting control op */
2545 break;
2546 case 'r':
2547 if (mnemonic[2] == 's')
2548 return 3; /* frstor/frstpm */
2549 break;
2550 case 's':
2551 if (mnemonic[2] == 'a')
2552 return 3; /* fsave */
2553 if (mnemonic[2] == 't')
2554 {
2555 switch (mnemonic[3])
2556 {
2557 case 'c': /* fstcw */
2558 case 'd': /* fstdw */
2559 case 'e': /* fstenv */
2560 case 's': /* fsts[gw] */
2561 return 3;
2562 }
2563 }
2564 break;
2565 case 'x':
2566 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2567 return 0; /* fxsave/fxrstor are not really math ops */
2568 break;
2569 }
252b5132 2570
9306ca4a 2571 return 1;
252b5132
RH		 2572}
2573
c0f3af97
L		 2574/* Build the VEX prefix. */
2575
2576static void
fa99fab2 2577build_vex_prefix (const template *t)
c0f3af97
L		 2578{
2579 unsigned int register_specifier;
2580 unsigned int implied_prefix;
2581 unsigned int vector_length;
2582
2583 /* Check register specifier. */
2584 if (i.vex.register_specifier)
2585 {
2586 register_specifier = i.vex.register_specifier->reg_num;
2587 if ((i.vex.register_specifier->reg_flags & RegRex))
2588 register_specifier += 8;
2589 register_specifier = ~register_specifier & 0xf;
2590 }
2591 else
2592 register_specifier = 0xf;
2593
fa99fab2
L		 2594 /* Use 2-byte VEX prefix by swappping destination and source
2595 operand. */
2596 if (!i.swap_operand
2597 && i.operands == i.reg_operands
2598 && i.tm.opcode_modifier.vex0f
2599 && i.tm.opcode_modifier.s
2600 && i.rex == REX_B)
2601 {
2602 unsigned int xchg = i.operands - 1;
2603 union i386_op temp_op;
2604 i386_operand_type temp_type;
2605
2606 temp_type = i.types[xchg];
2607 i.types[xchg] = i.types[0];
2608 i.types[0] = temp_type;
2609 temp_op = i.op[xchg];
2610 i.op[xchg] = i.op[0];
2611 i.op[0] = temp_op;
2612
9c2799c2 2613 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2614
2615 i.rex = REX_R;
2616 xchg = i.rm.regmem;
2617 i.rm.regmem = i.rm.reg;
2618 i.rm.reg = xchg;
2619
2620 /* Use the next insn. */
2621 i.tm = t[1];
2622 }
2623
c0f3af97
L		 2624 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2625
2626 switch ((i.tm.base_opcode >> 8) & 0xff)
2627 {
2628 case 0:
2629 implied_prefix = 0;
2630 break;
2631 case DATA_PREFIX_OPCODE:
2632 implied_prefix = 1;
2633 break;
2634 case REPE_PREFIX_OPCODE:
2635 implied_prefix = 2;
2636 break;
2637 case REPNE_PREFIX_OPCODE:
2638 implied_prefix = 3;
2639 break;
2640 default:
2641 abort ();
2642 }
2643
2644 /* Use 2-byte VEX prefix if possible. */
2645 if (i.tm.opcode_modifier.vex0f
2646 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2647 {
2648 /* 2-byte VEX prefix. */
2649 unsigned int r;
2650
2651 i.vex.length = 2;
2652 i.vex.bytes[0] = 0xc5;
2653
2654 /* Check the REX.R bit. */
2655 r = (i.rex & REX_R) ? 0 : 1;
2656 i.vex.bytes[1] = (r << 7
2657 | register_specifier << 3
2658 | vector_length << 2
2659 | implied_prefix);
2660 }
2661 else
2662 {
2663 /* 3-byte VEX prefix. */
2664 unsigned int m, w;
2665
2666 if (i.tm.opcode_modifier.vex0f)
2667 m = 0x1;
2668 else if (i.tm.opcode_modifier.vex0f38)
2669 m = 0x2;
2670 else if (i.tm.opcode_modifier.vex0f3a)
2671 m = 0x3;
2672 else
2673 abort ();
2674
2675 i.vex.length = 3;
2676 i.vex.bytes[0] = 0xc4;
2677
2678 /* The high 3 bits of the second VEX byte are 1's compliment
2679 of RXB bits from REX. */
2680 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2681
2682 /* Check the REX.W bit. */
2683 w = (i.rex & REX_W) ? 1 : 0;
2684 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2685 {
2686 if (w)
2687 abort ();
2688
2689 if (i.tm.opcode_modifier.vexw1)
2690 w = 1;
2691 }
2692
2693 i.vex.bytes[2] = (w << 7
2694 | register_specifier << 3
2695 | vector_length << 2
2696 | implied_prefix);
2697 }
2698}
2699
65da13b5
L		 2700static void
2701process_immext (void)
2702{
2703 expressionS *exp;
2704
2705 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2706 {
1fed0ba1
L		 2707 /* SSE3 Instructions have the fixed operands with an opcode
2708 suffix which is coded in the same place as an 8-bit immediate
2709 field would be. Here we check those operands and remove them
2710 afterwards. */
65da13b5
L		 2711 unsigned int x;
2712
2713 for (x = 0; x < i.operands; x++)
2714 if (i.op[x].regs->reg_num != x)
2715 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2716 register_prefix, i.op[x].regs->reg_name, x + 1,
2717 i.tm.name);
2718
2719 i.operands = 0;
65da13b5
L		 2720 }
2721
c0f3af97 2722 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2723 which is coded in the same place as an 8-bit immediate field
2724 would be. Here we fake an 8-bit immediate operand from the
2725 opcode suffix stored in tm.extension_opcode.
2726
c1e679ec 2727 AVX instructions also use this encoding, for some of
c0f3af97 2728 3 argument instructions. */
65da13b5 2729
9c2799c2 2730 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2731 && (i.operands <= 2
2732 || (i.tm.opcode_modifier.vex
2733 && i.operands <= 4)));
65da13b5
L		 2734
2735 exp = &im_expressions[i.imm_operands++];
2736 i.op[i.operands].imms = exp;
2737 i.types[i.operands] = imm8;
2738 i.operands++;
2739 exp->X_op = O_constant;
2740 exp->X_add_number = i.tm.extension_opcode;
2741 i.tm.extension_opcode = None;
2742}
2743
252b5132
RH		 2744/* This is the guts of the machine-dependent assembler. LINE points to a
2745 machine dependent instruction. This function is supposed to emit
2746 the frags/bytes it assembles to. */
2747
2748void
65da13b5 2749md_assemble (char *line)
252b5132 2750{
40fb9820 2751 unsigned int j;
252b5132 2752 char mnemonic[MAX_MNEM_SIZE];
fa99fab2 2753 const template *t;
252b5132 2754
47926f60 2755 /* Initialize globals. */
252b5132
RH		 2756 memset (&i, '\0', sizeof (i));
2757 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2758 i.reloc[j] = NO_RELOC;
252b5132
RH		 2759 memset (disp_expressions, '\0', sizeof (disp_expressions));
2760 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2761 save_stack_p = save_stack;
252b5132
RH		 2762
2763 /* First parse an instruction mnemonic & call i386_operand for the operands.
2764 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2765 start of a (possibly prefixed) mnemonic. */
252b5132 2766
29b0f896
AM		 2767 line = parse_insn (line, mnemonic);
2768 if (line == NULL)
2769 return;
252b5132 2770
29b0f896 2771 line = parse_operands (line, mnemonic);
ee86248c 2772 this_operand = -1;
29b0f896
AM		 2773 if (line == NULL)
2774 return;
252b5132 2775
29b0f896
AM		 2776 /* Now we've parsed the mnemonic into a set of templates, and have the
2777 operands at hand. */
2778
2779 /* All intel opcodes have reversed operands except for "bound" and
2780 "enter". We also don't reverse intersegment "jmp" and "call"
2781 instructions with 2 immediate operands so that the immediate segment
050dfa73 2782 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2783 if (intel_syntax
2784 && i.operands > 1
29b0f896 2785 && (strcmp (mnemonic, "bound") != 0)
30123838 2786 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2787 && !(operand_type_check (i.types[0], imm)
2788 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2789 swap_operands ();
2790
ec56d5c0
JB		 2791 /* The order of the immediates should be reversed
2792 for 2 immediates extrq and insertq instructions */
2793 if (i.imm_operands == 2
2794 && (strcmp (mnemonic, "extrq") == 0
2795 || strcmp (mnemonic, "insertq") == 0))
2796 swap_2_operands (0, 1);
2797
29b0f896
AM		 2798 if (i.imm_operands)
2799 optimize_imm ();
2800
b300c311
L		 2801 /* Don't optimize displacement for movabs since it only takes 64bit
2802 displacement. */
2803 if (i.disp_operands
2804 && (flag_code != CODE_64BIT
2805 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2806 optimize_disp ();
2807
2808 /* Next, we find a template that matches the given insn,
2809 making sure the overlap of the given operands types is consistent
2810 with the template operand types. */
252b5132 2811
fa99fab2 2812 if (!(t = match_template ()))
29b0f896 2813 return;
252b5132 2814
daf50ae7 2815 if (sse_check != sse_check_none
81f8a913 2816 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2817 && (i.tm.cpu_flags.bitfield.cpusse
2818 || i.tm.cpu_flags.bitfield.cpusse2
2819 || i.tm.cpu_flags.bitfield.cpusse3
2820 || i.tm.cpu_flags.bitfield.cpussse3
2821 || i.tm.cpu_flags.bitfield.cpusse4_1
2822 || i.tm.cpu_flags.bitfield.cpusse4_2))
2823 {
2824 (sse_check == sse_check_warning
2825 ? as_warn
2826 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2827 }
2828
321fd21e
L		 2829 /* Zap movzx and movsx suffix. The suffix has been set from
2830 "word ptr" or "byte ptr" on the source operand in Intel syntax
2831 or extracted from mnemonic in AT&T syntax. But we'll use
2832 the destination register to choose the suffix for encoding. */
2833 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2834 {
321fd21e
L		 2835 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2836 there is no suffix, the default will be byte extension. */
2837 if (i.reg_operands != 2
2838 && !i.suffix
7ab9ffdd 2839 && intel_syntax)
321fd21e
L		 2840 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2841
2842 i.suffix = 0;
cd61ebfe 2843 }
24eab124 2844
40fb9820 2845 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2846 if (!add_prefix (FWAIT_OPCODE))
2847 return;
252b5132 2848
29b0f896 2849 /* Check string instruction segment overrides. */
40fb9820 2850 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2851 {
2852 if (!check_string ())
5dd0794d 2853 return;
fc0763e6 2854 i.disp_operands = 0;
29b0f896 2855 }
5dd0794d 2856
29b0f896
AM		 2857 if (!process_suffix ())
2858 return;
e413e4e9 2859
bc0844ae
L		 2860 /* Update operand types. */
2861 for (j = 0; j < i.operands; j++)
2862 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
2863
29b0f896
AM		 2864 /* Make still unresolved immediate matches conform to size of immediate
2865 given in i.suffix. */
2866 if (!finalize_imm ())
2867 return;
252b5132 2868
40fb9820 2869 if (i.types[0].bitfield.imm1)
29b0f896 2870 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2871
9afe6eb8
L		 2872 /* We only need to check those implicit registers for instructions
2873 with 3 operands or less. */
2874 if (i.operands <= 3)
2875 for (j = 0; j < i.operands; j++)
2876 if (i.types[j].bitfield.inoutportreg
2877 || i.types[j].bitfield.shiftcount
2878 || i.types[j].bitfield.acc
2879 || i.types[j].bitfield.floatacc)
2880 i.reg_operands--;
40fb9820 2881
c0f3af97
L		 2882 /* ImmExt should be processed after SSE2AVX. */
2883 if (!i.tm.opcode_modifier.sse2avx
2884 && i.tm.opcode_modifier.immext)
65da13b5 2885 process_immext ();
252b5132 2886
29b0f896
AM		 2887 /* For insns with operands there are more diddles to do to the opcode. */
2888 if (i.operands)
2889 {
2890 if (!process_operands ())
2891 return;
2892 }
40fb9820 2893 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2894 {
2895 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2896 as_warn (_("translating to `%sp'"), i.tm.name);
2897 }
252b5132 2898
c0f3af97 2899 if (i.tm.opcode_modifier.vex)
fa99fab2 2900 build_vex_prefix (t);
c0f3af97 2901
29b0f896
AM		 2902 /* Handle conversion of 'int $3' --> special int3 insn. */
2903 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2904 {
2905 i.tm.base_opcode = INT3_OPCODE;
2906 i.imm_operands = 0;
2907 }
252b5132 2908
40fb9820
L		 2909 if ((i.tm.opcode_modifier.jump
2910 || i.tm.opcode_modifier.jumpbyte
2911 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2912 && i.op[0].disps->X_op == O_constant)
2913 {
2914 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2915 the absolute address given by the constant. Since ix86 jumps and
2916 calls are pc relative, we need to generate a reloc. */
2917 i.op[0].disps->X_add_symbol = &abs_symbol;
2918 i.op[0].disps->X_op = O_symbol;
2919 }
252b5132 2920
40fb9820 2921 if (i.tm.opcode_modifier.rex64)
161a04f6 2922 i.rex |= REX_W;
252b5132 2923
29b0f896
AM		 2924 /* For 8 bit registers we need an empty rex prefix. Also if the
2925 instruction already has a prefix, we need to convert old
2926 registers to new ones. */
773f551c 2927
40fb9820 2928 if ((i.types[0].bitfield.reg8
29b0f896 2929 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2930 || (i.types[1].bitfield.reg8
29b0f896 2931 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2932 || ((i.types[0].bitfield.reg8
2933 || i.types[1].bitfield.reg8)
29b0f896
AM		 2934 && i.rex != 0))
2935 {
2936 int x;
726c5dcd 2937
29b0f896
AM		 2938 i.rex |= REX_OPCODE;
2939 for (x = 0; x < 2; x++)
2940 {
2941 /* Look for 8 bit operand that uses old registers. */
40fb9820 2942 if (i.types[x].bitfield.reg8
29b0f896 2943 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2944 {
29b0f896
AM		 2945 /* In case it is "hi" register, give up. */
2946 if (i.op[x].regs->reg_num > 3)
a540244d 2947 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2948 "instruction requiring REX prefix."),
a540244d 2949 register_prefix, i.op[x].regs->reg_name);
773f551c 2950
29b0f896
AM		 2951 /* Otherwise it is equivalent to the extended register.
2952 Since the encoding doesn't change this is merely
2953 cosmetic cleanup for debug output. */
2954
2955 i.op[x].regs = i.op[x].regs + 8;
773f551c 2956 }
29b0f896
AM		 2957 }
2958 }
773f551c 2959
7ab9ffdd 2960 if (i.rex != 0)
29b0f896
AM		 2961 add_prefix (REX_OPCODE | i.rex);
2962
2963 /* We are ready to output the insn. */
2964 output_insn ();
2965}
2966
2967static char *
e3bb37b5 2968parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2969{
2970 char *l = line;
2971 char *token_start = l;
2972 char *mnem_p;
5c6af06e
JB		 2973 int supported;
2974 const template *t;
b6169b20 2975 char *dot_p = NULL;
29b0f896
AM		 2976
2977 /* Non-zero if we found a prefix only acceptable with string insns. */
2978 const char *expecting_string_instruction = NULL;
45288df1 2979
29b0f896
AM		 2980 while (1)
2981 {
2982 mnem_p = mnemonic;
2983 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2984 {
b6169b20
L		 2985 if (*mnem_p == '.')
2986 dot_p = mnem_p;
29b0f896
AM		 2987 mnem_p++;
2988 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2989 {
29b0f896
AM		 2990 as_bad (_("no such instruction: `%s'"), token_start);
2991 return NULL;
2992 }
2993 l++;
2994 }
2995 if (!is_space_char (*l)
2996 && *l != END_OF_INSN
e44823cf
JB		 2997 && (intel_syntax
2998 || (*l != PREFIX_SEPARATOR
2999 && *l != ',')))
29b0f896
AM		 3000 {
3001 as_bad (_("invalid character %s in mnemonic"),
3002 output_invalid (*l));
3003 return NULL;
3004 }
3005 if (token_start == l)
3006 {
e44823cf 3007 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3008 as_bad (_("expecting prefix; got nothing"));
3009 else
3010 as_bad (_("expecting mnemonic; got nothing"));
3011 return NULL;
3012 }
45288df1 3013
29b0f896
AM		 3014 /* Look up instruction (or prefix) via hash table. */
3015 current_templates = hash_find (op_hash, mnemonic);
47926f60 3016
29b0f896
AM		 3017 if (*l != END_OF_INSN
3018 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3019 && current_templates
40fb9820 3020 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3021 {
c6fb90c8 3022 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3023 {
3024 as_bad ((flag_code != CODE_64BIT
3025 ? _("`%s' is only supported in 64-bit mode")
3026 : _("`%s' is not supported in 64-bit mode")),
3027 current_templates->start->name);
3028 return NULL;
3029 }
29b0f896
AM		 3030 /* If we are in 16-bit mode, do not allow addr16 or data16.
3031 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3032 if ((current_templates->start->opcode_modifier.size16
3033 || current_templates->start->opcode_modifier.size32)
29b0f896 3034 && flag_code != CODE_64BIT
40fb9820 3035 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3036 ^ (flag_code == CODE_16BIT)))
3037 {
3038 as_bad (_("redundant %s prefix"),
3039 current_templates->start->name);
3040 return NULL;
45288df1 3041 }
29b0f896
AM		 3042 /* Add prefix, checking for repeated prefixes. */
3043 switch (add_prefix (current_templates->start->base_opcode))
3044 {
3045 case 0:
3046 return NULL;
3047 case 2:
3048 expecting_string_instruction = current_templates->start->name;
3049 break;
3050 }
3051 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3052 token_start = ++l;
3053 }
3054 else
3055 break;
3056 }
45288df1 3057
30a55f88 3058 if (!current_templates)
b6169b20 3059 {
30a55f88
L		 3060 /* Check if we should swap operand in encoding. */
3061 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3062 i.swap_operand = 1;
3063 else
3064 goto check_suffix;
3065 mnem_p = dot_p;
3066 *dot_p = '\0';
3067 current_templates = hash_find (op_hash, mnemonic);
b6169b20
L		 3068 }
3069
29b0f896
AM		 3070 if (!current_templates)
3071 {
b6169b20 3072check_suffix:
29b0f896
AM		 3073 /* See if we can get a match by trimming off a suffix. */
3074 switch (mnem_p[-1])
3075 {
3076 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3077 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3078 i.suffix = SHORT_MNEM_SUFFIX;
3079 else
29b0f896
AM		 3080 case BYTE_MNEM_SUFFIX:
3081 case QWORD_MNEM_SUFFIX:
3082 i.suffix = mnem_p[-1];
3083 mnem_p[-1] = '\0';
3084 current_templates = hash_find (op_hash, mnemonic);
3085 break;
3086 case SHORT_MNEM_SUFFIX:
3087 case LONG_MNEM_SUFFIX:
3088 if (!intel_syntax)
3089 {
3090 i.suffix = mnem_p[-1];
3091 mnem_p[-1] = '\0';
3092 current_templates = hash_find (op_hash, mnemonic);
3093 }
3094 break;
252b5132 3095
29b0f896
AM		 3096 /* Intel Syntax. */
3097 case 'd':
3098 if (intel_syntax)
3099 {
9306ca4a 3100 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3101 i.suffix = SHORT_MNEM_SUFFIX;
3102 else
3103 i.suffix = LONG_MNEM_SUFFIX;
3104 mnem_p[-1] = '\0';
3105 current_templates = hash_find (op_hash, mnemonic);
3106 }
3107 break;
3108 }
3109 if (!current_templates)
3110 {
3111 as_bad (_("no such instruction: `%s'"), token_start);
3112 return NULL;
3113 }
3114 }
252b5132 3115
40fb9820
L		 3116 if (current_templates->start->opcode_modifier.jump
3117 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3118 {
3119 /* Check for a branch hint. We allow ",pt" and ",pn" for
3120 predict taken and predict not taken respectively.
3121 I'm not sure that branch hints actually do anything on loop
3122 and jcxz insns (JumpByte) for current Pentium4 chips. They
3123 may work in the future and it doesn't hurt to accept them
3124 now. */
3125 if (l[0] == ',' && l[1] == 'p')
3126 {
3127 if (l[2] == 't')
3128 {
3129 if (!add_prefix (DS_PREFIX_OPCODE))
3130 return NULL;
3131 l += 3;
3132 }
3133 else if (l[2] == 'n')
3134 {
3135 if (!add_prefix (CS_PREFIX_OPCODE))
3136 return NULL;
3137 l += 3;
3138 }
3139 }
3140 }
3141 /* Any other comma loses. */
3142 if (*l == ',')
3143 {
3144 as_bad (_("invalid character %s in mnemonic"),
3145 output_invalid (*l));
3146 return NULL;
3147 }
252b5132 3148
29b0f896 3149 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3150 supported = 0;
3151 for (t = current_templates->start; t < current_templates->end; ++t)
3152 {
c0f3af97
L		 3153 supported |= cpu_flags_match (t);
3154 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3155 goto skip;
5c6af06e 3156 }
3629bb00 3157
c0f3af97 3158 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3159 {
3160 as_bad (flag_code == CODE_64BIT
3161 ? _("`%s' is not supported in 64-bit mode")
3162 : _("`%s' is only supported in 64-bit mode"),
3163 current_templates->start->name);
3164 return NULL;
3165 }
c0f3af97 3166 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3167 {
3629bb00 3168 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3169 current_templates->start->name,
41aacd83 3170 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3171 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3172 return NULL;
29b0f896 3173 }
3629bb00
L		 3174
3175skip:
3176 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3177 && (flag_code != CODE_16BIT))
29b0f896
AM		 3178 {
3179 as_warn (_("use .code16 to ensure correct addressing mode"));
3180 }
252b5132 3181
29b0f896 3182 /* Check for rep/repne without a string instruction. */
f41bbced 3183 if (expecting_string_instruction)
29b0f896 3184 {
f41bbced
JB		 3185 static templates override;
3186
3187 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3188 if (t->opcode_modifier.isstring)
f41bbced
JB		 3189 break;
3190 if (t >= current_templates->end)
3191 {
3192 as_bad (_("expecting string instruction after `%s'"),
64e74474 3193 expecting_string_instruction);
f41bbced
JB		 3194 return NULL;
3195 }
3196 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3197 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3198 break;
3199 override.end = t;
3200 current_templates = &override;
29b0f896 3201 }
252b5132 3202
29b0f896
AM		 3203 return l;
3204}
252b5132 3205
29b0f896 3206static char *
e3bb37b5 3207parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3208{
3209 char *token_start;
3138f287 3210
29b0f896
AM		 3211 /* 1 if operand is pending after ','. */
3212 unsigned int expecting_operand = 0;
252b5132 3213
29b0f896
AM		 3214 /* Non-zero if operand parens not balanced. */
3215 unsigned int paren_not_balanced;
3216
3217 while (*l != END_OF_INSN)
3218 {
3219 /* Skip optional white space before operand. */
3220 if (is_space_char (*l))
3221 ++l;
3222 if (!is_operand_char (*l) && *l != END_OF_INSN)
3223 {
3224 as_bad (_("invalid character %s before operand %d"),
3225 output_invalid (*l),
3226 i.operands + 1);
3227 return NULL;
3228 }
3229 token_start = l; /* after white space */
3230 paren_not_balanced = 0;
3231 while (paren_not_balanced || *l != ',')
3232 {
3233 if (*l == END_OF_INSN)
3234 {
3235 if (paren_not_balanced)
3236 {
3237 if (!intel_syntax)
3238 as_bad (_("unbalanced parenthesis in operand %d."),
3239 i.operands + 1);
3240 else
3241 as_bad (_("unbalanced brackets in operand %d."),
3242 i.operands + 1);
3243 return NULL;
3244 }
3245 else
3246 break; /* we are done */
3247 }
3248 else if (!is_operand_char (*l) && !is_space_char (*l))
3249 {
3250 as_bad (_("invalid character %s in operand %d"),
3251 output_invalid (*l),
3252 i.operands + 1);
3253 return NULL;
3254 }
3255 if (!intel_syntax)
3256 {
3257 if (*l == '(')
3258 ++paren_not_balanced;
3259 if (*l == ')')
3260 --paren_not_balanced;
3261 }
3262 else
3263 {
3264 if (*l == '[')
3265 ++paren_not_balanced;
3266 if (*l == ']')
3267 --paren_not_balanced;
3268 }
3269 l++;
3270 }
3271 if (l != token_start)
3272 { /* Yes, we've read in another operand. */
3273 unsigned int operand_ok;
3274 this_operand = i.operands++;
7d5e4556 3275 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3276 if (i.operands > MAX_OPERANDS)
3277 {
3278 as_bad (_("spurious operands; (%d operands/instruction max)"),
3279 MAX_OPERANDS);
3280 return NULL;
3281 }
3282 /* Now parse operand adding info to 'i' as we go along. */
3283 END_STRING_AND_SAVE (l);
3284
3285 if (intel_syntax)
3286 operand_ok =
3287 i386_intel_operand (token_start,
3288 intel_float_operand (mnemonic));
3289 else
a7619375 3290 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3291
3292 RESTORE_END_STRING (l);
3293 if (!operand_ok)
3294 return NULL;
3295 }
3296 else
3297 {
3298 if (expecting_operand)
3299 {
3300 expecting_operand_after_comma:
3301 as_bad (_("expecting operand after ','; got nothing"));
3302 return NULL;
3303 }
3304 if (*l == ',')
3305 {
3306 as_bad (_("expecting operand before ','; got nothing"));
3307 return NULL;
3308 }
3309 }
7f3f1ea2 3310
29b0f896
AM		 3311 /* Now *l must be either ',' or END_OF_INSN. */
3312 if (*l == ',')
3313 {
3314 if (*++l == END_OF_INSN)
3315 {
3316 /* Just skip it, if it's \n complain. */
3317 goto expecting_operand_after_comma;
3318 }
3319 expecting_operand = 1;
3320 }
3321 }
3322 return l;
3323}
7f3f1ea2 3324
050dfa73 3325static void
4d456e3d 3326swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3327{
3328 union i386_op temp_op;
40fb9820 3329 i386_operand_type temp_type;
050dfa73 3330 enum bfd_reloc_code_real temp_reloc;
4eed87de 3331
050dfa73
MM		 3332 temp_type = i.types[xchg2];
3333 i.types[xchg2] = i.types[xchg1];
3334 i.types[xchg1] = temp_type;
3335 temp_op = i.op[xchg2];
3336 i.op[xchg2] = i.op[xchg1];
3337 i.op[xchg1] = temp_op;
3338 temp_reloc = i.reloc[xchg2];
3339 i.reloc[xchg2] = i.reloc[xchg1];
3340 i.reloc[xchg1] = temp_reloc;
3341}
3342
29b0f896 3343static void
e3bb37b5 3344swap_operands (void)
29b0f896 3345{
b7c61d9a 3346 switch (i.operands)
050dfa73 3347 {
c0f3af97 3348 case 5:
b7c61d9a 3349 case 4:
4d456e3d 3350 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3351 case 3:
3352 case 2:
4d456e3d 3353 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3354 break;
3355 default:
3356 abort ();
29b0f896 3357 }
29b0f896
AM		 3358
3359 if (i.mem_operands == 2)
3360 {
3361 const seg_entry *temp_seg;
3362 temp_seg = i.seg[0];
3363 i.seg[0] = i.seg[1];
3364 i.seg[1] = temp_seg;
3365 }
3366}
252b5132 3367
29b0f896
AM		 3368/* Try to ensure constant immediates are represented in the smallest
3369 opcode possible. */
3370static void
e3bb37b5 3371optimize_imm (void)
29b0f896
AM		 3372{
3373 char guess_suffix = 0;
3374 int op;
252b5132 3375
29b0f896
AM		 3376 if (i.suffix)
3377 guess_suffix = i.suffix;
3378 else if (i.reg_operands)
3379 {
3380 /* Figure out a suffix from the last register operand specified.
3381 We can't do this properly yet, ie. excluding InOutPortReg,
3382 but the following works for instructions with immediates.
3383 In any case, we can't set i.suffix yet. */
3384 for (op = i.operands; --op >= 0;)
40fb9820 3385 if (i.types[op].bitfield.reg8)
7ab9ffdd 3386 {
40fb9820
L		 3387 guess_suffix = BYTE_MNEM_SUFFIX;
3388 break;
3389 }
3390 else if (i.types[op].bitfield.reg16)
252b5132 3391 {
40fb9820
L		 3392 guess_suffix = WORD_MNEM_SUFFIX;
3393 break;
3394 }
3395 else if (i.types[op].bitfield.reg32)
3396 {
3397 guess_suffix = LONG_MNEM_SUFFIX;
3398 break;
3399 }
3400 else if (i.types[op].bitfield.reg64)
3401 {
3402 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3403 break;
252b5132 3404 }
29b0f896
AM		 3405 }
3406 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3407 guess_suffix = WORD_MNEM_SUFFIX;
3408
3409 for (op = i.operands; --op >= 0;)
40fb9820 3410 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3411 {
3412 switch (i.op[op].imms->X_op)
252b5132 3413 {
29b0f896
AM		 3414 case O_constant:
3415 /* If a suffix is given, this operand may be shortened. */
3416 switch (guess_suffix)
252b5132 3417 {
29b0f896 3418 case LONG_MNEM_SUFFIX:
40fb9820
L		 3419 i.types[op].bitfield.imm32 = 1;
3420 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3421 break;
3422 case WORD_MNEM_SUFFIX:
40fb9820
L		 3423 i.types[op].bitfield.imm16 = 1;
3424 i.types[op].bitfield.imm32 = 1;
3425 i.types[op].bitfield.imm32s = 1;
3426 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3427 break;
3428 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3429 i.types[op].bitfield.imm8 = 1;
3430 i.types[op].bitfield.imm8s = 1;
3431 i.types[op].bitfield.imm16 = 1;
3432 i.types[op].bitfield.imm32 = 1;
3433 i.types[op].bitfield.imm32s = 1;
3434 i.types[op].bitfield.imm64 = 1;
29b0f896 3435 break;
252b5132 3436 }
252b5132 3437
29b0f896
AM		 3438 /* If this operand is at most 16 bits, convert it
3439 to a signed 16 bit number before trying to see
3440 whether it will fit in an even smaller size.
3441 This allows a 16-bit operand such as $0xffe0 to
3442 be recognised as within Imm8S range. */
40fb9820 3443 if ((i.types[op].bitfield.imm16)
29b0f896 3444 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3445 {
29b0f896
AM		 3446 i.op[op].imms->X_add_number =
3447 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3448 }
40fb9820 3449 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3450 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3451 == 0))
3452 {
3453 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3454 ^ ((offsetT) 1 << 31))
3455 - ((offsetT) 1 << 31));
3456 }
40fb9820 3457 i.types[op]
c6fb90c8
L		 3458 = operand_type_or (i.types[op],
3459 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3460
29b0f896
AM		 3461 /* We must avoid matching of Imm32 templates when 64bit
3462 only immediate is available. */
3463 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3464 i.types[op].bitfield.imm32 = 0;
29b0f896 3465 break;
252b5132 3466
29b0f896
AM		 3467 case O_absent:
3468 case O_register:
3469 abort ();
3470
3471 /* Symbols and expressions. */
3472 default:
9cd96992
JB		 3473 /* Convert symbolic operand to proper sizes for matching, but don't
3474 prevent matching a set of insns that only supports sizes other
3475 than those matching the insn suffix. */
3476 {
40fb9820 3477 i386_operand_type mask, allowed;
9cd96992
JB		 3478 const template *t;
3479
0dfbf9d7
L		 3480 operand_type_set (&mask, 0);
3481 operand_type_set (&allowed, 0);
40fb9820 3482
4eed87de
AM		 3483 for (t = current_templates->start;
3484 t < current_templates->end;
3485 ++t)
c6fb90c8
L		 3486 allowed = operand_type_or (allowed,
3487 t->operand_types[op]);
9cd96992
JB		 3488 switch (guess_suffix)
3489 {
3490 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3491 mask.bitfield.imm64 = 1;
3492 mask.bitfield.imm32s = 1;
9cd96992
JB		 3493 break;
3494 case LONG_MNEM_SUFFIX:
40fb9820 3495 mask.bitfield.imm32 = 1;
9cd96992
JB		 3496 break;
3497 case WORD_MNEM_SUFFIX:
40fb9820 3498 mask.bitfield.imm16 = 1;
9cd96992
JB		 3499 break;
3500 case BYTE_MNEM_SUFFIX:
40fb9820 3501 mask.bitfield.imm8 = 1;
9cd96992
JB		 3502 break;
3503 default:
9cd96992
JB		 3504 break;
3505 }
c6fb90c8 3506 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3507 if (!operand_type_all_zero (&allowed))
c6fb90c8 3508 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3509 }
29b0f896 3510 break;
252b5132 3511 }
29b0f896
AM		 3512 }
3513}
47926f60 3514
29b0f896
AM		 3515/* Try to use the smallest displacement type too. */
3516static void
e3bb37b5 3517optimize_disp (void)
29b0f896
AM		 3518{
3519 int op;
3e73aa7c 3520
29b0f896 3521 for (op = i.operands; --op >= 0;)
40fb9820 3522 if (operand_type_check (i.types[op], disp))
252b5132 3523 {
b300c311 3524 if (i.op[op].disps->X_op == O_constant)
252b5132 3525 {
b300c311 3526 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3527
40fb9820 3528 if (i.types[op].bitfield.disp16
b300c311
L		 3529 && (disp & ~(offsetT) 0xffff) == 0)
3530 {
3531 /* If this operand is at most 16 bits, convert
3532 to a signed 16 bit number and don't use 64bit
3533 displacement. */
3534 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3535 i.types[op].bitfield.disp64 = 0;
b300c311 3536 }
40fb9820 3537 if (i.types[op].bitfield.disp32
b300c311
L		 3538 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3539 {
3540 /* If this operand is at most 32 bits, convert
3541 to a signed 32 bit number and don't use 64bit
3542 displacement. */
3543 disp &= (((offsetT) 2 << 31) - 1);
3544 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3545 i.types[op].bitfield.disp64 = 0;
b300c311 3546 }
40fb9820 3547 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3548 {
40fb9820
L		 3549 i.types[op].bitfield.disp8 = 0;
3550 i.types[op].bitfield.disp16 = 0;
3551 i.types[op].bitfield.disp32 = 0;
3552 i.types[op].bitfield.disp32s = 0;
3553 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3554 i.op[op].disps = 0;
3555 i.disp_operands--;
3556 }
3557 else if (flag_code == CODE_64BIT)
3558 {
3559 if (fits_in_signed_long (disp))
28a9d8f5 3560 {
40fb9820
L		 3561 i.types[op].bitfield.disp64 = 0;
3562 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3563 }
b300c311 3564 if (fits_in_unsigned_long (disp))
40fb9820 3565 i.types[op].bitfield.disp32 = 1;
b300c311 3566 }
40fb9820
L		 3567 if ((i.types[op].bitfield.disp32
3568 || i.types[op].bitfield.disp32s
3569 || i.types[op].bitfield.disp16)
b300c311 3570 && fits_in_signed_byte (disp))
40fb9820 3571 i.types[op].bitfield.disp8 = 1;
252b5132 3572 }
67a4f2b7
AO		 3573 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3574 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3575 {
3576 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3577 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3578 i.types[op].bitfield.disp8 = 0;
3579 i.types[op].bitfield.disp16 = 0;
3580 i.types[op].bitfield.disp32 = 0;
3581 i.types[op].bitfield.disp32s = 0;
3582 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3583 }
3584 else
b300c311 3585 /* We only support 64bit displacement on constants. */
40fb9820 3586 i.types[op].bitfield.disp64 = 0;
252b5132 3587 }
29b0f896
AM		 3588}
3589
fa99fab2 3590static const template *
e3bb37b5 3591match_template (void)
29b0f896
AM		 3592{
3593 /* Points to template once we've found it. */
3594 const template *t;
40fb9820 3595 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3596 i386_operand_type overlap4;
29b0f896 3597 unsigned int found_reverse_match;
40fb9820
L		 3598 i386_opcode_modifier suffix_check;
3599 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3600 int addr_prefix_disp;
a5c311ca 3601 unsigned int j;
3629bb00 3602 unsigned int found_cpu_match;
45664ddb 3603 unsigned int check_register;
29b0f896 3604
c0f3af97
L		 3605#if MAX_OPERANDS != 5
3606# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3607#endif
3608
29b0f896 3609 found_reverse_match = 0;
539e75ad 3610 addr_prefix_disp = -1;
40fb9820
L		 3611
3612 memset (&suffix_check, 0, sizeof (suffix_check));
3613 if (i.suffix == BYTE_MNEM_SUFFIX)
3614 suffix_check.no_bsuf = 1;
3615 else if (i.suffix == WORD_MNEM_SUFFIX)
3616 suffix_check.no_wsuf = 1;
3617 else if (i.suffix == SHORT_MNEM_SUFFIX)
3618 suffix_check.no_ssuf = 1;
3619 else if (i.suffix == LONG_MNEM_SUFFIX)
3620 suffix_check.no_lsuf = 1;
3621 else if (i.suffix == QWORD_MNEM_SUFFIX)
3622 suffix_check.no_qsuf = 1;
3623 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3624 suffix_check.no_ldsuf = 1;
29b0f896 3625
45aa61fe 3626 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3627 {
539e75ad
L		 3628 addr_prefix_disp = -1;
3629
29b0f896
AM		 3630 /* Must have right number of operands. */
3631 if (i.operands != t->operands)
3632 continue;
3633
50aecf8c 3634 /* Check processor support. */
c0f3af97
L		 3635 found_cpu_match = (cpu_flags_match (t)
3636 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3637 if (!found_cpu_match)
3638 continue;
3639
e1d4d893
L		 3640 /* Check old gcc support. */
3641 if (!old_gcc && t->opcode_modifier.oldgcc)
3642 continue;
3643
3644 /* Check AT&T mnemonic. */
3645 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3646 continue;
3647
5c07affc
L		 3648 /* Check AT&T syntax Intel syntax. */
3649 if ((intel_syntax && t->opcode_modifier.attsyntax)
3650 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3651 continue;
3652
20592a94 3653 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3654 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3655 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3656 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3657 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3658 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3659 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3660 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3661 continue;
3662
5c07affc 3663 if (!operand_size_match (t))
7d5e4556 3664 continue;
539e75ad 3665
5c07affc
L		 3666 for (j = 0; j < MAX_OPERANDS; j++)
3667 operand_types[j] = t->operand_types[j];
3668
45aa61fe
AM		 3669 /* In general, don't allow 64-bit operands in 32-bit mode. */
3670 if (i.suffix == QWORD_MNEM_SUFFIX
3671 && flag_code != CODE_64BIT
3672 && (intel_syntax
40fb9820 3673 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3674 && !intel_float_operand (t->name))
3675 : intel_float_operand (t->name) != 2)
40fb9820 3676 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3677 && !operand_types[0].bitfield.regxmm
3678 && !operand_types[0].bitfield.regymm)
40fb9820 3679 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3680 && !!operand_types[t->operands > 1].bitfield.regxmm
3681 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3682 && (t->base_opcode != 0x0fc7
3683 || t->extension_opcode != 1 /* cmpxchg8b */))
3684 continue;
3685
192dc9c6
JB		 3686 /* In general, don't allow 32-bit operands on pre-386. */
3687 else if (i.suffix == LONG_MNEM_SUFFIX
3688 && !cpu_arch_flags.bitfield.cpui386
3689 && (intel_syntax
3690 ? (!t->opcode_modifier.ignoresize
3691 && !intel_float_operand (t->name))
3692 : intel_float_operand (t->name) != 2)
3693 && ((!operand_types[0].bitfield.regmmx
3694 && !operand_types[0].bitfield.regxmm)
3695 || (!operand_types[t->operands > 1].bitfield.regmmx
3696 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3697 continue;
3698
29b0f896 3699 /* Do not verify operands when there are none. */
50aecf8c 3700 else
29b0f896 3701 {
c6fb90c8 3702 if (!t->operands)
2dbab7d5
L		 3703 /* We've found a match; break out of loop. */
3704 break;
29b0f896 3705 }
252b5132 3706
539e75ad
L		 3707 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3708 into Disp32/Disp16/Disp32 operand. */
3709 if (i.prefix[ADDR_PREFIX] != 0)
3710 {
40fb9820 3711 /* There should be only one Disp operand. */
539e75ad
L		 3712 switch (flag_code)
3713 {
3714 case CODE_16BIT:
40fb9820
L		 3715 for (j = 0; j < MAX_OPERANDS; j++)
3716 {
3717 if (operand_types[j].bitfield.disp16)
3718 {
3719 addr_prefix_disp = j;
3720 operand_types[j].bitfield.disp32 = 1;
3721 operand_types[j].bitfield.disp16 = 0;
3722 break;
3723 }
3724 }
539e75ad
L		 3725 break;
3726 case CODE_32BIT:
40fb9820
L		 3727 for (j = 0; j < MAX_OPERANDS; j++)
3728 {
3729 if (operand_types[j].bitfield.disp32)
3730 {
3731 addr_prefix_disp = j;
3732 operand_types[j].bitfield.disp32 = 0;
3733 operand_types[j].bitfield.disp16 = 1;
3734 break;
3735 }
3736 }
539e75ad
L		 3737 break;
3738 case CODE_64BIT:
40fb9820
L		 3739 for (j = 0; j < MAX_OPERANDS; j++)
3740 {
3741 if (operand_types[j].bitfield.disp64)
3742 {
3743 addr_prefix_disp = j;
3744 operand_types[j].bitfield.disp64 = 0;
3745 operand_types[j].bitfield.disp32 = 1;
3746 break;
3747 }
3748 }
539e75ad
L		 3749 break;
3750 }
539e75ad
L		 3751 }
3752
45664ddb
L		 3753 /* We check register size only if size of operands can be
3754 encoded the canonical way. */
3755 check_register = t->opcode_modifier.w;
c6fb90c8 3756 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3757 switch (t->operands)
3758 {
3759 case 1:
40fb9820 3760 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3761 continue;
3762 break;
3763 case 2:
8b38ad71
L		 3764 /* xchg %eax, %eax is a special case. It is an aliase for nop
3765 only in 32bit mode and we can use opcode 0x90. In 64bit
3766 mode, we can't use 0x90 for xchg %eax, %eax since it should
3767 zero-extend %eax to %rax. */
3768 if (flag_code == CODE_64BIT
3769 && t->base_opcode == 0x90
0dfbf9d7
L		 3770 && operand_type_equal (&i.types [0], &acc32)
3771 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3772 continue;
b6169b20
L		 3773 if (i.swap_operand)
3774 {
3775 /* If we swap operand in encoding, we either match
3776 the next one or reverse direction of operands. */
3777 if (t->opcode_modifier.s)
3778 continue;
3779 else if (t->opcode_modifier.d)
3780 goto check_reverse;
3781 }
3782
29b0f896 3783 case 3:
fa99fab2
L		 3784 /* If we swap operand in encoding, we match the next one. */
3785 if (i.swap_operand && t->opcode_modifier.s)
3786 continue;
f48ff2ae 3787 case 4:
c0f3af97 3788 case 5:
c6fb90c8 3789 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3790 if (!operand_type_match (overlap0, i.types[0])
3791 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3792 || (check_register
3793 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3794 operand_types[0],
3795 overlap1, i.types[1],
3796 operand_types[1])))
29b0f896
AM		 3797 {
3798 /* Check if other direction is valid ... */
40fb9820 3799 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3800 continue;
3801
b6169b20 3802check_reverse:
29b0f896 3803 /* Try reversing direction of operands. */
c6fb90c8
L		 3804 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3805 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3806 if (!operand_type_match (overlap0, i.types[0])
3807 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3808 || (check_register
3809 && !operand_type_register_match (overlap0,
3810 i.types[0],
3811 operand_types[1],
3812 overlap1,
3813 i.types[1],
3814 operand_types[0])))
29b0f896
AM		 3815 {
3816 /* Does not match either direction. */
3817 continue;
3818 }
3819 /* found_reverse_match holds which of D or FloatDR
3820 we've found. */
40fb9820 3821 if (t->opcode_modifier.d)
8a2ed489 3822 found_reverse_match = Opcode_D;
40fb9820 3823 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3824 found_reverse_match = Opcode_FloatD;
3825 else
3826 found_reverse_match = 0;
40fb9820 3827 if (t->opcode_modifier.floatr)
8a2ed489 3828 found_reverse_match |= Opcode_FloatR;
29b0f896 3829 }
f48ff2ae 3830 else
29b0f896 3831 {
f48ff2ae 3832 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3833 switch (t->operands)
3834 {
c0f3af97
L		 3835 case 5:
3836 overlap4 = operand_type_and (i.types[4],
3837 operand_types[4]);
d1cbb4db 3838 case 4:
c6fb90c8
L		 3839 overlap3 = operand_type_and (i.types[3],
3840 operand_types[3]);
d1cbb4db 3841 case 3:
c6fb90c8
L		 3842 overlap2 = operand_type_and (i.types[2],
3843 operand_types[2]);
d1cbb4db
L		 3844 break;
3845 }
29b0f896 3846
f48ff2ae
L		 3847 switch (t->operands)
3848 {
c0f3af97
L		 3849 case 5:
3850 if (!operand_type_match (overlap4, i.types[4])
3851 || !operand_type_register_match (overlap3,
3852 i.types[3],
3853 operand_types[3],
3854 overlap4,
3855 i.types[4],
3856 operand_types[4]))
3857 continue;
f48ff2ae 3858 case 4:
40fb9820 3859 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3860 || (check_register
3861 && !operand_type_register_match (overlap2,
3862 i.types[2],
3863 operand_types[2],
3864 overlap3,
3865 i.types[3],
3866 operand_types[3])))
f48ff2ae
L		 3867 continue;
3868 case 3:
3869 /* Here we make use of the fact that there are no
3870 reverse match 3 operand instructions, and all 3
3871 operand instructions only need to be checked for
3872 register consistency between operands 2 and 3. */
40fb9820 3873 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3874 || (check_register
3875 && !operand_type_register_match (overlap1,
3876 i.types[1],
3877 operand_types[1],
3878 overlap2,
3879 i.types[2],
3880 operand_types[2])))
f48ff2ae
L		 3881 continue;
3882 break;
3883 }
29b0f896 3884 }
f48ff2ae 3885 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3886 slip through to break. */
3887 }
3629bb00 3888 if (!found_cpu_match)
29b0f896
AM		 3889 {
3890 found_reverse_match = 0;
3891 continue;
3892 }
c0f3af97 3893
29b0f896
AM		 3894 /* We've found a match; break out of loop. */
3895 break;
3896 }
3897
3898 if (t == current_templates->end)
3899 {
3900 /* We found no match. */
95f283e8
L		 3901 if (intel_syntax)
3902 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3903 current_templates->start->name);
3904 else
3905 as_bad (_("suffix or operands invalid for `%s'"),
3906 current_templates->start->name);
fa99fab2 3907 return NULL;
29b0f896 3908 }
252b5132 3909
29b0f896
AM		 3910 if (!quiet_warnings)
3911 {
3912 if (!intel_syntax
40fb9820
L		 3913 && (i.types[0].bitfield.jumpabsolute
3914 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3915 {
3916 as_warn (_("indirect %s without `*'"), t->name);
3917 }
3918
40fb9820
L		 3919 if (t->opcode_modifier.isprefix
3920 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3921 {
3922 /* Warn them that a data or address size prefix doesn't
3923 affect assembly of the next line of code. */
3924 as_warn (_("stand-alone `%s' prefix"), t->name);
3925 }
3926 }
3927
3928 /* Copy the template we found. */
3929 i.tm = *t;
539e75ad
L		 3930
3931 if (addr_prefix_disp != -1)
3932 i.tm.operand_types[addr_prefix_disp]
3933 = operand_types[addr_prefix_disp];
3934
29b0f896
AM		 3935 if (found_reverse_match)
3936 {
3937 /* If we found a reverse match we must alter the opcode
3938 direction bit. found_reverse_match holds bits to change
3939 (different for int & float insns). */
3940
3941 i.tm.base_opcode ^= found_reverse_match;
3942
539e75ad
L		 3943 i.tm.operand_types[0] = operand_types[1];
3944 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3945 }
3946
fa99fab2 3947 return t;
29b0f896
AM		 3948}
3949
3950static int
e3bb37b5 3951check_string (void)
29b0f896 3952{
40fb9820
L		 3953 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3954 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3955 {
3956 if (i.seg[0] != NULL && i.seg[0] != &es)
3957 {
a87af027 3958 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3959 i.tm.name,
a87af027
JB		 3960 mem_op + 1,
3961 register_prefix);
29b0f896
AM		 3962 return 0;
3963 }
3964 /* There's only ever one segment override allowed per instruction.
3965 This instruction possibly has a legal segment override on the
3966 second operand, so copy the segment to where non-string
3967 instructions store it, allowing common code. */
3968 i.seg[0] = i.seg[1];
3969 }
40fb9820 3970 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3971 {
3972 if (i.seg[1] != NULL && i.seg[1] != &es)
3973 {
a87af027 3974 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3975 i.tm.name,
a87af027
JB		 3976 mem_op + 2,
3977 register_prefix);
29b0f896
AM		 3978 return 0;
3979 }
3980 }
3981 return 1;
3982}
3983
3984static int
543613e9 3985process_suffix (void)
29b0f896
AM		 3986{
3987 /* If matched instruction specifies an explicit instruction mnemonic
3988 suffix, use it. */
40fb9820
L		 3989 if (i.tm.opcode_modifier.size16)
3990 i.suffix = WORD_MNEM_SUFFIX;
3991 else if (i.tm.opcode_modifier.size32)
3992 i.suffix = LONG_MNEM_SUFFIX;
3993 else if (i.tm.opcode_modifier.size64)
3994 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3995 else if (i.reg_operands)
3996 {
3997 /* If there's no instruction mnemonic suffix we try to invent one
3998 based on register operands. */
3999 if (!i.suffix)
4000 {
4001 /* We take i.suffix from the last register operand specified,
4002 Destination register type is more significant than source
381d071f
L		 4003 register type. crc32 in SSE4.2 prefers source register
4004 type. */
4005 if (i.tm.base_opcode == 0xf20f38f1)
4006 {
40fb9820
L		 4007 if (i.types[0].bitfield.reg16)
4008 i.suffix = WORD_MNEM_SUFFIX;
4009 else if (i.types[0].bitfield.reg32)
4010 i.suffix = LONG_MNEM_SUFFIX;
4011 else if (i.types[0].bitfield.reg64)
4012 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4013 }
9344ff29 4014 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4015 {
40fb9820 4016 if (i.types[0].bitfield.reg8)
20592a94
L		 4017 i.suffix = BYTE_MNEM_SUFFIX;
4018 }
381d071f
L		 4019
4020 if (!i.suffix)
4021 {
4022 int op;
4023
20592a94
L		 4024 if (i.tm.base_opcode == 0xf20f38f1
4025 || i.tm.base_opcode == 0xf20f38f0)
4026 {
4027 /* We have to know the operand size for crc32. */
4028 as_bad (_("ambiguous memory operand size for `%s`"),
4029 i.tm.name);
4030 return 0;
4031 }
4032
381d071f 4033 for (op = i.operands; --op >= 0;)
40fb9820 4034 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4035 {
40fb9820
L		 4036 if (i.types[op].bitfield.reg8)
4037 {
4038 i.suffix = BYTE_MNEM_SUFFIX;
4039 break;
4040 }
4041 else if (i.types[op].bitfield.reg16)
4042 {
4043 i.suffix = WORD_MNEM_SUFFIX;
4044 break;
4045 }
4046 else if (i.types[op].bitfield.reg32)
4047 {
4048 i.suffix = LONG_MNEM_SUFFIX;
4049 break;
4050 }
4051 else if (i.types[op].bitfield.reg64)
4052 {
4053 i.suffix = QWORD_MNEM_SUFFIX;
4054 break;
4055 }
381d071f
L		 4056 }
4057 }
29b0f896
AM		 4058 }
4059 else if (i.suffix == BYTE_MNEM_SUFFIX)
4060 {
4061 if (!check_byte_reg ())
4062 return 0;
4063 }
4064 else if (i.suffix == LONG_MNEM_SUFFIX)
4065 {
4066 if (!check_long_reg ())
4067 return 0;
4068 }
4069 else if (i.suffix == QWORD_MNEM_SUFFIX)
4070 {
955e1e6a
L		 4071 if (intel_syntax
4072 && i.tm.opcode_modifier.ignoresize
4073 && i.tm.opcode_modifier.no_qsuf)
4074 i.suffix = 0;
4075 else if (!check_qword_reg ())
29b0f896
AM		 4076 return 0;
4077 }
4078 else if (i.suffix == WORD_MNEM_SUFFIX)
4079 {
4080 if (!check_word_reg ())
4081 return 0;
4082 }
c0f3af97
L		 4083 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4084 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4085 {
c0f3af97 4086 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4087 should check if it is a valid suffix. */
4088 }
40fb9820 4089 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4090 /* Do nothing if the instruction is going to ignore the prefix. */
4091 ;
4092 else
4093 abort ();
4094 }
40fb9820 4095 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4096 && !i.suffix
4097 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4098 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4099 {
4100 i.suffix = stackop_size;
4101 }
9306ca4a
JB		 4102 else if (intel_syntax
4103 && !i.suffix
40fb9820
L		 4104 && (i.tm.operand_types[0].bitfield.jumpabsolute
4105 || i.tm.opcode_modifier.jumpbyte
4106 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4107 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4108 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4109 {
4110 switch (flag_code)
4111 {
4112 case CODE_64BIT:
40fb9820 4113 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4114 {
4115 i.suffix = QWORD_MNEM_SUFFIX;
4116 break;
4117 }
4118 case CODE_32BIT:
40fb9820 4119 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4120 i.suffix = LONG_MNEM_SUFFIX;
4121 break;
4122 case CODE_16BIT:
40fb9820 4123 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4124 i.suffix = WORD_MNEM_SUFFIX;
4125 break;
4126 }
4127 }
252b5132 4128
9306ca4a 4129 if (!i.suffix)
29b0f896 4130 {
9306ca4a
JB		 4131 if (!intel_syntax)
4132 {
40fb9820 4133 if (i.tm.opcode_modifier.w)
9306ca4a 4134 {
4eed87de
AM		 4135 as_bad (_("no instruction mnemonic suffix given and "
4136 "no register operands; can't size instruction"));
9306ca4a
JB		 4137 return 0;
4138 }
4139 }
4140 else
4141 {
40fb9820 4142 unsigned int suffixes;
7ab9ffdd 4143
40fb9820
L		 4144 suffixes = !i.tm.opcode_modifier.no_bsuf;
4145 if (!i.tm.opcode_modifier.no_wsuf)
4146 suffixes |= 1 << 1;
4147 if (!i.tm.opcode_modifier.no_lsuf)
4148 suffixes |= 1 << 2;
fc4adea1 4149 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4150 suffixes |= 1 << 3;
4151 if (!i.tm.opcode_modifier.no_ssuf)
4152 suffixes |= 1 << 4;
4153 if (!i.tm.opcode_modifier.no_qsuf)
4154 suffixes |= 1 << 5;
4155
4156 /* There are more than suffix matches. */
4157 if (i.tm.opcode_modifier.w
9306ca4a 4158 || ((suffixes & (suffixes - 1))
40fb9820
L		 4159 && !i.tm.opcode_modifier.defaultsize
4160 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4161 {
4162 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4163 return 0;
4164 }
4165 }
29b0f896 4166 }
252b5132 4167
9306ca4a
JB		 4168 /* Change the opcode based on the operand size given by i.suffix;
4169 We don't need to change things for byte insns. */
4170
582d5edd
L		 4171 if (i.suffix
4172 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4173 && i.suffix != XMMWORD_MNEM_SUFFIX
4174 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4175 {
4176 /* It's not a byte, select word/dword operation. */
40fb9820 4177 if (i.tm.opcode_modifier.w)
29b0f896 4178 {
40fb9820 4179 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4180 i.tm.base_opcode |= 8;
4181 else
4182 i.tm.base_opcode |= 1;
4183 }
0f3f3d8b 4184
29b0f896
AM		 4185 /* Now select between word & dword operations via the operand
4186 size prefix, except for instructions that will ignore this
4187 prefix anyway. */
ca61edf2 4188 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4189 {
ca61edf2
L		 4190 /* The address size override prefix changes the size of the
4191 first operand. */
40fb9820
L		 4192 if ((flag_code == CODE_32BIT
4193 && i.op->regs[0].reg_type.bitfield.reg16)
4194 || (flag_code != CODE_32BIT
4195 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4196 if (!add_prefix (ADDR_PREFIX_OPCODE))
4197 return 0;
4198 }
4199 else if (i.suffix != QWORD_MNEM_SUFFIX
4200 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4201 && !i.tm.opcode_modifier.ignoresize
4202 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4203 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4204 || (flag_code == CODE_64BIT
40fb9820 4205 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4206 {
4207 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4208
40fb9820 4209 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4210 prefix = ADDR_PREFIX_OPCODE;
252b5132 4211
29b0f896
AM		 4212 if (!add_prefix (prefix))
4213 return 0;
24eab124 4214 }
252b5132 4215
29b0f896
AM		 4216 /* Set mode64 for an operand. */
4217 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4218 && flag_code == CODE_64BIT
40fb9820 4219 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4220 {
4221 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4222 need rex64. cmpxchg8b is also a special case. */
4223 if (! (i.operands == 2
4224 && i.tm.base_opcode == 0x90
4225 && i.tm.extension_opcode == None
0dfbf9d7
L		 4226 && operand_type_equal (&i.types [0], &acc64)
4227 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4228 && ! (i.operands == 1
4229 && i.tm.base_opcode == 0xfc7
4230 && i.tm.extension_opcode == 1
40fb9820
L		 4231 && !operand_type_check (i.types [0], reg)
4232 && operand_type_check (i.types [0], anymem)))
f6bee062 4233 i.rex |= REX_W;
46e883c5 4234 }
3e73aa7c 4235
29b0f896
AM		 4236 /* Size floating point instruction. */
4237 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4238 if (i.tm.opcode_modifier.floatmf)
543613e9 4239 i.tm.base_opcode ^= 4;
29b0f896 4240 }
7ecd2f8b 4241
29b0f896
AM		 4242 return 1;
4243}
3e73aa7c 4244
29b0f896 4245static int
543613e9 4246check_byte_reg (void)
29b0f896
AM		 4247{
4248 int op;
543613e9 4249
29b0f896
AM		 4250 for (op = i.operands; --op >= 0;)
4251 {
4252 /* If this is an eight bit register, it's OK. If it's the 16 or
4253 32 bit version of an eight bit register, we will just use the
4254 low portion, and that's OK too. */
40fb9820 4255 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4256 continue;
4257
ca61edf2
L		 4258 /* Don't generate this warning if not needed. */
4259 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4260 continue;
4261
9344ff29
L		 4262 /* crc32 doesn't generate this warning. */
4263 if (i.tm.base_opcode == 0xf20f38f0)
4264 continue;
4265
40fb9820
L		 4266 if ((i.types[op].bitfield.reg16
4267 || i.types[op].bitfield.reg32
4268 || i.types[op].bitfield.reg64)
4269 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4270 {
4271 /* Prohibit these changes in the 64bit mode, since the
4272 lowering is more complicated. */
4273 if (flag_code == CODE_64BIT
40fb9820 4274 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4275 {
2ca3ace5
L		 4276 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4277 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4278 i.suffix);
4279 return 0;
4280 }
4281#if REGISTER_WARNINGS
4282 if (!quiet_warnings
40fb9820 4283 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4284 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4285 register_prefix,
40fb9820 4286 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4287 ? REGNAM_AL - REGNAM_AX
4288 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4289 register_prefix,
29b0f896
AM		 4290 i.op[op].regs->reg_name,
4291 i.suffix);
4292#endif
4293 continue;
4294 }
4295 /* Any other register is bad. */
40fb9820
L		 4296 if (i.types[op].bitfield.reg16
4297 || i.types[op].bitfield.reg32
4298 || i.types[op].bitfield.reg64
4299 || i.types[op].bitfield.regmmx
4300 || i.types[op].bitfield.regxmm
c0f3af97 4301 || i.types[op].bitfield.regymm
40fb9820
L		 4302 || i.types[op].bitfield.sreg2
4303 || i.types[op].bitfield.sreg3
4304 || i.types[op].bitfield.control
4305 || i.types[op].bitfield.debug
4306 || i.types[op].bitfield.test
4307 || i.types[op].bitfield.floatreg
4308 || i.types[op].bitfield.floatacc)
29b0f896 4309 {
a540244d
L		 4310 as_bad (_("`%s%s' not allowed with `%s%c'"),
4311 register_prefix,
29b0f896
AM		 4312 i.op[op].regs->reg_name,
4313 i.tm.name,
4314 i.suffix);
4315 return 0;
4316 }
4317 }
4318 return 1;
4319}
4320
4321static int
e3bb37b5 4322check_long_reg (void)
29b0f896
AM		 4323{
4324 int op;
4325
4326 for (op = i.operands; --op >= 0;)
4327 /* Reject eight bit registers, except where the template requires
4328 them. (eg. movzb) */
40fb9820
L		 4329 if (i.types[op].bitfield.reg8
4330 && (i.tm.operand_types[op].bitfield.reg16
4331 || i.tm.operand_types[op].bitfield.reg32
4332 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4333 {
a540244d
L		 4334 as_bad (_("`%s%s' not allowed with `%s%c'"),
4335 register_prefix,
29b0f896
AM		 4336 i.op[op].regs->reg_name,
4337 i.tm.name,
4338 i.suffix);
4339 return 0;
4340 }
4341 /* Warn if the e prefix on a general reg is missing. */
4342 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4343 && i.types[op].bitfield.reg16
4344 && (i.tm.operand_types[op].bitfield.reg32
4345 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4346 {
4347 /* Prohibit these changes in the 64bit mode, since the
4348 lowering is more complicated. */
4349 if (flag_code == CODE_64BIT)
252b5132 4350 {
2ca3ace5
L		 4351 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4352 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4353 i.suffix);
4354 return 0;
252b5132 4355 }
29b0f896
AM		 4356#if REGISTER_WARNINGS
4357 else
a540244d
L		 4358 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4359 register_prefix,
29b0f896 4360 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4361 register_prefix,
29b0f896
AM		 4362 i.op[op].regs->reg_name,
4363 i.suffix);
4364#endif
252b5132 4365 }
29b0f896 4366 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4367 else if (i.types[op].bitfield.reg64
4368 && (i.tm.operand_types[op].bitfield.reg32
4369 || i.tm.operand_types[op].bitfield.acc))
252b5132 4370 {
34828aad 4371 if (intel_syntax
ca61edf2 4372 && i.tm.opcode_modifier.toqword
40fb9820 4373 && !i.types[0].bitfield.regxmm)
34828aad 4374 {
ca61edf2 4375 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4376 i.suffix = QWORD_MNEM_SUFFIX;
4377 }
4378 else
4379 {
4380 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4381 register_prefix, i.op[op].regs->reg_name,
4382 i.suffix);
4383 return 0;
4384 }
29b0f896
AM		 4385 }
4386 return 1;
4387}
252b5132 4388
29b0f896 4389static int
e3bb37b5 4390check_qword_reg (void)
29b0f896
AM		 4391{
4392 int op;
252b5132 4393
29b0f896
AM		 4394 for (op = i.operands; --op >= 0; )
4395 /* Reject eight bit registers, except where the template requires
4396 them. (eg. movzb) */
40fb9820
L		 4397 if (i.types[op].bitfield.reg8
4398 && (i.tm.operand_types[op].bitfield.reg16
4399 || i.tm.operand_types[op].bitfield.reg32
4400 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4401 {
a540244d
L		 4402 as_bad (_("`%s%s' not allowed with `%s%c'"),
4403 register_prefix,
29b0f896
AM		 4404 i.op[op].regs->reg_name,
4405 i.tm.name,
4406 i.suffix);
4407 return 0;
4408 }
4409 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4410 else if ((i.types[op].bitfield.reg16
4411 || i.types[op].bitfield.reg32)
4412 && (i.tm.operand_types[op].bitfield.reg32
4413 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4414 {
4415 /* Prohibit these changes in the 64bit mode, since the
4416 lowering is more complicated. */
34828aad 4417 if (intel_syntax
ca61edf2 4418 && i.tm.opcode_modifier.todword
40fb9820 4419 && !i.types[0].bitfield.regxmm)
34828aad 4420 {
ca61edf2 4421 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4422 i.suffix = LONG_MNEM_SUFFIX;
4423 }
4424 else
4425 {
4426 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4427 register_prefix, i.op[op].regs->reg_name,
4428 i.suffix);
4429 return 0;
4430 }
252b5132 4431 }
29b0f896
AM		 4432 return 1;
4433}
252b5132 4434
29b0f896 4435static int
e3bb37b5 4436check_word_reg (void)
29b0f896
AM		 4437{
4438 int op;
4439 for (op = i.operands; --op >= 0;)
4440 /* Reject eight bit registers, except where the template requires
4441 them. (eg. movzb) */
40fb9820
L		 4442 if (i.types[op].bitfield.reg8
4443 && (i.tm.operand_types[op].bitfield.reg16
4444 || i.tm.operand_types[op].bitfield.reg32
4445 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4446 {
a540244d
L		 4447 as_bad (_("`%s%s' not allowed with `%s%c'"),
4448 register_prefix,
29b0f896
AM		 4449 i.op[op].regs->reg_name,
4450 i.tm.name,
4451 i.suffix);
4452 return 0;
4453 }
4454 /* Warn if the e prefix on a general reg is present. */
4455 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4456 && i.types[op].bitfield.reg32
4457 && (i.tm.operand_types[op].bitfield.reg16
4458 || i.tm.operand_types[op].bitfield.acc))
252b5132 4459 {
29b0f896
AM		 4460 /* Prohibit these changes in the 64bit mode, since the
4461 lowering is more complicated. */
4462 if (flag_code == CODE_64BIT)
252b5132 4463 {
2ca3ace5
L		 4464 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4465 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4466 i.suffix);
4467 return 0;
252b5132 4468 }
29b0f896
AM		 4469 else
4470#if REGISTER_WARNINGS
a540244d
L		 4471 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4472 register_prefix,
29b0f896 4473 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4474 register_prefix,
29b0f896
AM		 4475 i.op[op].regs->reg_name,
4476 i.suffix);
4477#endif
4478 }
4479 return 1;
4480}
252b5132 4481
29b0f896 4482static int
40fb9820 4483update_imm (unsigned int j)
29b0f896 4484{
bc0844ae 4485 i386_operand_type overlap = i.types[j];
40fb9820
L		 4486 if ((overlap.bitfield.imm8
4487 || overlap.bitfield.imm8s
4488 || overlap.bitfield.imm16
4489 || overlap.bitfield.imm32
4490 || overlap.bitfield.imm32s
4491 || overlap.bitfield.imm64)
0dfbf9d7
L		 4492 && !operand_type_equal (&overlap, &imm8)
4493 && !operand_type_equal (&overlap, &imm8s)
4494 && !operand_type_equal (&overlap, &imm16)
4495 && !operand_type_equal (&overlap, &imm32)
4496 && !operand_type_equal (&overlap, &imm32s)
4497 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4498 {
4499 if (i.suffix)
4500 {
40fb9820
L		 4501 i386_operand_type temp;
4502
0dfbf9d7 4503 operand_type_set (&temp, 0);
7ab9ffdd 4504 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4505 {
4506 temp.bitfield.imm8 = overlap.bitfield.imm8;
4507 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4508 }
4509 else if (i.suffix == WORD_MNEM_SUFFIX)
4510 temp.bitfield.imm16 = overlap.bitfield.imm16;
4511 else if (i.suffix == QWORD_MNEM_SUFFIX)
4512 {
4513 temp.bitfield.imm64 = overlap.bitfield.imm64;
4514 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4515 }
4516 else
4517 temp.bitfield.imm32 = overlap.bitfield.imm32;
4518 overlap = temp;
29b0f896 4519 }
0dfbf9d7
L		 4520 else if (operand_type_equal (&overlap, &imm16_32_32s)
4521 || operand_type_equal (&overlap, &imm16_32)
4522 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4523 {
40fb9820 4524 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4525 overlap = imm16;
40fb9820 4526 else
65da13b5 4527 overlap = imm32s;
29b0f896 4528 }
0dfbf9d7
L		 4529 if (!operand_type_equal (&overlap, &imm8)
4530 && !operand_type_equal (&overlap, &imm8s)
4531 && !operand_type_equal (&overlap, &imm16)
4532 && !operand_type_equal (&overlap, &imm32)
4533 && !operand_type_equal (&overlap, &imm32s)
4534 && !operand_type_equal (&overlap, &imm64))
29b0f896 4535 {
4eed87de
AM		 4536 as_bad (_("no instruction mnemonic suffix given; "
4537 "can't determine immediate size"));
29b0f896
AM		 4538 return 0;
4539 }
4540 }
40fb9820 4541 i.types[j] = overlap;
29b0f896 4542
40fb9820
L		 4543 return 1;
4544}
4545
4546static int
4547finalize_imm (void)
4548{
bc0844ae 4549 unsigned int j, n;
29b0f896 4550
bc0844ae
L		 4551 /* Update the first 2 immediate operands. */
4552 n = i.operands > 2 ? 2 : i.operands;
4553 if (n)
4554 {
4555 for (j = 0; j < n; j++)
4556 if (update_imm (j) == 0)
4557 return 0;
40fb9820 4558
bc0844ae
L		 4559 /* The 3rd operand can't be immediate operand. */
4560 gas_assert (operand_type_check (i.types[2], imm) == 0);
4561 }
29b0f896
AM		 4562
4563 return 1;
4564}
4565
c0f3af97
L		 4566static int
4567bad_implicit_operand (int xmm)
4568{
4569 const char *reg = xmm ? "xmm0" : "ymm0";
4570 if (intel_syntax)
4571 as_bad (_("the last operand of `%s' must be `%s%s'"),
4572 i.tm.name, register_prefix, reg);
4573 else
4574 as_bad (_("the first operand of `%s' must be `%s%s'"),
4575 i.tm.name, register_prefix, reg);
4576 return 0;
4577}
4578
29b0f896 4579static int
e3bb37b5 4580process_operands (void)
29b0f896
AM		 4581{
4582 /* Default segment register this instruction will use for memory
4583 accesses. 0 means unknown. This is only for optimizing out
4584 unnecessary segment overrides. */
4585 const seg_entry *default_seg = 0;
4586
c0f3af97
L		 4587 if (i.tm.opcode_modifier.sse2avx
4588 && (i.tm.opcode_modifier.vexnds
4589 || i.tm.opcode_modifier.vexndd))
29b0f896 4590 {
c0f3af97
L		 4591 unsigned int dup = i.operands;
4592 unsigned int dest = dup - 1;
9fcfb3d7
L		 4593 unsigned int j;
4594
c0f3af97 4595 /* The destination must be an xmm register. */
9c2799c2 4596 gas_assert (i.reg_operands
7ab9ffdd
L		 4597 && MAX_OPERANDS > dup
4598 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4599
4600 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4601 {
c0f3af97 4602 /* The first operand is implicit and must be xmm0. */
9c2799c2 4603 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4604 if (i.op[0].regs->reg_num != 0)
4605 return bad_implicit_operand (1);
4606
4607 if (i.tm.opcode_modifier.vex3sources)
4608 {
4609 /* Keep xmm0 for instructions with VEX prefix and 3
4610 sources. */
4611 goto duplicate;
4612 }
e2ec9d29 4613 else
c0f3af97
L		 4614 {
4615 /* We remove the first xmm0 and keep the number of
4616 operands unchanged, which in fact duplicates the
4617 destination. */
4618 for (j = 1; j < i.operands; j++)
4619 {
4620 i.op[j - 1] = i.op[j];
4621 i.types[j - 1] = i.types[j];
4622 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4623 }
4624 }
4625 }
4626 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4627 {
9c2799c2 4628 gas_assert ((MAX_OPERANDS - 1) > dup
7ab9ffdd 4629 && i.tm.opcode_modifier.vex3sources);
c0f3af97
L		 4630
4631 /* Add the implicit xmm0 for instructions with VEX prefix
4632 and 3 sources. */
4633 for (j = i.operands; j > 0; j--)
4634 {
4635 i.op[j] = i.op[j - 1];
4636 i.types[j] = i.types[j - 1];
4637 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4638 }
4639 i.op[0].regs
4640 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4641 i.types[0] = regxmm;
c0f3af97
L		 4642 i.tm.operand_types[0] = regxmm;
4643
4644 i.operands += 2;
4645 i.reg_operands += 2;
4646 i.tm.operands += 2;
4647
4648 dup++;
4649 dest++;
4650 i.op[dup] = i.op[dest];
4651 i.types[dup] = i.types[dest];
4652 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4653 }
c0f3af97
L		 4654 else
4655 {
4656duplicate:
4657 i.operands++;
4658 i.reg_operands++;
4659 i.tm.operands++;
4660
4661 i.op[dup] = i.op[dest];
4662 i.types[dup] = i.types[dest];
4663 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4664 }
4665
4666 if (i.tm.opcode_modifier.immext)
4667 process_immext ();
4668 }
4669 else if (i.tm.opcode_modifier.firstxmm0)
4670 {
4671 unsigned int j;
4672
4673 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4674 gas_assert (i.reg_operands
7ab9ffdd
L		 4675 && (operand_type_equal (&i.types[0], &regxmm)
4676 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4677 if (i.op[0].regs->reg_num != 0)
4678 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4679
4680 for (j = 1; j < i.operands; j++)
4681 {
4682 i.op[j - 1] = i.op[j];
4683 i.types[j - 1] = i.types[j];
4684
4685 /* We need to adjust fields in i.tm since they are used by
4686 build_modrm_byte. */
4687 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4688 }
4689
e2ec9d29
L		 4690 i.operands--;
4691 i.reg_operands--;
e2ec9d29
L		 4692 i.tm.operands--;
4693 }
4694 else if (i.tm.opcode_modifier.regkludge)
4695 {
4696 /* The imul $imm, %reg instruction is converted into
4697 imul $imm, %reg, %reg, and the clr %reg instruction
4698 is converted into xor %reg, %reg. */
4699
4700 unsigned int first_reg_op;
4701
4702 if (operand_type_check (i.types[0], reg))
4703 first_reg_op = 0;
4704 else
4705 first_reg_op = 1;
4706 /* Pretend we saw the extra register operand. */
9c2799c2 4707 gas_assert (i.reg_operands == 1
7ab9ffdd 4708 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4709 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4710 i.types[first_reg_op + 1] = i.types[first_reg_op];
4711 i.operands++;
4712 i.reg_operands++;
29b0f896
AM		 4713 }
4714
40fb9820 4715 if (i.tm.opcode_modifier.shortform)
29b0f896 4716 {
40fb9820
L		 4717 if (i.types[0].bitfield.sreg2
4718 || i.types[0].bitfield.sreg3)
29b0f896 4719 {
4eed87de
AM		 4720 if (i.tm.base_opcode == POP_SEG_SHORT
4721 && i.op[0].regs->reg_num == 1)
29b0f896 4722 {
a87af027 4723 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4724 return 0;
29b0f896 4725 }
4eed87de
AM		 4726 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4727 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4728 i.rex |= REX_B;
4eed87de
AM		 4729 }
4730 else
4731 {
7ab9ffdd 4732 /* The register or float register operand is in operand
85f10a01 4733 0 or 1. */
40fb9820 4734 unsigned int op;
7ab9ffdd
L		 4735
4736 if (i.types[0].bitfield.floatreg
4737 || operand_type_check (i.types[0], reg))
4738 op = 0;
4739 else
4740 op = 1;
4eed87de
AM		 4741 /* Register goes in low 3 bits of opcode. */
4742 i.tm.base_opcode |= i.op[op].regs->reg_num;
4743 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4744 i.rex |= REX_B;
40fb9820 4745 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4746 {
4eed87de
AM		 4747 /* Warn about some common errors, but press on regardless.
4748 The first case can be generated by gcc (<= 2.8.1). */
4749 if (i.operands == 2)
4750 {
4751 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4752 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4753 register_prefix, i.op[!intel_syntax].regs->reg_name,
4754 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4755 }
4756 else
4757 {
4758 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4759 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4760 register_prefix, i.op[0].regs->reg_name);
4eed87de 4761 }
29b0f896
AM		 4762 }
4763 }
4764 }
40fb9820 4765 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4766 {
4767 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4768 must be put into the modrm byte). Now, we make the modrm and
4769 index base bytes based on all the info we've collected. */
29b0f896
AM		 4770
4771 default_seg = build_modrm_byte ();
4772 }
8a2ed489 4773 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4774 {
4775 default_seg = &ds;
4776 }
40fb9820 4777 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4778 {
4779 /* For the string instructions that allow a segment override
4780 on one of their operands, the default segment is ds. */
4781 default_seg = &ds;
4782 }
4783
75178d9d
L		 4784 if (i.tm.base_opcode == 0x8d /* lea */
4785 && i.seg[0]
4786 && !quiet_warnings)
30123838 4787 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4788
4789 /* If a segment was explicitly specified, and the specified segment
4790 is not the default, use an opcode prefix to select it. If we
4791 never figured out what the default segment is, then default_seg
4792 will be zero at this point, and the specified segment prefix will
4793 always be used. */
29b0f896
AM		 4794 if ((i.seg[0]) && (i.seg[0] != default_seg))
4795 {
4796 if (!add_prefix (i.seg[0]->seg_prefix))
4797 return 0;
4798 }
4799 return 1;
4800}
4801
4802static const seg_entry *
e3bb37b5 4803build_modrm_byte (void)
29b0f896
AM		 4804{
4805 const seg_entry *default_seg = 0;
c0f3af97 4806 unsigned int source, dest;
7ab9ffdd 4807 int vex_3_sources;
c0f3af97
L		 4808
4809 /* The first operand of instructions with VEX prefix and 3 sources
4810 must be VEX_Imm4. */
4811 vex_3_sources = i.tm.opcode_modifier.vex3sources;
4812 if (vex_3_sources)
4813 {
4814 unsigned int nds, reg;
4815
922d8de8
DR		 4816 if (i.tm.opcode_modifier.veximmext
4817 && i.tm.opcode_modifier.immext)
4818 {
4819 dest = i.operands - 2;
4820 gas_assert (dest == 3);
4821 }
4822 else
0bfee649 4823 dest = i.operands - 1;
c0f3af97 4824 nds = dest - 1;
922d8de8
DR		 4825
4826 /* This instruction must have 4 register operands
4827 or 3 register operands plus 1 memory operand.
4828 It must have VexNDS and VexImmExt. */
4829 gas_assert ((i.reg_operands == 4
7ab9ffdd
L		 4830 || (i.reg_operands == 3 && i.mem_operands == 1))
4831 && i.tm.opcode_modifier.vexnds
4832 && i.tm.opcode_modifier.veximmext
922d8de8
DR		 4833 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4834 || operand_type_equal (&i.tm.operand_types[dest], &regymm)));
c0f3af97 4835
0bfee649
L		 4836 /* Generate an 8bit immediate operand to encode the register
4837 operand. */
4838 expressionS *exp = &im_expressions[i.imm_operands++];
4839 i.op[i.operands].imms = exp;
4840 i.types[i.operands] = imm8;
4841 i.operands++;
922d8de8
DR		 4842 /* If VexW1 is set, the first operand is the source and
4843 the second operand is encoded in the immediate operand. */
4844 if (i.tm.opcode_modifier.vexw1)
4845 {
4846 source = 0;
4847 reg = 1;
4848 }
4849 else
4850 {
4851 source = 1;
4852 reg = 0;
4853 }
4854 /* FMA4 swaps REG and NDS. */
4855 if (i.tm.cpu_flags.bitfield.cpufma4)
4856 {
4857 unsigned int tmp;
4858 tmp = reg;
4859 reg = nds;
4860 nds = tmp;
4861 }
4862 gas_assert ((operand_type_equal (&i.tm.operand_types[reg], &regxmm)
4863 || operand_type_equal (&i.tm.operand_types[reg],
4864 &regymm))
4865 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
4866 || operand_type_equal (&i.tm.operand_types[nds],
4867 &regymm)));
0bfee649
L		 4868 exp->X_op = O_constant;
4869 exp->X_add_number
922d8de8
DR		 4870 = ((i.op[reg].regs->reg_num
4871 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 4872 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 4873 }
4874 else
4875 source = dest = 0;
29b0f896
AM		 4876
4877 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 4878 implicit registers do not count. If there are 3 register
4879 operands, it must be a instruction with VexNDS. For a
4880 instruction with VexNDD, the destination register is encoded
4881 in VEX prefix. If there are 4 register operands, it must be
4882 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 4883 if (i.mem_operands == 0
4884 && ((i.reg_operands == 2
4885 && !i.tm.opcode_modifier.vexndd)
4886 || (i.reg_operands == 3
4887 && i.tm.opcode_modifier.vexnds)
4888 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 4889 {
cab737b9
L		 4890 switch (i.operands)
4891 {
4892 case 2:
4893 source = 0;
4894 break;
4895 case 3:
c81128dc
L		 4896 /* When there are 3 operands, one of them may be immediate,
4897 which may be the first or the last operand. Otherwise,
c0f3af97
L		 4898 the first operand must be shift count register (cl) or it
4899 is an instruction with VexNDS. */
9c2799c2 4900 gas_assert (i.imm_operands == 1
7ab9ffdd
L		 4901 || (i.imm_operands == 0
4902 && (i.tm.opcode_modifier.vexnds
4903 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 4904 if (operand_type_check (i.types[0], imm)
4905 || i.types[0].bitfield.shiftcount)
4906 source = 1;
4907 else
4908 source = 0;
cab737b9
L		 4909 break;
4910 case 4:
368d64cc
L		 4911 /* When there are 4 operands, the first two must be 8bit
4912 immediate operands. The source operand will be the 3rd
c0f3af97
L		 4913 one.
4914
4915 For instructions with VexNDS, if the first operand
4916 an imm8, the source operand is the 2nd one. If the last
4917 operand is imm8, the source operand is the first one. */
9c2799c2 4918 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 4919 && i.types[0].bitfield.imm8
4920 && i.types[1].bitfield.imm8)
4921 || (i.tm.opcode_modifier.vexnds
4922 && i.imm_operands == 1
4923 && (i.types[0].bitfield.imm8
4924 || i.types[i.operands - 1].bitfield.imm8)));
c0f3af97
L		 4925 if (i.tm.opcode_modifier.vexnds)
4926 {
4927 if (i.types[0].bitfield.imm8)
4928 source = 1;
4929 else
4930 source = 0;
4931 }
4932 else
4933 source = 2;
4934 break;
4935 case 5:
cab737b9
L		 4936 break;
4937 default:
4938 abort ();
4939 }
4940
c0f3af97
L		 4941 if (!vex_3_sources)
4942 {
4943 dest = source + 1;
4944
4945 if (i.tm.opcode_modifier.vexnds)
4946 {
4947 /* For instructions with VexNDS, the register-only
4948 source operand must be XMM or YMM register. It is
fa99fab2
L		 4949 encoded in VEX prefix. We need to clear RegMem bit
4950 before calling operand_type_equal. */
4951 i386_operand_type op = i.tm.operand_types[dest];
4952 op.bitfield.regmem = 0;
c0f3af97 4953 if ((dest + 1) >= i.operands
fa99fab2
L		 4954 || (!operand_type_equal (&op, &regxmm)
4955 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 4956 abort ();
4957 i.vex.register_specifier = i.op[dest].regs;
4958 dest++;
4959 }
4960 }
29b0f896
AM		 4961
4962 i.rm.mode = 3;
4963 /* One of the register operands will be encoded in the i.tm.reg
4964 field, the other in the combined i.tm.mode and i.tm.regmem
4965 fields. If no form of this instruction supports a memory
4966 destination operand, then we assume the source operand may
4967 sometimes be a memory operand and so we need to store the
4968 destination in the i.rm.reg field. */
40fb9820
L		 4969 if (!i.tm.operand_types[dest].bitfield.regmem
4970 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4971 {
4972 i.rm.reg = i.op[dest].regs->reg_num;
4973 i.rm.regmem = i.op[source].regs->reg_num;
4974 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4975 i.rex |= REX_R;
29b0f896 4976 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4977 i.rex |= REX_B;
29b0f896
AM		 4978 }
4979 else
4980 {
4981 i.rm.reg = i.op[source].regs->reg_num;
4982 i.rm.regmem = i.op[dest].regs->reg_num;
4983 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4984 i.rex |= REX_B;
29b0f896 4985 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4986 i.rex |= REX_R;
29b0f896 4987 }
161a04f6 4988 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4989 {
40fb9820
L		 4990 if (!i.types[0].bitfield.control
4991 && !i.types[1].bitfield.control)
c4a530c5 4992 abort ();
161a04f6 4993 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4994 add_prefix (LOCK_PREFIX_OPCODE);
4995 }
29b0f896
AM		 4996 }
4997 else
4998 { /* If it's not 2 reg operands... */
c0f3af97
L		 4999 unsigned int mem;
5000
29b0f896
AM		 5001 if (i.mem_operands)
5002 {
5003 unsigned int fake_zero_displacement = 0;
99018f42 5004 unsigned int op;
4eed87de 5005
7ab9ffdd
L		 5006 for (op = 0; op < i.operands; op++)
5007 if (operand_type_check (i.types[op], anymem))
5008 break;
7ab9ffdd 5009 gas_assert (op < i.operands);
29b0f896
AM		 5010
5011 default_seg = &ds;
5012
5013 if (i.base_reg == 0)
5014 {
5015 i.rm.mode = 0;
5016 if (!i.disp_operands)
5017 fake_zero_displacement = 1;
5018 if (i.index_reg == 0)
5019 {
5020 /* Operand is just <disp> */
20f0a1fc 5021 if (flag_code == CODE_64BIT)
29b0f896
AM		 5022 {
5023 /* 64bit mode overwrites the 32bit absolute
5024 addressing by RIP relative addressing and
5025 absolute addressing is encoded by one of the
5026 redundant SIB forms. */
5027 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5028 i.sib.base = NO_BASE_REGISTER;
5029 i.sib.index = NO_INDEX_REGISTER;
fc225355 5030 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5031 ? disp32s : disp32);
20f0a1fc 5032 }
fc225355
L		 5033 else if ((flag_code == CODE_16BIT)
5034 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5035 {
5036 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5037 i.types[op] = disp16;
20f0a1fc
NC		 5038 }
5039 else
5040 {
5041 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5042 i.types[op] = disp32;
29b0f896
AM		 5043 }
5044 }
5045 else /* !i.base_reg && i.index_reg */
5046 {
db51cc60
L		 5047 if (i.index_reg->reg_num == RegEiz
5048 || i.index_reg->reg_num == RegRiz)
5049 i.sib.index = NO_INDEX_REGISTER;
5050 else
5051 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5052 i.sib.base = NO_BASE_REGISTER;
5053 i.sib.scale = i.log2_scale_factor;
5054 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5055 i.types[op].bitfield.disp8 = 0;
5056 i.types[op].bitfield.disp16 = 0;
5057 i.types[op].bitfield.disp64 = 0;
29b0f896 5058 if (flag_code != CODE_64BIT)
40fb9820
L		 5059 {
5060 /* Must be 32 bit */
5061 i.types[op].bitfield.disp32 = 1;
5062 i.types[op].bitfield.disp32s = 0;
5063 }
29b0f896 5064 else
40fb9820
L		 5065 {
5066 i.types[op].bitfield.disp32 = 0;
5067 i.types[op].bitfield.disp32s = 1;
5068 }
29b0f896 5069 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5070 i.rex |= REX_X;
29b0f896
AM		 5071 }
5072 }
5073 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5074 else if (i.base_reg->reg_num == RegRip ||
5075 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5076 {
5077 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5078 i.types[op].bitfield.disp8 = 0;
5079 i.types[op].bitfield.disp16 = 0;
5080 i.types[op].bitfield.disp32 = 0;
5081 i.types[op].bitfield.disp32s = 1;
5082 i.types[op].bitfield.disp64 = 0;
71903a11 5083 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5084 if (! i.disp_operands)
5085 fake_zero_displacement = 1;
29b0f896 5086 }
40fb9820 5087 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5088 {
5089 switch (i.base_reg->reg_num)
5090 {
5091 case 3: /* (%bx) */
5092 if (i.index_reg == 0)
5093 i.rm.regmem = 7;
5094 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5095 i.rm.regmem = i.index_reg->reg_num - 6;
5096 break;
5097 case 5: /* (%bp) */
5098 default_seg = &ss;
5099 if (i.index_reg == 0)
5100 {
5101 i.rm.regmem = 6;
40fb9820 5102 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5103 {
5104 /* fake (%bp) into 0(%bp) */
40fb9820 5105 i.types[op].bitfield.disp8 = 1;
252b5132 5106 fake_zero_displacement = 1;
29b0f896
AM		 5107 }
5108 }
5109 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5110 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5111 break;
5112 default: /* (%si) -> 4 or (%di) -> 5 */
5113 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5114 }
5115 i.rm.mode = mode_from_disp_size (i.types[op]);
5116 }
5117 else /* i.base_reg and 32/64 bit mode */
5118 {
5119 if (flag_code == CODE_64BIT
40fb9820
L		 5120 && operand_type_check (i.types[op], disp))
5121 {
5122 i386_operand_type temp;
0dfbf9d7 5123 operand_type_set (&temp, 0);
40fb9820
L		 5124 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5125 i.types[op] = temp;
5126 if (i.prefix[ADDR_PREFIX] == 0)
5127 i.types[op].bitfield.disp32s = 1;
5128 else
5129 i.types[op].bitfield.disp32 = 1;
5130 }
20f0a1fc 5131
29b0f896
AM		 5132 i.rm.regmem = i.base_reg->reg_num;
5133 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5134 i.rex |= REX_B;
29b0f896
AM		 5135 i.sib.base = i.base_reg->reg_num;
5136 /* x86-64 ignores REX prefix bit here to avoid decoder
5137 complications. */
5138 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5139 {
5140 default_seg = &ss;
5141 if (i.disp_operands == 0)
5142 {
5143 fake_zero_displacement = 1;
40fb9820 5144 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5145 }
5146 }
5147 else if (i.base_reg->reg_num == ESP_REG_NUM)
5148 {
5149 default_seg = &ss;
5150 }
5151 i.sib.scale = i.log2_scale_factor;
5152 if (i.index_reg == 0)
5153 {
5154 /* <disp>(%esp) becomes two byte modrm with no index
5155 register. We've already stored the code for esp
5156 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5157 Any base register besides %esp will not use the
5158 extra modrm byte. */
5159 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5160 }
5161 else
5162 {
db51cc60
L		 5163 if (i.index_reg->reg_num == RegEiz
5164 || i.index_reg->reg_num == RegRiz)
5165 i.sib.index = NO_INDEX_REGISTER;
5166 else
5167 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5168 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5169 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5170 i.rex |= REX_X;
29b0f896 5171 }
67a4f2b7
AO		 5172
5173 if (i.disp_operands
5174 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5175 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5176 i.rm.mode = 0;
5177 else
5178 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5179 }
252b5132 5180
29b0f896
AM		 5181 if (fake_zero_displacement)
5182 {
5183 /* Fakes a zero displacement assuming that i.types[op]
5184 holds the correct displacement size. */
5185 expressionS *exp;
5186
9c2799c2 5187 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5188 exp = &disp_expressions[i.disp_operands++];
5189 i.op[op].disps = exp;
5190 exp->X_op = O_constant;
5191 exp->X_add_number = 0;
5192 exp->X_add_symbol = (symbolS *) 0;
5193 exp->X_op_symbol = (symbolS *) 0;
5194 }
c0f3af97
L		 5195
5196 mem = op;
29b0f896 5197 }
c0f3af97
L		 5198 else
5199 mem = ~0;
252b5132 5200
29b0f896
AM		 5201 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5202 (if any) based on i.tm.extension_opcode. Again, we must be
5203 careful to make sure that segment/control/debug/test/MMX
5204 registers are coded into the i.rm.reg field. */
5205 if (i.reg_operands)
5206 {
99018f42 5207 unsigned int op;
7ab9ffdd
L		 5208 unsigned int vex_reg = ~0;
5209
5210 for (op = 0; op < i.operands; op++)
5211 if (i.types[op].bitfield.reg8
5212 || i.types[op].bitfield.reg16
5213 || i.types[op].bitfield.reg32
5214 || i.types[op].bitfield.reg64
5215 || i.types[op].bitfield.regmmx
5216 || i.types[op].bitfield.regxmm
5217 || i.types[op].bitfield.regymm
5218 || i.types[op].bitfield.sreg2
5219 || i.types[op].bitfield.sreg3
5220 || i.types[op].bitfield.control
5221 || i.types[op].bitfield.debug
5222 || i.types[op].bitfield.test)
5223 break;
c0209578 5224
7ab9ffdd
L		 5225 if (vex_3_sources)
5226 op = dest;
5227 else if (i.tm.opcode_modifier.vexnds)
5228 {
5229 /* For instructions with VexNDS, the register-only
5230 source operand is encoded in VEX prefix. */
5231 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5232
7ab9ffdd 5233 if (op > mem)
c0f3af97 5234 {
7ab9ffdd
L		 5235 vex_reg = op++;
5236 gas_assert (op < i.operands);
c0f3af97
L		 5237 }
5238 else
c0f3af97 5239 {
7ab9ffdd
L		 5240 vex_reg = op + 1;
5241 gas_assert (vex_reg < i.operands);
c0f3af97 5242 }
7ab9ffdd
L		 5243 }
5244 else if (i.tm.opcode_modifier.vexndd)
5245 {
5246 /* For instructions with VexNDD, there should be
5247 no memory operand and the register destination
5248 is encoded in VEX prefix. */
5249 gas_assert (i.mem_operands == 0
5250 && (op + 2) == i.operands);
5251 vex_reg = op + 1;
5252 }
5253 else
5254 gas_assert (op < i.operands);
99018f42 5255
7ab9ffdd
L		 5256 if (vex_reg != (unsigned int) ~0)
5257 {
5258 gas_assert (i.reg_operands == 2);
5259
5260 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5261 & regxmm)
5262 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5263 &regymm))
5264 abort ();
5265 i.vex.register_specifier = i.op[vex_reg].regs;
5266 }
5267
5268 /* If there is an extension opcode to put here, the
5269 register number must be put into the regmem field. */
5270 if (i.tm.extension_opcode != None)
5271 {
5272 i.rm.regmem = i.op[op].regs->reg_num;
5273 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5274 i.rex |= REX_B;
5275 }
5276 else
5277 {
5278 i.rm.reg = i.op[op].regs->reg_num;
5279 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5280 i.rex |= REX_R;
5281 }
252b5132 5282
29b0f896
AM		 5283 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5284 must set it to 3 to indicate this is a register operand
5285 in the regmem field. */
5286 if (!i.mem_operands)
5287 i.rm.mode = 3;
5288 }
252b5132 5289
29b0f896 5290 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5291 if (i.tm.extension_opcode != None)
29b0f896
AM		 5292 i.rm.reg = i.tm.extension_opcode;
5293 }
5294 return default_seg;
5295}
252b5132 5296
29b0f896 5297static void
e3bb37b5 5298output_branch (void)
29b0f896
AM		 5299{
5300 char *p;
5301 int code16;
5302 int prefix;
5303 relax_substateT subtype;
5304 symbolS *sym;
5305 offsetT off;
5306
5307 code16 = 0;
5308 if (flag_code == CODE_16BIT)
5309 code16 = CODE16;
5310
5311 prefix = 0;
5312 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5313 {
29b0f896
AM		 5314 prefix = 1;
5315 i.prefixes -= 1;
5316 code16 ^= CODE16;
252b5132 5317 }
29b0f896
AM		 5318 /* Pentium4 branch hints. */
5319 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5320 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5321 {
29b0f896
AM		 5322 prefix++;
5323 i.prefixes--;
5324 }
5325 if (i.prefix[REX_PREFIX] != 0)
5326 {
5327 prefix++;
5328 i.prefixes--;
2f66722d
AM		 5329 }
5330
29b0f896
AM		 5331 if (i.prefixes != 0 && !intel_syntax)
5332 as_warn (_("skipping prefixes on this instruction"));
5333
5334 /* It's always a symbol; End frag & setup for relax.
5335 Make sure there is enough room in this frag for the largest
5336 instruction we may generate in md_convert_frag. This is 2
5337 bytes for the opcode and room for the prefix and largest
5338 displacement. */
5339 frag_grow (prefix + 2 + 4);
5340 /* Prefix and 1 opcode byte go in fr_fix. */
5341 p = frag_more (prefix + 1);
5342 if (i.prefix[DATA_PREFIX] != 0)
5343 *p++ = DATA_PREFIX_OPCODE;
5344 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5345 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5346 *p++ = i.prefix[SEG_PREFIX];
5347 if (i.prefix[REX_PREFIX] != 0)
5348 *p++ = i.prefix[REX_PREFIX];
5349 *p = i.tm.base_opcode;
5350
5351 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5352 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5353 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5354 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5355 else
5356 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5357 subtype |= code16;
3e73aa7c 5358
29b0f896
AM		 5359 sym = i.op[0].disps->X_add_symbol;
5360 off = i.op[0].disps->X_add_number;
3e73aa7c 5361
29b0f896
AM		 5362 if (i.op[0].disps->X_op != O_constant
5363 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5364 {
29b0f896
AM		 5365 /* Handle complex expressions. */
5366 sym = make_expr_symbol (i.op[0].disps);
5367 off = 0;
5368 }
3e73aa7c 5369
29b0f896
AM		 5370 /* 1 possible extra opcode + 4 byte displacement go in var part.
5371 Pass reloc in fr_var. */
5372 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5373}
3e73aa7c 5374
29b0f896 5375static void
e3bb37b5 5376output_jump (void)
29b0f896
AM		 5377{
5378 char *p;
5379 int size;
3e02c1cc 5380 fixS *fixP;
29b0f896 5381
40fb9820 5382 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5383 {
5384 /* This is a loop or jecxz type instruction. */
5385 size = 1;
5386 if (i.prefix[ADDR_PREFIX] != 0)
5387 {
5388 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5389 i.prefixes -= 1;
5390 }
5391 /* Pentium4 branch hints. */
5392 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5393 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5394 {
5395 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5396 i.prefixes--;
3e73aa7c
JH		 5397 }
5398 }
29b0f896
AM		 5399 else
5400 {
5401 int code16;
3e73aa7c 5402
29b0f896
AM		 5403 code16 = 0;
5404 if (flag_code == CODE_16BIT)
5405 code16 = CODE16;
3e73aa7c 5406
29b0f896
AM		 5407 if (i.prefix[DATA_PREFIX] != 0)
5408 {
5409 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5410 i.prefixes -= 1;
5411 code16 ^= CODE16;
5412 }
252b5132 5413
29b0f896
AM		 5414 size = 4;
5415 if (code16)
5416 size = 2;
5417 }
9fcc94b6 5418
29b0f896
AM		 5419 if (i.prefix[REX_PREFIX] != 0)
5420 {
5421 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5422 i.prefixes -= 1;
5423 }
252b5132 5424
29b0f896
AM		 5425 if (i.prefixes != 0 && !intel_syntax)
5426 as_warn (_("skipping prefixes on this instruction"));
e0890092 5427
29b0f896
AM		 5428 p = frag_more (1 + size);
5429 *p++ = i.tm.base_opcode;
e0890092 5430
3e02c1cc
AM		 5431 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5432 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5433
5434 /* All jumps handled here are signed, but don't use a signed limit
5435 check for 32 and 16 bit jumps as we want to allow wrap around at
5436 4G and 64k respectively. */
5437 if (size == 1)
5438 fixP->fx_signed = 1;
29b0f896 5439}
e0890092 5440
29b0f896 5441static void
e3bb37b5 5442output_interseg_jump (void)
29b0f896
AM		 5443{
5444 char *p;
5445 int size;
5446 int prefix;
5447 int code16;
252b5132 5448
29b0f896
AM		 5449 code16 = 0;
5450 if (flag_code == CODE_16BIT)
5451 code16 = CODE16;
a217f122 5452
29b0f896
AM		 5453 prefix = 0;
5454 if (i.prefix[DATA_PREFIX] != 0)
5455 {
5456 prefix = 1;
5457 i.prefixes -= 1;
5458 code16 ^= CODE16;
5459 }
5460 if (i.prefix[REX_PREFIX] != 0)
5461 {
5462 prefix++;
5463 i.prefixes -= 1;
5464 }
252b5132 5465
29b0f896
AM		 5466 size = 4;
5467 if (code16)
5468 size = 2;
252b5132 5469
29b0f896
AM		 5470 if (i.prefixes != 0 && !intel_syntax)
5471 as_warn (_("skipping prefixes on this instruction"));
252b5132 5472
29b0f896
AM		 5473 /* 1 opcode; 2 segment; offset */
5474 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5475
29b0f896
AM		 5476 if (i.prefix[DATA_PREFIX] != 0)
5477 *p++ = DATA_PREFIX_OPCODE;
252b5132 5478
29b0f896
AM		 5479 if (i.prefix[REX_PREFIX] != 0)
5480 *p++ = i.prefix[REX_PREFIX];
252b5132 5481
29b0f896
AM		 5482 *p++ = i.tm.base_opcode;
5483 if (i.op[1].imms->X_op == O_constant)
5484 {
5485 offsetT n = i.op[1].imms->X_add_number;
252b5132 5486
29b0f896
AM		 5487 if (size == 2
5488 && !fits_in_unsigned_word (n)
5489 && !fits_in_signed_word (n))
5490 {
5491 as_bad (_("16-bit jump out of range"));
5492 return;
5493 }
5494 md_number_to_chars (p, n, size);
5495 }
5496 else
5497 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5498 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5499 if (i.op[0].imms->X_op != O_constant)
5500 as_bad (_("can't handle non absolute segment in `%s'"),
5501 i.tm.name);
5502 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5503}
a217f122 5504
29b0f896 5505static void
e3bb37b5 5506output_insn (void)
29b0f896 5507{
2bbd9c25
JJ		 5508 fragS *insn_start_frag;
5509 offsetT insn_start_off;
5510
29b0f896
AM		 5511 /* Tie dwarf2 debug info to the address at the start of the insn.
5512 We can't do this after the insn has been output as the current
5513 frag may have been closed off. eg. by frag_var. */
5514 dwarf2_emit_insn (0);
5515
2bbd9c25
JJ		 5516 insn_start_frag = frag_now;
5517 insn_start_off = frag_now_fix ();
5518
29b0f896 5519 /* Output jumps. */
40fb9820 5520 if (i.tm.opcode_modifier.jump)
29b0f896 5521 output_branch ();
40fb9820
L		 5522 else if (i.tm.opcode_modifier.jumpbyte
5523 || i.tm.opcode_modifier.jumpdword)
29b0f896 5524 output_jump ();
40fb9820 5525 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5526 output_interseg_jump ();
5527 else
5528 {
5529 /* Output normal instructions here. */
5530 char *p;
5531 unsigned char *q;
47465058 5532 unsigned int j;
331d2d0d 5533 unsigned int prefix;
4dffcebc 5534
c0f3af97
L		 5535 /* Since the VEX prefix contains the implicit prefix, we don't
5536 need the explicit prefix. */
5537 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5538 {
c0f3af97 5539 switch (i.tm.opcode_length)
bc4bd9ab 5540 {
c0f3af97
L		 5541 case 3:
5542 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5543 {
c0f3af97
L		 5544 prefix = (i.tm.base_opcode >> 24) & 0xff;
5545 goto check_prefix;
5546 }
5547 break;
5548 case 2:
5549 if ((i.tm.base_opcode & 0xff0000) != 0)
5550 {
5551 prefix = (i.tm.base_opcode >> 16) & 0xff;
5552 if (i.tm.cpu_flags.bitfield.cpupadlock)
5553 {
4dffcebc 5554check_prefix:
c0f3af97
L		 5555 if (prefix != REPE_PREFIX_OPCODE
5556 || (i.prefix[LOCKREP_PREFIX]
5557 != REPE_PREFIX_OPCODE))
5558 add_prefix (prefix);
5559 }
5560 else
4dffcebc
L		 5561 add_prefix (prefix);
5562 }
c0f3af97
L		 5563 break;
5564 case 1:
5565 break;
5566 default:
5567 abort ();
bc4bd9ab 5568 }
c0f3af97
L		 5569
5570 /* The prefix bytes. */
5571 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5572 if (*q)
5573 FRAG_APPEND_1_CHAR (*q);
0f10071e 5574 }
252b5132 5575
c0f3af97
L		 5576 if (i.tm.opcode_modifier.vex)
5577 {
5578 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5579 if (*q)
5580 switch (j)
5581 {
5582 case REX_PREFIX:
5583 /* REX byte is encoded in VEX prefix. */
5584 break;
5585 case SEG_PREFIX:
5586 case ADDR_PREFIX:
5587 FRAG_APPEND_1_CHAR (*q);
5588 break;
5589 default:
5590 /* There should be no other prefixes for instructions
5591 with VEX prefix. */
5592 abort ();
5593 }
5594
5595 /* Now the VEX prefix. */
5596 p = frag_more (i.vex.length);
5597 for (j = 0; j < i.vex.length; j++)
5598 p[j] = i.vex.bytes[j];
5599 }
252b5132 5600
29b0f896 5601 /* Now the opcode; be careful about word order here! */
4dffcebc 5602 if (i.tm.opcode_length == 1)
29b0f896
AM		 5603 {
5604 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5605 }
5606 else
5607 {
4dffcebc 5608 switch (i.tm.opcode_length)
331d2d0d 5609 {
4dffcebc 5610 case 3:
331d2d0d
L		 5611 p = frag_more (3);
5612 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5613 break;
5614 case 2:
5615 p = frag_more (2);
5616 break;
5617 default:
5618 abort ();
5619 break;
331d2d0d 5620 }
0f10071e 5621
29b0f896
AM		 5622 /* Put out high byte first: can't use md_number_to_chars! */
5623 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5624 *p = i.tm.base_opcode & 0xff;
5625 }
3e73aa7c 5626
29b0f896 5627 /* Now the modrm byte and sib byte (if present). */
40fb9820 5628 if (i.tm.opcode_modifier.modrm)
29b0f896 5629 {
4a3523fa
L		 5630 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5631 | i.rm.reg << 3
5632 | i.rm.mode << 6));
29b0f896
AM		 5633 /* If i.rm.regmem == ESP (4)
5634 && i.rm.mode != (Register mode)
5635 && not 16 bit
5636 ==> need second modrm byte. */
5637 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5638 && i.rm.mode != 3
40fb9820 5639 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5640 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5641 | i.sib.index << 3
5642 | i.sib.scale << 6));
29b0f896 5643 }
3e73aa7c 5644
29b0f896 5645 if (i.disp_operands)
2bbd9c25 5646 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5647
29b0f896 5648 if (i.imm_operands)
2bbd9c25 5649 output_imm (insn_start_frag, insn_start_off);
29b0f896 5650 }
252b5132 5651
29b0f896
AM		 5652#ifdef DEBUG386
5653 if (flag_debug)
5654 {
7b81dfbb 5655 pi ("" /*line*/, &i);
29b0f896
AM		 5656 }
5657#endif /* DEBUG386 */
5658}
252b5132 5659
e205caa7
L		 5660/* Return the size of the displacement operand N. */
5661
5662static int
5663disp_size (unsigned int n)
5664{
5665 int size = 4;
40fb9820
L		 5666 if (i.types[n].bitfield.disp64)
5667 size = 8;
5668 else if (i.types[n].bitfield.disp8)
5669 size = 1;
5670 else if (i.types[n].bitfield.disp16)
5671 size = 2;
e205caa7
L		 5672 return size;
5673}
5674
5675/* Return the size of the immediate operand N. */
5676
5677static int
5678imm_size (unsigned int n)
5679{
5680 int size = 4;
40fb9820
L		 5681 if (i.types[n].bitfield.imm64)
5682 size = 8;
5683 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5684 size = 1;
5685 else if (i.types[n].bitfield.imm16)
5686 size = 2;
e205caa7
L		 5687 return size;
5688}
5689
29b0f896 5690static void
64e74474 5691output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5692{
5693 char *p;
5694 unsigned int n;
252b5132 5695
29b0f896
AM		 5696 for (n = 0; n < i.operands; n++)
5697 {
40fb9820 5698 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5699 {
5700 if (i.op[n].disps->X_op == O_constant)
5701 {
e205caa7 5702 int size = disp_size (n);
29b0f896 5703 offsetT val;
252b5132 5704
29b0f896
AM		 5705 val = offset_in_range (i.op[n].disps->X_add_number,
5706 size);
5707 p = frag_more (size);
5708 md_number_to_chars (p, val, size);
5709 }
5710 else
5711 {
f86103b7 5712 enum bfd_reloc_code_real reloc_type;
e205caa7 5713 int size = disp_size (n);
40fb9820 5714 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5715 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5716
e205caa7 5717 /* We can't have 8 bit displacement here. */
9c2799c2 5718 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 5719
29b0f896
AM		 5720 /* The PC relative address is computed relative
5721 to the instruction boundary, so in case immediate
5722 fields follows, we need to adjust the value. */
5723 if (pcrel && i.imm_operands)
5724 {
29b0f896 5725 unsigned int n1;
e205caa7 5726 int sz = 0;
252b5132 5727
29b0f896 5728 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5729 if (operand_type_check (i.types[n1], imm))
252b5132 5730 {
e205caa7
L		 5731 /* Only one immediate is allowed for PC
5732 relative address. */
9c2799c2 5733 gas_assert (sz == 0);
e205caa7
L		 5734 sz = imm_size (n1);
5735 i.op[n].disps->X_add_number -= sz;
252b5132 5736 }
29b0f896 5737 /* We should find the immediate. */
9c2799c2 5738 gas_assert (sz != 0);
29b0f896 5739 }
520dc8e8 5740
29b0f896 5741 p = frag_more (size);
2bbd9c25 5742 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5743 if (GOT_symbol
2bbd9c25 5744 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5745 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5746 || reloc_type == BFD_RELOC_X86_64_32S
5747 || (reloc_type == BFD_RELOC_64
5748 && object_64bit))
d6ab8113
JB		 5749 && (i.op[n].disps->X_op == O_symbol
5750 || (i.op[n].disps->X_op == O_add
5751 && ((symbol_get_value_expression
5752 (i.op[n].disps->X_op_symbol)->X_op)
5753 == O_subtract))))
5754 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5755 {
5756 offsetT add;
5757
5758 if (insn_start_frag == frag_now)
5759 add = (p - frag_now->fr_literal) - insn_start_off;
5760 else
5761 {
5762 fragS *fr;
5763
5764 add = insn_start_frag->fr_fix - insn_start_off;
5765 for (fr = insn_start_frag->fr_next;
5766 fr && fr != frag_now; fr = fr->fr_next)
5767 add += fr->fr_fix;
5768 add += p - frag_now->fr_literal;
5769 }
5770
4fa24527 5771 if (!object_64bit)
7b81dfbb
AJ		 5772 {
5773 reloc_type = BFD_RELOC_386_GOTPC;
5774 i.op[n].imms->X_add_number += add;
5775 }
5776 else if (reloc_type == BFD_RELOC_64)
5777 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5778 else
7b81dfbb
AJ		 5779 /* Don't do the adjustment for x86-64, as there
5780 the pcrel addressing is relative to the _next_
5781 insn, and that is taken care of in other code. */
d6ab8113 5782 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5783 }
062cd5e7 5784 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5785 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5786 }
5787 }
5788 }
5789}
252b5132 5790
29b0f896 5791static void
64e74474 5792output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5793{
5794 char *p;
5795 unsigned int n;
252b5132 5796
29b0f896
AM		 5797 for (n = 0; n < i.operands; n++)
5798 {
40fb9820 5799 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5800 {
5801 if (i.op[n].imms->X_op == O_constant)
5802 {
e205caa7 5803 int size = imm_size (n);
29b0f896 5804 offsetT val;
b4cac588 5805
29b0f896
AM		 5806 val = offset_in_range (i.op[n].imms->X_add_number,
5807 size);
5808 p = frag_more (size);
5809 md_number_to_chars (p, val, size);
5810 }
5811 else
5812 {
5813 /* Not absolute_section.
5814 Need a 32-bit fixup (don't support 8bit
5815 non-absolute imms). Try to support other
5816 sizes ... */
f86103b7 5817 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5818 int size = imm_size (n);
5819 int sign;
29b0f896 5820
40fb9820 5821 if (i.types[n].bitfield.imm32s
a7d61044 5822 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5823 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5824 sign = 1;
e205caa7
L		 5825 else
5826 sign = 0;
520dc8e8 5827
29b0f896
AM		 5828 p = frag_more (size);
5829 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5830
2bbd9c25
JJ		 5831 /* This is tough to explain. We end up with this one if we
5832 * have operands that look like
5833 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5834 * obtain the absolute address of the GOT, and it is strongly
5835 * preferable from a performance point of view to avoid using
5836 * a runtime relocation for this. The actual sequence of
5837 * instructions often look something like:
5838 *
5839 * call .L66
5840 * .L66:
5841 * popl %ebx
5842 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5843 *
5844 * The call and pop essentially return the absolute address
5845 * of the label .L66 and store it in %ebx. The linker itself
5846 * will ultimately change the first operand of the addl so
5847 * that %ebx points to the GOT, but to keep things simple, the
5848 * .o file must have this operand set so that it generates not
5849 * the absolute address of .L66, but the absolute address of
5850 * itself. This allows the linker itself simply treat a GOTPC
5851 * relocation as asking for a pcrel offset to the GOT to be
5852 * added in, and the addend of the relocation is stored in the
5853 * operand field for the instruction itself.
5854 *
5855 * Our job here is to fix the operand so that it would add
5856 * the correct offset so that %ebx would point to itself. The
5857 * thing that is tricky is that .-.L66 will point to the
5858 * beginning of the instruction, so we need to further modify
5859 * the operand so that it will point to itself. There are
5860 * other cases where you have something like:
5861 *
5862 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5863 *
5864 * and here no correction would be required. Internally in
5865 * the assembler we treat operands of this form as not being
5866 * pcrel since the '.' is explicitly mentioned, and I wonder
5867 * whether it would simplify matters to do it this way. Who
5868 * knows. In earlier versions of the PIC patches, the
5869 * pcrel_adjust field was used to store the correction, but
5870 * since the expression is not pcrel, I felt it would be
5871 * confusing to do it this way. */
5872
d6ab8113 5873 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5874 || reloc_type == BFD_RELOC_X86_64_32S
5875 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5876 && GOT_symbol
5877 && GOT_symbol == i.op[n].imms->X_add_symbol
5878 && (i.op[n].imms->X_op == O_symbol
5879 || (i.op[n].imms->X_op == O_add
5880 && ((symbol_get_value_expression
5881 (i.op[n].imms->X_op_symbol)->X_op)
5882 == O_subtract))))
5883 {
2bbd9c25
JJ		 5884 offsetT add;
5885
5886 if (insn_start_frag == frag_now)
5887 add = (p - frag_now->fr_literal) - insn_start_off;
5888 else
5889 {
5890 fragS *fr;
5891
5892 add = insn_start_frag->fr_fix - insn_start_off;
5893 for (fr = insn_start_frag->fr_next;
5894 fr && fr != frag_now; fr = fr->fr_next)
5895 add += fr->fr_fix;
5896 add += p - frag_now->fr_literal;
5897 }
5898
4fa24527 5899 if (!object_64bit)
d6ab8113 5900 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5901 else if (size == 4)
d6ab8113 5902 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5903 else if (size == 8)
5904 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5905 i.op[n].imms->X_add_number += add;
29b0f896 5906 }
29b0f896
AM		 5907 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5908 i.op[n].imms, 0, reloc_type);
5909 }
5910 }
5911 }
252b5132
RH		 5912}
5913\f
d182319b
JB		 5914/* x86_cons_fix_new is called via the expression parsing code when a
5915 reloc is needed. We use this hook to get the correct .got reloc. */
5916static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5917static int cons_sign = -1;
5918
5919void
e3bb37b5 5920x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5921 expressionS *exp)
d182319b
JB		 5922{
5923 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5924
5925 got_reloc = NO_RELOC;
5926
5927#ifdef TE_PE
5928 if (exp->X_op == O_secrel)
5929 {
5930 exp->X_op = O_symbol;
5931 r = BFD_RELOC_32_SECREL;
5932 }
5933#endif
5934
5935 fix_new_exp (frag, off, len, exp, 0, r);
5936}
5937
718ddfc0
JB		 5938#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5939# define lex_got(reloc, adjust, types) NULL
5940#else
f3c180ae
AM		 5941/* Parse operands of the form
5942 <symbol>@GOTOFF+<nnn>
5943 and similar .plt or .got references.
5944
5945 If we find one, set up the correct relocation in RELOC and copy the
5946 input string, minus the `@GOTOFF' into a malloc'd buffer for
5947 parsing by the calling routine. Return this buffer, and if ADJUST
5948 is non-null set it to the length of the string we removed from the
5949 input line. Otherwise return NULL. */
5950static char *
3956db08 5951lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5952 int *adjust,
40fb9820 5953 i386_operand_type *types)
f3c180ae 5954{
7b81dfbb
AJ		 5955 /* Some of the relocations depend on the size of what field is to
5956 be relocated. But in our callers i386_immediate and i386_displacement
5957 we don't yet know the operand size (this will be set by insn
5958 matching). Hence we record the word32 relocation here,
5959 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5960 static const struct {
5961 const char *str;
4fa24527 5962 const enum bfd_reloc_code_real rel[2];
40fb9820 5963 const i386_operand_type types64;
f3c180ae 5964 } gotrel[] = {
4eed87de
AM		 5965 { "PLTOFF", { 0,
5966 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5967 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5968 { "PLT", { BFD_RELOC_386_PLT32,
5969 BFD_RELOC_X86_64_PLT32 },
40fb9820 5970 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5971 { "GOTPLT", { 0,
5972 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5973 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5974 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5975 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5976 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5977 { "GOTPCREL", { 0,
5978 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5979 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5980 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5981 BFD_RELOC_X86_64_TLSGD },
40fb9820 5982 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5983 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5984 0 },
40fb9820 5985 OPERAND_TYPE_NONE },
4eed87de
AM		 5986 { "TLSLD", { 0,
5987 BFD_RELOC_X86_64_TLSLD },
40fb9820 5988 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5989 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5990 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5991 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5992 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5993 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5994 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5995 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5996 0 },
40fb9820 5997 OPERAND_TYPE_NONE },
4eed87de
AM		 5998 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5999 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 6000
40fb9820 6001 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6002 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6003 0 },
40fb9820 6004 OPERAND_TYPE_NONE },
4eed87de
AM		 6005 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6006 0 },
40fb9820 6007 OPERAND_TYPE_NONE },
4eed87de
AM		 6008 { "GOT", { BFD_RELOC_386_GOT32,
6009 BFD_RELOC_X86_64_GOT32 },
40fb9820 6010 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6011 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6012 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6013 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6014 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6015 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6016 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6017 };
6018 char *cp;
6019 unsigned int j;
6020
718ddfc0
JB		 6021 if (!IS_ELF)
6022 return NULL;
6023
f3c180ae 6024 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6025 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6026 return NULL;
6027
47465058 6028 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6029 {
6030 int len;
6031
6032 len = strlen (gotrel[j].str);
28f81592 6033 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6034 {
4fa24527 6035 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6036 {
28f81592
AM		 6037 int first, second;
6038 char *tmpbuf, *past_reloc;
f3c180ae 6039
4fa24527 6040 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6041 if (adjust)
6042 *adjust = len;
f3c180ae 6043
3956db08
JB		 6044 if (types)
6045 {
6046 if (flag_code != CODE_64BIT)
40fb9820
L		 6047 {
6048 types->bitfield.imm32 = 1;
6049 types->bitfield.disp32 = 1;
6050 }
3956db08
JB		 6051 else
6052 *types = gotrel[j].types64;
6053 }
6054
f3c180ae
AM		 6055 if (GOT_symbol == NULL)
6056 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6057
28f81592 6058 /* The length of the first part of our input line. */
f3c180ae 6059 first = cp - input_line_pointer;
28f81592
AM		 6060
6061 /* The second part goes from after the reloc token until
67c11a9b 6062 (and including) an end_of_line char or comma. */
28f81592 6063 past_reloc = cp + 1 + len;
67c11a9b
AM		 6064 cp = past_reloc;
6065 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6066 ++cp;
6067 second = cp + 1 - past_reloc;
28f81592
AM		 6068
6069 /* Allocate and copy string. The trailing NUL shouldn't
6070 be necessary, but be safe. */
6071 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6072 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6073 if (second != 0 && *past_reloc != ' ')
6074 /* Replace the relocation token with ' ', so that
6075 errors like foo@GOTOFF1 will be detected. */
6076 tmpbuf[first++] = ' ';
6077 memcpy (tmpbuf + first, past_reloc, second);
6078 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6079 return tmpbuf;
6080 }
6081
4fa24527
JB		 6082 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6083 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6084 return NULL;
6085 }
6086 }
6087
6088 /* Might be a symbol version string. Don't as_bad here. */
6089 return NULL;
6090}
6091
f3c180ae 6092void
e3bb37b5 6093x86_cons (expressionS *exp, int size)
f3c180ae 6094{
ee86248c
JB		 6095 intel_syntax = -intel_syntax;
6096
4fa24527 6097 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6098 {
6099 /* Handle @GOTOFF and the like in an expression. */
6100 char *save;
6101 char *gotfree_input_line;
6102 int adjust;
6103
6104 save = input_line_pointer;
3956db08 6105 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6106 if (gotfree_input_line)
6107 input_line_pointer = gotfree_input_line;
6108
6109 expression (exp);
6110
6111 if (gotfree_input_line)
6112 {
6113 /* expression () has merrily parsed up to the end of line,
6114 or a comma - in the wrong buffer. Transfer how far
6115 input_line_pointer has moved to the right buffer. */
6116 input_line_pointer = (save
6117 + (input_line_pointer - gotfree_input_line)
6118 + adjust);
6119 free (gotfree_input_line);
3992d3b7
AM		 6120 if (exp->X_op == O_constant
6121 || exp->X_op == O_absent
6122 || exp->X_op == O_illegal
6123 || exp->X_op == O_register
6124 || exp->X_op == O_big)
6125 {
6126 char c = *input_line_pointer;
6127 *input_line_pointer = 0;
6128 as_bad (_("missing or invalid expression `%s'"), save);
6129 *input_line_pointer = c;
6130 }
f3c180ae
AM		 6131 }
6132 }
6133 else
6134 expression (exp);
ee86248c
JB		 6135
6136 intel_syntax = -intel_syntax;
6137
6138 if (intel_syntax)
6139 i386_intel_simplify (exp);
f3c180ae
AM		 6140}
6141#endif
6142
d182319b 6143static void signed_cons (int size)
6482c264 6144{
d182319b
JB		 6145 if (flag_code == CODE_64BIT)
6146 cons_sign = 1;
6147 cons (size);
6148 cons_sign = -1;
6482c264
NC		 6149}
6150
d182319b 6151#ifdef TE_PE
6482c264
NC		 6152static void
6153pe_directive_secrel (dummy)
6154 int dummy ATTRIBUTE_UNUSED;
6155{
6156 expressionS exp;
6157
6158 do
6159 {
6160 expression (&exp);
6161 if (exp.X_op == O_symbol)
6162 exp.X_op = O_secrel;
6163
6164 emit_expr (&exp, 4);
6165 }
6166 while (*input_line_pointer++ == ',');
6167
6168 input_line_pointer--;
6169 demand_empty_rest_of_line ();
6170}
6482c264
NC		 6171#endif
6172
252b5132 6173static int
70e41ade 6174i386_immediate (char *imm_start)
252b5132
RH		 6175{
6176 char *save_input_line_pointer;
f3c180ae 6177 char *gotfree_input_line;
252b5132 6178 segT exp_seg = 0;
47926f60 6179 expressionS *exp;
40fb9820
L		 6180 i386_operand_type types;
6181
0dfbf9d7 6182 operand_type_set (&types, ~0);
252b5132
RH		 6183
6184 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6185 {
31b2323c
L		 6186 as_bad (_("at most %d immediate operands are allowed"),
6187 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6188 return 0;
6189 }
6190
6191 exp = &im_expressions[i.imm_operands++];
520dc8e8 6192 i.op[this_operand].imms = exp;
252b5132
RH		 6193
6194 if (is_space_char (*imm_start))
6195 ++imm_start;
6196
6197 save_input_line_pointer = input_line_pointer;
6198 input_line_pointer = imm_start;
6199
3956db08 6200 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6201 if (gotfree_input_line)
6202 input_line_pointer = gotfree_input_line;
252b5132
RH		 6203
6204 exp_seg = expression (exp);
6205
83183c0c 6206 SKIP_WHITESPACE ();
252b5132 6207 if (*input_line_pointer)
f3c180ae 6208 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6209
6210 input_line_pointer = save_input_line_pointer;
f3c180ae 6211 if (gotfree_input_line)
ee86248c
JB		 6212 {
6213 free (gotfree_input_line);
6214
6215 if (exp->X_op == O_constant || exp->X_op == O_register)
6216 exp->X_op = O_illegal;
6217 }
6218
6219 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6220}
252b5132 6221
ee86248c
JB		 6222static int
6223i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6224 i386_operand_type types, const char *imm_start)
6225{
6226 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6227 {
3992d3b7 6228 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6229 imm_start);
3992d3b7 6230 return 0;
252b5132 6231 }
3e73aa7c 6232 else if (exp->X_op == O_constant)
252b5132 6233 {
47926f60 6234 /* Size it properly later. */
40fb9820 6235 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6236 /* If BFD64, sign extend val. */
4eed87de
AM		 6237 if (!use_rela_relocations
6238 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6239 exp->X_add_number
6240 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6241 }
4c63da97 6242#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6243 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6244 && exp_seg != absolute_section
47926f60 6245 && exp_seg != text_section
24eab124
AM		 6246 && exp_seg != data_section
6247 && exp_seg != bss_section
6248 && exp_seg != undefined_section
f86103b7 6249 && !bfd_is_com_section (exp_seg))
252b5132 6250 {
d0b47220 6251 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6252 return 0;
6253 }
6254#endif
bb8f5920
L		 6255 else if (!intel_syntax && exp->X_op == O_register)
6256 {
6257 as_bad (_("illegal immediate register operand %s"), imm_start);
6258 return 0;
6259 }
252b5132
RH		 6260 else
6261 {
6262 /* This is an address. The size of the address will be
24eab124 6263 determined later, depending on destination register,
3e73aa7c 6264 suffix, or the default for the section. */
40fb9820
L		 6265 i.types[this_operand].bitfield.imm8 = 1;
6266 i.types[this_operand].bitfield.imm16 = 1;
6267 i.types[this_operand].bitfield.imm32 = 1;
6268 i.types[this_operand].bitfield.imm32s = 1;
6269 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6270 i.types[this_operand] = operand_type_and (i.types[this_operand],
6271 types);
252b5132
RH		 6272 }
6273
6274 return 1;
6275}
6276
551c1ca1 6277static char *
e3bb37b5 6278i386_scale (char *scale)
252b5132 6279{
551c1ca1
AM		 6280 offsetT val;
6281 char *save = input_line_pointer;
252b5132 6282
551c1ca1
AM		 6283 input_line_pointer = scale;
6284 val = get_absolute_expression ();
6285
6286 switch (val)
252b5132 6287 {
551c1ca1 6288 case 1:
252b5132
RH		 6289 i.log2_scale_factor = 0;
6290 break;
551c1ca1 6291 case 2:
252b5132
RH		 6292 i.log2_scale_factor = 1;
6293 break;
551c1ca1 6294 case 4:
252b5132
RH		 6295 i.log2_scale_factor = 2;
6296 break;
551c1ca1 6297 case 8:
252b5132
RH		 6298 i.log2_scale_factor = 3;
6299 break;
6300 default:
a724f0f4
JB		 6301 {
6302 char sep = *input_line_pointer;
6303
6304 *input_line_pointer = '\0';
6305 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6306 scale);
6307 *input_line_pointer = sep;
6308 input_line_pointer = save;
6309 return NULL;
6310 }
252b5132 6311 }
29b0f896 6312 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6313 {
6314 as_warn (_("scale factor of %d without an index register"),
24eab124 6315 1 << i.log2_scale_factor);
252b5132 6316 i.log2_scale_factor = 0;
252b5132 6317 }
551c1ca1
AM		 6318 scale = input_line_pointer;
6319 input_line_pointer = save;
6320 return scale;
252b5132
RH		 6321}
6322
252b5132 6323static int
e3bb37b5 6324i386_displacement (char *disp_start, char *disp_end)
252b5132 6325{
29b0f896 6326 expressionS *exp;
252b5132
RH		 6327 segT exp_seg = 0;
6328 char *save_input_line_pointer;
f3c180ae 6329 char *gotfree_input_line;
40fb9820
L		 6330 int override;
6331 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6332 int ret;
252b5132 6333
31b2323c
L		 6334 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6335 {
6336 as_bad (_("at most %d displacement operands are allowed"),
6337 MAX_MEMORY_OPERANDS);
6338 return 0;
6339 }
6340
0dfbf9d7 6341 operand_type_set (&bigdisp, 0);
40fb9820
L		 6342 if ((i.types[this_operand].bitfield.jumpabsolute)
6343 || (!current_templates->start->opcode_modifier.jump
6344 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6345 {
40fb9820 6346 bigdisp.bitfield.disp32 = 1;
e05278af 6347 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6348 if (flag_code == CODE_64BIT)
6349 {
6350 if (!override)
6351 {
6352 bigdisp.bitfield.disp32s = 1;
6353 bigdisp.bitfield.disp64 = 1;
6354 }
6355 }
6356 else if ((flag_code == CODE_16BIT) ^ override)
6357 {
6358 bigdisp.bitfield.disp32 = 0;
6359 bigdisp.bitfield.disp16 = 1;
6360 }
e05278af
JB		 6361 }
6362 else
6363 {
6364 /* For PC-relative branches, the width of the displacement
6365 is dependent upon data size, not address size. */
e05278af 6366 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6367 if (flag_code == CODE_64BIT)
6368 {
6369 if (override || i.suffix == WORD_MNEM_SUFFIX)
6370 bigdisp.bitfield.disp16 = 1;
6371 else
6372 {
6373 bigdisp.bitfield.disp32 = 1;
6374 bigdisp.bitfield.disp32s = 1;
6375 }
6376 }
6377 else
e05278af
JB		 6378 {
6379 if (!override)
6380 override = (i.suffix == (flag_code != CODE_16BIT
6381 ? WORD_MNEM_SUFFIX
6382 : LONG_MNEM_SUFFIX));
40fb9820
L		 6383 bigdisp.bitfield.disp32 = 1;
6384 if ((flag_code == CODE_16BIT) ^ override)
6385 {
6386 bigdisp.bitfield.disp32 = 0;
6387 bigdisp.bitfield.disp16 = 1;
6388 }
e05278af 6389 }
e05278af 6390 }
c6fb90c8
L		 6391 i.types[this_operand] = operand_type_or (i.types[this_operand],
6392 bigdisp);
252b5132
RH		 6393
6394 exp = &disp_expressions[i.disp_operands];
520dc8e8 6395 i.op[this_operand].disps = exp;
252b5132
RH		 6396 i.disp_operands++;
6397 save_input_line_pointer = input_line_pointer;
6398 input_line_pointer = disp_start;
6399 END_STRING_AND_SAVE (disp_end);
6400
6401#ifndef GCC_ASM_O_HACK
6402#define GCC_ASM_O_HACK 0
6403#endif
6404#if GCC_ASM_O_HACK
6405 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6406 if (i.types[this_operand].bitfield.baseIndex
24eab124 6407 && displacement_string_end[-1] == '+')
252b5132
RH		 6408 {
6409 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6410 constraint within gcc asm statements.
6411 For instance:
6412
6413 #define _set_tssldt_desc(n,addr,limit,type) \
6414 __asm__ __volatile__ ( \
6415 "movw %w2,%0\n\t" \
6416 "movw %w1,2+%0\n\t" \
6417 "rorl $16,%1\n\t" \
6418 "movb %b1,4+%0\n\t" \
6419 "movb %4,5+%0\n\t" \
6420 "movb $0,6+%0\n\t" \
6421 "movb %h1,7+%0\n\t" \
6422 "rorl $16,%1" \
6423 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6424
6425 This works great except that the output assembler ends
6426 up looking a bit weird if it turns out that there is
6427 no offset. You end up producing code that looks like:
6428
6429 #APP
6430 movw $235,(%eax)
6431 movw %dx,2+(%eax)
6432 rorl $16,%edx
6433 movb %dl,4+(%eax)
6434 movb $137,5+(%eax)
6435 movb $0,6+(%eax)
6436 movb %dh,7+(%eax)
6437 rorl $16,%edx
6438 #NO_APP
6439
47926f60 6440 So here we provide the missing zero. */
24eab124
AM		 6441
6442 *displacement_string_end = '0';
252b5132
RH		 6443 }
6444#endif
3956db08 6445 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6446 if (gotfree_input_line)
6447 input_line_pointer = gotfree_input_line;
252b5132 6448
24eab124 6449 exp_seg = expression (exp);
252b5132 6450
636c26b0
AM		 6451 SKIP_WHITESPACE ();
6452 if (*input_line_pointer)
6453 as_bad (_("junk `%s' after expression"), input_line_pointer);
6454#if GCC_ASM_O_HACK
6455 RESTORE_END_STRING (disp_end + 1);
6456#endif
636c26b0 6457 input_line_pointer = save_input_line_pointer;
636c26b0 6458 if (gotfree_input_line)
ee86248c
JB		 6459 {
6460 free (gotfree_input_line);
6461
6462 if (exp->X_op == O_constant || exp->X_op == O_register)
6463 exp->X_op = O_illegal;
6464 }
6465
6466 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6467
6468 RESTORE_END_STRING (disp_end);
6469
6470 return ret;
6471}
6472
6473static int
6474i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6475 i386_operand_type types, const char *disp_start)
6476{
6477 i386_operand_type bigdisp;
6478 int ret = 1;
636c26b0 6479
24eab124
AM		 6480 /* We do this to make sure that the section symbol is in
6481 the symbol table. We will ultimately change the relocation
47926f60 6482 to be relative to the beginning of the section. */
1ae12ab7 6483 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6484 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6485 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6486 {
636c26b0 6487 if (exp->X_op != O_symbol)
3992d3b7 6488 goto inv_disp;
636c26b0 6489
e5cb08ac 6490 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6491 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6492 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6493 exp->X_op = O_subtract;
6494 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6495 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6496 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6497 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6498 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6499 else
29b0f896 6500 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6501 }
252b5132 6502
3992d3b7
AM		 6503 else if (exp->X_op == O_absent
6504 || exp->X_op == O_illegal
ee86248c 6505 || exp->X_op == O_big)
2daf4fd8 6506 {
3992d3b7
AM		 6507 inv_disp:
6508 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6509 disp_start);
3992d3b7 6510 ret = 0;
2daf4fd8
AM		 6511 }
6512
4c63da97 6513#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6514 else if (exp->X_op != O_constant
6515 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6516 && exp_seg != absolute_section
6517 && exp_seg != text_section
6518 && exp_seg != data_section
6519 && exp_seg != bss_section
6520 && exp_seg != undefined_section
6521 && !bfd_is_com_section (exp_seg))
24eab124 6522 {
d0b47220 6523 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6524 ret = 0;
24eab124 6525 }
252b5132 6526#endif
3956db08 6527
40fb9820
L		 6528 /* Check if this is a displacement only operand. */
6529 bigdisp = i.types[this_operand];
6530 bigdisp.bitfield.disp8 = 0;
6531 bigdisp.bitfield.disp16 = 0;
6532 bigdisp.bitfield.disp32 = 0;
6533 bigdisp.bitfield.disp32s = 0;
6534 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6535 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6536 i.types[this_operand] = operand_type_and (i.types[this_operand],
6537 types);
3956db08 6538
3992d3b7 6539 return ret;
252b5132
RH		 6540}
6541
eecb386c 6542/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6543 Return 1 on success, 0 on a failure. */
6544
252b5132 6545static int
e3bb37b5 6546i386_index_check (const char *operand_string)
252b5132 6547{
3e73aa7c 6548 int ok;
fc0763e6 6549 const char *kind = "base/index";
24eab124 6550#if INFER_ADDR_PREFIX
eecb386c
AM		 6551 int fudged = 0;
6552
24eab124
AM		 6553 tryprefix:
6554#endif
3e73aa7c 6555 ok = 1;
fc0763e6
JB		 6556 if (current_templates->start->opcode_modifier.isstring
6557 && !current_templates->start->opcode_modifier.immext
6558 && (current_templates->end[-1].opcode_modifier.isstring
6559 || i.mem_operands))
6560 {
6561 /* Memory operands of string insns are special in that they only allow
6562 a single register (rDI, rSI, or rBX) as their memory address. */
6563 unsigned int expected;
6564
6565 kind = "string address";
6566
6567 if (current_templates->start->opcode_modifier.w)
6568 {
6569 i386_operand_type type = current_templates->end[-1].operand_types[0];
6570
6571 if (!type.bitfield.baseindex
6572 || ((!i.mem_operands != !intel_syntax)
6573 && current_templates->end[-1].operand_types[1]
6574 .bitfield.baseindex))
6575 type = current_templates->end[-1].operand_types[1];
6576 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6577 }
6578 else
6579 expected = 3 /* rBX */;
6580
6581 if (!i.base_reg || i.index_reg
6582 || operand_type_check (i.types[this_operand], disp))
6583 ok = -1;
6584 else if (!(flag_code == CODE_64BIT
6585 ? i.prefix[ADDR_PREFIX]
6586 ? i.base_reg->reg_type.bitfield.reg32
6587 : i.base_reg->reg_type.bitfield.reg64
6588 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6589 ? i.base_reg->reg_type.bitfield.reg32
6590 : i.base_reg->reg_type.bitfield.reg16))
6591 ok = 0;
6592 else if (i.base_reg->reg_num != expected)
6593 ok = -1;
6594
6595 if (ok < 0)
6596 {
6597 unsigned int j;
6598
6599 for (j = 0; j < i386_regtab_size; ++j)
6600 if ((flag_code == CODE_64BIT
6601 ? i.prefix[ADDR_PREFIX]
6602 ? i386_regtab[j].reg_type.bitfield.reg32
6603 : i386_regtab[j].reg_type.bitfield.reg64
6604 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6605 ? i386_regtab[j].reg_type.bitfield.reg32
6606 : i386_regtab[j].reg_type.bitfield.reg16)
6607 && i386_regtab[j].reg_num == expected)
6608 break;
9c2799c2 6609 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6610 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6611 operand_string,
6612 intel_syntax ? '[' : '(',
6613 register_prefix,
6614 i386_regtab[j].reg_name,
6615 intel_syntax ? ']' : ')');
6616 ok = 1;
6617 }
6618 }
6619 else if (flag_code == CODE_64BIT)
64e74474 6620 {
64e74474 6621 if ((i.base_reg
40fb9820
L		 6622 && ((i.prefix[ADDR_PREFIX] == 0
6623 && !i.base_reg->reg_type.bitfield.reg64)
6624 || (i.prefix[ADDR_PREFIX]
6625 && !i.base_reg->reg_type.bitfield.reg32))
6626 && (i.index_reg
9a04903e
JB		 6627 || i.base_reg->reg_num !=
6628 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6629 || (i.index_reg
40fb9820
L		 6630 && (!i.index_reg->reg_type.bitfield.baseindex
6631 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6632 && i.index_reg->reg_num != RegRiz
6633 && !i.index_reg->reg_type.bitfield.reg64
6634 )
40fb9820 6635 || (i.prefix[ADDR_PREFIX]
db51cc60 6636 && i.index_reg->reg_num != RegEiz
40fb9820 6637 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6638 ok = 0;
3e73aa7c
JH		 6639 }
6640 else
6641 {
6642 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6643 {
6644 /* 16bit checks. */
6645 if ((i.base_reg
40fb9820
L		 6646 && (!i.base_reg->reg_type.bitfield.reg16
6647 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6648 || (i.index_reg
40fb9820
L		 6649 && (!i.index_reg->reg_type.bitfield.reg16
6650 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6651 || !(i.base_reg
6652 && i.base_reg->reg_num < 6
6653 && i.index_reg->reg_num >= 6
6654 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6655 ok = 0;
6656 }
6657 else
e5cb08ac 6658 {
3e73aa7c
JH		 6659 /* 32bit checks. */
6660 if ((i.base_reg
40fb9820 6661 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6662 || (i.index_reg
db51cc60
L		 6663 && ((!i.index_reg->reg_type.bitfield.reg32
6664 && i.index_reg->reg_num != RegEiz)
40fb9820 6665 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6666 ok = 0;
3e73aa7c
JH		 6667 }
6668 }
6669 if (!ok)
24eab124
AM		 6670 {
6671#if INFER_ADDR_PREFIX
fc0763e6 6672 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6673 {
6674 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6675 i.prefixes += 1;
b23bac36
AM		 6676 /* Change the size of any displacement too. At most one of
6677 Disp16 or Disp32 is set.
6678 FIXME. There doesn't seem to be any real need for separate
6679 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6680 Removing them would probably clean up the code quite a lot. */
4eed87de 6681 if (flag_code != CODE_64BIT
40fb9820
L		 6682 && (i.types[this_operand].bitfield.disp16
6683 || i.types[this_operand].bitfield.disp32))
6684 i.types[this_operand]
c6fb90c8 6685 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6686 fudged = 1;
24eab124
AM		 6687 goto tryprefix;
6688 }
eecb386c 6689 if (fudged)
fc0763e6
JB		 6690 as_bad (_("`%s' is not a valid %s expression"),
6691 operand_string,
6692 kind);
eecb386c 6693 else
c388dee8 6694#endif
fc0763e6 6695 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6696 operand_string,
fc0763e6
JB		 6697 flag_code_names[i.prefix[ADDR_PREFIX]
6698 ? flag_code == CODE_32BIT
6699 ? CODE_16BIT
6700 : CODE_32BIT
6701 : flag_code],
6702 kind);
24eab124 6703 }
20f0a1fc 6704 return ok;
24eab124 6705}
252b5132 6706
fc0763e6 6707/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6708 on error. */
252b5132 6709
252b5132 6710static int
a7619375 6711i386_att_operand (char *operand_string)
252b5132 6712{
af6bdddf
AM		 6713 const reg_entry *r;
6714 char *end_op;
24eab124 6715 char *op_string = operand_string;
252b5132 6716
24eab124 6717 if (is_space_char (*op_string))
252b5132
RH		 6718 ++op_string;
6719
24eab124 6720 /* We check for an absolute prefix (differentiating,
47926f60 6721 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6722 if (*op_string == ABSOLUTE_PREFIX)
6723 {
6724 ++op_string;
6725 if (is_space_char (*op_string))
6726 ++op_string;
40fb9820 6727 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6728 }
252b5132 6729
47926f60 6730 /* Check if operand is a register. */
4d1bb795 6731 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6732 {
40fb9820
L		 6733 i386_operand_type temp;
6734
24eab124
AM		 6735 /* Check for a segment override by searching for ':' after a
6736 segment register. */
6737 op_string = end_op;
6738 if (is_space_char (*op_string))
6739 ++op_string;
40fb9820
L		 6740 if (*op_string == ':'
6741 && (r->reg_type.bitfield.sreg2
6742 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6743 {
6744 switch (r->reg_num)
6745 {
6746 case 0:
6747 i.seg[i.mem_operands] = &es;
6748 break;
6749 case 1:
6750 i.seg[i.mem_operands] = &cs;
6751 break;
6752 case 2:
6753 i.seg[i.mem_operands] = &ss;
6754 break;
6755 case 3:
6756 i.seg[i.mem_operands] = &ds;
6757 break;
6758 case 4:
6759 i.seg[i.mem_operands] = &fs;
6760 break;
6761 case 5:
6762 i.seg[i.mem_operands] = &gs;
6763 break;
6764 }
252b5132 6765
24eab124 6766 /* Skip the ':' and whitespace. */
252b5132
RH		 6767 ++op_string;
6768 if (is_space_char (*op_string))
24eab124 6769 ++op_string;
252b5132 6770
24eab124
AM		 6771 if (!is_digit_char (*op_string)
6772 && !is_identifier_char (*op_string)
6773 && *op_string != '('
6774 && *op_string != ABSOLUTE_PREFIX)
6775 {
6776 as_bad (_("bad memory operand `%s'"), op_string);
6777 return 0;
6778 }
47926f60 6779 /* Handle case of %es:*foo. */
24eab124
AM		 6780 if (*op_string == ABSOLUTE_PREFIX)
6781 {
6782 ++op_string;
6783 if (is_space_char (*op_string))
6784 ++op_string;
40fb9820 6785 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6786 }
6787 goto do_memory_reference;
6788 }
6789 if (*op_string)
6790 {
d0b47220 6791 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6792 return 0;
6793 }
40fb9820
L		 6794 temp = r->reg_type;
6795 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6796 i.types[this_operand] = operand_type_or (i.types[this_operand],
6797 temp);
7d5e4556 6798 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6799 i.op[this_operand].regs = r;
24eab124
AM		 6800 i.reg_operands++;
6801 }
af6bdddf
AM		 6802 else if (*op_string == REGISTER_PREFIX)
6803 {
6804 as_bad (_("bad register name `%s'"), op_string);
6805 return 0;
6806 }
24eab124 6807 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6808 {
24eab124 6809 ++op_string;
40fb9820 6810 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6811 {
d0b47220 6812 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6813 return 0;
6814 }
6815 if (!i386_immediate (op_string))
6816 return 0;
6817 }
6818 else if (is_digit_char (*op_string)
6819 || is_identifier_char (*op_string)
e5cb08ac 6820 || *op_string == '(')
24eab124 6821 {
47926f60 6822 /* This is a memory reference of some sort. */
af6bdddf 6823 char *base_string;
252b5132 6824
47926f60 6825 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6826 char *displacement_string_start;
6827 char *displacement_string_end;
252b5132 6828
24eab124 6829 do_memory_reference:
24eab124 6830 if ((i.mem_operands == 1
40fb9820 6831 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6832 || i.mem_operands == 2)
6833 {
6834 as_bad (_("too many memory references for `%s'"),
6835 current_templates->start->name);
6836 return 0;
6837 }
252b5132 6838
24eab124
AM		 6839 /* Check for base index form. We detect the base index form by
6840 looking for an ')' at the end of the operand, searching
6841 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6842 after the '('. */
af6bdddf 6843 base_string = op_string + strlen (op_string);
c3332e24 6844
af6bdddf
AM		 6845 --base_string;
6846 if (is_space_char (*base_string))
6847 --base_string;
252b5132 6848
47926f60 6849 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6850 displacement_string_start = op_string;
6851 displacement_string_end = base_string + 1;
252b5132 6852
24eab124
AM		 6853 if (*base_string == ')')
6854 {
af6bdddf 6855 char *temp_string;
24eab124
AM		 6856 unsigned int parens_balanced = 1;
6857 /* We've already checked that the number of left & right ()'s are
47926f60 6858 equal, so this loop will not be infinite. */
24eab124
AM		 6859 do
6860 {
6861 base_string--;
6862 if (*base_string == ')')
6863 parens_balanced++;
6864 if (*base_string == '(')
6865 parens_balanced--;
6866 }
6867 while (parens_balanced);
c3332e24 6868
af6bdddf 6869 temp_string = base_string;
c3332e24 6870
24eab124 6871 /* Skip past '(' and whitespace. */
252b5132
RH		 6872 ++base_string;
6873 if (is_space_char (*base_string))
24eab124 6874 ++base_string;
252b5132 6875
af6bdddf 6876 if (*base_string == ','
4eed87de
AM		 6877 || ((i.base_reg = parse_register (base_string, &end_op))
6878 != NULL))
252b5132 6879 {
af6bdddf 6880 displacement_string_end = temp_string;
252b5132 6881
40fb9820 6882 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6883
af6bdddf 6884 if (i.base_reg)
24eab124 6885 {
24eab124
AM		 6886 base_string = end_op;
6887 if (is_space_char (*base_string))
6888 ++base_string;
af6bdddf
AM		 6889 }
6890
6891 /* There may be an index reg or scale factor here. */
6892 if (*base_string == ',')
6893 {
6894 ++base_string;
6895 if (is_space_char (*base_string))
6896 ++base_string;
6897
4eed87de
AM		 6898 if ((i.index_reg = parse_register (base_string, &end_op))
6899 != NULL)
24eab124 6900 {
af6bdddf 6901 base_string = end_op;
24eab124
AM		 6902 if (is_space_char (*base_string))
6903 ++base_string;
af6bdddf
AM		 6904 if (*base_string == ',')
6905 {
6906 ++base_string;
6907 if (is_space_char (*base_string))
6908 ++base_string;
6909 }
e5cb08ac 6910 else if (*base_string != ')')
af6bdddf 6911 {
4eed87de
AM		 6912 as_bad (_("expecting `,' or `)' "
6913 "after index register in `%s'"),
af6bdddf
AM		 6914 operand_string);
6915 return 0;
6916 }
24eab124 6917 }
af6bdddf 6918 else if (*base_string == REGISTER_PREFIX)
24eab124 6919 {
af6bdddf 6920 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6921 return 0;
6922 }
252b5132 6923
47926f60 6924 /* Check for scale factor. */
551c1ca1 6925 if (*base_string != ')')
af6bdddf 6926 {
551c1ca1
AM		 6927 char *end_scale = i386_scale (base_string);
6928
6929 if (!end_scale)
af6bdddf 6930 return 0;
24eab124 6931
551c1ca1 6932 base_string = end_scale;
af6bdddf
AM		 6933 if (is_space_char (*base_string))
6934 ++base_string;
6935 if (*base_string != ')')
6936 {
4eed87de
AM		 6937 as_bad (_("expecting `)' "
6938 "after scale factor in `%s'"),
af6bdddf
AM		 6939 operand_string);
6940 return 0;
6941 }
6942 }
6943 else if (!i.index_reg)
24eab124 6944 {
4eed87de
AM		 6945 as_bad (_("expecting index register or scale factor "
6946 "after `,'; got '%c'"),
af6bdddf 6947 *base_string);
24eab124
AM		 6948 return 0;
6949 }
6950 }
af6bdddf 6951 else if (*base_string != ')')
24eab124 6952 {
4eed87de
AM		 6953 as_bad (_("expecting `,' or `)' "
6954 "after base register in `%s'"),
af6bdddf 6955 operand_string);
24eab124
AM		 6956 return 0;
6957 }
c3332e24 6958 }
af6bdddf 6959 else if (*base_string == REGISTER_PREFIX)
c3332e24 6960 {
af6bdddf 6961 as_bad (_("bad register name `%s'"), base_string);
24eab124 6962 return 0;
c3332e24 6963 }
24eab124
AM		 6964 }
6965
6966 /* If there's an expression beginning the operand, parse it,
6967 assuming displacement_string_start and
6968 displacement_string_end are meaningful. */
6969 if (displacement_string_start != displacement_string_end)
6970 {
6971 if (!i386_displacement (displacement_string_start,
6972 displacement_string_end))
6973 return 0;
6974 }
6975
6976 /* Special case for (%dx) while doing input/output op. */
6977 if (i.base_reg
0dfbf9d7
L		 6978 && operand_type_equal (&i.base_reg->reg_type,
6979 &reg16_inoutportreg)
24eab124
AM		 6980 && i.index_reg == 0
6981 && i.log2_scale_factor == 0
6982 && i.seg[i.mem_operands] == 0
40fb9820 6983 && !operand_type_check (i.types[this_operand], disp))
24eab124 6984 {
65da13b5 6985 i.types[this_operand] = inoutportreg;
24eab124
AM		 6986 return 1;
6987 }
6988
eecb386c
AM		 6989 if (i386_index_check (operand_string) == 0)
6990 return 0;
5c07affc 6991 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 6992 i.mem_operands++;
6993 }
6994 else
ce8a8b2f
AM		 6995 {
6996 /* It's not a memory operand; argh! */
24eab124
AM		 6997 as_bad (_("invalid char %s beginning operand %d `%s'"),
6998 output_invalid (*op_string),
6999 this_operand + 1,
7000 op_string);
7001 return 0;
7002 }
47926f60 7003 return 1; /* Normal return. */
252b5132
RH		 7004}
7005\f
ee7fcc42
AM		 7006/* md_estimate_size_before_relax()
7007
7008 Called just before relax() for rs_machine_dependent frags. The x86
7009 assembler uses these frags to handle variable size jump
7010 instructions.
7011
7012 Any symbol that is now undefined will not become defined.
7013 Return the correct fr_subtype in the frag.
7014 Return the initial "guess for variable size of frag" to caller.
7015 The guess is actually the growth beyond the fixed part. Whatever
7016 we do to grow the fixed or variable part contributes to our
7017 returned value. */
7018
252b5132
RH		 7019int
7020md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7021 fragS *fragP;
7022 segT segment;
252b5132 7023{
252b5132 7024 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7025 check for un-relaxable symbols. On an ELF system, we can't relax
7026 an externally visible symbol, because it may be overridden by a
7027 shared library. */
7028 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7029#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7030 || (IS_ELF
31312f95 7031 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7032 || S_IS_WEAK (fragP->fr_symbol)
7033 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7034 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7035#endif
7036#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7037 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7038 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7039#endif
7040 )
252b5132 7041 {
b98ef147
AM		 7042 /* Symbol is undefined in this segment, or we need to keep a
7043 reloc so that weak symbols can be overridden. */
7044 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7045 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7046 unsigned char *opcode;
7047 int old_fr_fix;
f6af82bd 7048
ee7fcc42
AM		 7049 if (fragP->fr_var != NO_RELOC)
7050 reloc_type = fragP->fr_var;
b98ef147 7051 else if (size == 2)
f6af82bd
AM		 7052 reloc_type = BFD_RELOC_16_PCREL;
7053 else
7054 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7055
ee7fcc42
AM		 7056 old_fr_fix = fragP->fr_fix;
7057 opcode = (unsigned char *) fragP->fr_opcode;
7058
fddf5b5b 7059 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7060 {
fddf5b5b
AM		 7061 case UNCOND_JUMP:
7062 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7063 opcode[0] = 0xe9;
252b5132 7064 fragP->fr_fix += size;
062cd5e7
AS		 7065 fix_new (fragP, old_fr_fix, size,
7066 fragP->fr_symbol,
7067 fragP->fr_offset, 1,
7068 reloc_type);
252b5132
RH		 7069 break;
7070
fddf5b5b 7071 case COND_JUMP86:
412167cb
AM		 7072 if (size == 2
7073 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7074 {
7075 /* Negate the condition, and branch past an
7076 unconditional jump. */
7077 opcode[0] ^= 1;
7078 opcode[1] = 3;
7079 /* Insert an unconditional jump. */
7080 opcode[2] = 0xe9;
7081 /* We added two extra opcode bytes, and have a two byte
7082 offset. */
7083 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7084 fix_new (fragP, old_fr_fix + 2, 2,
7085 fragP->fr_symbol,
7086 fragP->fr_offset, 1,
7087 reloc_type);
fddf5b5b
AM		 7088 break;
7089 }
7090 /* Fall through. */
7091
7092 case COND_JUMP:
412167cb
AM		 7093 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7094 {
3e02c1cc
AM		 7095 fixS *fixP;
7096
412167cb 7097 fragP->fr_fix += 1;
3e02c1cc
AM		 7098 fixP = fix_new (fragP, old_fr_fix, 1,
7099 fragP->fr_symbol,
7100 fragP->fr_offset, 1,
7101 BFD_RELOC_8_PCREL);
7102 fixP->fx_signed = 1;
412167cb
AM		 7103 break;
7104 }
93c2a809 7105
24eab124 7106 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7107 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7108 opcode[1] = opcode[0] + 0x10;
f6af82bd 7109 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7110 /* We've added an opcode byte. */
7111 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7112 fix_new (fragP, old_fr_fix + 1, size,
7113 fragP->fr_symbol,
7114 fragP->fr_offset, 1,
7115 reloc_type);
252b5132 7116 break;
fddf5b5b
AM		 7117
7118 default:
7119 BAD_CASE (fragP->fr_subtype);
7120 break;
252b5132
RH		 7121 }
7122 frag_wane (fragP);
ee7fcc42 7123 return fragP->fr_fix - old_fr_fix;
252b5132 7124 }
93c2a809 7125
93c2a809
AM		 7126 /* Guess size depending on current relax state. Initially the relax
7127 state will correspond to a short jump and we return 1, because
7128 the variable part of the frag (the branch offset) is one byte
7129 long. However, we can relax a section more than once and in that
7130 case we must either set fr_subtype back to the unrelaxed state,
7131 or return the value for the appropriate branch. */
7132 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7133}
7134
47926f60
KH		 7135/* Called after relax() is finished.
7136
7137 In: Address of frag.
7138 fr_type == rs_machine_dependent.
7139 fr_subtype is what the address relaxed to.
7140
7141 Out: Any fixSs and constants are set up.
7142 Caller will turn frag into a ".space 0". */
7143
252b5132
RH		 7144void
7145md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7146 bfd *abfd ATTRIBUTE_UNUSED;
7147 segT sec ATTRIBUTE_UNUSED;
29b0f896 7148 fragS *fragP;
252b5132 7149{
29b0f896 7150 unsigned char *opcode;
252b5132 7151 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7152 offsetT target_address;
7153 offsetT opcode_address;
252b5132 7154 unsigned int extension = 0;
847f7ad4 7155 offsetT displacement_from_opcode_start;
252b5132
RH		 7156
7157 opcode = (unsigned char *) fragP->fr_opcode;
7158
47926f60 7159 /* Address we want to reach in file space. */
252b5132 7160 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7161
47926f60 7162 /* Address opcode resides at in file space. */
252b5132
RH		 7163 opcode_address = fragP->fr_address + fragP->fr_fix;
7164
47926f60 7165 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7166 displacement_from_opcode_start = target_address - opcode_address;
7167
fddf5b5b 7168 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7169 {
47926f60
KH		 7170 /* Don't have to change opcode. */
7171 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7172 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7173 }
7174 else
7175 {
7176 if (no_cond_jump_promotion
7177 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7178 as_warn_where (fragP->fr_file, fragP->fr_line,
7179 _("long jump required"));
252b5132 7180
fddf5b5b
AM		 7181 switch (fragP->fr_subtype)
7182 {
7183 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7184 extension = 4; /* 1 opcode + 4 displacement */
7185 opcode[0] = 0xe9;
7186 where_to_put_displacement = &opcode[1];
7187 break;
252b5132 7188
fddf5b5b
AM		 7189 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7190 extension = 2; /* 1 opcode + 2 displacement */
7191 opcode[0] = 0xe9;
7192 where_to_put_displacement = &opcode[1];
7193 break;
252b5132 7194
fddf5b5b
AM		 7195 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7196 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7197 extension = 5; /* 2 opcode + 4 displacement */
7198 opcode[1] = opcode[0] + 0x10;
7199 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7200 where_to_put_displacement = &opcode[2];
7201 break;
252b5132 7202
fddf5b5b
AM		 7203 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7204 extension = 3; /* 2 opcode + 2 displacement */
7205 opcode[1] = opcode[0] + 0x10;
7206 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7207 where_to_put_displacement = &opcode[2];
7208 break;
252b5132 7209
fddf5b5b
AM		 7210 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7211 extension = 4;
7212 opcode[0] ^= 1;
7213 opcode[1] = 3;
7214 opcode[2] = 0xe9;
7215 where_to_put_displacement = &opcode[3];
7216 break;
7217
7218 default:
7219 BAD_CASE (fragP->fr_subtype);
7220 break;
7221 }
252b5132 7222 }
fddf5b5b 7223
7b81dfbb
AJ		 7224 /* If size if less then four we are sure that the operand fits,
7225 but if it's 4, then it could be that the displacement is larger
7226 then -/+ 2GB. */
7227 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7228 && object_64bit
7229 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7230 + ((addressT) 1 << 31))
7231 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7232 {
7233 as_bad_where (fragP->fr_file, fragP->fr_line,
7234 _("jump target out of range"));
7235 /* Make us emit 0. */
7236 displacement_from_opcode_start = extension;
7237 }
47926f60 7238 /* Now put displacement after opcode. */
252b5132
RH		 7239 md_number_to_chars ((char *) where_to_put_displacement,
7240 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7241 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7242 fragP->fr_fix += extension;
7243}
7244\f
252b5132
RH		 7245/* Apply a fixup (fixS) to segment data, once it has been determined
7246 by our caller that we have all the info we need to fix it up.
7247
7248 On the 386, immediates, displacements, and data pointers are all in
7249 the same (little-endian) format, so we don't need to care about which
7250 we are handling. */
7251
94f592af 7252void
55cf6793 7253md_apply_fix (fixP, valP, seg)
47926f60
KH		 7254 /* The fix we're to put in. */
7255 fixS *fixP;
47926f60 7256 /* Pointer to the value of the bits. */
c6682705 7257 valueT *valP;
47926f60
KH		 7258 /* Segment fix is from. */
7259 segT seg ATTRIBUTE_UNUSED;
252b5132 7260{
94f592af 7261 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7262 valueT value = *valP;
252b5132 7263
f86103b7 7264#if !defined (TE_Mach)
93382f6d
AM		 7265 if (fixP->fx_pcrel)
7266 {
7267 switch (fixP->fx_r_type)
7268 {
5865bb77
ILT		 7269 default:
7270 break;
7271
d6ab8113
JB		 7272 case BFD_RELOC_64:
7273 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7274 break;
93382f6d 7275 case BFD_RELOC_32:
ae8887b5 7276 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7277 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7278 break;
7279 case BFD_RELOC_16:
7280 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7281 break;
7282 case BFD_RELOC_8:
7283 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7284 break;
7285 }
7286 }
252b5132 7287
a161fe53 7288 if (fixP->fx_addsy != NULL
31312f95 7289 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7290 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7291 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7292 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7293 && !use_rela_relocations)
252b5132 7294 {
31312f95
AM		 7295 /* This is a hack. There should be a better way to handle this.
7296 This covers for the fact that bfd_install_relocation will
7297 subtract the current location (for partial_inplace, PC relative
7298 relocations); see more below. */
252b5132 7299#ifndef OBJ_AOUT
718ddfc0 7300 if (IS_ELF
252b5132
RH		 7301#ifdef TE_PE
7302 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7303#endif
7304 )
7305 value += fixP->fx_where + fixP->fx_frag->fr_address;
7306#endif
7307#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7308 if (IS_ELF)
252b5132 7309 {
6539b54b 7310 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7311
6539b54b 7312 if ((sym_seg == seg
2f66722d 7313 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7314 && sym_seg != absolute_section))
c25bc9fc 7315 && !TC_FORCE_RELOCATION (fixP))
2f66722d
AM		 7316 {
7317 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7318 bfd_install_relocation subtracts them out again. I think
7319 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7320 it. FIXME. */
7321 value += fixP->fx_where + fixP->fx_frag->fr_address;
7322 }
252b5132
RH		 7323 }
7324#endif
7325#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7326 /* For some reason, the PE format does not store a
7327 section address offset for a PC relative symbol. */
7328 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7329 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7330 value += md_pcrel_from (fixP);
7331#endif
7332 }
fbeb56a4
DK		 7333#if defined (OBJ_COFF) && defined (TE_PE)
7334 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7335 {
7336 value -= S_GET_VALUE (fixP->fx_addsy);
7337 }
7338#endif
252b5132
RH		 7339
7340 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7341 and we must not disappoint it. */
252b5132 7342#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7343 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7344 switch (fixP->fx_r_type)
7345 {
7346 case BFD_RELOC_386_PLT32:
3e73aa7c 7347 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7348 /* Make the jump instruction point to the address of the operand. At
7349 runtime we merely add the offset to the actual PLT entry. */
7350 value = -4;
7351 break;
31312f95 7352
13ae64f3
JJ		 7353 case BFD_RELOC_386_TLS_GD:
7354 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7355 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7356 case BFD_RELOC_386_TLS_IE:
7357 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7358 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7359 case BFD_RELOC_X86_64_TLSGD:
7360 case BFD_RELOC_X86_64_TLSLD:
7361 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7362 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7363 value = 0; /* Fully resolved at runtime. No addend. */
7364 /* Fallthrough */
7365 case BFD_RELOC_386_TLS_LE:
7366 case BFD_RELOC_386_TLS_LDO_32:
7367 case BFD_RELOC_386_TLS_LE_32:
7368 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7369 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7370 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7371 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7372 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7373 break;
7374
67a4f2b7
AO		 7375 case BFD_RELOC_386_TLS_DESC_CALL:
7376 case BFD_RELOC_X86_64_TLSDESC_CALL:
7377 value = 0; /* Fully resolved at runtime. No addend. */
7378 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7379 fixP->fx_done = 0;
7380 return;
7381
00f7efb6
JJ		 7382 case BFD_RELOC_386_GOT32:
7383 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7384 value = 0; /* Fully resolved at runtime. No addend. */
7385 break;
47926f60
KH		 7386
7387 case BFD_RELOC_VTABLE_INHERIT:
7388 case BFD_RELOC_VTABLE_ENTRY:
7389 fixP->fx_done = 0;
94f592af 7390 return;
47926f60
KH		 7391
7392 default:
7393 break;
7394 }
7395#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7396 *valP = value;
f86103b7 7397#endif /* !defined (TE_Mach) */
3e73aa7c 7398
3e73aa7c 7399 /* Are we finished with this relocation now? */
c6682705 7400 if (fixP->fx_addsy == NULL)
3e73aa7c 7401 fixP->fx_done = 1;
fbeb56a4
DK		 7402#if defined (OBJ_COFF) && defined (TE_PE)
7403 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7404 {
7405 fixP->fx_done = 0;
7406 /* Remember value for tc_gen_reloc. */
7407 fixP->fx_addnumber = value;
7408 /* Clear out the frag for now. */
7409 value = 0;
7410 }
7411#endif
3e73aa7c
JH		 7412 else if (use_rela_relocations)
7413 {
7414 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7415 /* Remember value for tc_gen_reloc. */
7416 fixP->fx_addnumber = value;
3e73aa7c
JH		 7417 value = 0;
7418 }
f86103b7 7419
94f592af 7420 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7421}
252b5132 7422\f
252b5132 7423char *
499ac353 7424md_atof (int type, char *litP, int *sizeP)
252b5132 7425{
499ac353
NC		 7426 /* This outputs the LITTLENUMs in REVERSE order;
7427 in accord with the bigendian 386. */
7428 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7429}
7430\f
2d545b82 7431static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7432
252b5132 7433static char *
e3bb37b5 7434output_invalid (int c)
252b5132 7435{
3882b010 7436 if (ISPRINT (c))
f9f21a03
L		 7437 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7438 "'%c'", c);
252b5132 7439 else
f9f21a03 7440 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7441 "(0x%x)", (unsigned char) c);
252b5132
RH		 7442 return output_invalid_buf;
7443}
7444
af6bdddf 7445/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7446
7447static const reg_entry *
4d1bb795 7448parse_real_register (char *reg_string, char **end_op)
252b5132 7449{
af6bdddf
AM		 7450 char *s = reg_string;
7451 char *p;
252b5132
RH		 7452 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7453 const reg_entry *r;
7454
7455 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7456 if (*s == REGISTER_PREFIX)
7457 ++s;
7458
7459 if (is_space_char (*s))
7460 ++s;
7461
7462 p = reg_name_given;
af6bdddf 7463 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7464 {
7465 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7466 return (const reg_entry *) NULL;
7467 s++;
252b5132
RH		 7468 }
7469
6588847e
DN		 7470 /* For naked regs, make sure that we are not dealing with an identifier.
7471 This prevents confusing an identifier like `eax_var' with register
7472 `eax'. */
7473 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7474 return (const reg_entry *) NULL;
7475
af6bdddf 7476 *end_op = s;
252b5132
RH		 7477
7478 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7479
5f47d35b 7480 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7481 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7482 {
5f47d35b
AM		 7483 if (is_space_char (*s))
7484 ++s;
7485 if (*s == '(')
7486 {
af6bdddf 7487 ++s;
5f47d35b
AM		 7488 if (is_space_char (*s))
7489 ++s;
7490 if (*s >= '0' && *s <= '7')
7491 {
db557034 7492 int fpr = *s - '0';
af6bdddf 7493 ++s;
5f47d35b
AM		 7494 if (is_space_char (*s))
7495 ++s;
7496 if (*s == ')')
7497 {
7498 *end_op = s + 1;
db557034
AM		 7499 r = hash_find (reg_hash, "st(0)");
7500 know (r);
7501 return r + fpr;
5f47d35b 7502 }
5f47d35b 7503 }
47926f60 7504 /* We have "%st(" then garbage. */
5f47d35b
AM		 7505 return (const reg_entry *) NULL;
7506 }
7507 }
7508
a60de03c
JB		 7509 if (r == NULL || allow_pseudo_reg)
7510 return r;
7511
0dfbf9d7 7512 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7513 return (const reg_entry *) NULL;
7514
192dc9c6
JB		 7515 if ((r->reg_type.bitfield.reg32
7516 || r->reg_type.bitfield.sreg3
7517 || r->reg_type.bitfield.control
7518 || r->reg_type.bitfield.debug
7519 || r->reg_type.bitfield.test)
7520 && !cpu_arch_flags.bitfield.cpui386)
7521 return (const reg_entry *) NULL;
7522
309d3373
JB		 7523 if (r->reg_type.bitfield.floatreg
7524 && !cpu_arch_flags.bitfield.cpu8087
7525 && !cpu_arch_flags.bitfield.cpu287
7526 && !cpu_arch_flags.bitfield.cpu387)
7527 return (const reg_entry *) NULL;
7528
192dc9c6
JB		 7529 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7530 return (const reg_entry *) NULL;
7531
7532 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7533 return (const reg_entry *) NULL;
7534
40f12533
L		 7535 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7536 return (const reg_entry *) NULL;
7537
db51cc60 7538 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7539 if (!allow_index_reg
db51cc60
L		 7540 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7541 return (const reg_entry *) NULL;
7542
a60de03c
JB		 7543 if (((r->reg_flags & (RegRex64 | RegRex))
7544 || r->reg_type.bitfield.reg64)
40fb9820 7545 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7546 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7547 && flag_code != CODE_64BIT)
20f0a1fc 7548 return (const reg_entry *) NULL;
1ae00879 7549
b7240065
JB		 7550 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7551 return (const reg_entry *) NULL;
7552
252b5132
RH		 7553 return r;
7554}
4d1bb795
JB		 7555
7556/* REG_STRING starts *before* REGISTER_PREFIX. */
7557
7558static const reg_entry *
7559parse_register (char *reg_string, char **end_op)
7560{
7561 const reg_entry *r;
7562
7563 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7564 r = parse_real_register (reg_string, end_op);
7565 else
7566 r = NULL;
7567 if (!r)
7568 {
7569 char *save = input_line_pointer;
7570 char c;
7571 symbolS *symbolP;
7572
7573 input_line_pointer = reg_string;
7574 c = get_symbol_end ();
7575 symbolP = symbol_find (reg_string);
7576 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7577 {
7578 const expressionS *e = symbol_get_value_expression (symbolP);
7579
7580 know (e->X_op == O_register);
4eed87de 7581 know (e->X_add_number >= 0
c3fe08fa 7582 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7583 r = i386_regtab + e->X_add_number;
7584 *end_op = input_line_pointer;
7585 }
7586 *input_line_pointer = c;
7587 input_line_pointer = save;
7588 }
7589 return r;
7590}
7591
7592int
7593i386_parse_name (char *name, expressionS *e, char *nextcharP)
7594{
7595 const reg_entry *r;
7596 char *end = input_line_pointer;
7597
7598 *end = *nextcharP;
7599 r = parse_register (name, &input_line_pointer);
7600 if (r && end <= input_line_pointer)
7601 {
7602 *nextcharP = *input_line_pointer;
7603 *input_line_pointer = 0;
7604 e->X_op = O_register;
7605 e->X_add_number = r - i386_regtab;
7606 return 1;
7607 }
7608 input_line_pointer = end;
7609 *end = 0;
ee86248c 7610 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7611}
7612
7613void
7614md_operand (expressionS *e)
7615{
ee86248c
JB		 7616 char *end;
7617 const reg_entry *r;
4d1bb795 7618
ee86248c
JB		 7619 switch (*input_line_pointer)
7620 {
7621 case REGISTER_PREFIX:
7622 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7623 if (r)
7624 {
7625 e->X_op = O_register;
7626 e->X_add_number = r - i386_regtab;
7627 input_line_pointer = end;
7628 }
ee86248c
JB		 7629 break;
7630
7631 case '[':
9c2799c2 7632 gas_assert (intel_syntax);
ee86248c
JB		 7633 end = input_line_pointer++;
7634 expression (e);
7635 if (*input_line_pointer == ']')
7636 {
7637 ++input_line_pointer;
7638 e->X_op_symbol = make_expr_symbol (e);
7639 e->X_add_symbol = NULL;
7640 e->X_add_number = 0;
7641 e->X_op = O_index;
7642 }
7643 else
7644 {
7645 e->X_op = O_absent;
7646 input_line_pointer = end;
7647 }
7648 break;
4d1bb795
JB		 7649 }
7650}
7651
252b5132 7652\f
4cc782b5 7653#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7654const char *md_shortopts = "kVQ:sqn";
252b5132 7655#else
12b55ccc 7656const char *md_shortopts = "qn";
252b5132 7657#endif
6e0b89ee 7658
3e73aa7c 7659#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7660#define OPTION_64 (OPTION_MD_BASE + 1)
7661#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7662#define OPTION_MARCH (OPTION_MD_BASE + 3)
7663#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7664#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7665#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7666#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7667#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7668#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7669#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7670#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7671
99ad8390
NC		 7672struct option md_longopts[] =
7673{
3e73aa7c 7674 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7675#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7676 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7677 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7678#endif
b3b91714 7679 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7680 {"march", required_argument, NULL, OPTION_MARCH},
7681 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7682 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7683 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7684 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7685 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7686 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7687 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7688 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7689 {NULL, no_argument, NULL, 0}
7690};
7691size_t md_longopts_size = sizeof (md_longopts);
7692
7693int
9103f4f4 7694md_parse_option (int c, char *arg)
252b5132 7695{
9103f4f4 7696 unsigned int i;
6305a203 7697 char *arch, *next;
9103f4f4 7698
252b5132
RH		 7699 switch (c)
7700 {
12b55ccc
L		 7701 case 'n':
7702 optimize_align_code = 0;
7703 break;
7704
a38cf1db
AM		 7705 case 'q':
7706 quiet_warnings = 1;
252b5132
RH		 7707 break;
7708
7709#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7710 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7711 should be emitted or not. FIXME: Not implemented. */
7712 case 'Q':
252b5132
RH		 7713 break;
7714
7715 /* -V: SVR4 argument to print version ID. */
7716 case 'V':
7717 print_version_id ();
7718 break;
7719
a38cf1db
AM		 7720 /* -k: Ignore for FreeBSD compatibility. */
7721 case 'k':
252b5132 7722 break;
4cc782b5
ILT		 7723
7724 case 's':
7725 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7726 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7727 break;
99ad8390 7728#endif
321098a5
L		 7729#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7730 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7731 case OPTION_64:
7732 {
7733 const char **list, **l;
7734
3e73aa7c
JH		 7735 list = bfd_target_list ();
7736 for (l = list; *l != NULL; l++)
8620418b 7737 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7738 || strcmp (*l, "coff-x86-64") == 0
7739 || strcmp (*l, "pe-x86-64") == 0
7740 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7741 {
7742 default_arch = "x86_64";
7743 break;
7744 }
3e73aa7c 7745 if (*l == NULL)
6e0b89ee 7746 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7747 free (list);
7748 }
7749 break;
7750#endif
252b5132 7751
6e0b89ee
AM		 7752 case OPTION_32:
7753 default_arch = "i386";
7754 break;
7755
b3b91714
AM		 7756 case OPTION_DIVIDE:
7757#ifdef SVR4_COMMENT_CHARS
7758 {
7759 char *n, *t;
7760 const char *s;
7761
7762 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7763 t = n;
7764 for (s = i386_comment_chars; *s != '\0'; s++)
7765 if (*s != '/')
7766 *t++ = *s;
7767 *t = '\0';
7768 i386_comment_chars = n;
7769 }
7770#endif
7771 break;
7772
9103f4f4 7773 case OPTION_MARCH:
6305a203
L		 7774 arch = xstrdup (arg);
7775 do
9103f4f4 7776 {
6305a203
L		 7777 if (*arch == '.')
7778 as_fatal (_("Invalid -march= option: `%s'"), arg);
7779 next = strchr (arch, '+');
7780 if (next)
7781 *next++ = '\0';
7782 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7783 {
6305a203 7784 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7785 {
6305a203
L		 7786 /* Processor. */
7787 cpu_arch_name = cpu_arch[i].name;
7788 cpu_sub_arch_name = NULL;
7789 cpu_arch_flags = cpu_arch[i].flags;
7790 cpu_arch_isa = cpu_arch[i].type;
7791 cpu_arch_isa_flags = cpu_arch[i].flags;
7792 if (!cpu_arch_tune_set)
7793 {
7794 cpu_arch_tune = cpu_arch_isa;
7795 cpu_arch_tune_flags = cpu_arch_isa_flags;
7796 }
7797 break;
7798 }
7799 else if (*cpu_arch [i].name == '.'
7800 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7801 {
7802 /* ISA entension. */
7803 i386_cpu_flags flags;
309d3373
JB		 7804
7805 if (strncmp (arch, "no", 2))
7806 flags = cpu_flags_or (cpu_arch_flags,
7807 cpu_arch[i].flags);
7808 else
7809 flags = cpu_flags_and_not (cpu_arch_flags,
7810 cpu_arch[i].flags);
0dfbf9d7 7811 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7812 {
7813 if (cpu_sub_arch_name)
7814 {
7815 char *name = cpu_sub_arch_name;
7816 cpu_sub_arch_name = concat (name,
7817 cpu_arch[i].name,
1bf57e9f 7818 (const char *) NULL);
6305a203
L		 7819 free (name);
7820 }
7821 else
7822 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7823 cpu_arch_flags = flags;
7824 }
7825 break;
ccc9c027 7826 }
9103f4f4 7827 }
6305a203
L		 7828
7829 if (i >= ARRAY_SIZE (cpu_arch))
7830 as_fatal (_("Invalid -march= option: `%s'"), arg);
7831
7832 arch = next;
9103f4f4 7833 }
6305a203 7834 while (next != NULL );
9103f4f4
L		 7835 break;
7836
7837 case OPTION_MTUNE:
7838 if (*arg == '.')
7839 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7840 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7841 {
7842 if (strcmp (arg, cpu_arch [i].name) == 0)
7843 {
ccc9c027 7844 cpu_arch_tune_set = 1;
9103f4f4
L		 7845 cpu_arch_tune = cpu_arch [i].type;
7846 cpu_arch_tune_flags = cpu_arch[i].flags;
7847 break;
7848 }
7849 }
7850 if (i >= ARRAY_SIZE (cpu_arch))
7851 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7852 break;
7853
1efbbeb4
L		 7854 case OPTION_MMNEMONIC:
7855 if (strcasecmp (arg, "att") == 0)
7856 intel_mnemonic = 0;
7857 else if (strcasecmp (arg, "intel") == 0)
7858 intel_mnemonic = 1;
7859 else
7860 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7861 break;
7862
7863 case OPTION_MSYNTAX:
7864 if (strcasecmp (arg, "att") == 0)
7865 intel_syntax = 0;
7866 else if (strcasecmp (arg, "intel") == 0)
7867 intel_syntax = 1;
7868 else
7869 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7870 break;
7871
7872 case OPTION_MINDEX_REG:
7873 allow_index_reg = 1;
7874 break;
7875
7876 case OPTION_MNAKED_REG:
7877 allow_naked_reg = 1;
7878 break;
7879
7880 case OPTION_MOLD_GCC:
7881 old_gcc = 1;
1efbbeb4
L		 7882 break;
7883
c0f3af97
L		 7884 case OPTION_MSSE2AVX:
7885 sse2avx = 1;
7886 break;
7887
daf50ae7
L		 7888 case OPTION_MSSE_CHECK:
7889 if (strcasecmp (arg, "error") == 0)
7890 sse_check = sse_check_error;
7891 else if (strcasecmp (arg, "warning") == 0)
7892 sse_check = sse_check_warning;
7893 else if (strcasecmp (arg, "none") == 0)
7894 sse_check = sse_check_none;
7895 else
7896 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
7897 break;
7898
252b5132
RH		 7899 default:
7900 return 0;
7901 }
7902 return 1;
7903}
7904
7905void
7906md_show_usage (stream)
7907 FILE *stream;
7908{
4cc782b5
ILT		 7909#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7910 fprintf (stream, _("\
a38cf1db
AM		 7911 -Q ignored\n\
7912 -V print assembler version number\n\
b3b91714
AM		 7913 -k ignored\n"));
7914#endif
7915 fprintf (stream, _("\
12b55ccc 7916 -n Do not optimize code alignment\n\
b3b91714
AM		 7917 -q quieten some warnings\n"));
7918#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7919 fprintf (stream, _("\
a38cf1db 7920 -s ignored\n"));
b3b91714 7921#endif
321098a5
L		 7922#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7923 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 7924 fprintf (stream, _("\
7925 --32/--64 generate 32bit/64bit code\n"));
7926#endif
b3b91714
AM		 7927#ifdef SVR4_COMMENT_CHARS
7928 fprintf (stream, _("\
7929 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7930#else
7931 fprintf (stream, _("\
b3b91714 7932 --divide ignored\n"));
4cc782b5 7933#endif
9103f4f4 7934 fprintf (stream, _("\
6305a203
L		 7935 -march=CPU[,+EXTENSION...]\n\
7936 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 7937 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7938 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 7939 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 7940 generic32, generic64\n\
599121aa 7941 EXTENSION is combination of:\n\
309d3373
JB		 7942 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
7943 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
7944 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2 7945 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
922d8de8 7946 svme, abm, padlock, fma4\n"));
6305a203 7947 fprintf (stream, _("\
2cb4f3d5
L		 7948 -mtune=CPU optimize for CPU, CPU is one of:\n\
7949 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7950 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 7951 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 7952 generic32, generic64\n"));
ba104c83 7953 fprintf (stream, _("\
c0f3af97
L		 7954 -msse2avx encode SSE instructions with VEX prefix\n"));
7955 fprintf (stream, _("\
daf50ae7
L		 7956 -msse-check=[none|error|warning]\n\
7957 check SSE instructions\n"));
7958 fprintf (stream, _("\
ba104c83
L		 7959 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7960 fprintf (stream, _("\
7961 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7962 fprintf (stream, _("\
7963 -mindex-reg support pseudo index registers\n"));
7964 fprintf (stream, _("\
7965 -mnaked-reg don't require `%%' prefix for registers\n"));
7966 fprintf (stream, _("\
7967 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7968}
7969
3e73aa7c 7970#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 7971 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 7972 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 7973
7974/* Pick the target format to use. */
7975
47926f60 7976const char *
e3bb37b5 7977i386_target_format (void)
252b5132 7978{
3e73aa7c 7979 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7980 {
7981 set_code_flag (CODE_64BIT);
0dfbf9d7 7982 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7983 {
7984 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7985 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7986 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7987 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7988 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7989 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 7990 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 7991 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 7992 cpu_arch_isa_flags.bitfield.cpusse = 1;
7993 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
711eedef 7994 cpu_arch_isa_flags.bitfield.cpulm = 1;
40fb9820 7995 }
0dfbf9d7 7996 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7997 {
7998 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7999 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8000 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8001 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8002 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8003 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8004 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8005 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8006 cpu_arch_tune_flags.bitfield.cpusse = 1;
8007 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8008 }
9103f4f4 8009 }
3e73aa7c 8010 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8011 {
8012 set_code_flag (CODE_32BIT);
0dfbf9d7 8013 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8014 {
8015 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8016 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8017 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8018 }
0dfbf9d7 8019 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8020 {
8021 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8022 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8023 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8024 }
9103f4f4 8025 }
3e73aa7c
JH		 8026 else
8027 as_fatal (_("Unknown architecture"));
252b5132
RH		 8028 switch (OUTPUT_FLAVOR)
8029 {
321098a5 8030#if defined (TE_PE) || defined (TE_PEP)
872ce6ff 8031 case bfd_target_coff_flavour:
321098a5 8032 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
872ce6ff 8033#endif
4c63da97
AM		 8034#ifdef OBJ_MAYBE_AOUT
8035 case bfd_target_aout_flavour:
47926f60 8036 return AOUT_TARGET_FORMAT;
4c63da97
AM		 8037#endif
8038#ifdef OBJ_MAYBE_COFF
252b5132
RH		 8039 case bfd_target_coff_flavour:
8040 return "coff-i386";
4c63da97 8041#endif
3e73aa7c 8042#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8043 case bfd_target_elf_flavour:
3e73aa7c 8044 {
e5cb08ac 8045 if (flag_code == CODE_64BIT)
4fa24527
JB		 8046 {
8047 object_64bit = 1;
8048 use_rela_relocations = 1;
8049 }
9d7cbccd 8050 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 8051 }
e57f8c65
TG		 8052#endif
8053#if defined (OBJ_MACH_O)
8054 case bfd_target_mach_o_flavour:
8055 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8056#endif
252b5132
RH		 8057 default:
8058 abort ();
8059 return NULL;
8060 }
8061}
8062
47926f60 8063#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8064
8065#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8066void
8067i386_elf_emit_arch_note (void)
a847613f 8068{
718ddfc0 8069 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8070 {
8071 char *p;
8072 asection *seg = now_seg;
8073 subsegT subseg = now_subseg;
8074 Elf_Internal_Note i_note;
8075 Elf_External_Note e_note;
8076 asection *note_secp;
8077 int len;
8078
8079 /* Create the .note section. */
8080 note_secp = subseg_new (".note", 0);
8081 bfd_set_section_flags (stdoutput,
8082 note_secp,
8083 SEC_HAS_CONTENTS | SEC_READONLY);
8084
8085 /* Process the arch string. */
8086 len = strlen (cpu_arch_name);
8087
8088 i_note.namesz = len + 1;
8089 i_note.descsz = 0;
8090 i_note.type = NT_ARCH;
8091 p = frag_more (sizeof (e_note.namesz));
8092 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8093 p = frag_more (sizeof (e_note.descsz));
8094 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8095 p = frag_more (sizeof (e_note.type));
8096 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8097 p = frag_more (len + 1);
8098 strcpy (p, cpu_arch_name);
8099
8100 frag_align (2, 0, 0);
8101
8102 subseg_set (seg, subseg);
8103 }
8104}
8105#endif
252b5132 8106\f
252b5132
RH		 8107symbolS *
8108md_undefined_symbol (name)
8109 char *name;
8110{
18dc2407
ILT		 8111 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8112 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8113 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8114 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8115 {
8116 if (!GOT_symbol)
8117 {
8118 if (symbol_find (name))
8119 as_bad (_("GOT already in symbol table"));
8120 GOT_symbol = symbol_new (name, undefined_section,
8121 (valueT) 0, &zero_address_frag);
8122 };
8123 return GOT_symbol;
8124 }
252b5132
RH		 8125 return 0;
8126}
8127
8128/* Round up a section size to the appropriate boundary. */
47926f60 8129
252b5132
RH		 8130valueT
8131md_section_align (segment, size)
ab9da554 8132 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8133 valueT size;
8134{
4c63da97
AM		 8135#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8136 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8137 {
8138 /* For a.out, force the section size to be aligned. If we don't do
8139 this, BFD will align it for us, but it will not write out the
8140 final bytes of the section. This may be a bug in BFD, but it is
8141 easier to fix it here since that is how the other a.out targets
8142 work. */
8143 int align;
8144
8145 align = bfd_get_section_alignment (stdoutput, segment);
8146 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8147 }
252b5132
RH		 8148#endif
8149
8150 return size;
8151}
8152
8153/* On the i386, PC-relative offsets are relative to the start of the
8154 next instruction. That is, the address of the offset, plus its
8155 size, since the offset is always the last part of the insn. */
8156
8157long
e3bb37b5 8158md_pcrel_from (fixS *fixP)
252b5132
RH		 8159{
8160 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8161}
8162
8163#ifndef I386COFF
8164
8165static void
e3bb37b5 8166s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8167{
29b0f896 8168 int temp;
252b5132 8169
8a75718c
JB		 8170#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8171 if (IS_ELF)
8172 obj_elf_section_change_hook ();
8173#endif
252b5132
RH		 8174 temp = get_absolute_expression ();
8175 subseg_set (bss_section, (subsegT) temp);
8176 demand_empty_rest_of_line ();
8177}
8178
8179#endif
8180
252b5132 8181void
e3bb37b5 8182i386_validate_fix (fixS *fixp)
252b5132
RH		 8183{
8184 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8185 {
23df1078
JH		 8186 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8187 {
4fa24527 8188 if (!object_64bit)
23df1078
JH		 8189 abort ();
8190 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8191 }
8192 else
8193 {
4fa24527 8194 if (!object_64bit)
d6ab8113
JB		 8195 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8196 else
8197 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8198 }
252b5132
RH		 8199 fixp->fx_subsy = 0;
8200 }
8201}
8202
252b5132
RH		 8203arelent *
8204tc_gen_reloc (section, fixp)
ab9da554 8205 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8206 fixS *fixp;
8207{
8208 arelent *rel;
8209 bfd_reloc_code_real_type code;
8210
8211 switch (fixp->fx_r_type)
8212 {
3e73aa7c
JH		 8213 case BFD_RELOC_X86_64_PLT32:
8214 case BFD_RELOC_X86_64_GOT32:
8215 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8216 case BFD_RELOC_386_PLT32:
8217 case BFD_RELOC_386_GOT32:
8218 case BFD_RELOC_386_GOTOFF:
8219 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8220 case BFD_RELOC_386_TLS_GD:
8221 case BFD_RELOC_386_TLS_LDM:
8222 case BFD_RELOC_386_TLS_LDO_32:
8223 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8224 case BFD_RELOC_386_TLS_IE:
8225 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8226 case BFD_RELOC_386_TLS_LE_32:
8227 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8228 case BFD_RELOC_386_TLS_GOTDESC:
8229 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8230 case BFD_RELOC_X86_64_TLSGD:
8231 case BFD_RELOC_X86_64_TLSLD:
8232 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8233 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8234 case BFD_RELOC_X86_64_GOTTPOFF:
8235 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8236 case BFD_RELOC_X86_64_TPOFF64:
8237 case BFD_RELOC_X86_64_GOTOFF64:
8238 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8239 case BFD_RELOC_X86_64_GOT64:
8240 case BFD_RELOC_X86_64_GOTPCREL64:
8241 case BFD_RELOC_X86_64_GOTPC64:
8242 case BFD_RELOC_X86_64_GOTPLT64:
8243 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8244 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8245 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8246 case BFD_RELOC_RVA:
8247 case BFD_RELOC_VTABLE_ENTRY:
8248 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8249#ifdef TE_PE
8250 case BFD_RELOC_32_SECREL:
8251#endif
252b5132
RH		 8252 code = fixp->fx_r_type;
8253 break;
dbbaec26
L		 8254 case BFD_RELOC_X86_64_32S:
8255 if (!fixp->fx_pcrel)
8256 {
8257 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8258 code = fixp->fx_r_type;
8259 break;
8260 }
252b5132 8261 default:
93382f6d 8262 if (fixp->fx_pcrel)
252b5132 8263 {
93382f6d
AM		 8264 switch (fixp->fx_size)
8265 {
8266 default:
b091f402
AM		 8267 as_bad_where (fixp->fx_file, fixp->fx_line,
8268 _("can not do %d byte pc-relative relocation"),
8269 fixp->fx_size);
93382f6d
AM		 8270 code = BFD_RELOC_32_PCREL;
8271 break;
8272 case 1: code = BFD_RELOC_8_PCREL; break;
8273 case 2: code = BFD_RELOC_16_PCREL; break;
8274 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8275#ifdef BFD64
8276 case 8: code = BFD_RELOC_64_PCREL; break;
8277#endif
93382f6d
AM		 8278 }
8279 }
8280 else
8281 {
8282 switch (fixp->fx_size)
8283 {
8284 default:
b091f402
AM		 8285 as_bad_where (fixp->fx_file, fixp->fx_line,
8286 _("can not do %d byte relocation"),
8287 fixp->fx_size);
93382f6d
AM		 8288 code = BFD_RELOC_32;
8289 break;
8290 case 1: code = BFD_RELOC_8; break;
8291 case 2: code = BFD_RELOC_16; break;
8292 case 4: code = BFD_RELOC_32; break;
937149dd 8293#ifdef BFD64
3e73aa7c 8294 case 8: code = BFD_RELOC_64; break;
937149dd 8295#endif
93382f6d 8296 }
252b5132
RH		 8297 }
8298 break;
8299 }
252b5132 8300
d182319b
JB		 8301 if ((code == BFD_RELOC_32
8302 || code == BFD_RELOC_32_PCREL
8303 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8304 && GOT_symbol
8305 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8306 {
4fa24527 8307 if (!object_64bit)
d6ab8113
JB		 8308 code = BFD_RELOC_386_GOTPC;
8309 else
8310 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8311 }
7b81dfbb
AJ		 8312 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8313 && GOT_symbol
8314 && fixp->fx_addsy == GOT_symbol)
8315 {
8316 code = BFD_RELOC_X86_64_GOTPC64;
8317 }
252b5132
RH		 8318
8319 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8320 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8321 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8322
8323 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8324
3e73aa7c
JH		 8325 if (!use_rela_relocations)
8326 {
8327 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8328 vtable entry to be used in the relocation's section offset. */
8329 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8330 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8331#if defined (OBJ_COFF) && defined (TE_PE)
8332 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8333 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8334 else
8335#endif
c6682705 8336 rel->addend = 0;
3e73aa7c
JH		 8337 }
8338 /* Use the rela in 64bit mode. */
252b5132 8339 else
3e73aa7c 8340 {
062cd5e7
AS		 8341 if (!fixp->fx_pcrel)
8342 rel->addend = fixp->fx_offset;
8343 else
8344 switch (code)
8345 {
8346 case BFD_RELOC_X86_64_PLT32:
8347 case BFD_RELOC_X86_64_GOT32:
8348 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8349 case BFD_RELOC_X86_64_TLSGD:
8350 case BFD_RELOC_X86_64_TLSLD:
8351 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8352 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8353 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8354 rel->addend = fixp->fx_offset - fixp->fx_size;
8355 break;
8356 default:
8357 rel->addend = (section->vma
8358 - fixp->fx_size
8359 + fixp->fx_addnumber
8360 + md_pcrel_from (fixp));
8361 break;
8362 }
3e73aa7c
JH		 8363 }
8364
252b5132
RH		 8365 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8366 if (rel->howto == NULL)
8367 {
8368 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8369 _("cannot represent relocation type %s"),
252b5132
RH		 8370 bfd_get_reloc_code_name (code));
8371 /* Set howto to a garbage value so that we can keep going. */
8372 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8373 gas_assert (rel->howto != NULL);
252b5132
RH		 8374 }
8375
8376 return rel;
8377}
8378
ee86248c 8379#include "tc-i386-intel.c"
54cfded0 8380
a60de03c
JB		 8381void
8382tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8383{
a60de03c
JB		 8384 int saved_naked_reg;
8385 char saved_register_dot;
54cfded0 8386
a60de03c
JB		 8387 saved_naked_reg = allow_naked_reg;
8388 allow_naked_reg = 1;
8389 saved_register_dot = register_chars['.'];
8390 register_chars['.'] = '.';
8391 allow_pseudo_reg = 1;
8392 expression_and_evaluate (exp);
8393 allow_pseudo_reg = 0;
8394 register_chars['.'] = saved_register_dot;
8395 allow_naked_reg = saved_naked_reg;
8396
8397 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8398 {
a60de03c
JB		 8399 if ((addressT) exp->X_add_number < i386_regtab_size)
8400 {
8401 exp->X_op = O_constant;
8402 exp->X_add_number = i386_regtab[exp->X_add_number]
8403 .dw2_regnum[flag_code >> 1];
8404 }
8405 else
8406 exp->X_op = O_illegal;
54cfded0 8407 }
54cfded0
AM		 8408}
8409
8410void
8411tc_x86_frame_initial_instructions (void)
8412{
a60de03c
JB		 8413 static unsigned int sp_regno[2];
8414
8415 if (!sp_regno[flag_code >> 1])
8416 {
8417 char *saved_input = input_line_pointer;
8418 char sp[][4] = {"esp", "rsp"};
8419 expressionS exp;
a4447b93 8420
a60de03c
JB		 8421 input_line_pointer = sp[flag_code >> 1];
8422 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8423 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8424 sp_regno[flag_code >> 1] = exp.X_add_number;
8425 input_line_pointer = saved_input;
8426 }
a4447b93 8427
a60de03c 8428 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8429 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8430}
d2b2c203
DJ		 8431
8432int
8433i386_elf_section_type (const char *str, size_t len)
8434{
8435 if (flag_code == CODE_64BIT
8436 && len == sizeof ("unwind") - 1
8437 && strncmp (str, "unwind", 6) == 0)
8438 return SHT_X86_64_UNWIND;
8439
8440 return -1;
8441}
bb41ade5 8442
ad5fec3b
EB		 8443#ifdef TE_SOLARIS
8444void
8445i386_solaris_fix_up_eh_frame (segT sec)
8446{
8447 if (flag_code == CODE_64BIT)
8448 elf_section_type (sec) = SHT_X86_64_UNWIND;
8449}
8450#endif
8451
bb41ade5
AM		 8452#ifdef TE_PE
8453void
8454tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8455{
8456 expressionS expr;
8457
8458 expr.X_op = O_secrel;
8459 expr.X_add_symbol = symbol;
8460 expr.X_add_number = 0;
8461 emit_expr (&expr, size);
8462}
8463#endif
3b22753a
L		 8464
8465#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8466/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8467
01e1a5bc 8468bfd_vma
3b22753a
L		 8469x86_64_section_letter (int letter, char **ptr_msg)
8470{
8471 if (flag_code == CODE_64BIT)
8472 {
8473 if (letter == 'l')
8474 return SHF_X86_64_LARGE;
8475
8476 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8477 }
3b22753a 8478 else
64e74474 8479 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8480 return -1;
8481}
8482
01e1a5bc 8483bfd_vma
3b22753a
L		 8484x86_64_section_word (char *str, size_t len)
8485{
8620418b 8486 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8487 return SHF_X86_64_LARGE;
8488
8489 return -1;
8490}
8491
8492static void
8493handle_large_common (int small ATTRIBUTE_UNUSED)
8494{
8495 if (flag_code != CODE_64BIT)
8496 {
8497 s_comm_internal (0, elf_common_parse);
8498 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8499 }
8500 else
8501 {
8502 static segT lbss_section;
8503 asection *saved_com_section_ptr = elf_com_section_ptr;
8504 asection *saved_bss_section = bss_section;
8505
8506 if (lbss_section == NULL)
8507 {
8508 flagword applicable;
8509 segT seg = now_seg;
8510 subsegT subseg = now_subseg;
8511
8512 /* The .lbss section is for local .largecomm symbols. */
8513 lbss_section = subseg_new (".lbss", 0);
8514 applicable = bfd_applicable_section_flags (stdoutput);
8515 bfd_set_section_flags (stdoutput, lbss_section,
8516 applicable & SEC_ALLOC);
8517 seg_info (lbss_section)->bss = 1;
8518
8519 subseg_set (seg, subseg);
8520 }
8521
8522 elf_com_section_ptr = &_bfd_elf_large_com_section;
8523 bss_section = lbss_section;
8524
8525 s_comm_internal (0, elf_common_parse);
8526
8527 elf_com_section_ptr = saved_com_section_ptr;
8528 bss_section = saved_bss_section;
8529 }
8530}
8531#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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