]>
Commit | Line | Data |
---|---|---|
fe8c2806 | 1 | /* |
9b998b0c | 2 | * (C) Copyright 2000-2011 |
fe8c2806 WD |
3 | * Wolfgang Denk, DENX Software Engineering, [email protected]. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <watchdog.h> | |
26 | #include <command.h> | |
27 | #include <malloc.h> | |
52cb4d4f | 28 | #include <stdio_dev.h> |
fe8c2806 WD |
29 | #ifdef CONFIG_8xx |
30 | #include <mpc8xx.h> | |
31 | #endif | |
0db5bca8 WD |
32 | #ifdef CONFIG_5xx |
33 | #include <mpc5xx.h> | |
34 | #endif | |
cbd8a35c | 35 | #ifdef CONFIG_MPC5xxx |
945af8d7 WD |
36 | #include <mpc5xxx.h> |
37 | #endif | |
7def6b34 | 38 | #if defined(CONFIG_CMD_IDE) |
fe8c2806 WD |
39 | #include <ide.h> |
40 | #endif | |
7def6b34 | 41 | #if defined(CONFIG_CMD_SCSI) |
fe8c2806 WD |
42 | #include <scsi.h> |
43 | #endif | |
7def6b34 | 44 | #if defined(CONFIG_CMD_KGDB) |
fe8c2806 WD |
45 | #include <kgdb.h> |
46 | #endif | |
47 | #ifdef CONFIG_STATUS_LED | |
48 | #include <status_led.h> | |
49 | #endif | |
50 | #include <net.h> | |
272cc70b AF |
51 | #ifdef CONFIG_GENERIC_MMC |
52 | #include <mmc.h> | |
53 | #endif | |
281e00a3 | 54 | #include <serial.h> |
6d0f6bcf | 55 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
9c4c5ae3 | 56 | #if !defined(CONFIG_CPM2) |
fe8c2806 WD |
57 | #include <commproc.h> |
58 | #endif | |
7aa78614 | 59 | #endif |
fe8c2806 WD |
60 | #include <version.h> |
61 | #if defined(CONFIG_BAB7xx) | |
62 | #include <w83c553f.h> | |
63 | #endif | |
64 | #include <dtt.h> | |
65 | #if defined(CONFIG_POST) | |
66 | #include <post.h> | |
67 | #endif | |
56f94be3 WD |
68 | #if defined(CONFIG_LOGBUFFER) |
69 | #include <logbuff.h> | |
70 | #endif | |
9c67352f | 71 | #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) |
42d1f039 WD |
72 | #include <asm/cache.h> |
73 | #endif | |
1c43771b WD |
74 | #ifdef CONFIG_PS2KBD |
75 | #include <keyboard.h> | |
76 | #endif | |
fe8c2806 | 77 | |
ecf5b98c KG |
78 | #ifdef CONFIG_ADDR_MAP |
79 | #include <asm/mmu.h> | |
80 | #endif | |
81 | ||
fc39c2fd KG |
82 | #ifdef CONFIG_MP |
83 | #include <asm/mp.h> | |
84 | #endif | |
85 | ||
310cecb8 LCM |
86 | #ifdef CONFIG_BITBANGMII |
87 | #include <miiphy.h> | |
88 | #endif | |
89 | ||
6d0f6bcf | 90 | #ifdef CONFIG_SYS_UPDATE_FLASH_SIZE |
9b998b0c | 91 | extern int update_flash_size(int flash_size); |
fa230445 HS |
92 | #endif |
93 | ||
9045f33c | 94 | #if defined(CONFIG_SC3) |
ca43ba18 HS |
95 | extern void sc3_read_eeprom(void); |
96 | #endif | |
97 | ||
7def6b34 | 98 | #if defined(CONFIG_CMD_DOC) |
9b998b0c | 99 | void doc_init(void); |
fe8c2806 | 100 | #endif |
ea818dbb | 101 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
fe8c2806 WD |
102 | #include <i2c.h> |
103 | #endif | |
04a9e118 | 104 | #include <spi.h> |
d6ac2ed8 | 105 | #include <nand.h> |
fe8c2806 WD |
106 | |
107 | static char *failed = "*** failed ***\n"; | |
108 | ||
544d97e9 | 109 | #if defined(CONFIG_OXC) || defined(CONFIG_RMU) |
fe8c2806 | 110 | extern flash_info_t flash_info[]; |
17d704eb | 111 | #endif |
fe8c2806 | 112 | |
ca43ba18 HS |
113 | #if defined(CONFIG_START_IDE) |
114 | extern int board_start_ide(void); | |
115 | #endif | |
fe8c2806 | 116 | #include <environment.h> |
d87080b7 | 117 | |
bce84c4d | 118 | DECLARE_GLOBAL_DATA_PTR; |
fe8c2806 | 119 | |
6d0f6bcf JCPV |
120 | #if !defined(CONFIG_SYS_MEM_TOP_HIDE) |
121 | #define CONFIG_SYS_MEM_TOP_HIDE 0 | |
6fb4b640 SR |
122 | #endif |
123 | ||
3b57fe0a | 124 | extern ulong __init_end; |
3929fb0a | 125 | extern ulong __bss_end; |
3b57fe0a WD |
126 | ulong monitor_flash_len; |
127 | ||
7def6b34 | 128 | #if defined(CONFIG_CMD_BEDBUG) |
8bde7f77 WD |
129 | #include <bedbug/type.h> |
130 | #endif | |
131 | ||
9b998b0c WD |
132 | /* |
133 | * Utilities | |
fe8c2806 WD |
134 | */ |
135 | ||
fe8c2806 WD |
136 | /* |
137 | * All attempts to come up with a "common" initialization sequence | |
138 | * that works for all boards and architectures failed: some of the | |
139 | * requirements are just _too_ different. To get rid of the resulting | |
140 | * mess of board dependend #ifdef'ed code we now make the whole | |
141 | * initialization sequence configurable to the user. | |
142 | * | |
143 | * The requirements for any new initalization function is simple: it | |
144 | * receives a pointer to the "global data" structure as it's only | |
145 | * argument, and returns an integer return code, where 0 means | |
146 | * "continue" and != 0 means "fatal error, hang the system". | |
147 | */ | |
9b998b0c | 148 | typedef int (init_fnc_t)(void); |
fe8c2806 | 149 | |
9b998b0c WD |
150 | /* |
151 | * Init Utilities | |
152 | * | |
fe8c2806 WD |
153 | * Some of this code should be moved into the core functions, |
154 | * but let's get it working (again) first... | |
155 | */ | |
156 | ||
9b998b0c | 157 | static int init_baudrate(void) |
fe8c2806 | 158 | { |
1272592e SG |
159 | gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); |
160 | return 0; | |
fe8c2806 WD |
161 | } |
162 | ||
163 | /***********************************************************************/ | |
164 | ||
20051f2a | 165 | static void __board_add_ram_info(int use_default) |
79f240f7 KP |
166 | { |
167 | /* please define platform specific board_add_ram_info() */ | |
168 | } | |
9b998b0c WD |
169 | |
170 | void board_add_ram_info(int) | |
171 | __attribute__ ((weak, alias("__board_add_ram_info"))); | |
79f240f7 | 172 | |
20051f2a | 173 | static int __board_flash_wp_on(void) |
c62491d2 JS |
174 | { |
175 | /* | |
176 | * Most flashes can't be detected when write protection is enabled, | |
177 | * so provide a way to let U-Boot gracefully ignore write protected | |
178 | * devices. | |
179 | */ | |
180 | return 0; | |
181 | } | |
9b998b0c WD |
182 | |
183 | int board_flash_wp_on(void) | |
184 | __attribute__ ((weak, alias("__board_flash_wp_on"))); | |
d96f41e0 | 185 | |
20051f2a | 186 | static void __cpu_secondary_init_r(void) |
f9a33f1c KG |
187 | { |
188 | } | |
9b998b0c | 189 | |
f9a33f1c | 190 | void cpu_secondary_init_r(void) |
9b998b0c | 191 | __attribute__ ((weak, alias("__cpu_secondary_init_r"))); |
f9a33f1c | 192 | |
9b998b0c | 193 | static int init_func_ram(void) |
fe8c2806 | 194 | { |
fe8c2806 WD |
195 | #ifdef CONFIG_BOARD_TYPES |
196 | int board_type = gd->board_type; | |
197 | #else | |
198 | int board_type = 0; /* use dummy arg */ | |
199 | #endif | |
9b998b0c | 200 | puts("DRAM: "); |
fe8c2806 | 201 | |
9b998b0c WD |
202 | gd->ram_size = initdram(board_type); |
203 | ||
204 | if (gd->ram_size > 0) { | |
205 | print_size(gd->ram_size, ""); | |
d96f41e0 | 206 | board_add_ram_info(0); |
d96f41e0 | 207 | putc('\n'); |
9b998b0c | 208 | return 0; |
fe8c2806 | 209 | } |
9b998b0c WD |
210 | puts(failed); |
211 | return 1; | |
fe8c2806 WD |
212 | } |
213 | ||
214 | /***********************************************************************/ | |
215 | ||
ea818dbb | 216 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
9b998b0c | 217 | static int init_func_i2c(void) |
fe8c2806 | 218 | { |
9b998b0c | 219 | puts("I2C: "); |
3f4978c7 HS |
220 | #ifdef CONFIG_SYS_I2C |
221 | i2c_init_all(); | |
222 | #else | |
9b998b0c | 223 | i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
3f4978c7 | 224 | #endif |
9b998b0c WD |
225 | puts("ready\n"); |
226 | return 0; | |
fe8c2806 WD |
227 | } |
228 | #endif | |
229 | ||
04a9e118 | 230 | #if defined(CONFIG_HARD_SPI) |
9b998b0c | 231 | static int init_func_spi(void) |
04a9e118 | 232 | { |
9b998b0c WD |
233 | puts("SPI: "); |
234 | spi_init(); | |
235 | puts("ready\n"); | |
236 | return 0; | |
04a9e118 BW |
237 | } |
238 | #endif | |
239 | ||
fe8c2806 WD |
240 | /***********************************************************************/ |
241 | ||
242 | #if defined(CONFIG_WATCHDOG) | |
a6741bce | 243 | int init_func_watchdog_init(void) |
fe8c2806 | 244 | { |
9b998b0c WD |
245 | puts(" Watchdog enabled\n"); |
246 | WATCHDOG_RESET(); | |
247 | return 0; | |
fe8c2806 | 248 | } |
fe8c2806 | 249 | |
a6741bce | 250 | int init_func_watchdog_reset(void) |
fe8c2806 | 251 | { |
9b998b0c WD |
252 | WATCHDOG_RESET(); |
253 | return 0; | |
fe8c2806 | 254 | } |
fe8c2806 WD |
255 | #endif /* CONFIG_WATCHDOG */ |
256 | ||
9b998b0c WD |
257 | /* |
258 | * Initialization sequence | |
fe8c2806 WD |
259 | */ |
260 | ||
20051f2a | 261 | static init_fnc_t *init_sequence[] = { |
0e870980 PA |
262 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
263 | probecpu, | |
264 | #endif | |
91525c67 AV |
265 | #if defined(CONFIG_BOARD_EARLY_INIT_F) |
266 | board_early_init_f, | |
267 | #endif | |
66ca92a5 | 268 | #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) |
fe8c2806 | 269 | get_clocks, /* get CPU and bus clocks (etc.) */ |
090eb735 MK |
270 | #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ |
271 | && !defined(CONFIG_TQM885D) | |
e9132ea9 WD |
272 | adjust_sdram_tbs_8xx, |
273 | #endif | |
fe8c2806 | 274 | init_timebase, |
c178d3da | 275 | #endif |
6d0f6bcf | 276 | #ifdef CONFIG_SYS_ALLOC_DPRAM |
9c4c5ae3 | 277 | #if !defined(CONFIG_CPM2) |
fe8c2806 WD |
278 | dpram_init, |
279 | #endif | |
7aa78614 | 280 | #endif |
fe8c2806 WD |
281 | #if defined(CONFIG_BOARD_POSTCLK_INIT) |
282 | board_postclk_init, | |
283 | #endif | |
284 | env_init, | |
66ca92a5 | 285 | #if defined(CONFIG_8xx_CPUCLK_DEFAULT) |
9b998b0c WD |
286 | /* get CPU and bus clocks according to the environment variable */ |
287 | get_clocks_866, | |
288 | /* adjust sdram refresh rate according to the new clock */ | |
289 | sdram_adjust_866, | |
c178d3da WD |
290 | init_timebase, |
291 | #endif | |
fe8c2806 WD |
292 | init_baudrate, |
293 | serial_init, | |
294 | console_init_f, | |
295 | display_options, | |
296 | #if defined(CONFIG_8260) | |
297 | prt_8260_rsr, | |
298 | prt_8260_clks, | |
299 | #endif /* CONFIG_8260 */ | |
0f898604 | 300 | #if defined(CONFIG_MPC83xx) |
9be39a67 DL |
301 | prt_83xx_rsr, |
302 | #endif | |
fe8c2806 | 303 | checkcpu, |
cbd8a35c | 304 | #if defined(CONFIG_MPC5xxx) |
945af8d7 | 305 | prt_mpc5xxx_clks, |
cbd8a35c | 306 | #endif /* CONFIG_MPC5xxx */ |
fe8c2806 WD |
307 | checkboard, |
308 | INIT_FUNC_WATCHDOG_INIT | |
c837dcb1 | 309 | #if defined(CONFIG_MISC_INIT_F) |
fe8c2806 WD |
310 | misc_init_f, |
311 | #endif | |
312 | INIT_FUNC_WATCHDOG_RESET | |
ea818dbb | 313 | #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SYS_I2C) |
fe8c2806 WD |
314 | init_func_i2c, |
315 | #endif | |
04a9e118 BW |
316 | #if defined(CONFIG_HARD_SPI) |
317 | init_func_spi, | |
318 | #endif | |
4532cb69 WD |
319 | #ifdef CONFIG_POST |
320 | post_init_f, | |
fe8c2806 | 321 | #endif |
6f6430d7 SG |
322 | INIT_FUNC_WATCHDOG_RESET |
323 | init_func_ram, | |
6d0f6bcf | 324 | #if defined(CONFIG_SYS_DRAM_TEST) |
fe8c2806 | 325 | testdram, |
6d0f6bcf | 326 | #endif /* CONFIG_SYS_DRAM_TEST */ |
fe8c2806 | 327 | INIT_FUNC_WATCHDOG_RESET |
9b998b0c | 328 | NULL, /* Terminate this list */ |
fe8c2806 WD |
329 | }; |
330 | ||
81d93e5c KG |
331 | ulong get_effective_memsize(void) |
332 | { | |
333 | #ifndef CONFIG_VERY_BIG_RAM | |
334 | return gd->ram_size; | |
335 | #else | |
336 | /* limit stack to what we can reasonable map */ | |
337 | return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? | |
9b998b0c | 338 | CONFIG_MAX_MEM_MAPPED : gd->ram_size); |
81d93e5c KG |
339 | #endif |
340 | } | |
341 | ||
20051f2a | 342 | static int __fixup_cpu(void) |
123bd96d YS |
343 | { |
344 | return 0; | |
345 | } | |
346 | ||
347 | int fixup_cpu(void) __attribute__((weak, alias("__fixup_cpu"))); | |
348 | ||
9b998b0c | 349 | /* |
fe8c2806 WD |
350 | * This is the first part of the initialization sequence that is |
351 | * implemented in C, but still running from ROM. | |
352 | * | |
353 | * The main purpose is to provide a (serial) console interface as | |
354 | * soon as possible (so we can see any error messages), and to | |
355 | * initialize the RAM so that we can relocate the monitor code to | |
356 | * RAM. | |
357 | * | |
358 | * Be aware of the restrictions: global data is read-only, BSS is not | |
359 | * initialized, and stack space is limited to a few kB. | |
fe8c2806 WD |
360 | */ |
361 | ||
95d449ad MB |
362 | #ifdef CONFIG_LOGBUFFER |
363 | unsigned long logbuffer_base(void) | |
364 | { | |
6d0f6bcf | 365 | return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN; |
95d449ad MB |
366 | } |
367 | #endif | |
368 | ||
9b998b0c | 369 | void board_init_f(ulong bootflag) |
fe8c2806 | 370 | { |
fe8c2806 WD |
371 | bd_t *bd; |
372 | ulong len, addr, addr_sp; | |
7bc5ee07 | 373 | ulong *s; |
fe8c2806 WD |
374 | gd_t *id; |
375 | init_fnc_t **init_fnc_ptr; | |
9b998b0c | 376 | |
fe8c2806 | 377 | #ifdef CONFIG_PRAM |
fe8c2806 | 378 | ulong reg; |
fe8c2806 WD |
379 | #endif |
380 | ||
381 | /* Pointer is writable since we allocated a register for it */ | |
6d0f6bcf | 382 | gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); |
93f6a677 | 383 | /* compiler optimization barrier needed for GCC >= 3.4 */ |
9b998b0c | 384 | __asm__ __volatile__("":::"memory"); |
fe8c2806 | 385 | |
82826d54 DZ |
386 | #if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC512X) && \ |
387 | !defined(CONFIG_MPC83xx) && !defined(CONFIG_MPC85xx) && \ | |
388 | !defined(CONFIG_MPC86xx) | |
fe8c2806 | 389 | /* Clear initial global data */ |
9b998b0c | 390 | memset((void *) gd, 0, sizeof(gd_t)); |
fe8c2806 WD |
391 | #endif |
392 | ||
9b998b0c WD |
393 | for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) |
394 | if ((*init_fnc_ptr) () != 0) | |
395 | hang(); | |
fe8c2806 | 396 | |
9d256b67 BK |
397 | #ifdef CONFIG_POST |
398 | post_bootmode_init(); | |
20051f2a | 399 | post_run(NULL, POST_ROM | post_bootmode_get(NULL)); |
9d256b67 BK |
400 | #endif |
401 | ||
402 | WATCHDOG_RESET(); | |
403 | ||
fe8c2806 WD |
404 | /* |
405 | * Now that we have DRAM mapped and working, we can | |
406 | * relocate the code and continue running from DRAM. | |
407 | * | |
408 | * Reserve memory at end of RAM for (top down in that order): | |
14f73ca6 | 409 | * - area that won't get touched by U-Boot and Linux (optional) |
8bde7f77 | 410 | * - kernel log buffer |
fe8c2806 WD |
411 | * - protected RAM |
412 | * - LCD framebuffer | |
413 | * - monitor code | |
414 | * - board info struct | |
415 | */ | |
3929fb0a | 416 | len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE; |
fe8c2806 | 417 | |
14f73ca6 SR |
418 | /* |
419 | * Subtract specified amount of memory to hide so that it won't | |
420 | * get "touched" at all by U-Boot. By fixing up gd->ram_size | |
421 | * the Linux kernel should now get passed the now "corrected" | |
422 | * memory size and won't touch it either. This should work | |
423 | * for arch/ppc and arch/powerpc. Only Linux board ports in | |
424 | * arch/powerpc with bootwrapper support, that recalculate the | |
425 | * memory size from the SDRAM controller setup will have to | |
426 | * get fixed. | |
427 | */ | |
6d0f6bcf | 428 | gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; |
14f73ca6 | 429 | |
6d0f6bcf | 430 | addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize(); |
fe8c2806 | 431 | |
fc39c2fd KG |
432 | #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500)) |
433 | /* | |
434 | * We need to make sure the location we intend to put secondary core | |
435 | * boot code is reserved and not used by any part of u-boot | |
c0a14aed | 436 | */ |
eb539412 YS |
437 | if (addr > determine_mp_bootpg(NULL)) { |
438 | addr = determine_mp_bootpg(NULL); | |
9b998b0c | 439 | debug("Reserving MP boot page to %08lx\n", addr); |
fc39c2fd KG |
440 | } |
441 | #endif | |
442 | ||
228f29ac | 443 | #ifdef CONFIG_LOGBUFFER |
3d610186 | 444 | #ifndef CONFIG_ALT_LB_ADDR |
228f29ac WD |
445 | /* reserve kernel log buffer */ |
446 | addr -= (LOGBUFF_RESERVE); | |
9b998b0c WD |
447 | debug("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, |
448 | addr); | |
228f29ac | 449 | #endif |
3d610186 | 450 | #endif |
228f29ac | 451 | |
fe8c2806 WD |
452 | #ifdef CONFIG_PRAM |
453 | /* | |
454 | * reserve protected RAM | |
455 | */ | |
1272592e | 456 | reg = getenv_ulong("pram", 10, CONFIG_PRAM); |
9b998b0c | 457 | addr -= (reg << 10); /* size is in kB */ |
1272592e | 458 | debug("Reserving %ldk for protected RAM at %08lx\n", reg, addr); |
fe8c2806 WD |
459 | #endif /* CONFIG_PRAM */ |
460 | ||
461 | /* round down to next 4 kB limit */ | |
462 | addr &= ~(4096 - 1); | |
9b998b0c | 463 | debug("Top of RAM usable for U-Boot at: %08lx\n", addr); |
fe8c2806 WD |
464 | |
465 | #ifdef CONFIG_LCD | |
d32a1a4c MK |
466 | #ifdef CONFIG_FB_ADDR |
467 | gd->fb_base = CONFIG_FB_ADDR; | |
468 | #else | |
fe8c2806 | 469 | /* reserve memory for LCD display (always full pages) */ |
9b998b0c | 470 | addr = lcd_setmem(addr); |
fe8c2806 | 471 | gd->fb_base = addr; |
d32a1a4c | 472 | #endif /* CONFIG_FB_ADDR */ |
fe8c2806 WD |
473 | #endif /* CONFIG_LCD */ |
474 | ||
475 | #if defined(CONFIG_VIDEO) && defined(CONFIG_8xx) | |
476 | /* reserve memory for video display (always full pages) */ | |
9b998b0c | 477 | addr = video_setmem(addr); |
fe8c2806 WD |
478 | gd->fb_base = addr; |
479 | #endif /* CONFIG_VIDEO */ | |
480 | ||
481 | /* | |
482 | * reserve memory for U-Boot code, data & bss | |
682011ff | 483 | * round down to next 4 kB limit |
fe8c2806 WD |
484 | */ |
485 | addr -= len; | |
682011ff | 486 | addr &= ~(4096 - 1); |
7d314992 WD |
487 | #ifdef CONFIG_E500 |
488 | /* round down to next 64 kB limit so that IVPR stays aligned */ | |
489 | addr &= ~(65536 - 1); | |
490 | #endif | |
fe8c2806 | 491 | |
9b998b0c | 492 | debug("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr); |
fe8c2806 WD |
493 | |
494 | /* | |
495 | * reserve memory for malloc() arena | |
496 | */ | |
497 | addr_sp = addr - TOTAL_MALLOC_LEN; | |
9b998b0c WD |
498 | debug("Reserving %dk for malloc() at: %08lx\n", |
499 | TOTAL_MALLOC_LEN >> 10, addr_sp); | |
fe8c2806 WD |
500 | |
501 | /* | |
502 | * (permanently) allocate a Board Info struct | |
503 | * and a permanent copy of the "global" data | |
504 | */ | |
9b998b0c | 505 | addr_sp -= sizeof(bd_t); |
fe8c2806 | 506 | bd = (bd_t *) addr_sp; |
a1c4864a | 507 | memset(bd, 0, sizeof(bd_t)); |
fe8c2806 | 508 | gd->bd = bd; |
9b998b0c WD |
509 | debug("Reserving %zu Bytes for Board Info at: %08lx\n", |
510 | sizeof(bd_t), addr_sp); | |
511 | addr_sp -= sizeof(gd_t); | |
fe8c2806 | 512 | id = (gd_t *) addr_sp; |
9b998b0c WD |
513 | debug("Reserving %zu Bytes for Global Data at: %08lx\n", |
514 | sizeof(gd_t), addr_sp); | |
fe8c2806 WD |
515 | |
516 | /* | |
517 | * Finally, we set up a new (bigger) stack. | |
518 | * | |
519 | * Leave some safety gap for SP, force alignment on 16 byte boundary | |
520 | * Clear initial stack frame | |
521 | */ | |
522 | addr_sp -= 16; | |
523 | addr_sp &= ~0xF; | |
9b998b0c | 524 | s = (ulong *) addr_sp; |
7de8a716 JT |
525 | *s = 0; /* Terminate back chain */ |
526 | *++s = 0; /* NULL return address */ | |
9b998b0c | 527 | debug("Stack Pointer at: %08lx\n", addr_sp); |
fe8c2806 WD |
528 | |
529 | /* | |
530 | * Save local variables to board info struct | |
531 | */ | |
532 | ||
9b998b0c WD |
533 | bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */ |
534 | bd->bi_memsize = gd->ram_size; /* size in bytes */ | |
fe8c2806 | 535 | |
36116650 | 536 | #ifdef CONFIG_SYS_SRAM_BASE |
9b998b0c WD |
537 | bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */ |
538 | bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */ | |
fe8c2806 WD |
539 | #endif |
540 | ||
42d1f039 | 541 | #if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ |
debb7354 | 542 | defined(CONFIG_E500) || defined(CONFIG_MPC86xx) |
6d0f6bcf | 543 | bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */ |
fe8c2806 | 544 | #endif |
cbd8a35c | 545 | #if defined(CONFIG_MPC5xxx) |
6d0f6bcf | 546 | bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */ |
945af8d7 | 547 | #endif |
0f898604 | 548 | #if defined(CONFIG_MPC83xx) |
6d0f6bcf | 549 | bd->bi_immrbar = CONFIG_SYS_IMMR; |
f046ccd1 | 550 | #endif |
fe8c2806 | 551 | |
9b998b0c | 552 | WATCHDOG_RESET(); |
fe8c2806 WD |
553 | bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */ |
554 | bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */ | |
9c4c5ae3 | 555 | #if defined(CONFIG_CPM2) |
748cd059 | 556 | bd->bi_cpmfreq = gd->arch.cpm_clk; |
1206c184 | 557 | bd->bi_brgfreq = gd->arch.brg_clk; |
748cd059 SG |
558 | bd->bi_sccfreq = gd->arch.scc_clk; |
559 | bd->bi_vco = gd->arch.vco_out; | |
9c4c5ae3 | 560 | #endif /* CONFIG_CPM2 */ |
281ff9a4 | 561 | #if defined(CONFIG_MPC512X) |
fefb098b | 562 | bd->bi_ipsfreq = gd->arch.ips_clk; |
281ff9a4 | 563 | #endif /* CONFIG_MPC512X */ |
cbd8a35c | 564 | #if defined(CONFIG_MPC5xxx) |
b2877496 | 565 | bd->bi_ipbfreq = gd->arch.ipb_clk; |
945af8d7 | 566 | bd->bi_pcifreq = gd->pci_clk; |
cbd8a35c | 567 | #endif /* CONFIG_MPC5xxx */ |
fe8c2806 WD |
568 | bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ |
569 | ||
6d0f6bcf | 570 | #ifdef CONFIG_SYS_EXTBDINFO |
9b998b0c WD |
571 | strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); |
572 | strncpy((char *) bd->bi_r_version, U_BOOT_VERSION, | |
573 | sizeof(bd->bi_r_version)); | |
fe8c2806 WD |
574 | |
575 | bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */ | |
576 | bd->bi_plb_busfreq = gd->bus_clk; | |
343c48bd SR |
577 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ |
578 | defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ | |
579 | defined(CONFIG_440EPX) || defined(CONFIG_440GRX) | |
9b998b0c WD |
580 | bd->bi_pci_busfreq = get_PCI_freq(); |
581 | bd->bi_opbfreq = get_OPB_freq(); | |
9fea65a6 | 582 | #elif defined(CONFIG_XILINX_405) |
9b998b0c | 583 | bd->bi_pci_busfreq = get_PCI_freq(); |
fe8c2806 WD |
584 | #endif |
585 | #endif | |
586 | ||
9b998b0c | 587 | debug("New Stack Pointer is: %08lx\n", addr_sp); |
fe8c2806 | 588 | |
9b998b0c | 589 | WATCHDOG_RESET(); |
fe8c2806 | 590 | |
9b998b0c | 591 | gd->relocaddr = addr; /* Store relocation addr, useful for debug */ |
4b99327a | 592 | |
9b998b0c | 593 | memcpy(id, (void *) gd, sizeof(gd_t)); |
fe8c2806 | 594 | |
9b998b0c | 595 | relocate_code(addr_sp, id, addr); |
fe8c2806 WD |
596 | |
597 | /* NOTREACHED - relocate_code() does not return */ | |
598 | } | |
599 | ||
9b998b0c | 600 | /* |
fe8c2806 WD |
601 | * This is the next part if the initialization sequence: we are now |
602 | * running from RAM and have a "normal" C environment, i. e. global | |
603 | * data can be written, BSS has been cleared, the stack size in not | |
604 | * that critical any more, etc. | |
fe8c2806 | 605 | */ |
9b998b0c | 606 | void board_init_r(gd_t *id, ulong dest_addr) |
fe8c2806 | 607 | { |
fe8c2806 | 608 | bd_t *bd; |
a483a167 | 609 | ulong malloc_start; |
9b998b0c | 610 | |
6d0f6bcf | 611 | #ifndef CONFIG_SYS_NO_FLASH |
fe8c2806 WD |
612 | ulong flash_size; |
613 | #endif | |
614 | ||
615 | gd = id; /* initialize RAM version of global data */ | |
616 | bd = gd->bd; | |
617 | ||
618 | gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ | |
f82b3b63 | 619 | |
d4e8ada0 | 620 | /* The Malloc area is immediately below the monitor copy in DRAM */ |
a483a167 | 621 | malloc_start = dest_addr - TOTAL_MALLOC_LEN; |
13d46ab2 | 622 | |
f9476902 PT |
623 | #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) |
624 | /* | |
67ac13b1 SG |
625 | * The gd->arch.cpu pointer is set to an address in flash before |
626 | * relocation. We need to update it to point to the same CPU entry | |
627 | * in RAM. | |
f9476902 | 628 | */ |
67ac13b1 | 629 | gd->arch.cpu += dest_addr - CONFIG_SYS_MONITOR_BASE; |
123bd96d YS |
630 | |
631 | /* | |
632 | * If we didn't know the cpu mask & # cores, we can save them of | |
633 | * now rather than 'computing' them constantly | |
634 | */ | |
635 | fixup_cpu(); | |
a55bb834 KG |
636 | #endif |
637 | ||
638 | #ifdef CONFIG_SYS_EXTRA_ENV_RELOC | |
639 | /* | |
640 | * Some systems need to relocate the env_addr pointer early because the | |
641 | * location it points to will get invalidated before env_relocate is | |
642 | * called. One example is on systems that might use a L2 or L3 cache | |
643 | * in SRAM mode and initialize that cache from SRAM mode back to being | |
644 | * a cache in cpu_init_r. | |
645 | */ | |
646 | gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE; | |
f9476902 PT |
647 | #endif |
648 | ||
bb105f24 | 649 | serial_initialize(); |
fe8c2806 | 650 | |
9b998b0c | 651 | debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr); |
fe8c2806 | 652 | |
9b998b0c | 653 | WATCHDOG_RESET(); |
fe8c2806 | 654 | |
d025aa4b BB |
655 | /* |
656 | * Setup trap handlers | |
657 | */ | |
9b998b0c | 658 | trap_init(dest_addr); |
d025aa4b | 659 | |
c9315e6b | 660 | #ifdef CONFIG_ADDR_MAP |
ecf5b98c KG |
661 | init_addr_map(); |
662 | #endif | |
663 | ||
c837dcb1 | 664 | #if defined(CONFIG_BOARD_EARLY_INIT_R) |
9b998b0c | 665 | board_early_init_r(); |
c837dcb1 WD |
666 | #endif |
667 | ||
3b57fe0a | 668 | monitor_flash_len = (ulong)&__init_end - dest_addr; |
fe8c2806 | 669 | |
9b998b0c | 670 | WATCHDOG_RESET(); |
fe8c2806 | 671 | |
56f94be3 | 672 | #ifdef CONFIG_LOGBUFFER |
9b998b0c | 673 | logbuff_init_ptrs(); |
56f94be3 | 674 | #endif |
fe8c2806 | 675 | #ifdef CONFIG_POST |
9b998b0c | 676 | post_output_backlog(); |
fe8c2806 WD |
677 | #endif |
678 | ||
679 | WATCHDOG_RESET(); | |
680 | ||
1a2e203b | 681 | #if defined(CONFIG_SYS_DELAYED_ICACHE) |
9b998b0c | 682 | icache_enable(); /* it's time to enable the instruction cache */ |
fe8c2806 WD |
683 | #endif |
684 | ||
9c67352f WD |
685 | #if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500) |
686 | unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */ | |
42d1f039 WD |
687 | #endif |
688 | ||
76221a6c | 689 | #if defined(CONFIG_PCI) && defined(CONFIG_SYS_EARLY_PCI_INIT) |
fe8c2806 | 690 | /* |
76221a6c AS |
691 | * Do early PCI configuration _before_ the flash gets initialised, |
692 | * because PCU ressources are crucial for flash access on some boards. | |
fe8c2806 | 693 | */ |
9b998b0c | 694 | pci_init(); |
3bac3513 | 695 | #endif |
57d6c589 | 696 | #if defined(CONFIG_WINBOND_83C553) |
fe8c2806 WD |
697 | /* |
698 | * Initialise the ISA bridge | |
699 | */ | |
9b998b0c | 700 | initialise_w83c553f(); |
fe8c2806 WD |
701 | #endif |
702 | ||
9b998b0c | 703 | asm("sync ; isync"); |
fe8c2806 | 704 | |
9b998b0c | 705 | mem_malloc_init(malloc_start, TOTAL_MALLOC_LEN); |
c790b04d | 706 | |
6d0f6bcf | 707 | #if !defined(CONFIG_SYS_NO_FLASH) |
9b998b0c | 708 | puts("Flash: "); |
fe8c2806 | 709 | |
c62491d2 JS |
710 | if (board_flash_wp_on()) { |
711 | printf("Uninitialized - Write Protect On\n"); | |
712 | /* Since WP is on, we can't find real size. Set to 0 */ | |
713 | flash_size = 0; | |
9b998b0c WD |
714 | } else if ((flash_size = flash_init()) > 0) { |
715 | #ifdef CONFIG_SYS_FLASH_CHECKSUM | |
9b998b0c | 716 | print_size(flash_size, ""); |
fe8c2806 WD |
717 | /* |
718 | * Compute and print flash CRC if flashchecksum is set to 'y' | |
719 | * | |
720 | * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX | |
721 | */ | |
ec8a252c | 722 | if (getenv_yesno("flashchecksum") == 1) { |
9b998b0c WD |
723 | printf(" CRC: %08X", |
724 | crc32(0, | |
725 | (const unsigned char *) | |
726 | CONFIG_SYS_FLASH_BASE, flash_size) | |
727 | ); | |
fe8c2806 | 728 | } |
9b998b0c WD |
729 | putc('\n'); |
730 | #else /* !CONFIG_SYS_FLASH_CHECKSUM */ | |
731 | print_size(flash_size, "\n"); | |
732 | #endif /* CONFIG_SYS_FLASH_CHECKSUM */ | |
fe8c2806 | 733 | } else { |
9b998b0c WD |
734 | puts(failed); |
735 | hang(); | |
fe8c2806 WD |
736 | } |
737 | ||
9b998b0c WD |
738 | /* update start of FLASH memory */ |
739 | bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; | |
740 | /* size of FLASH memory (final value) */ | |
741 | bd->bi_flashsize = flash_size; | |
fa230445 | 742 | |
6d0f6bcf | 743 | #if defined(CONFIG_SYS_UPDATE_FLASH_SIZE) |
fa230445 | 744 | /* Make a update of the Memctrl. */ |
9b998b0c | 745 | update_flash_size(flash_size); |
fa230445 HS |
746 | #endif |
747 | ||
748 | ||
9b998b0c | 749 | #if defined(CONFIG_OXC) || defined(CONFIG_RMU) |
7e780369 | 750 | /* flash mapped at end of memory map */ |
14d0a02a | 751 | bd->bi_flashoffset = CONFIG_SYS_TEXT_BASE + flash_size; |
9b998b0c WD |
752 | #elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE |
753 | bd->bi_flashoffset = monitor_flash_len; /* reserved area for monitor */ | |
754 | #endif | |
6d0f6bcf | 755 | #endif /* !CONFIG_SYS_NO_FLASH */ |
fe8c2806 | 756 | |
9b998b0c | 757 | WATCHDOG_RESET(); |
fe8c2806 WD |
758 | |
759 | /* initialize higher level parts of CPU like time base and timers */ | |
9b998b0c | 760 | cpu_init_r(); |
fe8c2806 | 761 | |
9b998b0c | 762 | WATCHDOG_RESET(); |
fe8c2806 | 763 | |
fe8c2806 | 764 | #ifdef CONFIG_SPI |
9b998b0c WD |
765 | #if !defined(CONFIG_ENV_IS_IN_EEPROM) |
766 | spi_init_f(); | |
767 | #endif | |
768 | spi_init_r(); | |
fe8c2806 WD |
769 | #endif |
770 | ||
7def6b34 | 771 | #if defined(CONFIG_CMD_NAND) |
9b998b0c WD |
772 | WATCHDOG_RESET(); |
773 | puts("NAND: "); | |
887e2ec9 SR |
774 | nand_init(); /* go init the NAND */ |
775 | #endif | |
776 | ||
a8060359 TL |
777 | #ifdef CONFIG_GENERIC_MMC |
778 | /* | |
779 | * MMC initialization is called before relocating env. | |
780 | * Thus It is required that operations like pin multiplexer | |
781 | * be put in board_init. | |
782 | */ | |
9b998b0c WD |
783 | WATCHDOG_RESET(); |
784 | puts("MMC: "); | |
785 | mmc_initialize(bd); | |
a8060359 TL |
786 | #endif |
787 | ||
fe8c2806 | 788 | /* relocate environment function pointers etc. */ |
9b998b0c | 789 | env_relocate(); |
fe8c2806 | 790 | |
f9a33f1c KG |
791 | /* |
792 | * after non-volatile devices & environment is setup and cpu code have | |
793 | * another round to deal with any initialization that might require | |
794 | * full access to the environment or loading of some image (firmware) | |
795 | * from a non-volatile device | |
796 | */ | |
797 | cpu_secondary_init_r(); | |
798 | ||
fe8c2806 WD |
799 | /* |
800 | * Fill in missing fields of bd_info. | |
8bde7f77 WD |
801 | * We do this here, where we have "normal" access to the |
802 | * environment; we used to do this still running from ROM, | |
cdb74977 | 803 | * where had to use getenv_f(), which can be pretty slow when |
8bde7f77 | 804 | * the environment is in EEPROM. |
fe8c2806 | 805 | */ |
7abf0c58 | 806 | |
6d0f6bcf | 807 | #if defined(CONFIG_SYS_EXTBDINFO) |
7abf0c58 WD |
808 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) |
809 | #if defined(CONFIG_I2CFAST) | |
810 | /* | |
811 | * set bi_iic_fast for linux taking environment variable | |
812 | * "i2cfast" into account | |
813 | */ | |
814 | { | |
ec8a252c | 815 | if (getenv_yesno("i2cfast") == 1) { |
7abf0c58 WD |
816 | bd->bi_iic_fast[0] = 1; |
817 | bd->bi_iic_fast[1] = 1; | |
7abf0c58 WD |
818 | } |
819 | } | |
9b998b0c WD |
820 | #endif /* CONFIG_I2CFAST */ |
821 | #endif /* CONFIG_405GP, CONFIG_405EP */ | |
822 | #endif /* CONFIG_SYS_EXTBDINFO */ | |
7abf0c58 | 823 | |
9045f33c | 824 | #if defined(CONFIG_SC3) |
ca43ba18 HS |
825 | sc3_read_eeprom(); |
826 | #endif | |
d59feffb | 827 | |
9b998b0c | 828 | #if defined(CONFIG_ID_EEPROM) || defined(CONFIG_SYS_I2C_MAC_OFFSET) |
d59feffb HW |
829 | mac_read_from_eeprom(); |
830 | #endif | |
831 | ||
fe8c2806 WD |
832 | #ifdef CONFIG_HERMES |
833 | if ((gd->board_type >> 16) == 2) | |
834 | bd->bi_ethspeed = gd->board_type & 0xFFFF; | |
835 | else | |
836 | bd->bi_ethspeed = 0xFFFF; | |
837 | #endif | |
838 | ||
02a301cd | 839 | #ifdef CONFIG_CMD_NET |
eb85aa59 MF |
840 | /* kept around for legacy kernels only ... ignore the next section */ |
841 | eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr); | |
e2ffd59b | 842 | #ifdef CONFIG_HAS_ETH1 |
eb85aa59 | 843 | eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr); |
fe8c2806 | 844 | #endif |
e2ffd59b | 845 | #ifdef CONFIG_HAS_ETH2 |
eb85aa59 | 846 | eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr); |
fe8c2806 | 847 | #endif |
e2ffd59b | 848 | #ifdef CONFIG_HAS_ETH3 |
eb85aa59 | 849 | eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr); |
ba56f625 | 850 | #endif |
c68a05fe | 851 | #ifdef CONFIG_HAS_ETH4 |
eb85aa59 | 852 | eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr); |
c68a05fe | 853 | #endif |
c68a05fe | 854 | #ifdef CONFIG_HAS_ETH5 |
eb85aa59 | 855 | eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr); |
c68a05fe | 856 | #endif |
02a301cd | 857 | #endif /* CONFIG_CMD_NET */ |
c68a05fe | 858 | |
9b998b0c | 859 | WATCHDOG_RESET(); |
fe8c2806 | 860 | |
76221a6c | 861 | #if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) |
fe8c2806 WD |
862 | /* |
863 | * Do pci configuration | |
864 | */ | |
9b998b0c | 865 | pci_init(); |
fe8c2806 WD |
866 | #endif |
867 | ||
868 | /** leave this here (after malloc(), environment and PCI are working) **/ | |
52cb4d4f | 869 | /* Initialize stdio devices */ |
9b998b0c | 870 | stdio_init(); |
fe8c2806 | 871 | |
27b207fd | 872 | /* Initialize the jump table for applications */ |
9b998b0c | 873 | jumptable_init(); |
fe8c2806 | 874 | |
500856eb RJ |
875 | #if defined(CONFIG_API) |
876 | /* Initialize API */ | |
9b998b0c | 877 | api_init(); |
500856eb RJ |
878 | #endif |
879 | ||
fe8c2806 | 880 | /* Initialize the console (after the relocation and devices init) */ |
9b998b0c | 881 | console_init_r(); |
fe8c2806 | 882 | |
3a8f28d0 | 883 | #if defined(CONFIG_MISC_INIT_R) |
fe8c2806 | 884 | /* miscellaneous platform dependent initialisations */ |
9b998b0c | 885 | misc_init_r(); |
fe8c2806 WD |
886 | #endif |
887 | ||
888 | #ifdef CONFIG_HERMES | |
889 | if (bd->bi_ethspeed != 0xFFFF) | |
9b998b0c | 890 | hermes_start_lxt980((int) bd->bi_ethspeed); |
fe8c2806 WD |
891 | #endif |
892 | ||
7def6b34 | 893 | #if defined(CONFIG_CMD_KGDB) |
9b998b0c WD |
894 | WATCHDOG_RESET(); |
895 | puts("KGDB: "); | |
896 | kgdb_init(); | |
fe8c2806 WD |
897 | #endif |
898 | ||
9b998b0c | 899 | debug("U-Boot relocated to %08lx\n", dest_addr); |
fe8c2806 WD |
900 | |
901 | /* | |
902 | * Enable Interrupts | |
903 | */ | |
9b998b0c | 904 | interrupt_init(); |
fe8c2806 | 905 | |
566a494f | 906 | #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) |
9b998b0c | 907 | status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); |
fe8c2806 WD |
908 | #endif |
909 | ||
9b998b0c | 910 | udelay(20); |
fe8c2806 | 911 | |
fe8c2806 | 912 | /* Initialize from environment */ |
1272592e | 913 | load_addr = getenv_ulong("loadaddr", 16, load_addr); |
fe8c2806 | 914 | |
9b998b0c | 915 | WATCHDOG_RESET(); |
fe8c2806 | 916 | |
7def6b34 | 917 | #if defined(CONFIG_CMD_SCSI) |
9b998b0c WD |
918 | WATCHDOG_RESET(); |
919 | puts("SCSI: "); | |
920 | scsi_init(); | |
fe8c2806 WD |
921 | #endif |
922 | ||
7def6b34 | 923 | #if defined(CONFIG_CMD_DOC) |
9b998b0c WD |
924 | WATCHDOG_RESET(); |
925 | puts("DOC: "); | |
926 | doc_init(); | |
fe8c2806 WD |
927 | #endif |
928 | ||
310cecb8 LCM |
929 | #ifdef CONFIG_BITBANGMII |
930 | bb_miiphy_init(); | |
931 | #endif | |
7def6b34 | 932 | #if defined(CONFIG_CMD_NET) |
9b998b0c WD |
933 | WATCHDOG_RESET(); |
934 | puts("Net: "); | |
935 | eth_initialize(bd); | |
fe8c2806 WD |
936 | #endif |
937 | ||
004eca0c | 938 | #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) |
9b998b0c WD |
939 | WATCHDOG_RESET(); |
940 | debug("Reset Ethernet PHY\n"); | |
941 | reset_phy(); | |
63ff004c MB |
942 | #endif |
943 | ||
fe8c2806 | 944 | #ifdef CONFIG_POST |
9b998b0c | 945 | post_run(NULL, POST_RAM | post_bootmode_get(0)); |
fe8c2806 WD |
946 | #endif |
947 | ||
7def6b34 JL |
948 | #if defined(CONFIG_CMD_PCMCIA) \ |
949 | && !defined(CONFIG_CMD_IDE) | |
9b998b0c WD |
950 | WATCHDOG_RESET(); |
951 | puts("PCMCIA:"); | |
952 | pcmcia_init(); | |
fe8c2806 WD |
953 | #endif |
954 | ||
7def6b34 | 955 | #if defined(CONFIG_CMD_IDE) |
9b998b0c WD |
956 | WATCHDOG_RESET(); |
957 | #ifdef CONFIG_IDE_8xx_PCCARD | |
958 | puts("PCMCIA:"); | |
959 | #else | |
960 | puts("IDE: "); | |
fe8c2806 | 961 | #endif |
ca43ba18 HS |
962 | #if defined(CONFIG_START_IDE) |
963 | if (board_start_ide()) | |
9b998b0c | 964 | ide_init(); |
ca43ba18 | 965 | #else |
9b998b0c | 966 | ide_init(); |
ca43ba18 | 967 | #endif |
b3aff0cb | 968 | #endif |
fe8c2806 WD |
969 | |
970 | #ifdef CONFIG_LAST_STAGE_INIT | |
9b998b0c | 971 | WATCHDOG_RESET(); |
fe8c2806 WD |
972 | /* |
973 | * Some parts can be only initialized if all others (like | |
974 | * Interrupts) are up and running (i.e. the PC-style ISA | |
975 | * keyboard). | |
976 | */ | |
9b998b0c | 977 | last_stage_init(); |
fe8c2806 WD |
978 | #endif |
979 | ||
7def6b34 | 980 | #if defined(CONFIG_CMD_BEDBUG) |
9b998b0c WD |
981 | WATCHDOG_RESET(); |
982 | bedbug_init(); | |
fe8c2806 WD |
983 | #endif |
984 | ||
228f29ac | 985 | #if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) |
fe8c2806 WD |
986 | /* |
987 | * Export available size of memory for Linux, | |
988 | * taking into account the protected RAM at top of memory | |
989 | */ | |
990 | { | |
1272592e | 991 | ulong pram = 0; |
d01b1761 | 992 | char memsz[32]; |
fe8c2806 | 993 | |
1272592e SG |
994 | #ifdef CONFIG_PRAM |
995 | pram = getenv_ulong("pram", 10, CONFIG_PRAM); | |
228f29ac WD |
996 | #endif |
997 | #ifdef CONFIG_LOGBUFFER | |
3d610186 | 998 | #ifndef CONFIG_ALT_LB_ADDR |
228f29ac | 999 | /* Also take the logbuffer into account (pram is in kB) */ |
9b998b0c | 1000 | pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024; |
3d610186 | 1001 | #endif |
228f29ac | 1002 | #endif |
d01b1761 SG |
1003 | sprintf(memsz, "%ldk", (bd->bi_memsize / 1024) - pram); |
1004 | setenv("mem", memsz); | |
fe8c2806 WD |
1005 | } |
1006 | #endif | |
1007 | ||
1c43771b | 1008 | #ifdef CONFIG_PS2KBD |
9b998b0c | 1009 | puts("PS/2: "); |
1c43771b WD |
1010 | kbd_init(); |
1011 | #endif | |
1012 | ||
4532cb69 | 1013 | #ifdef CONFIG_MODEM_SUPPORT |
9b998b0c WD |
1014 | { |
1015 | extern int do_mdm_init; | |
1016 | ||
1017 | do_mdm_init = gd->do_mdm_init; | |
1018 | } | |
4532cb69 WD |
1019 | #endif |
1020 | ||
fe8c2806 WD |
1021 | /* Initialization complete - start the monitor */ |
1022 | ||
1023 | /* main_loop() can return to retry autoboot, if so just run it again. */ | |
1024 | for (;;) { | |
9b998b0c WD |
1025 | WATCHDOG_RESET(); |
1026 | main_loop(); | |
fe8c2806 WD |
1027 | } |
1028 | ||
1029 | /* NOTREACHED - no way out of command loop except booting */ | |
1030 | } | |
1031 | ||
9b998b0c | 1032 | #if 0 /* We could use plain global data, but the resulting code is bigger */ |
fe8c2806 WD |
1033 | /* |
1034 | * Pointer to initial global data area | |
1035 | * | |
1036 | * Here we initialize it. | |
1037 | */ | |
1038 | #undef XTRN_DECLARE_GLOBAL_DATA_PTR | |
1039 | #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */ | |
9b998b0c WD |
1040 | DECLARE_GLOBAL_DATA_PTR = |
1041 | (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); | |
1042 | #endif /* 0 */ | |
fe8c2806 WD |
1043 | |
1044 | /************************************************************************/ |