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Consolidate arch-specific sbrk() implementations
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fe8c2806 1/*
4707fb50 2 * (C) Copyright 2000-2006
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3 * Wolfgang Denk, DENX Software Engineering, [email protected].
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <watchdog.h>
26#include <command.h>
27#include <malloc.h>
52cb4d4f 28#include <stdio_dev.h>
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29#ifdef CONFIG_8xx
30#include <mpc8xx.h>
31#endif
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32#ifdef CONFIG_5xx
33#include <mpc5xx.h>
34#endif
cbd8a35c 35#ifdef CONFIG_MPC5xxx
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36#include <mpc5xxx.h>
37#endif
7def6b34 38#if defined(CONFIG_CMD_IDE)
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39#include <ide.h>
40#endif
7def6b34 41#if defined(CONFIG_CMD_SCSI)
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42#include <scsi.h>
43#endif
7def6b34 44#if defined(CONFIG_CMD_KGDB)
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45#include <kgdb.h>
46#endif
47#ifdef CONFIG_STATUS_LED
48#include <status_led.h>
49#endif
50#include <net.h>
272cc70b
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51#ifdef CONFIG_GENERIC_MMC
52#include <mmc.h>
53#endif
281e00a3 54#include <serial.h>
6d0f6bcf 55#ifdef CONFIG_SYS_ALLOC_DPRAM
9c4c5ae3 56#if !defined(CONFIG_CPM2)
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57#include <commproc.h>
58#endif
7aa78614 59#endif
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60#include <version.h>
61#if defined(CONFIG_BAB7xx)
62#include <w83c553f.h>
63#endif
64#include <dtt.h>
65#if defined(CONFIG_POST)
66#include <post.h>
67#endif
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68#if defined(CONFIG_LOGBUFFER)
69#include <logbuff.h>
70#endif
9c67352f 71#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
42d1f039
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72#include <asm/cache.h>
73#endif
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74#ifdef CONFIG_PS2KBD
75#include <keyboard.h>
76#endif
fe8c2806 77
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78#ifdef CONFIG_ADDR_MAP
79#include <asm/mmu.h>
80#endif
81
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82#ifdef CONFIG_MP
83#include <asm/mp.h>
84#endif
85
6d0f6bcf 86#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
fa230445
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87extern int update_flash_size (int flash_size);
88#endif
89
9045f33c 90#if defined(CONFIG_SC3)
ca43ba18
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91extern void sc3_read_eeprom(void);
92#endif
93
7def6b34 94#if defined(CONFIG_CMD_DOC)
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95void doc_init (void);
96#endif
97#if defined(CONFIG_HARD_I2C) || \
98 defined(CONFIG_SOFT_I2C)
99#include <i2c.h>
100#endif
04a9e118 101#include <spi.h>
d6ac2ed8 102#include <nand.h>
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103
104static char *failed = "*** failed ***\n";
105
17d704eb 106#if defined(CONFIG_OXC) || defined(CONFIG_PCU_E) || defined(CONFIG_RMU)
fe8c2806 107extern flash_info_t flash_info[];
17d704eb 108#endif
fe8c2806 109
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110#if defined(CONFIG_START_IDE)
111extern int board_start_ide(void);
112#endif
fe8c2806 113#include <environment.h>
d87080b7 114
bce84c4d 115DECLARE_GLOBAL_DATA_PTR;
fe8c2806 116
0e8d1586 117#if defined(CONFIG_ENV_IS_EMBEDDED)
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118#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
119#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
120 (CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \
9314cee6 121 defined(CONFIG_ENV_IS_IN_NVRAM)
6d0f6bcf 122#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
fe8c2806 123#else
6d0f6bcf 124#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN
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125#endif
126
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127#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
128#define CONFIG_SYS_MEM_TOP_HIDE 0
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129#endif
130
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131extern ulong __init_end;
132extern ulong _end;
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133ulong monitor_flash_len;
134
7def6b34 135#if defined(CONFIG_CMD_BEDBUG)
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136#include <bedbug/type.h>
137#endif
138
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139/************************************************************************
140 * Utilities *
141 ************************************************************************
142 */
143
144/*
145 * The Malloc area is immediately below the monitor copy in DRAM
146 */
147static void mem_malloc_init (void)
148{
e9514751 149#if !defined(CONFIG_RELOC_FIXUP_WORKS)
6d0f6bcf 150 mem_malloc_end = CONFIG_SYS_MONITOR_BASE + gd->reloc_off;
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151#endif
152 mem_malloc_start = mem_malloc_end - TOTAL_MALLOC_LEN;
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153 mem_malloc_brk = mem_malloc_start;
154
155 memset ((void *) mem_malloc_start,
156 0,
157 mem_malloc_end - mem_malloc_start);
158}
159
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160/*
161 * All attempts to come up with a "common" initialization sequence
162 * that works for all boards and architectures failed: some of the
163 * requirements are just _too_ different. To get rid of the resulting
164 * mess of board dependend #ifdef'ed code we now make the whole
165 * initialization sequence configurable to the user.
166 *
167 * The requirements for any new initalization function is simple: it
168 * receives a pointer to the "global data" structure as it's only
169 * argument, and returns an integer return code, where 0 means
170 * "continue" and != 0 means "fatal error, hang the system".
171 */
172typedef int (init_fnc_t) (void);
173
174/************************************************************************
175 * Init Utilities *
176 ************************************************************************
177 * Some of this code should be moved into the core functions,
178 * but let's get it working (again) first...
179 */
180
181static int init_baudrate (void)
182{
77ddac94 183 char tmp[64]; /* long enough for environment variables */
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184 int i = getenv_r ("baudrate", tmp, sizeof (tmp));
185
186 gd->baudrate = (i > 0)
187 ? (int) simple_strtoul (tmp, NULL, 10)
188 : CONFIG_BAUDRATE;
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189 return (0);
190}
191
192/***********************************************************************/
193
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194void __board_add_ram_info(int use_default)
195{
196 /* please define platform specific board_add_ram_info() */
197}
198void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
199
d96f41e0 200
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201static int init_func_ram (void)
202{
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203#ifdef CONFIG_BOARD_TYPES
204 int board_type = gd->board_type;
205#else
206 int board_type = 0; /* use dummy arg */
207#endif
208 puts ("DRAM: ");
209
210 if ((gd->ram_size = initdram (board_type)) > 0) {
d96f41e0 211 print_size (gd->ram_size, "");
d96f41e0 212 board_add_ram_info(0);
d96f41e0 213 putc('\n');
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214 return (0);
215 }
216 puts (failed);
217 return (1);
218}
219
220/***********************************************************************/
221
222#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
223static int init_func_i2c (void)
224{
225 puts ("I2C: ");
6d0f6bcf 226 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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227 puts ("ready\n");
228 return (0);
229}
230#endif
231
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232#if defined(CONFIG_HARD_SPI)
233static int init_func_spi (void)
234{
235 puts ("SPI: ");
236 spi_init ();
237 puts ("ready\n");
238 return (0);
239}
240#endif
241
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242/***********************************************************************/
243
244#if defined(CONFIG_WATCHDOG)
245static int init_func_watchdog_init (void)
246{
247 puts (" Watchdog enabled\n");
248 WATCHDOG_RESET ();
249 return (0);
250}
251# define INIT_FUNC_WATCHDOG_INIT init_func_watchdog_init,
252
253static int init_func_watchdog_reset (void)
254{
255 WATCHDOG_RESET ();
256 return (0);
257}
258# define INIT_FUNC_WATCHDOG_RESET init_func_watchdog_reset,
259#else
260# define INIT_FUNC_WATCHDOG_INIT /* undef */
261# define INIT_FUNC_WATCHDOG_RESET /* undef */
262#endif /* CONFIG_WATCHDOG */
263
264/************************************************************************
265 * Initialization sequence *
266 ************************************************************************
267 */
268
269init_fnc_t *init_sequence[] = {
270
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271#if defined(CONFIG_BOARD_EARLY_INIT_F)
272 board_early_init_f,
fe8c2806 273#endif
c178d3da 274
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275#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
276 probecpu,
277#endif
66ca92a5 278#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
fe8c2806 279 get_clocks, /* get CPU and bus clocks (etc.) */
090eb735
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280#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
281 && !defined(CONFIG_TQM885D)
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282 adjust_sdram_tbs_8xx,
283#endif
fe8c2806 284 init_timebase,
c178d3da 285#endif
6d0f6bcf 286#ifdef CONFIG_SYS_ALLOC_DPRAM
9c4c5ae3 287#if !defined(CONFIG_CPM2)
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288 dpram_init,
289#endif
7aa78614 290#endif
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291#if defined(CONFIG_BOARD_POSTCLK_INIT)
292 board_postclk_init,
293#endif
294 env_init,
66ca92a5 295#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
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WD
296 get_clocks_866, /* get CPU and bus clocks according to the environment variable */
297 sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
298 init_timebase,
299#endif
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300 init_baudrate,
301 serial_init,
302 console_init_f,
303 display_options,
304#if defined(CONFIG_8260)
305 prt_8260_rsr,
306 prt_8260_clks,
307#endif /* CONFIG_8260 */
0f898604 308#if defined(CONFIG_MPC83xx)
9be39a67
DL
309 prt_83xx_rsr,
310#endif
fe8c2806 311 checkcpu,
cbd8a35c 312#if defined(CONFIG_MPC5xxx)
945af8d7 313 prt_mpc5xxx_clks,
cbd8a35c 314#endif /* CONFIG_MPC5xxx */
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315#if defined(CONFIG_MPC8220)
316 prt_mpc8220_clks,
317#endif
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318 checkboard,
319 INIT_FUNC_WATCHDOG_INIT
c837dcb1 320#if defined(CONFIG_MISC_INIT_F)
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321 misc_init_f,
322#endif
323 INIT_FUNC_WATCHDOG_RESET
324#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
325 init_func_i2c,
326#endif
04a9e118
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327#if defined(CONFIG_HARD_SPI)
328 init_func_spi,
329#endif
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330#ifdef CONFIG_POST
331 post_init_f,
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332#endif
333 INIT_FUNC_WATCHDOG_RESET
334 init_func_ram,
6d0f6bcf 335#if defined(CONFIG_SYS_DRAM_TEST)
fe8c2806 336 testdram,
6d0f6bcf 337#endif /* CONFIG_SYS_DRAM_TEST */
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338 INIT_FUNC_WATCHDOG_RESET
339
340 NULL, /* Terminate this list */
341};
342
81d93e5c
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343ulong get_effective_memsize(void)
344{
345#ifndef CONFIG_VERY_BIG_RAM
346 return gd->ram_size;
347#else
348 /* limit stack to what we can reasonable map */
349 return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
350 CONFIG_MAX_MEM_MAPPED : gd->ram_size);
351#endif
352}
353
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354/************************************************************************
355 *
356 * This is the first part of the initialization sequence that is
357 * implemented in C, but still running from ROM.
358 *
359 * The main purpose is to provide a (serial) console interface as
360 * soon as possible (so we can see any error messages), and to
361 * initialize the RAM so that we can relocate the monitor code to
362 * RAM.
363 *
364 * Be aware of the restrictions: global data is read-only, BSS is not
365 * initialized, and stack space is limited to a few kB.
366 *
367 ************************************************************************
368 */
369
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370#ifdef CONFIG_LOGBUFFER
371unsigned long logbuffer_base(void)
372{
6d0f6bcf 373 return CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - LOGBUFF_LEN;
95d449ad
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374}
375#endif
376
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377void board_init_f (ulong bootflag)
378{
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379 bd_t *bd;
380 ulong len, addr, addr_sp;
7bc5ee07 381 ulong *s;
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382 gd_t *id;
383 init_fnc_t **init_fnc_ptr;
384#ifdef CONFIG_PRAM
385 int i;
386 ulong reg;
387 uchar tmp[64]; /* long enough for environment variables */
388#endif
389
390 /* Pointer is writable since we allocated a register for it */
6d0f6bcf 391 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
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392 /* compiler optimization barrier needed for GCC >= 3.4 */
393 __asm__ __volatile__("": : :"memory");
fe8c2806 394
0f898604 395#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83xx) && \
f060054d 396 !defined(CONFIG_MPC85xx) && !defined(CONFIG_MPC86xx)
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397 /* Clear initial global data */
398 memset ((void *) gd, 0, sizeof (gd_t));
399#endif
400
401 for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
402 if ((*init_fnc_ptr) () != 0) {
403 hang ();
404 }
405 }
406
407 /*
408 * Now that we have DRAM mapped and working, we can
409 * relocate the code and continue running from DRAM.
410 *
411 * Reserve memory at end of RAM for (top down in that order):
14f73ca6 412 * - area that won't get touched by U-Boot and Linux (optional)
8bde7f77 413 * - kernel log buffer
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414 * - protected RAM
415 * - LCD framebuffer
416 * - monitor code
417 * - board info struct
418 */
6d0f6bcf 419 len = (ulong)&_end - CONFIG_SYS_MONITOR_BASE;
fe8c2806 420
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SR
421 /*
422 * Subtract specified amount of memory to hide so that it won't
423 * get "touched" at all by U-Boot. By fixing up gd->ram_size
424 * the Linux kernel should now get passed the now "corrected"
425 * memory size and won't touch it either. This should work
426 * for arch/ppc and arch/powerpc. Only Linux board ports in
427 * arch/powerpc with bootwrapper support, that recalculate the
428 * memory size from the SDRAM controller setup will have to
429 * get fixed.
430 */
6d0f6bcf 431 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
14f73ca6 432
6d0f6bcf 433 addr = CONFIG_SYS_SDRAM_BASE + get_effective_memsize();
fe8c2806 434
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435#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
436 /*
437 * We need to make sure the location we intend to put secondary core
438 * boot code is reserved and not used by any part of u-boot
c0a14aed 439 */
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KG
440 if (addr > determine_mp_bootpg()) {
441 addr = determine_mp_bootpg();
442 debug ("Reserving MP boot page to %08lx\n", addr);
443 }
444#endif
445
228f29ac 446#ifdef CONFIG_LOGBUFFER
3d610186 447#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
448 /* reserve kernel log buffer */
449 addr -= (LOGBUFF_RESERVE);
9d2b18a0 450 debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr);
228f29ac 451#endif
3d610186 452#endif
228f29ac 453
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454#ifdef CONFIG_PRAM
455 /*
456 * reserve protected RAM
457 */
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458 i = getenv_r ("pram", (char *)tmp, sizeof (tmp));
459 reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM;
fe8c2806 460 addr -= (reg << 10); /* size is in kB */
9d2b18a0 461 debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
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WD
462#endif /* CONFIG_PRAM */
463
464 /* round down to next 4 kB limit */
465 addr &= ~(4096 - 1);
9d2b18a0 466 debug ("Top of RAM usable for U-Boot at: %08lx\n", addr);
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467
468#ifdef CONFIG_LCD
469 /* reserve memory for LCD display (always full pages) */
470 addr = lcd_setmem (addr);
471 gd->fb_base = addr;
472#endif /* CONFIG_LCD */
473
474#if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
475 /* reserve memory for video display (always full pages) */
476 addr = video_setmem (addr);
477 gd->fb_base = addr;
478#endif /* CONFIG_VIDEO */
479
480 /*
481 * reserve memory for U-Boot code, data & bss
682011ff 482 * round down to next 4 kB limit
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483 */
484 addr -= len;
682011ff 485 addr &= ~(4096 - 1);
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486#ifdef CONFIG_E500
487 /* round down to next 64 kB limit so that IVPR stays aligned */
488 addr &= ~(65536 - 1);
489#endif
fe8c2806 490
9d2b18a0 491 debug ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
fe8c2806 492
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493#ifdef CONFIG_AMIGAONEG3SE
494 gd->relocaddr = addr;
495#endif
496
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497 /*
498 * reserve memory for malloc() arena
499 */
500 addr_sp = addr - TOTAL_MALLOC_LEN;
9d2b18a0 501 debug ("Reserving %dk for malloc() at: %08lx\n",
fe8c2806 502 TOTAL_MALLOC_LEN >> 10, addr_sp);
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503
504 /*
505 * (permanently) allocate a Board Info struct
506 * and a permanent copy of the "global" data
507 */
508 addr_sp -= sizeof (bd_t);
509 bd = (bd_t *) addr_sp;
510 gd->bd = bd;
b64f190b 511 debug ("Reserving %zu Bytes for Board Info at: %08lx\n",
fe8c2806 512 sizeof (bd_t), addr_sp);
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513 addr_sp -= sizeof (gd_t);
514 id = (gd_t *) addr_sp;
b64f190b 515 debug ("Reserving %zu Bytes for Global Data at: %08lx\n",
fe8c2806 516 sizeof (gd_t), addr_sp);
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WD
517
518 /*
519 * Finally, we set up a new (bigger) stack.
520 *
521 * Leave some safety gap for SP, force alignment on 16 byte boundary
522 * Clear initial stack frame
523 */
524 addr_sp -= 16;
525 addr_sp &= ~0xF;
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WD
526 s = (ulong *)addr_sp;
527 *s-- = 0;
528 *s-- = 0;
529 addr_sp = (ulong)s;
9d2b18a0 530 debug ("Stack Pointer at: %08lx\n", addr_sp);
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531
532 /*
533 * Save local variables to board info struct
534 */
535
6d0f6bcf 536 bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */
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537 bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */
538
539#ifdef CONFIG_IP860
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540 bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */
541 bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */
983fda83 542#elif defined CONFIG_MPC8220
6d0f6bcf
JCPV
543 bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM memory */
544 bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM memory */
fe8c2806 545#else
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546 bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */
547 bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */
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548#endif
549
42d1f039 550#if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \
debb7354 551 defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
6d0f6bcf 552 bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
fe8c2806 553#endif
cbd8a35c 554#if defined(CONFIG_MPC5xxx)
6d0f6bcf 555 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
945af8d7 556#endif
0f898604 557#if defined(CONFIG_MPC83xx)
6d0f6bcf 558 bd->bi_immrbar = CONFIG_SYS_IMMR;
f046ccd1 559#endif
983fda83 560#if defined(CONFIG_MPC8220)
6d0f6bcf 561 bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
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WD
562 bd->bi_inpfreq = gd->inp_clk;
563 bd->bi_pcifreq = gd->pci_clk;
564 bd->bi_vcofreq = gd->vco_clk;
565 bd->bi_pevfreq = gd->pev_clk;
566 bd->bi_flbfreq = gd->flb_clk;
567
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WD
568 /* store bootparam to sram (backward compatible), here? */
569 {
6d0f6bcf 570 u32 *sram = (u32 *)CONFIG_SYS_SRAM_BASE;
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WD
571 *sram++ = gd->ram_size;
572 *sram++ = gd->bus_clk;
573 *sram++ = gd->inp_clk;
574 *sram++ = gd->cpu_clk;
575 *sram++ = gd->vco_clk;
576 *sram++ = gd->flb_clk;
577 *sram++ = 0xb8c3ba11; /* boot signature */
578 }
983fda83 579#endif
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WD
580
581 bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */
582
583 WATCHDOG_RESET ();
584 bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
585 bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
9c4c5ae3 586#if defined(CONFIG_CPM2)
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587 bd->bi_cpmfreq = gd->cpm_clk;
588 bd->bi_brgfreq = gd->brg_clk;
589 bd->bi_sccfreq = gd->scc_clk;
590 bd->bi_vco = gd->vco_out;
9c4c5ae3 591#endif /* CONFIG_CPM2 */
281ff9a4 592#if defined(CONFIG_MPC512X)
5d49e0e1 593 bd->bi_ipsfreq = gd->ips_clk;
281ff9a4 594#endif /* CONFIG_MPC512X */
cbd8a35c 595#if defined(CONFIG_MPC5xxx)
945af8d7
WD
596 bd->bi_ipbfreq = gd->ipb_clk;
597 bd->bi_pcifreq = gd->pci_clk;
cbd8a35c 598#endif /* CONFIG_MPC5xxx */
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WD
599 bd->bi_baudrate = gd->baudrate; /* Console Baudrate */
600
6d0f6bcf 601#ifdef CONFIG_SYS_EXTBDINFO
77ddac94
WD
602 strncpy ((char *)bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
603 strncpy ((char *)bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
fe8c2806
WD
604
605 bd->bi_procfreq = gd->cpu_clk; /* Processor Speed, In Hz */
606 bd->bi_plb_busfreq = gd->bus_clk;
343c48bd
SR
607#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
608 defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
609 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
fe8c2806 610 bd->bi_pci_busfreq = get_PCI_freq ();
109c0e3a 611 bd->bi_opbfreq = get_OPB_freq ();
9fea65a6 612#elif defined(CONFIG_XILINX_405)
028ab6b5 613 bd->bi_pci_busfreq = get_PCI_freq ();
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WD
614#endif
615#endif
616
9d2b18a0 617 debug ("New Stack Pointer is: %08lx\n", addr_sp);
fe8c2806
WD
618
619 WATCHDOG_RESET ();
620
621#ifdef CONFIG_POST
622 post_bootmode_init();
6dff5529 623 post_run (NULL, POST_ROM | post_bootmode_get(0));
fe8c2806
WD
624#endif
625
626 WATCHDOG_RESET();
627
27b207fd 628 memcpy (id, (void *)gd, sizeof (gd_t));
fe8c2806
WD
629
630 relocate_code (addr_sp, id, addr);
631
632 /* NOTREACHED - relocate_code() does not return */
633}
634
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WD
635/************************************************************************
636 *
637 * This is the next part if the initialization sequence: we are now
638 * running from RAM and have a "normal" C environment, i. e. global
639 * data can be written, BSS has been cleared, the stack size in not
640 * that critical any more, etc.
641 *
642 ************************************************************************
643 */
fe8c2806
WD
644void board_init_r (gd_t *id, ulong dest_addr)
645{
fe8c2806 646 cmd_tbl_t *cmdtp;
ff7dc067 647 char *s;
fe8c2806 648 bd_t *bd;
fe8c2806 649 extern void malloc_bin_reloc (void);
93f6d725 650#ifndef CONFIG_ENV_IS_NOWHERE
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WD
651 extern char * env_name_spec;
652#endif
653
6d0f6bcf 654#ifndef CONFIG_SYS_NO_FLASH
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WD
655 ulong flash_size;
656#endif
657
658 gd = id; /* initialize RAM version of global data */
659 bd = gd->bd;
660
661 gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
f82b3b63
GL
662
663#if defined(CONFIG_RELOC_FIXUP_WORKS)
664 gd->reloc_off = 0;
e9514751 665 mem_malloc_end = dest_addr;
f82b3b63 666#else
6d0f6bcf 667 gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
f82b3b63 668#endif
bb105f24
MB
669
670#ifdef CONFIG_SERIAL_MULTI
671 serial_initialize();
672#endif
fe8c2806 673
9d2b18a0 674 debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
fe8c2806
WD
675
676 WATCHDOG_RESET ();
677
d025aa4b
BB
678 /*
679 * Setup trap handlers
680 */
681 trap_init (dest_addr);
682
c9315e6b 683#ifdef CONFIG_ADDR_MAP
ecf5b98c
KG
684 init_addr_map();
685#endif
686
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WD
687#if defined(CONFIG_BOARD_EARLY_INIT_R)
688 board_early_init_r ();
689#endif
690
3b57fe0a 691 monitor_flash_len = (ulong)&__init_end - dest_addr;
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WD
692
693 /*
694 * We have to relocate the command table manually
695 */
8bde7f77 696 for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
fe8c2806 697 ulong addr;
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WD
698 addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
699#if 0
700 printf ("Command \"%s\": 0x%08lx => 0x%08lx\n",
701 cmdtp->name, (ulong) (cmdtp->cmd), addr);
702#endif
703 cmdtp->cmd =
704 (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
705
706 addr = (ulong)(cmdtp->name) + gd->reloc_off;
707 cmdtp->name = (char *)addr;
708
709 if (cmdtp->usage) {
710 addr = (ulong)(cmdtp->usage) + gd->reloc_off;
711 cmdtp->usage = (char *)addr;
712 }
6d0f6bcf 713#ifdef CONFIG_SYS_LONGHELP
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WD
714 if (cmdtp->help) {
715 addr = (ulong)(cmdtp->help) + gd->reloc_off;
716 cmdtp->help = (char *)addr;
717 }
718#endif
719 }
720 /* there are some other pointer constants we must deal with */
93f6d725 721#ifndef CONFIG_ENV_IS_NOWHERE
fe8c2806
WD
722 env_name_spec += gd->reloc_off;
723#endif
724
725 WATCHDOG_RESET ();
726
56f94be3 727#ifdef CONFIG_LOGBUFFER
228f29ac 728 logbuff_init_ptrs ();
56f94be3 729#endif
fe8c2806 730#ifdef CONFIG_POST
228f29ac 731 post_output_backlog ();
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WD
732 post_reloc ();
733#endif
734
735 WATCHDOG_RESET();
736
0f898604 737#if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83xx)
fe8c2806
WD
738 icache_enable (); /* it's time to enable the instruction cache */
739#endif
740
9c67352f
WD
741#if defined(CONFIG_SYS_INIT_RAM_LOCK) && defined(CONFIG_E500)
742 unlock_ram_in_cache(); /* it's time to unlock D-cache in e500 */
42d1f039
WD
743#endif
744
3bac3513 745#if defined(CONFIG_BAB7xx) || defined(CONFIG_CPC45)
fe8c2806 746 /*
3bac3513
WD
747 * Do PCI configuration on BAB7xx and CPC45 _before_ the flash
748 * gets initialised, because we need the ISA resp. PCI_to_LOCAL bus
749 * bridge there.
fe8c2806
WD
750 */
751 pci_init ();
3bac3513
WD
752#endif
753#if defined(CONFIG_BAB7xx)
fe8c2806
WD
754 /*
755 * Initialise the ISA bridge
756 */
757 initialise_w83c553f ();
758#endif
759
760 asm ("sync ; isync");
761
c790b04d
SR
762 /* initialize malloc() area */
763 mem_malloc_init ();
764 malloc_bin_reloc ();
765
6d0f6bcf 766#if !defined(CONFIG_SYS_NO_FLASH)
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WD
767 puts ("FLASH: ");
768
769 if ((flash_size = flash_init ()) > 0) {
6d0f6bcf 770# ifdef CONFIG_SYS_FLASH_CHECKSUM
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WD
771 print_size (flash_size, "");
772 /*
773 * Compute and print flash CRC if flashchecksum is set to 'y'
774 *
775 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
776 */
777 s = getenv ("flashchecksum");
778 if (s && (*s == 'y')) {
06c53bea 779 printf (" CRC: %08X",
6d0f6bcf 780 crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size)
7e780369 781 );
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WD
782 }
783 putc ('\n');
6d0f6bcf 784# else /* !CONFIG_SYS_FLASH_CHECKSUM */
fe8c2806 785 print_size (flash_size, "\n");
6d0f6bcf 786# endif /* CONFIG_SYS_FLASH_CHECKSUM */
fe8c2806
WD
787 } else {
788 puts (failed);
789 hang ();
790 }
791
6d0f6bcf 792 bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; /* update start of FLASH memory */
fe8c2806 793 bd->bi_flashsize = flash_size; /* size of FLASH memory (final value) */
fa230445 794
6d0f6bcf 795#if defined(CONFIG_SYS_UPDATE_FLASH_SIZE)
fa230445
HS
796 /* Make a update of the Memctrl. */
797 update_flash_size (flash_size);
798#endif
799
800
7e780369
WD
801# if defined(CONFIG_PCU_E) || defined(CONFIG_OXC) || defined(CONFIG_RMU)
802 /* flash mapped at end of memory map */
803 bd->bi_flashoffset = TEXT_BASE + flash_size;
6d0f6bcf 804# elif CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
3b57fe0a 805 bd->bi_flashoffset = monitor_flash_len; /* reserved area for startup monitor */
0cb61d7d 806# else
fe8c2806 807 bd->bi_flashoffset = 0;
0cb61d7d 808# endif
6d0f6bcf 809#else /* CONFIG_SYS_NO_FLASH */
fe8c2806
WD
810
811 bd->bi_flashsize = 0;
812 bd->bi_flashstart = 0;
813 bd->bi_flashoffset = 0;
6d0f6bcf 814#endif /* !CONFIG_SYS_NO_FLASH */
fe8c2806
WD
815
816 WATCHDOG_RESET ();
817
818 /* initialize higher level parts of CPU like time base and timers */
819 cpu_init_r ();
820
821 WATCHDOG_RESET ();
822
fe8c2806 823#ifdef CONFIG_SPI
bb1f8b4f 824# if !defined(CONFIG_ENV_IS_IN_EEPROM)
fe8c2806
WD
825 spi_init_f ();
826# endif
827 spi_init_r ();
828#endif
829
7def6b34 830#if defined(CONFIG_CMD_NAND)
887e2ec9
SR
831 WATCHDOG_RESET ();
832 puts ("NAND: ");
833 nand_init(); /* go init the NAND */
834#endif
835
fe8c2806
WD
836 /* relocate environment function pointers etc. */
837 env_relocate ();
838
839 /*
840 * Fill in missing fields of bd_info.
8bde7f77
WD
841 * We do this here, where we have "normal" access to the
842 * environment; we used to do this still running from ROM,
843 * where had to use getenv_r(), which can be pretty slow when
844 * the environment is in EEPROM.
fe8c2806 845 */
7abf0c58 846
6d0f6bcf 847#if defined(CONFIG_SYS_EXTBDINFO)
7abf0c58
WD
848#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
849#if defined(CONFIG_I2CFAST)
850 /*
851 * set bi_iic_fast for linux taking environment variable
852 * "i2cfast" into account
853 */
854 {
855 char *s = getenv ("i2cfast");
856 if (s && ((*s == 'y') || (*s == 'Y'))) {
857 bd->bi_iic_fast[0] = 1;
858 bd->bi_iic_fast[1] = 1;
859 } else {
860 bd->bi_iic_fast[0] = 0;
861 bd->bi_iic_fast[1] = 0;
862 }
863 }
864#else
865 bd->bi_iic_fast[0] = 0;
866 bd->bi_iic_fast[1] = 0;
867#endif /* CONFIG_I2CFAST */
868#endif /* CONFIG_405GP, CONFIG_405EP */
6d0f6bcf 869#endif /* CONFIG_SYS_EXTBDINFO */
7abf0c58 870
9045f33c 871#if defined(CONFIG_SC3)
ca43ba18
HS
872 sc3_read_eeprom();
873#endif
d59feffb 874
6d0f6bcf 875#if defined (CONFIG_ID_EEPROM) || defined (CONFIG_SYS_I2C_MAC_OFFSET)
d59feffb
HW
876 mac_read_from_eeprom();
877#endif
878
fe8c2806
WD
879#ifdef CONFIG_HERMES
880 if ((gd->board_type >> 16) == 2)
881 bd->bi_ethspeed = gd->board_type & 0xFFFF;
882 else
883 bd->bi_ethspeed = 0xFFFF;
884#endif
885
02a301cd 886#ifdef CONFIG_CMD_NET
eb85aa59
MF
887 /* kept around for legacy kernels only ... ignore the next section */
888 eth_getenv_enetaddr("ethaddr", bd->bi_enetaddr);
e2ffd59b 889#ifdef CONFIG_HAS_ETH1
eb85aa59 890 eth_getenv_enetaddr("eth1addr", bd->bi_enet1addr);
fe8c2806 891#endif
e2ffd59b 892#ifdef CONFIG_HAS_ETH2
eb85aa59 893 eth_getenv_enetaddr("eth2addr", bd->bi_enet2addr);
fe8c2806 894#endif
e2ffd59b 895#ifdef CONFIG_HAS_ETH3
eb85aa59 896 eth_getenv_enetaddr("eth3addr", bd->bi_enet3addr);
ba56f625 897#endif
c68a05fe 898#ifdef CONFIG_HAS_ETH4
eb85aa59 899 eth_getenv_enetaddr("eth4addr", bd->bi_enet4addr);
c68a05fe 900#endif
c68a05fe 901#ifdef CONFIG_HAS_ETH5
eb85aa59 902 eth_getenv_enetaddr("eth5addr", bd->bi_enet5addr);
c68a05fe 903#endif
02a301cd 904#endif /* CONFIG_CMD_NET */
c68a05fe 905
fe8c2806
WD
906 /* IP Address */
907 bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
908
909 WATCHDOG_RESET ();
910
979bdbc7 911#if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx) && !defined(CONFIG_CPC45)
fe8c2806
WD
912 /*
913 * Do pci configuration
914 */
915 pci_init ();
916#endif
917
918/** leave this here (after malloc(), environment and PCI are working) **/
52cb4d4f
JCPV
919 /* Initialize stdio devices */
920 stdio_init ();
fe8c2806 921
27b207fd
WD
922 /* Initialize the jump table for applications */
923 jumptable_init ();
fe8c2806 924
500856eb
RJ
925#if defined(CONFIG_API)
926 /* Initialize API */
927 api_init ();
928#endif
929
fe8c2806
WD
930 /* Initialize the console (after the relocation and devices init) */
931 console_init_r ();
fe8c2806
WD
932
933#if defined(CONFIG_CCM) || \
934 defined(CONFIG_COGENT) || \
935 defined(CONFIG_CPCI405) || \
936 defined(CONFIG_EVB64260) || \
56f94be3 937 defined(CONFIG_KUP4K) || \
0608e04d 938 defined(CONFIG_KUP4X) || \
fe8c2806
WD
939 defined(CONFIG_LWMON) || \
940 defined(CONFIG_PCU_E) || \
9045f33c 941 defined(CONFIG_SC3) || \
fe8c2806
WD
942 defined(CONFIG_W7O) || \
943 defined(CONFIG_MISC_INIT_R)
944 /* miscellaneous platform dependent initialisations */
945 misc_init_r ();
946#endif
947
948#ifdef CONFIG_HERMES
949 if (bd->bi_ethspeed != 0xFFFF)
950 hermes_start_lxt980 ((int) bd->bi_ethspeed);
951#endif
952
7def6b34 953#if defined(CONFIG_CMD_KGDB)
fe8c2806
WD
954 WATCHDOG_RESET ();
955 puts ("KGDB: ");
956 kgdb_init ();
957#endif
958
9d2b18a0 959 debug ("U-Boot relocated to %08lx\n", dest_addr);
fe8c2806
WD
960
961 /*
962 * Enable Interrupts
963 */
964 interrupt_init ();
965
966 /* Must happen after interrupts are initialized since
967 * an irq handler gets installed
968 */
42dfe7a1 969#ifdef CONFIG_SERIAL_SOFTWARE_FIFO
fe8c2806
WD
970 serial_buffered_init();
971#endif
972
566a494f 973#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
fe8c2806
WD
974 status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
975#endif
976
977 udelay (20);
978
979 set_timer (0);
980
fe8c2806
WD
981 /* Initialize from environment */
982 if ((s = getenv ("loadaddr")) != NULL) {
983 load_addr = simple_strtoul (s, NULL, 16);
984 }
7def6b34 985#if defined(CONFIG_CMD_NET)
fe8c2806
WD
986 if ((s = getenv ("bootfile")) != NULL) {
987 copy_filename (BootFile, s, sizeof (BootFile));
988 }
b3aff0cb 989#endif
fe8c2806
WD
990
991 WATCHDOG_RESET ();
992
9c2d63ec
HS
993#if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */
994 dtt_init ();
995#endif
7def6b34 996#if defined(CONFIG_CMD_SCSI)
fe8c2806
WD
997 WATCHDOG_RESET ();
998 puts ("SCSI: ");
999 scsi_init ();
1000#endif
1001
272cc70b
AF
1002#ifdef CONFIG_GENERIC_MMC
1003 WATCHDOG_RESET ();
1004 puts ("MMC: ");
1005 mmc_initialize (bd);
1006#endif
1007
7def6b34 1008#if defined(CONFIG_CMD_DOC)
fe8c2806
WD
1009 WATCHDOG_RESET ();
1010 puts ("DOC: ");
1011 doc_init ();
1012#endif
1013
7def6b34 1014#if defined(CONFIG_CMD_NET)
63ff004c 1015#if defined(CONFIG_NET_MULTI)
fe8c2806
WD
1016 WATCHDOG_RESET ();
1017 puts ("Net: ");
63ff004c 1018#endif
fe8c2806
WD
1019 eth_initialize (bd);
1020#endif
1021
7def6b34 1022#if defined(CONFIG_CMD_NET) && ( \
63ff004c
MB
1023 defined(CONFIG_CCM) || \
1024 defined(CONFIG_ELPT860) || \
1025 defined(CONFIG_EP8260) || \
1026 defined(CONFIG_IP860) || \
1027 defined(CONFIG_IVML24) || \
1028 defined(CONFIG_IVMS8) || \
1029 defined(CONFIG_MPC8260ADS) || \
1030 defined(CONFIG_MPC8266ADS) || \
1031 defined(CONFIG_MPC8560ADS) || \
1032 defined(CONFIG_PCU_E) || \
1033 defined(CONFIG_RPXSUPER) || \
1034 defined(CONFIG_STXGP3) || \
1035 defined(CONFIG_SPD823TS) || \
1036 defined(CONFIG_RESET_PHY_R) )
1037
1038 WATCHDOG_RESET ();
1039 debug ("Reset Ethernet PHY\n");
1040 reset_phy ();
1041#endif
1042
fe8c2806 1043#ifdef CONFIG_POST
6dff5529 1044 post_run (NULL, POST_RAM | post_bootmode_get(0));
fe8c2806
WD
1045#endif
1046
7def6b34
JL
1047#if defined(CONFIG_CMD_PCMCIA) \
1048 && !defined(CONFIG_CMD_IDE)
fe8c2806
WD
1049 WATCHDOG_RESET ();
1050 puts ("PCMCIA:");
1051 pcmcia_init ();
1052#endif
1053
7def6b34 1054#if defined(CONFIG_CMD_IDE)
fe8c2806
WD
1055 WATCHDOG_RESET ();
1056# ifdef CONFIG_IDE_8xx_PCCARD
1057 puts ("PCMCIA:");
1058# else
1059 puts ("IDE: ");
1060#endif
ca43ba18
HS
1061#if defined(CONFIG_START_IDE)
1062 if (board_start_ide())
1063 ide_init ();
1064#else
fe8c2806 1065 ide_init ();
ca43ba18 1066#endif
b3aff0cb 1067#endif
fe8c2806
WD
1068
1069#ifdef CONFIG_LAST_STAGE_INIT
1070 WATCHDOG_RESET ();
1071 /*
1072 * Some parts can be only initialized if all others (like
1073 * Interrupts) are up and running (i.e. the PC-style ISA
1074 * keyboard).
1075 */
1076 last_stage_init ();
1077#endif
1078
7def6b34 1079#if defined(CONFIG_CMD_BEDBUG)
fe8c2806
WD
1080 WATCHDOG_RESET ();
1081 bedbug_init ();
1082#endif
1083
228f29ac 1084#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
fe8c2806
WD
1085 /*
1086 * Export available size of memory for Linux,
1087 * taking into account the protected RAM at top of memory
1088 */
1089 {
1090 ulong pram;
fe8c2806 1091 uchar memsz[32];
228f29ac
WD
1092#ifdef CONFIG_PRAM
1093 char *s;
fe8c2806
WD
1094
1095 if ((s = getenv ("pram")) != NULL) {
1096 pram = simple_strtoul (s, NULL, 10);
1097 } else {
1098 pram = CONFIG_PRAM;
1099 }
228f29ac
WD
1100#else
1101 pram=0;
1102#endif
1103#ifdef CONFIG_LOGBUFFER
3d610186 1104#ifndef CONFIG_ALT_LB_ADDR
228f29ac
WD
1105 /* Also take the logbuffer into account (pram is in kB) */
1106 pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024;
3d610186 1107#endif
228f29ac 1108#endif
77ddac94
WD
1109 sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
1110 setenv ("mem", (char *)memsz);
fe8c2806
WD
1111 }
1112#endif
1113
1c43771b
WD
1114#ifdef CONFIG_PS2KBD
1115 puts ("PS/2: ");
1116 kbd_init();
1117#endif
1118
4532cb69
WD
1119#ifdef CONFIG_MODEM_SUPPORT
1120 {
1121 extern int do_mdm_init;
1122 do_mdm_init = gd->do_mdm_init;
1123 }
1124#endif
1125
fe8c2806
WD
1126 /* Initialization complete - start the monitor */
1127
1128 /* main_loop() can return to retry autoboot, if so just run it again. */
1129 for (;;) {
1130 WATCHDOG_RESET ();
1131 main_loop ();
1132 }
1133
1134 /* NOTREACHED - no way out of command loop except booting */
1135}
1136
1137void hang (void)
1138{
1139 puts ("### ERROR ### Please RESET the board ###\n");
63e73c9a 1140 show_boot_progress(-30);
fe8c2806
WD
1141 for (;;);
1142}
1143
4532cb69 1144
fe8c2806
WD
1145#if 0 /* We could use plain global data, but the resulting code is bigger */
1146/*
1147 * Pointer to initial global data area
1148 *
1149 * Here we initialize it.
1150 */
1151#undef XTRN_DECLARE_GLOBAL_DATA_PTR
1152#define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
6d0f6bcf 1153DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
fe8c2806
WD
1154#endif /* 0 */
1155
1156/************************************************************************/
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