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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[J-u-boot.git] / drivers / video / rockchip / rk_edp.c
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a355ece8 1// SPDX-License-Identifier: GPL-2.0
5852d539
SG		 2/*
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
5852d539
SG		 5 */
6
d678a59d 7#include <common.h>
5852d539
SG		 8#include <clk.h>
9#include <display.h>
10#include <dm.h>
cd529f7a 11#include <dm/device_compat.h>
5852d539 12#include <edid.h>
f7ae49fc 13#include <log.h>
336d4615 14#include <malloc.h>
5852d539
SG		 15#include <panel.h>
16#include <regmap.h>
cd529f7a 17#include <reset.h>
5852d539
SG		 18#include <syscon.h>
19#include <asm/gpio.h>
15f09a1a 20#include <asm/arch-rockchip/clock.h>
04d67ceb 21#include <asm/arch-rockchip/hardware.h>
15f09a1a
KY		 22#include <asm/arch-rockchip/edp_rk3288.h>
23#include <asm/arch-rockchip/grf_rk3288.h>
04d67ceb 24#include <asm/arch-rockchip/grf_rk3399.h>
5852d539 25
5852d539
SG		 26#define MAX_CR_LOOP 5
27#define MAX_EQ_LOOP 5
28#define DP_LINK_STATUS_SIZE 6
29
30static const char * const voltage_names[] = {
31 "0.4V", "0.6V", "0.8V", "1.2V"
32};
33static const char * const pre_emph_names[] = {
34 "0dB", "3.5dB", "6dB", "9.5dB"
35};
36
37#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
38#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
39
04d67ceb
APR		 40#define RK3288_GRF_SOC_CON6 0x025c
41#define RK3288_GRF_SOC_CON12 0x0274
42#define RK3399_GRF_SOC_CON20 0x6250
43#define RK3399_GRF_SOC_CON25 0x6264
44
45enum rockchip_dp_types {
46 RK3288_DP = 0,
47 RK3399_EDP
48};
49
50struct rockchip_dp_data {
51 unsigned long reg_vop_big_little;
52 unsigned long reg_vop_big_little_sel;
53 unsigned long reg_ref_clk_sel;
54 unsigned long ref_clk_sel_bit;
55 enum rockchip_dp_types chip_type;
56};
57
5852d539
SG		 58struct rk_edp_priv {
59 struct rk3288_edp *regs;
04d67ceb 60 void *grf;
5852d539
SG		 61 struct udevice *panel;
62 struct link_train link_train;
63 u8 train_set[4];
64};
65
04d67ceb 66static void rk_edp_init_refclk(struct rk3288_edp *regs, enum rockchip_dp_types chip_type)
5852d539
SG		 67{
68 writel(SEL_24M, &regs->analog_ctl_2);
04d67ceb
APR		 69 u32 reg;
70
71 reg = REF_CLK_24M;
72 if (chip_type == RK3288_DP)
73 reg ^= REF_CLK_MASK;
74 writel(reg, &regs->pll_reg_1);
75
5852d539
SG		 76
77 writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US |
78 V2L_CUR_SEL_1MA, &regs->pll_reg_2);
79
80 writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET |
81 LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE,
82 &regs->pll_reg_3);
83
84 writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL |
85 CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP,
86 &regs->pll_reg_5);
87
88 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, &regs->ssc_reg);
89
90 writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 |
91 LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL,
92 &regs->tx_common);
93
94 writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM,
95 &regs->dp_aux);
96
97 writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG,
98 &regs->dp_bias);
99
100 writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL,
101 &regs->dp_reserv2);
102}
103
104static void rk_edp_init_interrupt(struct rk3288_edp *regs)
105{
106 /* Set interrupt pin assertion polarity as high */
107 writel(INT_POL, &regs->int_ctl);
108
109 /* Clear pending registers */
110 writel(0xff, &regs->common_int_sta_1);
111 writel(0x4f, &regs->common_int_sta_2);
112 writel(0xff, &regs->common_int_sta_3);
113 writel(0x27, &regs->common_int_sta_4);
114 writel(0x7f, &regs->dp_int_sta);
115
116 /* 0:mask,1: unmask */
117 writel(0x00, &regs->common_int_mask_1);
118 writel(0x00, &regs->common_int_mask_2);
119 writel(0x00, &regs->common_int_mask_3);
120 writel(0x00, &regs->common_int_mask_4);
121 writel(0x00, &regs->int_sta_mask);
122}
123
124static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
125{
126 clrbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
127}
128
129static bool rk_edp_get_pll_locked(struct rk3288_edp *regs)
130{
131 u32 val;
132
133 val = readl(&regs->dp_debug_ctl);
134
135 return val & PLL_LOCK;
136}
137
138static int rk_edp_init_analog_func(struct rk3288_edp *regs)
139{
140 ulong start;
141
142 writel(0x00, &regs->dp_pd);
143 writel(PLL_LOCK_CHG, &regs->common_int_sta_1);
144
145 clrbits_le32(&regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
146
147 start = get_timer(0);
148 while (!rk_edp_get_pll_locked(regs)) {
149 if (get_timer(start) > PLL_LOCK_TIMEOUT) {
150 printf("%s: PLL is not locked\n", __func__);
151 return -ETIMEDOUT;
152 }
153 }
154
155 /* Enable Serdes FIFO function and Link symbol clock domain module */
156 clrbits_le32(&regs->func_en_2, SERDES_FIFO_FUNC_EN_N |
157 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N |
158 SSC_FUNC_EN_N);
159
160 return 0;
161}
162
163static void rk_edp_init_aux(struct rk3288_edp *regs)
164{
165 /* Clear inerrupts related to AUX channel */
166 writel(AUX_FUNC_EN_N, &regs->dp_int_sta);
167
168 /* Disable AUX channel module */
169 setbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);
170
171 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
172 writel(DEFER_CTRL_EN | DEFER_COUNT(1), &regs->aux_ch_defer_dtl);
173
174 /* Enable AUX channel module */
175 clrbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);
176}
177
178static int rk_edp_aux_enable(struct rk3288_edp *regs)
179{
180 ulong start;
181
182 setbits_le32(&regs->aux_ch_ctl_2, AUX_EN);
183 start = get_timer(0);
184 do {
185 if (!(readl(&regs->aux_ch_ctl_2) & AUX_EN))
186 return 0;
187 } while (get_timer(start) < 20);
188
189 return -ETIMEDOUT;
190}
191
192static int rk_edp_is_aux_reply(struct rk3288_edp *regs)
193{
194 ulong start;
195
196 start = get_timer(0);
197 while (!(readl(&regs->dp_int_sta) & RPLY_RECEIV)) {
198 if (get_timer(start) > 10)
199 return -ETIMEDOUT;
200 }
201
202 writel(RPLY_RECEIV, &regs->dp_int_sta);
203
204 return 0;
205}
206
207static int rk_edp_start_aux_transaction(struct rk3288_edp *regs)
208{
209 int val, ret;
210
211 /* Enable AUX CH operation */
212 ret = rk_edp_aux_enable(regs);
213 if (ret) {
214 debug("AUX CH enable timeout!\n");
215 return ret;
216 }
217
218 /* Is AUX CH command reply received? */
219 if (rk_edp_is_aux_reply(regs)) {
220 debug("AUX CH command reply failed!\n");
221 return ret;
222 }
223
224 /* Clear interrupt source for AUX CH access error */
225 val = readl(&regs->dp_int_sta);
226 if (val & AUX_ERR) {
227 writel(AUX_ERR, &regs->dp_int_sta);
228 return -EIO;
229 }
230
231 /* Check AUX CH error access status */
232 val = readl(&regs->dp_int_sta);
233 if (val & AUX_STATUS_MASK) {
234 debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK);
235 return -EIO;
236 }
237
238 return 0;
239}
240
241static int rk_edp_dpcd_transfer(struct rk3288_edp *regs,
242 unsigned int val_addr, u8 *in_data,
243 unsigned int length,
244 enum dpcd_request request)
245{
246 int val;
247 int i, try_times;
248 u8 *data;
249 int ret = 0;
250 u32 len = 0;
251
252 while (length) {
253 len = min(length, 16U);
254 for (try_times = 0; try_times < 10; try_times++) {
255 data = in_data;
256 /* Clear AUX CH data buffer */
257 writel(BUF_CLR, &regs->buf_data_ctl);
258
259 /* Select DPCD device address */
260 writel(AUX_ADDR_7_0(val_addr), &regs->aux_addr_7_0);
261 writel(AUX_ADDR_15_8(val_addr), &regs->aux_addr_15_8);
262 writel(AUX_ADDR_19_16(val_addr), &regs->aux_addr_19_16);
263
264 /*
265 * Set DisplayPort transaction and read 1 byte
266 * If bit 3 is 1, DisplayPort transaction.
267 * If Bit 3 is 0, I2C transaction.
268 */
269 if (request == DPCD_WRITE) {
270 val = AUX_LENGTH(len) |
271 AUX_TX_COMM_DP_TRANSACTION |
272 AUX_TX_COMM_WRITE;
273 for (i = 0; i < len; i++)
274 writel(*data++, &regs->buf_data[i]);
275 } else
276 val = AUX_LENGTH(len) |
277 AUX_TX_COMM_DP_TRANSACTION |
278 AUX_TX_COMM_READ;
279
280 writel(val, &regs->aux_ch_ctl_1);
281
282 /* Start AUX transaction */
283 ret = rk_edp_start_aux_transaction(regs);
284 if (ret == 0)
285 break;
286 else
287 printf("read dpcd Aux Transaction fail!\n");
288 }
289
290 if (ret)
291 return ret;
292
293 if (request == DPCD_READ) {
294 for (i = 0; i < len; i++)
295 *data++ = (u8)readl(&regs->buf_data[i]);
296 }
297
298 length -= len;
299 val_addr += len;
300 in_data += len;
301 }
302
303 return 0;
304}
305
306static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values,
307 size_t size)
308{
309 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ);
310}
311
312static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values,
313 size_t size)
314{
315 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE);
316}
317
318
319static int rk_edp_link_power_up(struct rk_edp_priv *edp)
320{
321 u8 value;
322 int ret;
323
324 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
325 if (edp->link_train.revision < 0x11)
326 return 0;
327
328 ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
329 if (ret)
330 return ret;
331
332 value &= ~DP_SET_POWER_MASK;
333 value |= DP_SET_POWER_D0;
334
335 ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
336 if (ret)
337 return ret;
338
339 /*
340 * According to the DP 1.1 specification, a "Sink Device must exit the
341 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
342 * Control Field" (register 0x600).
343 */
344 mdelay(1);
345
346 return 0;
347}
348
349static int rk_edp_link_configure(struct rk_edp_priv *edp)
350{
351 u8 values[2];
352
353 values[0] = edp->link_train.link_rate;
354 values[1] = edp->link_train.lane_count;
355
356 return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values,
357 sizeof(values));
358}
359
360static void rk_edp_set_link_training(struct rk_edp_priv *edp,
361 const u8 *training_values)
362{
363 int i;
364
365 for (i = 0; i < edp->link_train.lane_count; i++)
366 writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);
367}
368
369static u8 edp_link_status(const u8 *link_status, int r)
370{
371 return link_status[r - DPCD_LANE0_1_STATUS];
372}
373
374static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp,
375 u8 *link_status)
376{
377 return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status,
378 DP_LINK_STATUS_SIZE);
379}
380
381static u8 edp_get_lane_status(const u8 *link_status, int lane)
382{
383 int i = DPCD_LANE0_1_STATUS + (lane >> 1);
384 int s = (lane & 1) * 4;
385 u8 l = edp_link_status(link_status, i);
386
387 return (l >> s) & 0xf;
388}
389
390static int rk_edp_clock_recovery(const u8 *link_status, int lane_count)
391{
392 int lane;
393 u8 lane_status;
394
395 for (lane = 0; lane < lane_count; lane++) {
396 lane_status = edp_get_lane_status(link_status, lane);
397 if ((lane_status & DP_LANE_CR_DONE) == 0)
398 return -EIO;
399 }
400
401 return 0;
402}
403
404static int rk_edp_channel_eq(const u8 *link_status, int lane_count)
405{
406 u8 lane_align;
407 u8 lane_status;
408 int lane;
409
410 lane_align = edp_link_status(link_status,
411 DPCD_LANE_ALIGN_STATUS_UPDATED);
412 if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
413 return -EIO;
414 for (lane = 0; lane < lane_count; lane++) {
415 lane_status = edp_get_lane_status(link_status, lane);
416 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
417 return -EIO;
418 }
419
420 return 0;
421}
422
423static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane)
424{
425 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
426 int s = ((lane & 1) ?
427 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
428 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
429 u8 l = edp_link_status(link_status, i);
430
431 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
432}
433
434static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status,
435 int lane)
436{
437 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
438 int s = ((lane & 1) ?
439 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
440 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
441 u8 l = edp_link_status(link_status, i);
442
443 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
444}
445
446static void edp_get_adjust_train(const u8 *link_status, int lane_count,
447 u8 train_set[])
448{
449 uint v = 0;
450 uint p = 0;
451 int lane;
452
453 for (lane = 0; lane < lane_count; lane++) {
454 uint this_v, this_p;
455
456 this_v = rk_edp_get_adjust_request_voltage(link_status, lane);
457 this_p = rk_edp_get_adjust_request_pre_emphasis(link_status,
458 lane);
459
460 debug("requested signal parameters: lane %d voltage %s pre_emph %s\n",
461 lane,
462 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
463 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
464
465 if (this_v > v)
466 v = this_v;
467 if (this_p > p)
468 p = this_p;
469 }
470
471 if (v >= DP_VOLTAGE_MAX)
472 v |= DP_TRAIN_MAX_SWING_REACHED;
473
474 if (p >= DP_PRE_EMPHASIS_MAX)
475 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
476
477 debug("using signal parameters: voltage %s pre_emph %s\n",
478 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK)
479 >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
480 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK)
481 >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
482
483 for (lane = 0; lane < 4; lane++)
484 train_set[lane] = v | p;
485}
486
487static int rk_edp_link_train_cr(struct rk_edp_priv *edp)
488{
489 struct rk3288_edp *regs = edp->regs;
490 int clock_recovery;
491 uint voltage, tries = 0;
492 u8 status[DP_LINK_STATUS_SIZE];
493 int i, ret;
494 u8 value;
495
496 value = DP_TRAINING_PATTERN_1;
497 writel(value, &regs->dp_training_ptn_set);
498 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
499 if (ret)
500 return ret;
501 memset(edp->train_set, '\0', sizeof(edp->train_set));
502
503 /* clock recovery loop */
504 clock_recovery = 0;
505 tries = 0;
506 voltage = 0xff;
507
508 while (1) {
509 rk_edp_set_link_training(edp, edp->train_set);
510 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
511 edp->train_set,
512 edp->link_train.lane_count);
513 if (ret)
514 return ret;
515
516 mdelay(1);
517
518 ret = rk_edp_dpcd_read_link_status(edp, status);
519 if (ret) {
520 printf("displayport link status failed, ret=%d\n", ret);
521 break;
522 }
523
524 clock_recovery = rk_edp_clock_recovery(status,
525 edp->link_train.lane_count);
526 if (!clock_recovery)
527 break;
528
529 for (i = 0; i < edp->link_train.lane_count; i++) {
530 if ((edp->train_set[i] &
531 DP_TRAIN_MAX_SWING_REACHED) == 0)
532 break;
533 }
534 if (i == edp->link_train.lane_count) {
535 printf("clock recovery reached max voltage\n");
536 break;
537 }
538
539 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
540 voltage) {
541 if (++tries == MAX_CR_LOOP) {
542 printf("clock recovery tried 5 times\n");
543 break;
544 }
545 } else {
546 tries = 0;
547 }
548
549 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
550
551 /* Compute new train_set as requested by sink */
552 edp_get_adjust_train(status, edp->link_train.lane_count,
553 edp->train_set);
554 }
555 if (clock_recovery) {
556 printf("clock recovery failed: %d\n", clock_recovery);
557 return clock_recovery;
558 } else {
559 debug("clock recovery at voltage %d pre-emphasis %d\n",
560 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
561 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
562 DP_TRAIN_PRE_EMPHASIS_SHIFT);
563 return 0;
564 }
565}
566
567static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
568{
569 struct rk3288_edp *regs = edp->regs;
570 int channel_eq;
571 u8 value;
572 int tries;
573 u8 status[DP_LINK_STATUS_SIZE];
574 int ret;
575
576 value = DP_TRAINING_PATTERN_2;
577 writel(value, &regs->dp_training_ptn_set);
578 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
579 if (ret)
580 return ret;
581
582 /* channel equalization loop */
583 channel_eq = 0;
584 for (tries = 0; tries < 5; tries++) {
585 rk_edp_set_link_training(edp, edp->train_set);
127c8d85
ANY		 586 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
587 edp->train_set,
588 edp->link_train.lane_count);
589 if (ret)
590 return ret;
591
5852d539
SG		 592 udelay(400);
593
594 if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
595 printf("displayport link status failed\n");
596 return -1;
597 }
598
599 channel_eq = rk_edp_channel_eq(status,
600 edp->link_train.lane_count);
601 if (!channel_eq)
602 break;
603 edp_get_adjust_train(status, edp->link_train.lane_count,
604 edp->train_set);
605 }
606
607 if (channel_eq) {
608 printf("channel eq failed, ret=%d\n", channel_eq);
609 return channel_eq;
610 }
611
612 debug("channel eq at voltage %d pre-emphasis %d\n",
613 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
614 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
615 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
616
617 return 0;
618}
619
620static int rk_edp_init_training(struct rk_edp_priv *edp)
621{
622 u8 values[3];
623 int ret;
624
625 ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values,
626 sizeof(values));
627 if (ret < 0)
628 return ret;
629
630 edp->link_train.revision = values[0];
631 edp->link_train.link_rate = values[1];
632 edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK;
633
634 debug("max link rate:%d.%dGps max number of lanes:%d\n",
635 edp->link_train.link_rate * 27 / 100,
636 edp->link_train.link_rate * 27 % 100,
637 edp->link_train.lane_count);
638
639 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
640 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
641 debug("Rx Max Link Rate is abnormal :%x\n",
642 edp->link_train.link_rate);
643 return -EPERM;
644 }
645
646 if (edp->link_train.lane_count == 0) {
647 debug("Rx Max Lane count is abnormal :%x\n",
648 edp->link_train.lane_count);
649 return -EPERM;
650 }
651
652 ret = rk_edp_link_power_up(edp);
653 if (ret)
654 return ret;
655
656 return rk_edp_link_configure(edp);
657}
658
659static int rk_edp_hw_link_training(struct rk_edp_priv *edp)
660{
661 ulong start;
662 u32 val;
663 int ret;
664
665 /* Set link rate and count as you want to establish */
666 writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
667 writel(edp->link_train.lane_count, &edp->regs->lane_count_set);
668
669 ret = rk_edp_link_train_cr(edp);
670 if (ret)
671 return ret;
672 ret = rk_edp_link_train_ce(edp);
673 if (ret)
674 return ret;
675
676 writel(HW_LT_EN, &edp->regs->dp_hw_link_training);
677 start = get_timer(0);
678 do {
679 val = readl(&edp->regs->dp_hw_link_training);
680 if (!(val & HW_LT_EN))
681 break;
682 } while (get_timer(start) < 10);
683
684 if (val & HW_LT_ERR_CODE_MASK) {
685 printf("edp hw link training error: %d\n",
686 val >> HW_LT_ERR_CODE_SHIFT);
687 return -EIO;
688 }
689
690 return 0;
691}
692
693static int rk_edp_select_i2c_device(struct rk3288_edp *regs,
694 unsigned int device_addr,
695 unsigned int val_addr)
696{
697 int ret;
698
699 /* Set EDID device address */
700 writel(device_addr, &regs->aux_addr_7_0);
701 writel(0x0, &regs->aux_addr_15_8);
702 writel(0x0, &regs->aux_addr_19_16);
703
704 /* Set offset from base address of EDID device */
705 writel(val_addr, &regs->buf_data[0]);
706
707 /*
708 * Set I2C transaction and write address
709 * If bit 3 is 1, DisplayPort transaction.
710 * If Bit 3 is 0, I2C transaction.
711 */
712 writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
713 AUX_TX_COMM_WRITE, &regs->aux_ch_ctl_1);
714
715 /* Start AUX transaction */
716 ret = rk_edp_start_aux_transaction(regs);
717 if (ret != 0) {
718 debug("select_i2c_device Aux Transaction fail!\n");
719 return ret;
720 }
721
722 return 0;
723}
724
725static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr,
726 unsigned int val_addr, unsigned int count, u8 edid[])
727{
728 u32 val;
729 unsigned int i, j;
730 unsigned int cur_data_idx;
731 unsigned int defer = 0;
732 int ret = 0;
733
734 for (i = 0; i < count; i += 16) {
735 for (j = 0; j < 10; j++) { /* try 10 times */
736 /* Clear AUX CH data buffer */
737 writel(BUF_CLR, &regs->buf_data_ctl);
738
739 /* Set normal AUX CH command */
740 clrbits_le32(&regs->aux_ch_ctl_2, ADDR_ONLY);
741
742 /*
743 * If Rx sends defer, Tx sends only reads
744 * request without sending addres
745 */
746 if (!defer) {
747 ret = rk_edp_select_i2c_device(regs,
748 device_addr,
749 val_addr + i);
750 } else {
751 defer = 0;
752 }
753
754 /*
755 * Set I2C transaction and write data
756 * If bit 3 is 1, DisplayPort transaction.
757 * If Bit 3 is 0, I2C transaction.
758 */
759 writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
760 AUX_TX_COMM_READ, &regs->aux_ch_ctl_1);
761
762 /* Start AUX transaction */
763 ret = rk_edp_start_aux_transaction(regs);
764 if (ret == 0) {
765 break;
766 } else {
767 debug("Aux Transaction fail!\n");
768 continue;
769 }
770
771 /* Check if Rx sends defer */
772 val = readl(&regs->aux_rx_comm);
773 if (val == AUX_RX_COMM_AUX_DEFER ||
774 val == AUX_RX_COMM_I2C_DEFER) {
775 debug("Defer: %d\n\n", val);
776 defer = 1;
777 }
778 }
779
780 if (ret)
781 return ret;
782
783 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
784 val = readl(&regs->buf_data[cur_data_idx]);
785 edid[i + cur_data_idx] = (u8)val;
786 }
787 }
788
789 return 0;
790}
791
792static int rk_edp_set_link_train(struct rk_edp_priv *edp)
793{
794 int ret;
795
796 ret = rk_edp_init_training(edp);
797 if (ret) {
798 printf("DP LT init failed!\n");
799 return ret;
800 }
801
802 ret = rk_edp_hw_link_training(edp);
803 if (ret)
804 return ret;
805
806 return 0;
807}
808
809static void rk_edp_init_video(struct rk3288_edp *regs)
810{
811 writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG,
812 &regs->common_int_sta_1);
813 writel(CHA_CRI(4) | CHA_CTRL, &regs->sys_ctl_2);
814 writel(VID_HRES_TH(2) | VID_VRES_TH(0), &regs->video_ctl_8);
815}
816
817static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs)
818{
819 clrbits_le32(&regs->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
820}
821
822static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs,
823 enum clock_recovery_m_value_type type,
824 u32 m_value,
825 u32 n_value)
826{
827 if (type == REGISTER_M) {
828 setbits_le32(&regs->sys_ctl_4, FIX_M_VID);
829 writel(m_value & 0xff, &regs->m_vid_0);
830 writel((m_value >> 8) & 0xff, &regs->m_vid_1);
831 writel((m_value >> 16) & 0xff, &regs->m_vid_2);
832
833 writel(n_value & 0xf, &regs->n_vid_0);
834 writel((n_value >> 8) & 0xff, &regs->n_vid_1);
835 writel((n_value >> 16) & 0xff, &regs->n_vid_2);
836 } else {
837 clrbits_le32(&regs->sys_ctl_4, FIX_M_VID);
838
839 writel(0x00, &regs->n_vid_0);
840 writel(0x80, &regs->n_vid_1);
841 writel(0x00, &regs->n_vid_2);
842 }
843}
844
845static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs)
846{
847 ulong start;
848 u32 val;
849
850 start = get_timer(0);
851 do {
852 val = readl(&regs->sys_ctl_1);
853
854 /* must write value to update DET_STA bit status */
855 writel(val, &regs->sys_ctl_1);
856 val = readl(&regs->sys_ctl_1);
857 if (!(val & DET_STA))
858 continue;
859
860 val = readl(&regs->sys_ctl_2);
861
862 /* must write value to update CHA_STA bit status */
863 writel(val, &regs->sys_ctl_2);
864 val = readl(&regs->sys_ctl_2);
865 if (!(val & CHA_STA))
866 return 0;
867
868 } while (get_timer(start) < 100);
869
870 return -ETIMEDOUT;
871}
872
873static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp)
874{
875 ulong start;
876 u32 val;
877
878 start = get_timer(0);
879 do {
880 val = readl(&edp->regs->sys_ctl_3);
881
882 /* must write value to update STRM_VALID bit status */
883 writel(val, &edp->regs->sys_ctl_3);
884
885 val = readl(&edp->regs->sys_ctl_3);
886 if (!(val & STRM_VALID))
887 return 0;
888 } while (get_timer(start) < 100);
889
890 return -ETIMEDOUT;
891}
892
893static int rk_edp_config_video(struct rk_edp_priv *edp)
894{
895 int ret;
896
897 rk_edp_config_video_slave_mode(edp->regs);
898
899 if (!rk_edp_get_pll_locked(edp->regs)) {
900 debug("PLL is not locked yet.\n");
901 return -ETIMEDOUT;
902 }
903
904 ret = rk_edp_is_video_stream_clock_on(edp->regs);
905 if (ret)
906 return ret;
907
908 /* Set to use the register calculated M/N video */
909 rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0);
910
911 /* For video bist, Video timing must be generated by register */
912 clrbits_le32(&edp->regs->video_ctl_10, F_SEL);
913
914 /* Disable video mute */
915 clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE);
916
917 /* Enable video at next frame */
918 setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN);
919
920 return rk_edp_is_video_stream_on(edp);
921}
922
923static void rockchip_edp_force_hpd(struct rk_edp_priv *edp)
924{
925 setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL);
926}
927
928static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp)
929{
930 u32 val;
931
932 val = readl(&edp->regs->sys_ctl_3);
933 if (val & HPD_STATUS)
934 return 1;
935
936 return 0;
937}
938
939/*
940 * support edp HPD function
941 * some hardware version do not support edp hdp,
942 * we use 200ms to try to get the hpd single now,
943 * if we can not get edp hpd single, it will delay 200ms,
944 * also meet the edp power timing request, to compatible
945 * all of the hardware version
946 */
947static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp)
948{
949 ulong start;
950
951 start = get_timer(0);
952 do {
953 if (rockchip_edp_get_plug_in_status(edp))
954 return;
955 udelay(100);
956 } while (get_timer(start) < 200);
957
958 debug("do not get hpd single, force hpd\n");
959 rockchip_edp_force_hpd(edp);
960}
961
962static int rk_edp_enable(struct udevice *dev, int panel_bpp,
963 const struct display_timing *edid)
964{
965 struct rk_edp_priv *priv = dev_get_priv(dev);
966 int ret = 0;
967
968 ret = rk_edp_set_link_train(priv);
969 if (ret) {
970 printf("link train failed!\n");
971 return ret;
972 }
973
974 rk_edp_init_video(priv->regs);
975 ret = rk_edp_config_video(priv);
976 if (ret) {
977 printf("config video failed\n");
978 return ret;
979 }
980 ret = panel_enable_backlight(priv->panel);
981 if (ret) {
982 debug("%s: backlight error: %d\n", __func__, ret);
983 return ret;
984 }
985
986 return 0;
987}
988
989static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
990{
991 struct rk_edp_priv *priv = dev_get_priv(dev);
992 u32 edid_size = EDID_LENGTH;
993 int ret;
994 int i;
995
996 for (i = 0; i < 3; i++) {
997 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER,
998 EDID_LENGTH, &buf[EDID_HEADER]);
999 if (ret) {
1000 debug("EDID read failed\n");
1001 continue;
1002 }
1003
1004 /*
1005 * check if the EDID has an extension flag, and read additional
1006 * EDID data if needed
1007 */
1008 if (buf[EDID_EXTENSION_FLAG]) {
1009 edid_size += EDID_LENGTH;
1010 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR,
1011 EDID_LENGTH, EDID_LENGTH,
1012 &buf[EDID_LENGTH]);
1013 if (ret) {
1014 debug("EDID Read failed!\n");
1015 continue;
1016 }
1017 }
1018 goto done;
1019 }
1020
1021 /* After 3 attempts, give up */
1022 return ret;
1023
1024done:
1025 return edid_size;
1026}
1027
d1998a9f 1028static int rk_edp_of_to_plat(struct udevice *dev)
5852d539
SG		 1029{
1030 struct rk_edp_priv *priv = dev_get_priv(dev);
1031
653ac184 1032 priv->regs = dev_read_addr_ptr(dev);
5852d539
SG		 1033 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1034
1035 return 0;
1036}
1037
f418676e
SG		 1038static int rk_edp_remove(struct udevice *dev)
1039{
1040 struct rk_edp_priv *priv = dev_get_priv(dev);
1041 struct rk3288_edp *regs = priv->regs;
1042
1043 setbits_le32(&regs->video_ctl_1, VIDEO_MUTE);
1044 clrbits_le32(&regs->video_ctl_1, VIDEO_EN);
1045 clrbits_le32(&regs->sys_ctl_3, F_HPD | HPD_CTRL);
1046 setbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
1047
1048 return 0;
1049}
1050
1051static int rk_edp_probe(struct udevice *dev)
5852d539 1052{
caa4daa2 1053 struct display_plat *uc_plat = dev_get_uclass_plat(dev);
5852d539
SG		 1054 struct rk_edp_priv *priv = dev_get_priv(dev);
1055 struct rk3288_edp *regs = priv->regs;
04d67ceb 1056 struct rockchip_dp_data *edp_data = (struct rockchip_dp_data *)dev_get_driver_data(dev);
cd529f7a 1057 struct reset_ctl dp_rst;
04d67ceb 1058
135aa950 1059 struct clk clk;
5852d539
SG		 1060 int ret;
1061
1062 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
1063 &priv->panel);
1064 if (ret) {
1065 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
1066 dev->name, ret);
1067 return ret;
1068 }
1069
cd529f7a
APR		 1070 ret = reset_get_by_name(dev, "dp", &dp_rst);
1071 if (ret) {
0944e77f
JJ		 1072 ret = reset_get_by_name(dev, "edp", &dp_rst);
1073 if (ret) {
1074 dev_err(dev, "failed to get dp reset (ret=%d)\n", ret);
1075 return ret;
1076 }
cd529f7a
APR		 1077 }
1078
1079 ret = reset_assert(&dp_rst);
1080 if (ret) {
1081 dev_err(dev, "failed to assert dp reset (ret=%d)\n", ret);
1082 return ret;
1083 }
1084 udelay(20);
1085
1086 ret = reset_deassert(&dp_rst);
1087 if (ret) {
1088 dev_err(dev, "failed to deassert dp reset (ret=%d)\n", ret);
1089 return ret;
1090 }
1091
5852d539
SG		 1092 int vop_id = uc_plat->source_id;
1093 debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id);
1094
04d67ceb
APR		 1095 if (edp_data->chip_type == RK3288_DP) {
1096 ret = clk_get_by_index(dev, 1, &clk);
c9309f40 1097 if (ret >= 0)
04d67ceb 1098 ret = clk_set_rate(&clk, 0);
04d67ceb
APR		 1099 if (ret) {
1100 debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
1101 return ret;
1102 }
5852d539 1103 }
5852d539 1104 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
c9309f40 1105 if (ret >= 0)
135aa950 1106 ret = clk_set_rate(&clk, 192000000);
5852d539
SG		 1107 if (ret < 0) {
1108 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
1109 __func__, uc_plat->src_dev->name, ret);
1110 return ret;
1111 }
1112
1113 /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
04d67ceb
APR		 1114 rk_setreg(priv->grf + edp_data->reg_ref_clk_sel,
1115 edp_data->ref_clk_sel_bit);
5852d539
SG		 1116
1117 /* select epd signal from vop0 or vop1 */
04d67ceb
APR		 1118 rk_clrsetreg(priv->grf + edp_data->reg_vop_big_little,
1119 edp_data->reg_vop_big_little_sel,
1120 (vop_id == 1) ? edp_data->reg_vop_big_little_sel : 0);
5852d539
SG		 1121
1122 rockchip_edp_wait_hpd(priv);
1123
04d67ceb 1124 rk_edp_init_refclk(regs, edp_data->chip_type);
5852d539
SG		 1125 rk_edp_init_interrupt(regs);
1126 rk_edp_enable_sw_function(regs);
1127 ret = rk_edp_init_analog_func(regs);
1128 if (ret)
1129 return ret;
1130 rk_edp_init_aux(regs);
1131
1132 return 0;
1133}
1134
1135static const struct dm_display_ops dp_rockchip_ops = {
1136 .read_edid = rk_edp_read_edid,
1137 .enable = rk_edp_enable,
1138};
1139
04d67ceb
APR		 1140static const struct rockchip_dp_data rk3399_edp = {
1141 .reg_vop_big_little = RK3399_GRF_SOC_CON20,
1142 .reg_vop_big_little_sel = BIT(5),
1143 .reg_ref_clk_sel = RK3399_GRF_SOC_CON25,
1144 .ref_clk_sel_bit = BIT(11),
1145 .chip_type = RK3399_EDP,
1146};
1147
1148static const struct rockchip_dp_data rk3288_dp = {
1149 .reg_vop_big_little = RK3288_GRF_SOC_CON6,
1150 .reg_vop_big_little_sel = BIT(5),
1151 .reg_ref_clk_sel = RK3288_GRF_SOC_CON12,
1152 .ref_clk_sel_bit = BIT(4),
1153 .chip_type = RK3288_DP,
1154};
1155
5852d539 1156static const struct udevice_id rockchip_dp_ids[] = {
0944e77f 1157 { .compatible = "rockchip,rk3288-dp", .data = (ulong)&rk3288_dp },
04d67ceb
APR		 1158 { .compatible = "rockchip,rk3288-edp", .data = (ulong)&rk3288_dp },
1159 { .compatible = "rockchip,rk3399-edp", .data = (ulong)&rk3399_edp },
5852d539
SG		 1160 { }
1161};
1162
1163U_BOOT_DRIVER(dp_rockchip) = {
1164 .name = "edp_rockchip",
1165 .id = UCLASS_DISPLAY,
1166 .of_match = rockchip_dp_ids,
1167 .ops = &dp_rockchip_ops,
d1998a9f 1168 .of_to_plat = rk_edp_of_to_plat,
5852d539 1169 .probe = rk_edp_probe,
f418676e 1170 .remove = rk_edp_remove,
41575d8e 1171 .priv_auto = sizeof(struct rk_edp_priv),
5852d539 1172};
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