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[J-u-boot.git] / drivers / video / rockchip / rk_edp.c
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a355ece8 1// SPDX-License-Identifier: GPL-2.0
5852d539
SG		 2/*
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
5852d539
SG		 5 */
6
5852d539
SG		 7#include <clk.h>
8#include <display.h>
9#include <dm.h>
cd529f7a 10#include <dm/device_compat.h>
5852d539 11#include <edid.h>
f7ae49fc 12#include <log.h>
336d4615 13#include <malloc.h>
5852d539
SG		 14#include <panel.h>
15#include <regmap.h>
cd529f7a 16#include <reset.h>
5852d539
SG		 17#include <syscon.h>
18#include <asm/gpio.h>
15f09a1a 19#include <asm/arch-rockchip/clock.h>
04d67ceb 20#include <asm/arch-rockchip/hardware.h>
15f09a1a
KY		 21#include <asm/arch-rockchip/edp_rk3288.h>
22#include <asm/arch-rockchip/grf_rk3288.h>
04d67ceb 23#include <asm/arch-rockchip/grf_rk3399.h>
5852d539 24
5852d539
SG		 25#define MAX_CR_LOOP 5
26#define MAX_EQ_LOOP 5
27#define DP_LINK_STATUS_SIZE 6
28
29static const char * const voltage_names[] = {
30 "0.4V", "0.6V", "0.8V", "1.2V"
31};
32static const char * const pre_emph_names[] = {
33 "0dB", "3.5dB", "6dB", "9.5dB"
34};
35
36#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
37#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
38
04d67ceb
APR		 39#define RK3288_GRF_SOC_CON6 0x025c
40#define RK3288_GRF_SOC_CON12 0x0274
41#define RK3399_GRF_SOC_CON20 0x6250
42#define RK3399_GRF_SOC_CON25 0x6264
43
44enum rockchip_dp_types {
45 RK3288_DP = 0,
46 RK3399_EDP
47};
48
49struct rockchip_dp_data {
50 unsigned long reg_vop_big_little;
51 unsigned long reg_vop_big_little_sel;
52 unsigned long reg_ref_clk_sel;
53 unsigned long ref_clk_sel_bit;
54 enum rockchip_dp_types chip_type;
55};
56
5852d539
SG		 57struct rk_edp_priv {
58 struct rk3288_edp *regs;
04d67ceb 59 void *grf;
5852d539
SG		 60 struct udevice *panel;
61 struct link_train link_train;
62 u8 train_set[4];
63};
64
04d67ceb 65static void rk_edp_init_refclk(struct rk3288_edp *regs, enum rockchip_dp_types chip_type)
5852d539
SG		 66{
67 writel(SEL_24M, &regs->analog_ctl_2);
04d67ceb
APR		 68 u32 reg;
69
70 reg = REF_CLK_24M;
71 if (chip_type == RK3288_DP)
72 reg ^= REF_CLK_MASK;
73 writel(reg, &regs->pll_reg_1);
74
5852d539
SG		 75
76 writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US |
77 V2L_CUR_SEL_1MA, &regs->pll_reg_2);
78
79 writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET |
80 LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE,
81 &regs->pll_reg_3);
82
83 writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL |
84 CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP,
85 &regs->pll_reg_5);
86
87 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, &regs->ssc_reg);
88
89 writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 |
90 LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL,
91 &regs->tx_common);
92
93 writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM,
94 &regs->dp_aux);
95
96 writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG,
97 &regs->dp_bias);
98
99 writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL,
100 &regs->dp_reserv2);
101}
102
103static void rk_edp_init_interrupt(struct rk3288_edp *regs)
104{
105 /* Set interrupt pin assertion polarity as high */
106 writel(INT_POL, &regs->int_ctl);
107
108 /* Clear pending registers */
109 writel(0xff, &regs->common_int_sta_1);
110 writel(0x4f, &regs->common_int_sta_2);
111 writel(0xff, &regs->common_int_sta_3);
112 writel(0x27, &regs->common_int_sta_4);
113 writel(0x7f, &regs->dp_int_sta);
114
115 /* 0:mask,1: unmask */
116 writel(0x00, &regs->common_int_mask_1);
117 writel(0x00, &regs->common_int_mask_2);
118 writel(0x00, &regs->common_int_mask_3);
119 writel(0x00, &regs->common_int_mask_4);
120 writel(0x00, &regs->int_sta_mask);
121}
122
123static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
124{
125 clrbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
126}
127
128static bool rk_edp_get_pll_locked(struct rk3288_edp *regs)
129{
130 u32 val;
131
132 val = readl(&regs->dp_debug_ctl);
133
134 return val & PLL_LOCK;
135}
136
137static int rk_edp_init_analog_func(struct rk3288_edp *regs)
138{
139 ulong start;
140
141 writel(0x00, &regs->dp_pd);
142 writel(PLL_LOCK_CHG, &regs->common_int_sta_1);
143
144 clrbits_le32(&regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
145
146 start = get_timer(0);
147 while (!rk_edp_get_pll_locked(regs)) {
148 if (get_timer(start) > PLL_LOCK_TIMEOUT) {
149 printf("%s: PLL is not locked\n", __func__);
150 return -ETIMEDOUT;
151 }
152 }
153
154 /* Enable Serdes FIFO function and Link symbol clock domain module */
155 clrbits_le32(&regs->func_en_2, SERDES_FIFO_FUNC_EN_N |
156 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N |
157 SSC_FUNC_EN_N);
158
159 return 0;
160}
161
162static void rk_edp_init_aux(struct rk3288_edp *regs)
163{
164 /* Clear inerrupts related to AUX channel */
165 writel(AUX_FUNC_EN_N, &regs->dp_int_sta);
166
167 /* Disable AUX channel module */
168 setbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);
169
170 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
171 writel(DEFER_CTRL_EN | DEFER_COUNT(1), &regs->aux_ch_defer_dtl);
172
173 /* Enable AUX channel module */
174 clrbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);
175}
176
177static int rk_edp_aux_enable(struct rk3288_edp *regs)
178{
179 ulong start;
180
181 setbits_le32(&regs->aux_ch_ctl_2, AUX_EN);
182 start = get_timer(0);
183 do {
184 if (!(readl(&regs->aux_ch_ctl_2) & AUX_EN))
185 return 0;
186 } while (get_timer(start) < 20);
187
188 return -ETIMEDOUT;
189}
190
191static int rk_edp_is_aux_reply(struct rk3288_edp *regs)
192{
193 ulong start;
194
195 start = get_timer(0);
196 while (!(readl(&regs->dp_int_sta) & RPLY_RECEIV)) {
197 if (get_timer(start) > 10)
198 return -ETIMEDOUT;
199 }
200
201 writel(RPLY_RECEIV, &regs->dp_int_sta);
202
203 return 0;
204}
205
206static int rk_edp_start_aux_transaction(struct rk3288_edp *regs)
207{
208 int val, ret;
209
210 /* Enable AUX CH operation */
211 ret = rk_edp_aux_enable(regs);
212 if (ret) {
213 debug("AUX CH enable timeout!\n");
214 return ret;
215 }
216
217 /* Is AUX CH command reply received? */
218 if (rk_edp_is_aux_reply(regs)) {
219 debug("AUX CH command reply failed!\n");
220 return ret;
221 }
222
223 /* Clear interrupt source for AUX CH access error */
224 val = readl(&regs->dp_int_sta);
225 if (val & AUX_ERR) {
226 writel(AUX_ERR, &regs->dp_int_sta);
227 return -EIO;
228 }
229
230 /* Check AUX CH error access status */
231 val = readl(&regs->dp_int_sta);
232 if (val & AUX_STATUS_MASK) {
233 debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK);
234 return -EIO;
235 }
236
237 return 0;
238}
239
240static int rk_edp_dpcd_transfer(struct rk3288_edp *regs,
241 unsigned int val_addr, u8 *in_data,
242 unsigned int length,
243 enum dpcd_request request)
244{
245 int val;
246 int i, try_times;
247 u8 *data;
248 int ret = 0;
249 u32 len = 0;
250
251 while (length) {
252 len = min(length, 16U);
253 for (try_times = 0; try_times < 10; try_times++) {
254 data = in_data;
255 /* Clear AUX CH data buffer */
256 writel(BUF_CLR, &regs->buf_data_ctl);
257
258 /* Select DPCD device address */
259 writel(AUX_ADDR_7_0(val_addr), &regs->aux_addr_7_0);
260 writel(AUX_ADDR_15_8(val_addr), &regs->aux_addr_15_8);
261 writel(AUX_ADDR_19_16(val_addr), &regs->aux_addr_19_16);
262
263 /*
264 * Set DisplayPort transaction and read 1 byte
265 * If bit 3 is 1, DisplayPort transaction.
266 * If Bit 3 is 0, I2C transaction.
267 */
268 if (request == DPCD_WRITE) {
269 val = AUX_LENGTH(len) |
270 AUX_TX_COMM_DP_TRANSACTION |
271 AUX_TX_COMM_WRITE;
272 for (i = 0; i < len; i++)
273 writel(*data++, &regs->buf_data[i]);
274 } else
275 val = AUX_LENGTH(len) |
276 AUX_TX_COMM_DP_TRANSACTION |
277 AUX_TX_COMM_READ;
278
279 writel(val, &regs->aux_ch_ctl_1);
280
281 /* Start AUX transaction */
282 ret = rk_edp_start_aux_transaction(regs);
283 if (ret == 0)
284 break;
285 else
286 printf("read dpcd Aux Transaction fail!\n");
287 }
288
289 if (ret)
290 return ret;
291
292 if (request == DPCD_READ) {
293 for (i = 0; i < len; i++)
294 *data++ = (u8)readl(&regs->buf_data[i]);
295 }
296
297 length -= len;
298 val_addr += len;
299 in_data += len;
300 }
301
302 return 0;
303}
304
305static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values,
306 size_t size)
307{
308 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ);
309}
310
311static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values,
312 size_t size)
313{
314 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE);
315}
316
317
318static int rk_edp_link_power_up(struct rk_edp_priv *edp)
319{
320 u8 value;
321 int ret;
322
323 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
324 if (edp->link_train.revision < 0x11)
325 return 0;
326
327 ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
328 if (ret)
329 return ret;
330
331 value &= ~DP_SET_POWER_MASK;
332 value |= DP_SET_POWER_D0;
333
334 ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
335 if (ret)
336 return ret;
337
338 /*
339 * According to the DP 1.1 specification, a "Sink Device must exit the
340 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
341 * Control Field" (register 0x600).
342 */
343 mdelay(1);
344
345 return 0;
346}
347
348static int rk_edp_link_configure(struct rk_edp_priv *edp)
349{
350 u8 values[2];
351
352 values[0] = edp->link_train.link_rate;
353 values[1] = edp->link_train.lane_count;
354
355 return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values,
356 sizeof(values));
357}
358
359static void rk_edp_set_link_training(struct rk_edp_priv *edp,
360 const u8 *training_values)
361{
362 int i;
363
364 for (i = 0; i < edp->link_train.lane_count; i++)
365 writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);
366}
367
368static u8 edp_link_status(const u8 *link_status, int r)
369{
370 return link_status[r - DPCD_LANE0_1_STATUS];
371}
372
373static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp,
374 u8 *link_status)
375{
376 return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status,
377 DP_LINK_STATUS_SIZE);
378}
379
380static u8 edp_get_lane_status(const u8 *link_status, int lane)
381{
382 int i = DPCD_LANE0_1_STATUS + (lane >> 1);
383 int s = (lane & 1) * 4;
384 u8 l = edp_link_status(link_status, i);
385
386 return (l >> s) & 0xf;
387}
388
389static int rk_edp_clock_recovery(const u8 *link_status, int lane_count)
390{
391 int lane;
392 u8 lane_status;
393
394 for (lane = 0; lane < lane_count; lane++) {
395 lane_status = edp_get_lane_status(link_status, lane);
396 if ((lane_status & DP_LANE_CR_DONE) == 0)
397 return -EIO;
398 }
399
400 return 0;
401}
402
403static int rk_edp_channel_eq(const u8 *link_status, int lane_count)
404{
405 u8 lane_align;
406 u8 lane_status;
407 int lane;
408
409 lane_align = edp_link_status(link_status,
410 DPCD_LANE_ALIGN_STATUS_UPDATED);
411 if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
412 return -EIO;
413 for (lane = 0; lane < lane_count; lane++) {
414 lane_status = edp_get_lane_status(link_status, lane);
415 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
416 return -EIO;
417 }
418
419 return 0;
420}
421
422static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane)
423{
424 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
425 int s = ((lane & 1) ?
426 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
427 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
428 u8 l = edp_link_status(link_status, i);
429
430 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
431}
432
433static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status,
434 int lane)
435{
436 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
437 int s = ((lane & 1) ?
438 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
439 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
440 u8 l = edp_link_status(link_status, i);
441
442 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
443}
444
445static void edp_get_adjust_train(const u8 *link_status, int lane_count,
446 u8 train_set[])
447{
448 uint v = 0;
449 uint p = 0;
450 int lane;
451
452 for (lane = 0; lane < lane_count; lane++) {
453 uint this_v, this_p;
454
455 this_v = rk_edp_get_adjust_request_voltage(link_status, lane);
456 this_p = rk_edp_get_adjust_request_pre_emphasis(link_status,
457 lane);
458
459 debug("requested signal parameters: lane %d voltage %s pre_emph %s\n",
460 lane,
461 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
462 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
463
464 if (this_v > v)
465 v = this_v;
466 if (this_p > p)
467 p = this_p;
468 }
469
470 if (v >= DP_VOLTAGE_MAX)
471 v |= DP_TRAIN_MAX_SWING_REACHED;
472
473 if (p >= DP_PRE_EMPHASIS_MAX)
474 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
475
476 debug("using signal parameters: voltage %s pre_emph %s\n",
477 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK)
478 >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
479 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK)
480 >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
481
482 for (lane = 0; lane < 4; lane++)
483 train_set[lane] = v | p;
484}
485
486static int rk_edp_link_train_cr(struct rk_edp_priv *edp)
487{
488 struct rk3288_edp *regs = edp->regs;
489 int clock_recovery;
490 uint voltage, tries = 0;
491 u8 status[DP_LINK_STATUS_SIZE];
492 int i, ret;
493 u8 value;
494
495 value = DP_TRAINING_PATTERN_1;
496 writel(value, &regs->dp_training_ptn_set);
497 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
498 if (ret)
499 return ret;
500 memset(edp->train_set, '\0', sizeof(edp->train_set));
501
502 /* clock recovery loop */
503 clock_recovery = 0;
504 tries = 0;
505 voltage = 0xff;
506
507 while (1) {
508 rk_edp_set_link_training(edp, edp->train_set);
509 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
510 edp->train_set,
511 edp->link_train.lane_count);
512 if (ret)
513 return ret;
514
515 mdelay(1);
516
517 ret = rk_edp_dpcd_read_link_status(edp, status);
518 if (ret) {
519 printf("displayport link status failed, ret=%d\n", ret);
520 break;
521 }
522
523 clock_recovery = rk_edp_clock_recovery(status,
524 edp->link_train.lane_count);
525 if (!clock_recovery)
526 break;
527
528 for (i = 0; i < edp->link_train.lane_count; i++) {
529 if ((edp->train_set[i] &
530 DP_TRAIN_MAX_SWING_REACHED) == 0)
531 break;
532 }
533 if (i == edp->link_train.lane_count) {
534 printf("clock recovery reached max voltage\n");
535 break;
536 }
537
538 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
539 voltage) {
540 if (++tries == MAX_CR_LOOP) {
541 printf("clock recovery tried 5 times\n");
542 break;
543 }
544 } else {
545 tries = 0;
546 }
547
548 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
549
550 /* Compute new train_set as requested by sink */
551 edp_get_adjust_train(status, edp->link_train.lane_count,
552 edp->train_set);
553 }
554 if (clock_recovery) {
555 printf("clock recovery failed: %d\n", clock_recovery);
556 return clock_recovery;
557 } else {
558 debug("clock recovery at voltage %d pre-emphasis %d\n",
559 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
560 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
561 DP_TRAIN_PRE_EMPHASIS_SHIFT);
562 return 0;
563 }
564}
565
566static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
567{
568 struct rk3288_edp *regs = edp->regs;
569 int channel_eq;
570 u8 value;
571 int tries;
572 u8 status[DP_LINK_STATUS_SIZE];
573 int ret;
574
575 value = DP_TRAINING_PATTERN_2;
576 writel(value, &regs->dp_training_ptn_set);
577 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
578 if (ret)
579 return ret;
580
581 /* channel equalization loop */
582 channel_eq = 0;
583 for (tries = 0; tries < 5; tries++) {
584 rk_edp_set_link_training(edp, edp->train_set);
127c8d85
ANY		 585 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
586 edp->train_set,
587 edp->link_train.lane_count);
588 if (ret)
589 return ret;
590
5852d539
SG		 591 udelay(400);
592
593 if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
594 printf("displayport link status failed\n");
595 return -1;
596 }
597
598 channel_eq = rk_edp_channel_eq(status,
599 edp->link_train.lane_count);
600 if (!channel_eq)
601 break;
602 edp_get_adjust_train(status, edp->link_train.lane_count,
603 edp->train_set);
604 }
605
606 if (channel_eq) {
607 printf("channel eq failed, ret=%d\n", channel_eq);
608 return channel_eq;
609 }
610
611 debug("channel eq at voltage %d pre-emphasis %d\n",
612 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
613 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
614 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
615
616 return 0;
617}
618
619static int rk_edp_init_training(struct rk_edp_priv *edp)
620{
621 u8 values[3];
622 int ret;
623
624 ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values,
625 sizeof(values));
626 if (ret < 0)
627 return ret;
628
629 edp->link_train.revision = values[0];
630 edp->link_train.link_rate = values[1];
631 edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK;
632
633 debug("max link rate:%d.%dGps max number of lanes:%d\n",
634 edp->link_train.link_rate * 27 / 100,
635 edp->link_train.link_rate * 27 % 100,
636 edp->link_train.lane_count);
637
638 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
639 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
640 debug("Rx Max Link Rate is abnormal :%x\n",
641 edp->link_train.link_rate);
642 return -EPERM;
643 }
644
645 if (edp->link_train.lane_count == 0) {
646 debug("Rx Max Lane count is abnormal :%x\n",
647 edp->link_train.lane_count);
648 return -EPERM;
649 }
650
651 ret = rk_edp_link_power_up(edp);
652 if (ret)
653 return ret;
654
655 return rk_edp_link_configure(edp);
656}
657
658static int rk_edp_hw_link_training(struct rk_edp_priv *edp)
659{
660 ulong start;
661 u32 val;
662 int ret;
663
664 /* Set link rate and count as you want to establish */
665 writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
666 writel(edp->link_train.lane_count, &edp->regs->lane_count_set);
667
668 ret = rk_edp_link_train_cr(edp);
669 if (ret)
670 return ret;
671 ret = rk_edp_link_train_ce(edp);
672 if (ret)
673 return ret;
674
675 writel(HW_LT_EN, &edp->regs->dp_hw_link_training);
676 start = get_timer(0);
677 do {
678 val = readl(&edp->regs->dp_hw_link_training);
679 if (!(val & HW_LT_EN))
680 break;
681 } while (get_timer(start) < 10);
682
683 if (val & HW_LT_ERR_CODE_MASK) {
684 printf("edp hw link training error: %d\n",
685 val >> HW_LT_ERR_CODE_SHIFT);
686 return -EIO;
687 }
688
689 return 0;
690}
691
692static int rk_edp_select_i2c_device(struct rk3288_edp *regs,
693 unsigned int device_addr,
694 unsigned int val_addr)
695{
696 int ret;
697
698 /* Set EDID device address */
699 writel(device_addr, &regs->aux_addr_7_0);
700 writel(0x0, &regs->aux_addr_15_8);
701 writel(0x0, &regs->aux_addr_19_16);
702
703 /* Set offset from base address of EDID device */
704 writel(val_addr, &regs->buf_data[0]);
705
706 /*
707 * Set I2C transaction and write address
708 * If bit 3 is 1, DisplayPort transaction.
709 * If Bit 3 is 0, I2C transaction.
710 */
711 writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
712 AUX_TX_COMM_WRITE, &regs->aux_ch_ctl_1);
713
714 /* Start AUX transaction */
715 ret = rk_edp_start_aux_transaction(regs);
716 if (ret != 0) {
717 debug("select_i2c_device Aux Transaction fail!\n");
718 return ret;
719 }
720
721 return 0;
722}
723
724static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr,
725 unsigned int val_addr, unsigned int count, u8 edid[])
726{
727 u32 val;
728 unsigned int i, j;
729 unsigned int cur_data_idx;
730 unsigned int defer = 0;
731 int ret = 0;
732
733 for (i = 0; i < count; i += 16) {
734 for (j = 0; j < 10; j++) { /* try 10 times */
735 /* Clear AUX CH data buffer */
736 writel(BUF_CLR, &regs->buf_data_ctl);
737
738 /* Set normal AUX CH command */
739 clrbits_le32(&regs->aux_ch_ctl_2, ADDR_ONLY);
740
741 /*
742 * If Rx sends defer, Tx sends only reads
743 * request without sending addres
744 */
745 if (!defer) {
746 ret = rk_edp_select_i2c_device(regs,
747 device_addr,
748 val_addr + i);
749 } else {
750 defer = 0;
751 }
752
753 /*
754 * Set I2C transaction and write data
755 * If bit 3 is 1, DisplayPort transaction.
756 * If Bit 3 is 0, I2C transaction.
757 */
758 writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
759 AUX_TX_COMM_READ, &regs->aux_ch_ctl_1);
760
761 /* Start AUX transaction */
762 ret = rk_edp_start_aux_transaction(regs);
763 if (ret == 0) {
764 break;
765 } else {
766 debug("Aux Transaction fail!\n");
767 continue;
768 }
769
770 /* Check if Rx sends defer */
771 val = readl(&regs->aux_rx_comm);
772 if (val == AUX_RX_COMM_AUX_DEFER ||
773 val == AUX_RX_COMM_I2C_DEFER) {
774 debug("Defer: %d\n\n", val);
775 defer = 1;
776 }
777 }
778
779 if (ret)
780 return ret;
781
782 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
783 val = readl(&regs->buf_data[cur_data_idx]);
784 edid[i + cur_data_idx] = (u8)val;
785 }
786 }
787
788 return 0;
789}
790
791static int rk_edp_set_link_train(struct rk_edp_priv *edp)
792{
793 int ret;
794
795 ret = rk_edp_init_training(edp);
796 if (ret) {
797 printf("DP LT init failed!\n");
798 return ret;
799 }
800
801 ret = rk_edp_hw_link_training(edp);
802 if (ret)
803 return ret;
804
805 return 0;
806}
807
808static void rk_edp_init_video(struct rk3288_edp *regs)
809{
810 writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG,
811 &regs->common_int_sta_1);
812 writel(CHA_CRI(4) | CHA_CTRL, &regs->sys_ctl_2);
813 writel(VID_HRES_TH(2) | VID_VRES_TH(0), &regs->video_ctl_8);
814}
815
816static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs)
817{
818 clrbits_le32(&regs->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
819}
820
821static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs,
822 enum clock_recovery_m_value_type type,
823 u32 m_value,
824 u32 n_value)
825{
826 if (type == REGISTER_M) {
827 setbits_le32(&regs->sys_ctl_4, FIX_M_VID);
828 writel(m_value & 0xff, &regs->m_vid_0);
829 writel((m_value >> 8) & 0xff, &regs->m_vid_1);
830 writel((m_value >> 16) & 0xff, &regs->m_vid_2);
831
832 writel(n_value & 0xf, &regs->n_vid_0);
833 writel((n_value >> 8) & 0xff, &regs->n_vid_1);
834 writel((n_value >> 16) & 0xff, &regs->n_vid_2);
835 } else {
836 clrbits_le32(&regs->sys_ctl_4, FIX_M_VID);
837
838 writel(0x00, &regs->n_vid_0);
839 writel(0x80, &regs->n_vid_1);
840 writel(0x00, &regs->n_vid_2);
841 }
842}
843
844static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs)
845{
846 ulong start;
847 u32 val;
848
849 start = get_timer(0);
850 do {
851 val = readl(&regs->sys_ctl_1);
852
853 /* must write value to update DET_STA bit status */
854 writel(val, &regs->sys_ctl_1);
855 val = readl(&regs->sys_ctl_1);
856 if (!(val & DET_STA))
857 continue;
858
859 val = readl(&regs->sys_ctl_2);
860
861 /* must write value to update CHA_STA bit status */
862 writel(val, &regs->sys_ctl_2);
863 val = readl(&regs->sys_ctl_2);
864 if (!(val & CHA_STA))
865 return 0;
866
867 } while (get_timer(start) < 100);
868
869 return -ETIMEDOUT;
870}
871
872static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp)
873{
874 ulong start;
875 u32 val;
876
877 start = get_timer(0);
878 do {
879 val = readl(&edp->regs->sys_ctl_3);
880
881 /* must write value to update STRM_VALID bit status */
882 writel(val, &edp->regs->sys_ctl_3);
883
884 val = readl(&edp->regs->sys_ctl_3);
885 if (!(val & STRM_VALID))
886 return 0;
887 } while (get_timer(start) < 100);
888
889 return -ETIMEDOUT;
890}
891
892static int rk_edp_config_video(struct rk_edp_priv *edp)
893{
894 int ret;
895
896 rk_edp_config_video_slave_mode(edp->regs);
897
898 if (!rk_edp_get_pll_locked(edp->regs)) {
899 debug("PLL is not locked yet.\n");
900 return -ETIMEDOUT;
901 }
902
903 ret = rk_edp_is_video_stream_clock_on(edp->regs);
904 if (ret)
905 return ret;
906
907 /* Set to use the register calculated M/N video */
908 rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0);
909
910 /* For video bist, Video timing must be generated by register */
911 clrbits_le32(&edp->regs->video_ctl_10, F_SEL);
912
913 /* Disable video mute */
914 clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE);
915
916 /* Enable video at next frame */
917 setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN);
918
919 return rk_edp_is_video_stream_on(edp);
920}
921
922static void rockchip_edp_force_hpd(struct rk_edp_priv *edp)
923{
924 setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL);
925}
926
927static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp)
928{
929 u32 val;
930
931 val = readl(&edp->regs->sys_ctl_3);
932 if (val & HPD_STATUS)
933 return 1;
934
935 return 0;
936}
937
938/*
939 * support edp HPD function
940 * some hardware version do not support edp hdp,
941 * we use 200ms to try to get the hpd single now,
942 * if we can not get edp hpd single, it will delay 200ms,
943 * also meet the edp power timing request, to compatible
944 * all of the hardware version
945 */
946static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp)
947{
948 ulong start;
949
950 start = get_timer(0);
951 do {
952 if (rockchip_edp_get_plug_in_status(edp))
953 return;
954 udelay(100);
955 } while (get_timer(start) < 200);
956
957 debug("do not get hpd single, force hpd\n");
958 rockchip_edp_force_hpd(edp);
959}
960
961static int rk_edp_enable(struct udevice *dev, int panel_bpp,
962 const struct display_timing *edid)
963{
964 struct rk_edp_priv *priv = dev_get_priv(dev);
965 int ret = 0;
966
967 ret = rk_edp_set_link_train(priv);
968 if (ret) {
969 printf("link train failed!\n");
970 return ret;
971 }
972
973 rk_edp_init_video(priv->regs);
974 ret = rk_edp_config_video(priv);
975 if (ret) {
976 printf("config video failed\n");
977 return ret;
978 }
979 ret = panel_enable_backlight(priv->panel);
980 if (ret) {
981 debug("%s: backlight error: %d\n", __func__, ret);
982 return ret;
983 }
984
985 return 0;
986}
987
988static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
989{
990 struct rk_edp_priv *priv = dev_get_priv(dev);
991 u32 edid_size = EDID_LENGTH;
992 int ret;
993 int i;
994
995 for (i = 0; i < 3; i++) {
996 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER,
997 EDID_LENGTH, &buf[EDID_HEADER]);
998 if (ret) {
999 debug("EDID read failed\n");
1000 continue;
1001 }
1002
1003 /*
1004 * check if the EDID has an extension flag, and read additional
1005 * EDID data if needed
1006 */
1007 if (buf[EDID_EXTENSION_FLAG]) {
1008 edid_size += EDID_LENGTH;
1009 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR,
1010 EDID_LENGTH, EDID_LENGTH,
1011 &buf[EDID_LENGTH]);
1012 if (ret) {
1013 debug("EDID Read failed!\n");
1014 continue;
1015 }
1016 }
1017 goto done;
1018 }
1019
1020 /* After 3 attempts, give up */
1021 return ret;
1022
1023done:
1024 return edid_size;
1025}
1026
d1998a9f 1027static int rk_edp_of_to_plat(struct udevice *dev)
5852d539
SG		 1028{
1029 struct rk_edp_priv *priv = dev_get_priv(dev);
1030
653ac184 1031 priv->regs = dev_read_addr_ptr(dev);
5852d539
SG		 1032 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1033
1034 return 0;
1035}
1036
f418676e
SG		 1037static int rk_edp_remove(struct udevice *dev)
1038{
1039 struct rk_edp_priv *priv = dev_get_priv(dev);
1040 struct rk3288_edp *regs = priv->regs;
1041
1042 setbits_le32(&regs->video_ctl_1, VIDEO_MUTE);
1043 clrbits_le32(&regs->video_ctl_1, VIDEO_EN);
1044 clrbits_le32(&regs->sys_ctl_3, F_HPD | HPD_CTRL);
1045 setbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
1046
1047 return 0;
1048}
1049
1050static int rk_edp_probe(struct udevice *dev)
5852d539 1051{
caa4daa2 1052 struct display_plat *uc_plat = dev_get_uclass_plat(dev);
5852d539
SG		 1053 struct rk_edp_priv *priv = dev_get_priv(dev);
1054 struct rk3288_edp *regs = priv->regs;
04d67ceb 1055 struct rockchip_dp_data *edp_data = (struct rockchip_dp_data *)dev_get_driver_data(dev);
cd529f7a 1056 struct reset_ctl dp_rst;
04d67ceb 1057
135aa950 1058 struct clk clk;
5852d539
SG		 1059 int ret;
1060
1061 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
1062 &priv->panel);
1063 if (ret) {
1064 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
1065 dev->name, ret);
1066 return ret;
1067 }
1068
cd529f7a
APR		 1069 ret = reset_get_by_name(dev, "dp", &dp_rst);
1070 if (ret) {
0944e77f
JJ		 1071 ret = reset_get_by_name(dev, "edp", &dp_rst);
1072 if (ret) {
1073 dev_err(dev, "failed to get dp reset (ret=%d)\n", ret);
1074 return ret;
1075 }
cd529f7a
APR		 1076 }
1077
1078 ret = reset_assert(&dp_rst);
1079 if (ret) {
1080 dev_err(dev, "failed to assert dp reset (ret=%d)\n", ret);
1081 return ret;
1082 }
1083 udelay(20);
1084
1085 ret = reset_deassert(&dp_rst);
1086 if (ret) {
1087 dev_err(dev, "failed to deassert dp reset (ret=%d)\n", ret);
1088 return ret;
1089 }
1090
5852d539
SG		 1091 int vop_id = uc_plat->source_id;
1092 debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id);
1093
04d67ceb
APR		 1094 if (edp_data->chip_type == RK3288_DP) {
1095 ret = clk_get_by_index(dev, 1, &clk);
c9309f40 1096 if (ret >= 0)
04d67ceb 1097 ret = clk_set_rate(&clk, 0);
04d67ceb
APR		 1098 if (ret) {
1099 debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
1100 return ret;
1101 }
5852d539 1102 }
5852d539 1103 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
c9309f40 1104 if (ret >= 0)
135aa950 1105 ret = clk_set_rate(&clk, 192000000);
5852d539
SG		 1106 if (ret < 0) {
1107 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
1108 __func__, uc_plat->src_dev->name, ret);
1109 return ret;
1110 }
1111
1112 /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
04d67ceb
APR		 1113 rk_setreg(priv->grf + edp_data->reg_ref_clk_sel,
1114 edp_data->ref_clk_sel_bit);
5852d539
SG		 1115
1116 /* select epd signal from vop0 or vop1 */
04d67ceb
APR		 1117 rk_clrsetreg(priv->grf + edp_data->reg_vop_big_little,
1118 edp_data->reg_vop_big_little_sel,
1119 (vop_id == 1) ? edp_data->reg_vop_big_little_sel : 0);
5852d539
SG		 1120
1121 rockchip_edp_wait_hpd(priv);
1122
04d67ceb 1123 rk_edp_init_refclk(regs, edp_data->chip_type);
5852d539
SG		 1124 rk_edp_init_interrupt(regs);
1125 rk_edp_enable_sw_function(regs);
1126 ret = rk_edp_init_analog_func(regs);
1127 if (ret)
1128 return ret;
1129 rk_edp_init_aux(regs);
1130
1131 return 0;
1132}
1133
1134static const struct dm_display_ops dp_rockchip_ops = {
1135 .read_edid = rk_edp_read_edid,
1136 .enable = rk_edp_enable,
1137};
1138
04d67ceb
APR		 1139static const struct rockchip_dp_data rk3399_edp = {
1140 .reg_vop_big_little = RK3399_GRF_SOC_CON20,
1141 .reg_vop_big_little_sel = BIT(5),
1142 .reg_ref_clk_sel = RK3399_GRF_SOC_CON25,
1143 .ref_clk_sel_bit = BIT(11),
1144 .chip_type = RK3399_EDP,
1145};
1146
1147static const struct rockchip_dp_data rk3288_dp = {
1148 .reg_vop_big_little = RK3288_GRF_SOC_CON6,
1149 .reg_vop_big_little_sel = BIT(5),
1150 .reg_ref_clk_sel = RK3288_GRF_SOC_CON12,
1151 .ref_clk_sel_bit = BIT(4),
1152 .chip_type = RK3288_DP,
1153};
1154
5852d539 1155static const struct udevice_id rockchip_dp_ids[] = {
0944e77f 1156 { .compatible = "rockchip,rk3288-dp", .data = (ulong)&rk3288_dp },
04d67ceb
APR		 1157 { .compatible = "rockchip,rk3288-edp", .data = (ulong)&rk3288_dp },
1158 { .compatible = "rockchip,rk3399-edp", .data = (ulong)&rk3399_edp },
5852d539
SG		 1159 { }
1160};
1161
1162U_BOOT_DRIVER(dp_rockchip) = {
1163 .name = "edp_rockchip",
1164 .id = UCLASS_DISPLAY,
1165 .of_match = rockchip_dp_ids,
1166 .ops = &dp_rockchip_ops,
d1998a9f 1167 .of_to_plat = rk_edp_of_to_plat,
5852d539 1168 .probe = rk_edp_probe,
f418676e 1169 .remove = rk_edp_remove,
41575d8e 1170 .priv_auto = sizeof(struct rk_edp_priv),
5852d539 1171};
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