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rockchip: gru: Allow setting up clocks in U-Boot proper
[J-u-boot.git] / drivers / video / rockchip / rk_edp.c
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83d290c5 1// SPDX-License-Identifier: GPL-2.0+
5852d539
SG		 2/*
3 * Copyright (c) 2015 Google, Inc
4 * Copyright 2014 Rockchip Inc.
5852d539
SG		 5 */
6
7#include <common.h>
8#include <clk.h>
9#include <display.h>
10#include <dm.h>
11#include <edid.h>
f7ae49fc 12#include <log.h>
336d4615 13#include <malloc.h>
5852d539
SG		 14#include <panel.h>
15#include <regmap.h>
16#include <syscon.h>
17#include <asm/gpio.h>
18#include <asm/io.h>
15f09a1a
KY		 19#include <asm/arch-rockchip/clock.h>
20#include <asm/arch-rockchip/edp_rk3288.h>
21#include <asm/arch-rockchip/grf_rk3288.h>
973e31fd 22#include <asm/arch-rockchip/hardware.h>
5852d539 23#include <dt-bindings/clock/rk3288-cru.h>
c05ed00a 24#include <linux/delay.h>
5852d539 25
5852d539
SG		 26#define MAX_CR_LOOP 5
27#define MAX_EQ_LOOP 5
28#define DP_LINK_STATUS_SIZE 6
29
30static const char * const voltage_names[] = {
31 "0.4V", "0.6V", "0.8V", "1.2V"
32};
33static const char * const pre_emph_names[] = {
34 "0dB", "3.5dB", "6dB", "9.5dB"
35};
36
37#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
38#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
39
40struct rk_edp_priv {
41 struct rk3288_edp *regs;
42 struct rk3288_grf *grf;
43 struct udevice *panel;
44 struct link_train link_train;
45 u8 train_set[4];
46};
47
48static void rk_edp_init_refclk(struct rk3288_edp *regs)
49{
50 writel(SEL_24M, &regs->analog_ctl_2);
51 writel(REF_CLK_24M, &regs->pll_reg_1);
52
53 writel(LDO_OUTPUT_V_SEL_145 | KVCO_DEFALUT | CHG_PUMP_CUR_SEL_5US |
54 V2L_CUR_SEL_1MA, &regs->pll_reg_2);
55
56 writel(LOCK_DET_CNT_SEL_256 | LOOP_FILTER_RESET | PALL_SSC_RESET |
57 LOCK_DET_BYPASS | PLL_LOCK_DET_MODE | PLL_LOCK_DET_FORCE,
58 &regs->pll_reg_3);
59
60 writel(REGULATOR_V_SEL_950MV | STANDBY_CUR_SEL |
61 CHG_PUMP_INOUT_CTRL_1200MV | CHG_PUMP_INPUT_CTRL_OP,
62 &regs->pll_reg_5);
63
64 writel(SSC_OFFSET | SSC_MODE | SSC_DEPTH, &regs->ssc_reg);
65
66 writel(TX_SWING_PRE_EMP_MODE | PRE_DRIVER_PW_CTRL1 |
67 LP_MODE_CLK_REGULATOR | RESISTOR_MSB_CTRL | RESISTOR_CTRL,
68 &regs->tx_common);
69
70 writel(DP_AUX_COMMON_MODE | DP_AUX_EN | AUX_TERM_50OHM,
71 &regs->dp_aux);
72
73 writel(DP_BG_OUT_SEL | DP_DB_CUR_CTRL | DP_BG_SEL | DP_RESISTOR_TUNE_BG,
74 &regs->dp_bias);
75
76 writel(CH1_CH3_SWING_EMP_CTRL | CH0_CH2_SWING_EMP_CTRL,
77 &regs->dp_reserv2);
78}
79
80static void rk_edp_init_interrupt(struct rk3288_edp *regs)
81{
82 /* Set interrupt pin assertion polarity as high */
83 writel(INT_POL, &regs->int_ctl);
84
85 /* Clear pending registers */
86 writel(0xff, &regs->common_int_sta_1);
87 writel(0x4f, &regs->common_int_sta_2);
88 writel(0xff, &regs->common_int_sta_3);
89 writel(0x27, &regs->common_int_sta_4);
90 writel(0x7f, &regs->dp_int_sta);
91
92 /* 0:mask,1: unmask */
93 writel(0x00, &regs->common_int_mask_1);
94 writel(0x00, &regs->common_int_mask_2);
95 writel(0x00, &regs->common_int_mask_3);
96 writel(0x00, &regs->common_int_mask_4);
97 writel(0x00, &regs->int_sta_mask);
98}
99
100static void rk_edp_enable_sw_function(struct rk3288_edp *regs)
101{
102 clrbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
103}
104
105static bool rk_edp_get_pll_locked(struct rk3288_edp *regs)
106{
107 u32 val;
108
109 val = readl(&regs->dp_debug_ctl);
110
111 return val & PLL_LOCK;
112}
113
114static int rk_edp_init_analog_func(struct rk3288_edp *regs)
115{
116 ulong start;
117
118 writel(0x00, &regs->dp_pd);
119 writel(PLL_LOCK_CHG, &regs->common_int_sta_1);
120
121 clrbits_le32(&regs->dp_debug_ctl, F_PLL_LOCK | PLL_LOCK_CTRL);
122
123 start = get_timer(0);
124 while (!rk_edp_get_pll_locked(regs)) {
125 if (get_timer(start) > PLL_LOCK_TIMEOUT) {
126 printf("%s: PLL is not locked\n", __func__);
127 return -ETIMEDOUT;
128 }
129 }
130
131 /* Enable Serdes FIFO function and Link symbol clock domain module */
132 clrbits_le32(&regs->func_en_2, SERDES_FIFO_FUNC_EN_N |
133 LS_CLK_DOMAIN_FUNC_EN_N | AUX_FUNC_EN_N |
134 SSC_FUNC_EN_N);
135
136 return 0;
137}
138
139static void rk_edp_init_aux(struct rk3288_edp *regs)
140{
141 /* Clear inerrupts related to AUX channel */
142 writel(AUX_FUNC_EN_N, &regs->dp_int_sta);
143
144 /* Disable AUX channel module */
145 setbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);
146
147 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
148 writel(DEFER_CTRL_EN | DEFER_COUNT(1), &regs->aux_ch_defer_dtl);
149
150 /* Enable AUX channel module */
151 clrbits_le32(&regs->func_en_2, AUX_FUNC_EN_N);
152}
153
154static int rk_edp_aux_enable(struct rk3288_edp *regs)
155{
156 ulong start;
157
158 setbits_le32(&regs->aux_ch_ctl_2, AUX_EN);
159 start = get_timer(0);
160 do {
161 if (!(readl(&regs->aux_ch_ctl_2) & AUX_EN))
162 return 0;
163 } while (get_timer(start) < 20);
164
165 return -ETIMEDOUT;
166}
167
168static int rk_edp_is_aux_reply(struct rk3288_edp *regs)
169{
170 ulong start;
171
172 start = get_timer(0);
173 while (!(readl(&regs->dp_int_sta) & RPLY_RECEIV)) {
174 if (get_timer(start) > 10)
175 return -ETIMEDOUT;
176 }
177
178 writel(RPLY_RECEIV, &regs->dp_int_sta);
179
180 return 0;
181}
182
183static int rk_edp_start_aux_transaction(struct rk3288_edp *regs)
184{
185 int val, ret;
186
187 /* Enable AUX CH operation */
188 ret = rk_edp_aux_enable(regs);
189 if (ret) {
190 debug("AUX CH enable timeout!\n");
191 return ret;
192 }
193
194 /* Is AUX CH command reply received? */
195 if (rk_edp_is_aux_reply(regs)) {
196 debug("AUX CH command reply failed!\n");
197 return ret;
198 }
199
200 /* Clear interrupt source for AUX CH access error */
201 val = readl(&regs->dp_int_sta);
202 if (val & AUX_ERR) {
203 writel(AUX_ERR, &regs->dp_int_sta);
204 return -EIO;
205 }
206
207 /* Check AUX CH error access status */
208 val = readl(&regs->dp_int_sta);
209 if (val & AUX_STATUS_MASK) {
210 debug("AUX CH error happens: %d\n\n", val & AUX_STATUS_MASK);
211 return -EIO;
212 }
213
214 return 0;
215}
216
217static int rk_edp_dpcd_transfer(struct rk3288_edp *regs,
218 unsigned int val_addr, u8 *in_data,
219 unsigned int length,
220 enum dpcd_request request)
221{
222 int val;
223 int i, try_times;
224 u8 *data;
225 int ret = 0;
226 u32 len = 0;
227
228 while (length) {
229 len = min(length, 16U);
230 for (try_times = 0; try_times < 10; try_times++) {
231 data = in_data;
232 /* Clear AUX CH data buffer */
233 writel(BUF_CLR, &regs->buf_data_ctl);
234
235 /* Select DPCD device address */
236 writel(AUX_ADDR_7_0(val_addr), &regs->aux_addr_7_0);
237 writel(AUX_ADDR_15_8(val_addr), &regs->aux_addr_15_8);
238 writel(AUX_ADDR_19_16(val_addr), &regs->aux_addr_19_16);
239
240 /*
241 * Set DisplayPort transaction and read 1 byte
242 * If bit 3 is 1, DisplayPort transaction.
243 * If Bit 3 is 0, I2C transaction.
244 */
245 if (request == DPCD_WRITE) {
246 val = AUX_LENGTH(len) |
247 AUX_TX_COMM_DP_TRANSACTION |
248 AUX_TX_COMM_WRITE;
249 for (i = 0; i < len; i++)
250 writel(*data++, &regs->buf_data[i]);
251 } else
252 val = AUX_LENGTH(len) |
253 AUX_TX_COMM_DP_TRANSACTION |
254 AUX_TX_COMM_READ;
255
256 writel(val, &regs->aux_ch_ctl_1);
257
258 /* Start AUX transaction */
259 ret = rk_edp_start_aux_transaction(regs);
260 if (ret == 0)
261 break;
262 else
263 printf("read dpcd Aux Transaction fail!\n");
264 }
265
266 if (ret)
267 return ret;
268
269 if (request == DPCD_READ) {
270 for (i = 0; i < len; i++)
271 *data++ = (u8)readl(&regs->buf_data[i]);
272 }
273
274 length -= len;
275 val_addr += len;
276 in_data += len;
277 }
278
279 return 0;
280}
281
282static int rk_edp_dpcd_read(struct rk3288_edp *regs, u32 addr, u8 *values,
283 size_t size)
284{
285 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_READ);
286}
287
288static int rk_edp_dpcd_write(struct rk3288_edp *regs, u32 addr, u8 *values,
289 size_t size)
290{
291 return rk_edp_dpcd_transfer(regs, addr, values, size, DPCD_WRITE);
292}
293
294
295static int rk_edp_link_power_up(struct rk_edp_priv *edp)
296{
297 u8 value;
298 int ret;
299
300 /* DP_SET_POWER register is only available on DPCD v1.1 and later */
301 if (edp->link_train.revision < 0x11)
302 return 0;
303
304 ret = rk_edp_dpcd_read(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
305 if (ret)
306 return ret;
307
308 value &= ~DP_SET_POWER_MASK;
309 value |= DP_SET_POWER_D0;
310
311 ret = rk_edp_dpcd_write(edp->regs, DPCD_LINK_POWER_STATE, &value, 1);
312 if (ret)
313 return ret;
314
315 /*
316 * According to the DP 1.1 specification, a "Sink Device must exit the
317 * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
318 * Control Field" (register 0x600).
319 */
320 mdelay(1);
321
322 return 0;
323}
324
325static int rk_edp_link_configure(struct rk_edp_priv *edp)
326{
327 u8 values[2];
328
329 values[0] = edp->link_train.link_rate;
330 values[1] = edp->link_train.lane_count;
331
332 return rk_edp_dpcd_write(edp->regs, DPCD_LINK_BW_SET, values,
333 sizeof(values));
334}
335
336static void rk_edp_set_link_training(struct rk_edp_priv *edp,
337 const u8 *training_values)
338{
339 int i;
340
341 for (i = 0; i < edp->link_train.lane_count; i++)
342 writel(training_values[i], &edp->regs->ln_link_trn_ctl[i]);
343}
344
345static u8 edp_link_status(const u8 *link_status, int r)
346{
347 return link_status[r - DPCD_LANE0_1_STATUS];
348}
349
350static int rk_edp_dpcd_read_link_status(struct rk_edp_priv *edp,
351 u8 *link_status)
352{
353 return rk_edp_dpcd_read(edp->regs, DPCD_LANE0_1_STATUS, link_status,
354 DP_LINK_STATUS_SIZE);
355}
356
357static u8 edp_get_lane_status(const u8 *link_status, int lane)
358{
359 int i = DPCD_LANE0_1_STATUS + (lane >> 1);
360 int s = (lane & 1) * 4;
361 u8 l = edp_link_status(link_status, i);
362
363 return (l >> s) & 0xf;
364}
365
366static int rk_edp_clock_recovery(const u8 *link_status, int lane_count)
367{
368 int lane;
369 u8 lane_status;
370
371 for (lane = 0; lane < lane_count; lane++) {
372 lane_status = edp_get_lane_status(link_status, lane);
373 if ((lane_status & DP_LANE_CR_DONE) == 0)
374 return -EIO;
375 }
376
377 return 0;
378}
379
380static int rk_edp_channel_eq(const u8 *link_status, int lane_count)
381{
382 u8 lane_align;
383 u8 lane_status;
384 int lane;
385
386 lane_align = edp_link_status(link_status,
387 DPCD_LANE_ALIGN_STATUS_UPDATED);
388 if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
389 return -EIO;
390 for (lane = 0; lane < lane_count; lane++) {
391 lane_status = edp_get_lane_status(link_status, lane);
392 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
393 return -EIO;
394 }
395
396 return 0;
397}
398
399static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane)
400{
401 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
402 int s = ((lane & 1) ?
403 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
404 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
405 u8 l = edp_link_status(link_status, i);
406
407 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
408}
409
410static uint rk_edp_get_adjust_request_pre_emphasis(const u8 *link_status,
411 int lane)
412{
413 int i = DPCD_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
414 int s = ((lane & 1) ?
415 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
416 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
417 u8 l = edp_link_status(link_status, i);
418
419 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
420}
421
422static void edp_get_adjust_train(const u8 *link_status, int lane_count,
423 u8 train_set[])
424{
425 uint v = 0;
426 uint p = 0;
427 int lane;
428
429 for (lane = 0; lane < lane_count; lane++) {
430 uint this_v, this_p;
431
432 this_v = rk_edp_get_adjust_request_voltage(link_status, lane);
433 this_p = rk_edp_get_adjust_request_pre_emphasis(link_status,
434 lane);
435
436 debug("requested signal parameters: lane %d voltage %s pre_emph %s\n",
437 lane,
438 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
439 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
440
441 if (this_v > v)
442 v = this_v;
443 if (this_p > p)
444 p = this_p;
445 }
446
447 if (v >= DP_VOLTAGE_MAX)
448 v |= DP_TRAIN_MAX_SWING_REACHED;
449
450 if (p >= DP_PRE_EMPHASIS_MAX)
451 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
452
453 debug("using signal parameters: voltage %s pre_emph %s\n",
454 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK)
455 >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
456 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK)
457 >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
458
459 for (lane = 0; lane < 4; lane++)
460 train_set[lane] = v | p;
461}
462
463static int rk_edp_link_train_cr(struct rk_edp_priv *edp)
464{
465 struct rk3288_edp *regs = edp->regs;
466 int clock_recovery;
467 uint voltage, tries = 0;
468 u8 status[DP_LINK_STATUS_SIZE];
469 int i, ret;
470 u8 value;
471
472 value = DP_TRAINING_PATTERN_1;
473 writel(value, &regs->dp_training_ptn_set);
474 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
475 if (ret)
476 return ret;
477 memset(edp->train_set, '\0', sizeof(edp->train_set));
478
479 /* clock recovery loop */
480 clock_recovery = 0;
481 tries = 0;
482 voltage = 0xff;
483
484 while (1) {
485 rk_edp_set_link_training(edp, edp->train_set);
486 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
487 edp->train_set,
488 edp->link_train.lane_count);
489 if (ret)
490 return ret;
491
492 mdelay(1);
493
494 ret = rk_edp_dpcd_read_link_status(edp, status);
495 if (ret) {
496 printf("displayport link status failed, ret=%d\n", ret);
497 break;
498 }
499
500 clock_recovery = rk_edp_clock_recovery(status,
501 edp->link_train.lane_count);
502 if (!clock_recovery)
503 break;
504
505 for (i = 0; i < edp->link_train.lane_count; i++) {
506 if ((edp->train_set[i] &
507 DP_TRAIN_MAX_SWING_REACHED) == 0)
508 break;
509 }
510 if (i == edp->link_train.lane_count) {
511 printf("clock recovery reached max voltage\n");
512 break;
513 }
514
515 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
516 voltage) {
517 if (++tries == MAX_CR_LOOP) {
518 printf("clock recovery tried 5 times\n");
519 break;
520 }
521 } else {
522 tries = 0;
523 }
524
525 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
526
527 /* Compute new train_set as requested by sink */
528 edp_get_adjust_train(status, edp->link_train.lane_count,
529 edp->train_set);
530 }
531 if (clock_recovery) {
532 printf("clock recovery failed: %d\n", clock_recovery);
533 return clock_recovery;
534 } else {
535 debug("clock recovery at voltage %d pre-emphasis %d\n",
536 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
537 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
538 DP_TRAIN_PRE_EMPHASIS_SHIFT);
539 return 0;
540 }
541}
542
543static int rk_edp_link_train_ce(struct rk_edp_priv *edp)
544{
545 struct rk3288_edp *regs = edp->regs;
546 int channel_eq;
547 u8 value;
548 int tries;
549 u8 status[DP_LINK_STATUS_SIZE];
550 int ret;
551
552 value = DP_TRAINING_PATTERN_2;
553 writel(value, &regs->dp_training_ptn_set);
554 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_PATTERN_SET, &value, 1);
555 if (ret)
556 return ret;
557
558 /* channel equalization loop */
559 channel_eq = 0;
560 for (tries = 0; tries < 5; tries++) {
561 rk_edp_set_link_training(edp, edp->train_set);
127c8d85
ANY		 562 ret = rk_edp_dpcd_write(regs, DPCD_TRAINING_LANE0_SET,
563 edp->train_set,
564 edp->link_train.lane_count);
565 if (ret)
566 return ret;
567
5852d539
SG		 568 udelay(400);
569
570 if (rk_edp_dpcd_read_link_status(edp, status) < 0) {
571 printf("displayport link status failed\n");
572 return -1;
573 }
574
575 channel_eq = rk_edp_channel_eq(status,
576 edp->link_train.lane_count);
577 if (!channel_eq)
578 break;
579 edp_get_adjust_train(status, edp->link_train.lane_count,
580 edp->train_set);
581 }
582
583 if (channel_eq) {
584 printf("channel eq failed, ret=%d\n", channel_eq);
585 return channel_eq;
586 }
587
588 debug("channel eq at voltage %d pre-emphasis %d\n",
589 edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
590 (edp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
591 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
592
593 return 0;
594}
595
596static int rk_edp_init_training(struct rk_edp_priv *edp)
597{
598 u8 values[3];
599 int ret;
600
601 ret = rk_edp_dpcd_read(edp->regs, DPCD_DPCD_REV, values,
602 sizeof(values));
603 if (ret < 0)
604 return ret;
605
606 edp->link_train.revision = values[0];
607 edp->link_train.link_rate = values[1];
608 edp->link_train.lane_count = values[2] & DP_MAX_LANE_COUNT_MASK;
609
610 debug("max link rate:%d.%dGps max number of lanes:%d\n",
611 edp->link_train.link_rate * 27 / 100,
612 edp->link_train.link_rate * 27 % 100,
613 edp->link_train.lane_count);
614
615 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
616 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
617 debug("Rx Max Link Rate is abnormal :%x\n",
618 edp->link_train.link_rate);
619 return -EPERM;
620 }
621
622 if (edp->link_train.lane_count == 0) {
623 debug("Rx Max Lane count is abnormal :%x\n",
624 edp->link_train.lane_count);
625 return -EPERM;
626 }
627
628 ret = rk_edp_link_power_up(edp);
629 if (ret)
630 return ret;
631
632 return rk_edp_link_configure(edp);
633}
634
635static int rk_edp_hw_link_training(struct rk_edp_priv *edp)
636{
637 ulong start;
638 u32 val;
639 int ret;
640
641 /* Set link rate and count as you want to establish */
642 writel(edp->link_train.link_rate, &edp->regs->link_bw_set);
643 writel(edp->link_train.lane_count, &edp->regs->lane_count_set);
644
645 ret = rk_edp_link_train_cr(edp);
646 if (ret)
647 return ret;
648 ret = rk_edp_link_train_ce(edp);
649 if (ret)
650 return ret;
651
652 writel(HW_LT_EN, &edp->regs->dp_hw_link_training);
653 start = get_timer(0);
654 do {
655 val = readl(&edp->regs->dp_hw_link_training);
656 if (!(val & HW_LT_EN))
657 break;
658 } while (get_timer(start) < 10);
659
660 if (val & HW_LT_ERR_CODE_MASK) {
661 printf("edp hw link training error: %d\n",
662 val >> HW_LT_ERR_CODE_SHIFT);
663 return -EIO;
664 }
665
666 return 0;
667}
668
669static int rk_edp_select_i2c_device(struct rk3288_edp *regs,
670 unsigned int device_addr,
671 unsigned int val_addr)
672{
673 int ret;
674
675 /* Set EDID device address */
676 writel(device_addr, &regs->aux_addr_7_0);
677 writel(0x0, &regs->aux_addr_15_8);
678 writel(0x0, &regs->aux_addr_19_16);
679
680 /* Set offset from base address of EDID device */
681 writel(val_addr, &regs->buf_data[0]);
682
683 /*
684 * Set I2C transaction and write address
685 * If bit 3 is 1, DisplayPort transaction.
686 * If Bit 3 is 0, I2C transaction.
687 */
688 writel(AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
689 AUX_TX_COMM_WRITE, &regs->aux_ch_ctl_1);
690
691 /* Start AUX transaction */
692 ret = rk_edp_start_aux_transaction(regs);
693 if (ret != 0) {
694 debug("select_i2c_device Aux Transaction fail!\n");
695 return ret;
696 }
697
698 return 0;
699}
700
701static int rk_edp_i2c_read(struct rk3288_edp *regs, unsigned int device_addr,
702 unsigned int val_addr, unsigned int count, u8 edid[])
703{
704 u32 val;
705 unsigned int i, j;
706 unsigned int cur_data_idx;
707 unsigned int defer = 0;
708 int ret = 0;
709
710 for (i = 0; i < count; i += 16) {
711 for (j = 0; j < 10; j++) { /* try 10 times */
712 /* Clear AUX CH data buffer */
713 writel(BUF_CLR, &regs->buf_data_ctl);
714
715 /* Set normal AUX CH command */
716 clrbits_le32(&regs->aux_ch_ctl_2, ADDR_ONLY);
717
718 /*
719 * If Rx sends defer, Tx sends only reads
720 * request without sending addres
721 */
722 if (!defer) {
723 ret = rk_edp_select_i2c_device(regs,
724 device_addr,
725 val_addr + i);
726 } else {
727 defer = 0;
728 }
729
730 /*
731 * Set I2C transaction and write data
732 * If bit 3 is 1, DisplayPort transaction.
733 * If Bit 3 is 0, I2C transaction.
734 */
735 writel(AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
736 AUX_TX_COMM_READ, &regs->aux_ch_ctl_1);
737
738 /* Start AUX transaction */
739 ret = rk_edp_start_aux_transaction(regs);
740 if (ret == 0) {
741 break;
742 } else {
743 debug("Aux Transaction fail!\n");
744 continue;
745 }
746
747 /* Check if Rx sends defer */
748 val = readl(&regs->aux_rx_comm);
749 if (val == AUX_RX_COMM_AUX_DEFER ||
750 val == AUX_RX_COMM_I2C_DEFER) {
751 debug("Defer: %d\n\n", val);
752 defer = 1;
753 }
754 }
755
756 if (ret)
757 return ret;
758
759 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
760 val = readl(&regs->buf_data[cur_data_idx]);
761 edid[i + cur_data_idx] = (u8)val;
762 }
763 }
764
765 return 0;
766}
767
768static int rk_edp_set_link_train(struct rk_edp_priv *edp)
769{
770 int ret;
771
772 ret = rk_edp_init_training(edp);
773 if (ret) {
774 printf("DP LT init failed!\n");
775 return ret;
776 }
777
778 ret = rk_edp_hw_link_training(edp);
779 if (ret)
780 return ret;
781
782 return 0;
783}
784
785static void rk_edp_init_video(struct rk3288_edp *regs)
786{
787 writel(VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG,
788 &regs->common_int_sta_1);
789 writel(CHA_CRI(4) | CHA_CTRL, &regs->sys_ctl_2);
790 writel(VID_HRES_TH(2) | VID_VRES_TH(0), &regs->video_ctl_8);
791}
792
793static void rk_edp_config_video_slave_mode(struct rk3288_edp *regs)
794{
795 clrbits_le32(&regs->func_en_1, VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
796}
797
798static void rk_edp_set_video_cr_mn(struct rk3288_edp *regs,
799 enum clock_recovery_m_value_type type,
800 u32 m_value,
801 u32 n_value)
802{
803 if (type == REGISTER_M) {
804 setbits_le32(&regs->sys_ctl_4, FIX_M_VID);
805 writel(m_value & 0xff, &regs->m_vid_0);
806 writel((m_value >> 8) & 0xff, &regs->m_vid_1);
807 writel((m_value >> 16) & 0xff, &regs->m_vid_2);
808
809 writel(n_value & 0xf, &regs->n_vid_0);
810 writel((n_value >> 8) & 0xff, &regs->n_vid_1);
811 writel((n_value >> 16) & 0xff, &regs->n_vid_2);
812 } else {
813 clrbits_le32(&regs->sys_ctl_4, FIX_M_VID);
814
815 writel(0x00, &regs->n_vid_0);
816 writel(0x80, &regs->n_vid_1);
817 writel(0x00, &regs->n_vid_2);
818 }
819}
820
821static int rk_edp_is_video_stream_clock_on(struct rk3288_edp *regs)
822{
823 ulong start;
824 u32 val;
825
826 start = get_timer(0);
827 do {
828 val = readl(&regs->sys_ctl_1);
829
830 /* must write value to update DET_STA bit status */
831 writel(val, &regs->sys_ctl_1);
832 val = readl(&regs->sys_ctl_1);
833 if (!(val & DET_STA))
834 continue;
835
836 val = readl(&regs->sys_ctl_2);
837
838 /* must write value to update CHA_STA bit status */
839 writel(val, &regs->sys_ctl_2);
840 val = readl(&regs->sys_ctl_2);
841 if (!(val & CHA_STA))
842 return 0;
843
844 } while (get_timer(start) < 100);
845
846 return -ETIMEDOUT;
847}
848
849static int rk_edp_is_video_stream_on(struct rk_edp_priv *edp)
850{
851 ulong start;
852 u32 val;
853
854 start = get_timer(0);
855 do {
856 val = readl(&edp->regs->sys_ctl_3);
857
858 /* must write value to update STRM_VALID bit status */
859 writel(val, &edp->regs->sys_ctl_3);
860
861 val = readl(&edp->regs->sys_ctl_3);
862 if (!(val & STRM_VALID))
863 return 0;
864 } while (get_timer(start) < 100);
865
866 return -ETIMEDOUT;
867}
868
869static int rk_edp_config_video(struct rk_edp_priv *edp)
870{
871 int ret;
872
873 rk_edp_config_video_slave_mode(edp->regs);
874
875 if (!rk_edp_get_pll_locked(edp->regs)) {
876 debug("PLL is not locked yet.\n");
877 return -ETIMEDOUT;
878 }
879
880 ret = rk_edp_is_video_stream_clock_on(edp->regs);
881 if (ret)
882 return ret;
883
884 /* Set to use the register calculated M/N video */
885 rk_edp_set_video_cr_mn(edp->regs, CALCULATED_M, 0, 0);
886
887 /* For video bist, Video timing must be generated by register */
888 clrbits_le32(&edp->regs->video_ctl_10, F_SEL);
889
890 /* Disable video mute */
891 clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE);
892
893 /* Enable video at next frame */
894 setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN);
895
896 return rk_edp_is_video_stream_on(edp);
897}
898
899static void rockchip_edp_force_hpd(struct rk_edp_priv *edp)
900{
901 setbits_le32(&edp->regs->sys_ctl_3, F_HPD | HPD_CTRL);
902}
903
904static int rockchip_edp_get_plug_in_status(struct rk_edp_priv *edp)
905{
906 u32 val;
907
908 val = readl(&edp->regs->sys_ctl_3);
909 if (val & HPD_STATUS)
910 return 1;
911
912 return 0;
913}
914
915/*
916 * support edp HPD function
917 * some hardware version do not support edp hdp,
918 * we use 200ms to try to get the hpd single now,
919 * if we can not get edp hpd single, it will delay 200ms,
920 * also meet the edp power timing request, to compatible
921 * all of the hardware version
922 */
923static void rockchip_edp_wait_hpd(struct rk_edp_priv *edp)
924{
925 ulong start;
926
927 start = get_timer(0);
928 do {
929 if (rockchip_edp_get_plug_in_status(edp))
930 return;
931 udelay(100);
932 } while (get_timer(start) < 200);
933
934 debug("do not get hpd single, force hpd\n");
935 rockchip_edp_force_hpd(edp);
936}
937
938static int rk_edp_enable(struct udevice *dev, int panel_bpp,
939 const struct display_timing *edid)
940{
941 struct rk_edp_priv *priv = dev_get_priv(dev);
942 int ret = 0;
943
944 ret = rk_edp_set_link_train(priv);
945 if (ret) {
946 printf("link train failed!\n");
947 return ret;
948 }
949
950 rk_edp_init_video(priv->regs);
951 ret = rk_edp_config_video(priv);
952 if (ret) {
953 printf("config video failed\n");
954 return ret;
955 }
956 ret = panel_enable_backlight(priv->panel);
957 if (ret) {
958 debug("%s: backlight error: %d\n", __func__, ret);
959 return ret;
960 }
961
962 return 0;
963}
964
965static int rk_edp_read_edid(struct udevice *dev, u8 *buf, int buf_size)
966{
967 struct rk_edp_priv *priv = dev_get_priv(dev);
968 u32 edid_size = EDID_LENGTH;
969 int ret;
970 int i;
971
972 for (i = 0; i < 3; i++) {
973 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR, EDID_HEADER,
974 EDID_LENGTH, &buf[EDID_HEADER]);
975 if (ret) {
976 debug("EDID read failed\n");
977 continue;
978 }
979
980 /*
981 * check if the EDID has an extension flag, and read additional
982 * EDID data if needed
983 */
984 if (buf[EDID_EXTENSION_FLAG]) {
985 edid_size += EDID_LENGTH;
986 ret = rk_edp_i2c_read(priv->regs, EDID_ADDR,
987 EDID_LENGTH, EDID_LENGTH,
988 &buf[EDID_LENGTH]);
989 if (ret) {
990 debug("EDID Read failed!\n");
991 continue;
992 }
993 }
994 goto done;
995 }
996
997 /* After 3 attempts, give up */
998 return ret;
999
1000done:
1001 return edid_size;
1002}
1003
1004static int rk_edp_ofdata_to_platdata(struct udevice *dev)
1005{
1006 struct rk_edp_priv *priv = dev_get_priv(dev);
1007
653ac184 1008 priv->regs = dev_read_addr_ptr(dev);
5852d539
SG		 1009 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
1010
1011 return 0;
1012}
1013
f418676e
SG		 1014static int rk_edp_remove(struct udevice *dev)
1015{
1016 struct rk_edp_priv *priv = dev_get_priv(dev);
1017 struct rk3288_edp *regs = priv->regs;
1018
1019 setbits_le32(&regs->video_ctl_1, VIDEO_MUTE);
1020 clrbits_le32(&regs->video_ctl_1, VIDEO_EN);
1021 clrbits_le32(&regs->sys_ctl_3, F_HPD | HPD_CTRL);
1022 setbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
1023
1024 return 0;
1025}
1026
1027static int rk_edp_probe(struct udevice *dev)
5852d539
SG		 1028{
1029 struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
1030 struct rk_edp_priv *priv = dev_get_priv(dev);
1031 struct rk3288_edp *regs = priv->regs;
135aa950 1032 struct clk clk;
5852d539
SG		 1033 int ret;
1034
1035 ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
1036 &priv->panel);
1037 if (ret) {
1038 debug("%s: Cannot find panel for '%s' (ret=%d)\n", __func__,
1039 dev->name, ret);
1040 return ret;
1041 }
1042
1043 int vop_id = uc_plat->source_id;
1044 debug("%s, uc_plat=%p, vop_id=%u\n", __func__, uc_plat, vop_id);
1045
1046 ret = clk_get_by_index(dev, 1, &clk);
1047 if (ret >= 0) {
135aa950
SW		 1048 ret = clk_set_rate(&clk, 0);
1049 clk_free(&clk);
5852d539
SG		 1050 }
1051 if (ret) {
1052 debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
1053 return ret;
1054 }
1055
1056 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
1057 if (ret >= 0) {
135aa950
SW		 1058 ret = clk_set_rate(&clk, 192000000);
1059 clk_free(&clk);
5852d539
SG		 1060 }
1061 if (ret < 0) {
1062 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
1063 __func__, uc_plat->src_dev->name, ret);
1064 return ret;
1065 }
1066
1067 /* grf_edp_ref_clk_sel: from internal 24MHz or 27MHz clock */
1068 rk_setreg(&priv->grf->soc_con12, 1 << 4);
1069
1070 /* select epd signal from vop0 or vop1 */
673eb44e
PW		 1071 rk_clrsetreg(&priv->grf->soc_con6, (1 << 5),
1072 (vop_id == 1) ? (1 << 5) : (0 << 5));
5852d539
SG		 1073
1074 rockchip_edp_wait_hpd(priv);
1075
1076 rk_edp_init_refclk(regs);
1077 rk_edp_init_interrupt(regs);
1078 rk_edp_enable_sw_function(regs);
1079 ret = rk_edp_init_analog_func(regs);
1080 if (ret)
1081 return ret;
1082 rk_edp_init_aux(regs);
1083
1084 return 0;
1085}
1086
1087static const struct dm_display_ops dp_rockchip_ops = {
1088 .read_edid = rk_edp_read_edid,
1089 .enable = rk_edp_enable,
1090};
1091
1092static const struct udevice_id rockchip_dp_ids[] = {
1093 { .compatible = "rockchip,rk3288-edp" },
1094 { }
1095};
1096
1097U_BOOT_DRIVER(dp_rockchip) = {
1098 .name = "edp_rockchip",
1099 .id = UCLASS_DISPLAY,
1100 .of_match = rockchip_dp_ids,
1101 .ops = &dp_rockchip_ops,
1102 .ofdata_to_platdata = rk_edp_ofdata_to_platdata,
1103 .probe = rk_edp_probe,
f418676e 1104 .remove = rk_edp_remove,
5852d539
SG		 1105 .priv_auto_alloc_size = sizeof(struct rk_edp_priv),
1106};
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