[J-u-boot.git] / drivers / net / ravb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * drivers/net/ravb.c
 *     This file is driver for Renesas Ethernet AVB.
 *
 * Copyright (C) 2015-2017  Renesas Electronics Corporation
 *
 * Based on the SuperH Ethernet driver.
 */

#include <common.h>
#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <miiphy.h>
#include <malloc.h>
#include <asm/cache.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/gpio.h>

/* Registers */
#define RAVB_REG_CCC		0x000
#define RAVB_REG_DBAT		0x004
#define RAVB_REG_CSR		0x00C
#define RAVB_REG_APSR		0x08C
#define RAVB_REG_RCR		0x090
#define RAVB_REG_TGC		0x300
#define RAVB_REG_TCCR		0x304
#define RAVB_REG_RIC0		0x360
#define RAVB_REG_RIC1		0x368
#define RAVB_REG_RIC2		0x370
#define RAVB_REG_TIC		0x378
#define RAVB_REG_ECMR		0x500
#define RAVB_REG_RFLR		0x508
#define RAVB_REG_ECSIPR		0x518
#define RAVB_REG_PIR		0x520
#define RAVB_REG_GECMR		0x5b0
#define RAVB_REG_MAHR		0x5c0
#define RAVB_REG_MALR		0x5c8

#define CCC_OPC_CONFIG		BIT(0)
#define CCC_OPC_OPERATION	BIT(1)
#define CCC_BOC			BIT(20)

#define CSR_OPS			0x0000000F
#define CSR_OPS_CONFIG		BIT(1)

#define APSR_RDM		BIT(13)
#define APSR_TDM		BIT(14)

#define TCCR_TSRQ0		BIT(0)

#define RFLR_RFL_MIN		0x05EE

#define PIR_MDI			BIT(3)
#define PIR_MDO			BIT(2)
#define PIR_MMD			BIT(1)
#define PIR_MDC			BIT(0)

#define ECMR_TRCCM		BIT(26)
#define ECMR_RZPF		BIT(20)
#define ECMR_PFR		BIT(18)
#define ECMR_RXF		BIT(17)
#define ECMR_RE			BIT(6)
#define ECMR_TE			BIT(5)
#define ECMR_DM			BIT(1)
#define ECMR_CHG_DM		(ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)

/* DMA Descriptors */
#define RAVB_NUM_BASE_DESC		16
#define RAVB_NUM_TX_DESC		8
#define RAVB_NUM_RX_DESC		8

#define RAVB_TX_QUEUE_OFFSET		0
#define RAVB_RX_QUEUE_OFFSET		4

#define RAVB_DESC_DT(n)			((n) << 28)
#define RAVB_DESC_DT_FSINGLE		RAVB_DESC_DT(0x7)
#define RAVB_DESC_DT_LINKFIX		RAVB_DESC_DT(0x9)
#define RAVB_DESC_DT_EOS		RAVB_DESC_DT(0xa)
#define RAVB_DESC_DT_FEMPTY		RAVB_DESC_DT(0xc)
#define RAVB_DESC_DT_EEMPTY		RAVB_DESC_DT(0x3)
#define RAVB_DESC_DT_MASK		RAVB_DESC_DT(0xf)

#define RAVB_DESC_DS(n)			(((n) & 0xfff) << 0)
#define RAVB_DESC_DS_MASK		0xfff

#define RAVB_RX_DESC_MSC_MC		BIT(23)
#define RAVB_RX_DESC_MSC_CEEF		BIT(22)
#define RAVB_RX_DESC_MSC_CRL		BIT(21)
#define RAVB_RX_DESC_MSC_FRE		BIT(20)
#define RAVB_RX_DESC_MSC_RTLF		BIT(19)
#define RAVB_RX_DESC_MSC_RTSF		BIT(18)
#define RAVB_RX_DESC_MSC_RFE		BIT(17)
#define RAVB_RX_DESC_MSC_CRC		BIT(16)
#define RAVB_RX_DESC_MSC_MASK		(0xff << 16)

#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
	(RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
	 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)

#define RAVB_TX_TIMEOUT_MS		1000

struct ravb_desc {
	u32	ctrl;
	u32	dptr;
};

struct ravb_rxdesc {
	struct ravb_desc	data;
	struct ravb_desc	link;
	u8			__pad[48];
	u8			packet[PKTSIZE_ALIGN];
};

struct ravb_priv {
	struct ravb_desc	base_desc[RAVB_NUM_BASE_DESC];
	struct ravb_desc	tx_desc[RAVB_NUM_TX_DESC];
	struct ravb_rxdesc	rx_desc[RAVB_NUM_RX_DESC];
	u32			rx_desc_idx;
	u32			tx_desc_idx;

	struct phy_device	*phydev;
	struct mii_dev		*bus;
	void __iomem		*iobase;
	struct clk_bulk		clks;
};

static inline void ravb_flush_dcache(u32 addr, u32 len)
{
	flush_dcache_range(addr, addr + len);
}

static inline void ravb_invalidate_dcache(u32 addr, u32 len)
{
	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
	u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
	invalidate_dcache_range(start, end);
}

static int ravb_send(struct udevice *dev, void *packet, int len)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
	unsigned int start;

	/* Update TX descriptor */
	ravb_flush_dcache((uintptr_t)packet, len);
	memset(desc, 0x0, sizeof(*desc));
	desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
	desc->dptr = (uintptr_t)packet;
	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));

	/* Restart the transmitter if disabled */
	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
		setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);

	/* Wait until packet is transmitted */
	start = get_timer(0);
	while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
		ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
		if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
			break;
		udelay(10);
	};

	if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
		return -ETIMEDOUT;

	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
	return 0;
}

static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
	int len;
	u8 *packet;

	/* Check if the rx descriptor is ready */
	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
		return -EAGAIN;

	/* Check for errors */
	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
		desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
		return -EAGAIN;
	}

	len = desc->data.ctrl & RAVB_DESC_DS_MASK;
	packet = (u8 *)(uintptr_t)desc->data.dptr;
	ravb_invalidate_dcache((uintptr_t)packet, len);

	*packetp = packet;
	return len;
}

static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];

	/* Make current descriptor available again */
	desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));

	/* Point to the next descriptor */
	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
	desc = &eth->rx_desc[eth->rx_desc_idx];
	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));

	return 0;
}

static int ravb_reset(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	/* Set config mode */
	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);

	/* Check the operating mode is changed to the config mode. */
	return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
				 CSR_OPS_CONFIG, true, 100, true);
}

static void ravb_base_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
	int i;

	/* Initialize all descriptors */
	memset(eth->base_desc, 0x0, desc_size);

	for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
		eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;

	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);

	/* Register the descriptor base address table */
	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
}

static void ravb_tx_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
	int i;

	/* Initialize all descriptors */
	memset(eth->tx_desc, 0x0, desc_size);
	eth->tx_desc_idx = 0;

	for (i = 0; i < RAVB_NUM_TX_DESC; i++)
		eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;

	/* Mark the end of the descriptors */
	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);

	/* Point the controller to the TX descriptor list. */
	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
			  sizeof(struct ravb_desc));
}

static void ravb_rx_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
	int i;

	/* Initialize all descriptors */
	memset(eth->rx_desc, 0x0, desc_size);
	eth->rx_desc_idx = 0;

	for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
		eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
					    RAVB_DESC_DS(PKTSIZE_ALIGN);
		eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;

		eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
		eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
	}

	/* Mark the end of the descriptors */
	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);

	/* Point the controller to the rx descriptor list */
	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
			  sizeof(struct ravb_desc));
}

static int ravb_phy_config(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct phy_device *phydev;
	int reg;

	phydev = phy_connect(eth->bus, -1, dev, pdata->phy_interface);
	if (!phydev)
		return -ENODEV;

	eth->phydev = phydev;

	phydev->supported &= SUPPORTED_100baseT_Full |
			     SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
			     SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_Pause |
			     SUPPORTED_Asym_Pause;

	if (pdata->max_speed != 1000) {
		phydev->supported &= ~SUPPORTED_1000baseT_Full;
		reg = phy_read(phydev, -1, MII_CTRL1000);
		reg &= ~(BIT(9) | BIT(8));
		phy_write(phydev, -1, MII_CTRL1000, reg);
	}

	phy_config(phydev);

	return 0;
}

/* Set Mac address */
static int ravb_write_hwaddr(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	unsigned char *mac = pdata->enetaddr;

	writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
	       eth->iobase + RAVB_REG_MAHR);

	writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);

	return 0;
}

/* E-MAC init function */
static int ravb_mac_init(struct ravb_priv *eth)
{
	/* Disable MAC Interrupt */
	writel(0, eth->iobase + RAVB_REG_ECSIPR);

	/* Recv frame limit set register */
	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);

	return 0;
}

/* AVB-DMAC init function */
static int ravb_dmac_init(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_plat(dev);
	int ret = 0;
	int mode = 0;
	unsigned int delay;
	bool explicit_delay = false;

	/* Set CONFIG mode */
	ret = ravb_reset(dev);
	if (ret)
		return ret;

	/* Disable all interrupts */
	writel(0, eth->iobase + RAVB_REG_RIC0);
	writel(0, eth->iobase + RAVB_REG_RIC1);
	writel(0, eth->iobase + RAVB_REG_RIC2);
	writel(0, eth->iobase + RAVB_REG_TIC);

	/* Set little endian */
	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);

	/* AVB rx set */
	writel(0x18000001, eth->iobase + RAVB_REG_RCR);

	/* FIFO size set */
	writel(0x00222210, eth->iobase + RAVB_REG_TGC);

	/* Delay CLK: 2ns (not applicable on R-Car E3/D3) */
	if ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77990) ||
	    (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77995))
		return 0;

	if (!dev_read_u32(dev, "rx-internal-delay-ps", &delay)) {
		/* Valid values are 0 and 1800, according to DT bindings */
		if (delay) {
			mode |= APSR_RDM;
			explicit_delay = true;
		}
	}

	if (!dev_read_u32(dev, "tx-internal-delay-ps", &delay)) {
		/* Valid values are 0 and 2000, according to DT bindings */
		if (delay) {
			mode |= APSR_TDM;
			explicit_delay = true;
		}
	}

	if (!explicit_delay) {
		if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
		    pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
			mode |= APSR_RDM;

		if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
		    pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
			mode |= APSR_TDM;
	}

	writel(mode, eth->iobase + RAVB_REG_APSR);

	return 0;
}

static int ravb_config(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct phy_device *phy = eth->phydev;
	u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
	int ret;

	/* Configure AVB-DMAC register */
	ravb_dmac_init(dev);

	/* Configure E-MAC registers */
	ravb_mac_init(eth);
	ravb_write_hwaddr(dev);

	ret = phy_startup(phy);
	if (ret)
		return ret;

	/* Set the transfer speed */
	if (phy->speed == 100)
		writel(0, eth->iobase + RAVB_REG_GECMR);
	else if (phy->speed == 1000)
		writel(1, eth->iobase + RAVB_REG_GECMR);

	/* Check if full duplex mode is supported by the phy */
	if (phy->duplex)
		mask |= ECMR_DM;

	writel(mask, eth->iobase + RAVB_REG_ECMR);

	return 0;
}

static int ravb_start(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	int ret;

	ret = ravb_reset(dev);
	if (ret)
		return ret;

	ravb_base_desc_init(eth);
	ravb_tx_desc_init(eth);
	ravb_rx_desc_init(eth);

	ret = ravb_config(dev);
	if (ret)
		return ret;

	/* Setting the control will start the AVB-DMAC process. */
	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);

	return 0;
}

static void ravb_stop(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	phy_shutdown(eth->phydev);
	ravb_reset(dev);
}

static int ravb_probe(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	struct ravb_priv *eth = dev_get_priv(dev);
	struct mii_dev *mdiodev;
	void __iomem *iobase;
	int ret;

	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
	eth->iobase = iobase;

	ret = clk_get_bulk(dev, &eth->clks);
	if (ret < 0)
		goto err_mdio_alloc;

	mdiodev = mdio_alloc();
	if (!mdiodev) {
		ret = -ENOMEM;
		goto err_mdio_alloc;
	}

	mdiodev->read = bb_miiphy_read;
	mdiodev->write = bb_miiphy_write;
	bb_miiphy_buses[0].priv = eth;
	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);

	ret = mdio_register(mdiodev);
	if (ret < 0)
		goto err_mdio_register;

	eth->bus = miiphy_get_dev_by_name(dev->name);

	/* Bring up PHY */
	ret = clk_enable_bulk(&eth->clks);
	if (ret)
		goto err_mdio_register;

	ret = ravb_reset(dev);
	if (ret)
		goto err_mdio_reset;

	ret = ravb_phy_config(dev);
	if (ret)
		goto err_mdio_reset;

	return 0;

err_mdio_reset:
	clk_release_bulk(&eth->clks);
err_mdio_register:
	mdio_free(mdiodev);
err_mdio_alloc:
	unmap_physmem(eth->iobase, MAP_NOCACHE);
	return ret;
}

static int ravb_remove(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	clk_release_bulk(&eth->clks);

	free(eth->phydev);
	mdio_unregister(eth->bus);
	mdio_free(eth->bus);
	unmap_physmem(eth->iobase, MAP_NOCACHE);

	return 0;
}

int ravb_bb_init(struct bb_miiphy_bus *bus)
{
	return 0;
}

int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
{
	struct ravb_priv *eth = bus->priv;

	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);

	return 0;
}

int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
	struct ravb_priv *eth = bus->priv;

	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);

	return 0;
}

int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
	struct ravb_priv *eth = bus->priv;

	if (v)
		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	else
		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);

	return 0;
}

int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
	struct ravb_priv *eth = bus->priv;

	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;

	return 0;
}

int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
	struct ravb_priv *eth = bus->priv;

	if (v)
		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	else
		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);

	return 0;
}

int ravb_bb_delay(struct bb_miiphy_bus *bus)
{
	udelay(10);

	return 0;
}

struct bb_miiphy_bus bb_miiphy_buses[] = {
	{
		.name		= "ravb",
		.init		= ravb_bb_init,
		.mdio_active	= ravb_bb_mdio_active,
		.mdio_tristate	= ravb_bb_mdio_tristate,
		.set_mdio	= ravb_bb_set_mdio,
		.get_mdio	= ravb_bb_get_mdio,
		.set_mdc	= ravb_bb_set_mdc,
		.delay		= ravb_bb_delay,
	},
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);

static const struct eth_ops ravb_ops = {
	.start			= ravb_start,
	.send			= ravb_send,
	.recv			= ravb_recv,
	.free_pkt		= ravb_free_pkt,
	.stop			= ravb_stop,
	.write_hwaddr		= ravb_write_hwaddr,
};

int ravb_of_to_plat(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_plat(dev);
	const fdt32_t *cell;

	pdata->iobase = dev_read_addr(dev);

	pdata->phy_interface = dev_read_phy_mode(dev);
	if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
		return -EINVAL;

	pdata->max_speed = 1000;
	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
	if (cell)
		pdata->max_speed = fdt32_to_cpu(*cell);

	sprintf(bb_miiphy_buses[0].name, dev->name);

	return 0;
}

static const struct udevice_id ravb_ids[] = {
	{ .compatible = "renesas,etheravb-rcar-gen3" },
	{ .compatible = "renesas,etheravb-rcar-gen4" },
	{ }
};

U_BOOT_DRIVER(eth_ravb) = {
	.name		= "ravb",
	.id		= UCLASS_ETH,
	.of_match	= ravb_ids,
	.of_to_plat = ravb_of_to_plat,
	.probe		= ravb_probe,
	.remove		= ravb_remove,
	.ops		= &ravb_ops,
	.priv_auto	= sizeof(struct ravb_priv),
	.plat_auto	= sizeof(struct eth_pdata),
	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
8ae51b6f MV	2	/*
	3	* drivers/net/ravb.c
	4	* This file is driver for Renesas Ethernet AVB.
	5	*
	6	* Copyright (C) 2015-2017 Renesas Electronics Corporation
	7	*
	8	* Based on the SuperH Ethernet driver.
8ae51b6f MV	9	*/
8ae51b6f MV	10
d678a59d	11	#include <common.h>
1fea9e25	12	#include <clk.h>
1eb69ae4	13	#include <cpu_func.h>
8ae51b6f MV	14	#include <dm.h>
8ae51b6f MV	15	#include <errno.h>
f7ae49fc	16	#include <log.h>
8ae51b6f MV	17	#include <miiphy.h>
8ae51b6f MV	18	#include <malloc.h>
90526e9f	19	#include <asm/cache.h>
cd93d625	20	#include <linux/bitops.h>
c05ed00a	21	#include <linux/delay.h>
8ae51b6f MV	22	#include <linux/mii.h>
	23	#include <wait_bit.h>
	24	#include <asm/io.h>
401d1c4f	25	#include <asm/global_data.h>
bddb44e9	26	#include <asm/gpio.h>
8ae51b6f MV	27
	28	/* Registers */
	29	#define RAVB_REG_CCC 0x000
	30	#define RAVB_REG_DBAT 0x004
	31	#define RAVB_REG_CSR 0x00C
	32	#define RAVB_REG_APSR 0x08C
	33	#define RAVB_REG_RCR 0x090
	34	#define RAVB_REG_TGC 0x300
	35	#define RAVB_REG_TCCR 0x304
	36	#define RAVB_REG_RIC0 0x360
	37	#define RAVB_REG_RIC1 0x368
	38	#define RAVB_REG_RIC2 0x370
	39	#define RAVB_REG_TIC 0x378
	40	#define RAVB_REG_ECMR 0x500
	41	#define RAVB_REG_RFLR 0x508
	42	#define RAVB_REG_ECSIPR 0x518
	43	#define RAVB_REG_PIR 0x520
	44	#define RAVB_REG_GECMR 0x5b0
	45	#define RAVB_REG_MAHR 0x5c0
	46	#define RAVB_REG_MALR 0x5c8
	47
	48	#define CCC_OPC_CONFIG BIT(0)
	49	#define CCC_OPC_OPERATION BIT(1)
	50	#define CCC_BOC BIT(20)
	51
	52	#define CSR_OPS 0x0000000F
	53	#define CSR_OPS_CONFIG BIT(1)
	54
a26c2b15	55	#define APSR_RDM BIT(13)
ef8c8781 MV	56	#define APSR_TDM BIT(14)
ef8c8781 MV	57
8ae51b6f MV	58	#define TCCR_TSRQ0 BIT(0)
	59
	60	#define RFLR_RFL_MIN 0x05EE
	61
	62	#define PIR_MDI BIT(3)
	63	#define PIR_MDO BIT(2)
	64	#define PIR_MMD BIT(1)
	65	#define PIR_MDC BIT(0)
	66
	67	#define ECMR_TRCCM BIT(26)
	68	#define ECMR_RZPF BIT(20)
	69	#define ECMR_PFR BIT(18)
	70	#define ECMR_RXF BIT(17)
	71	#define ECMR_RE BIT(6)
	72	#define ECMR_TE BIT(5)
	73	#define ECMR_DM BIT(1)
	74	#define ECMR_CHG_DM (ECMR_TRCCM \| ECMR_RZPF \| ECMR_PFR \| ECMR_RXF)
	75
	76	/* DMA Descriptors */
	77	#define RAVB_NUM_BASE_DESC 16
	78	#define RAVB_NUM_TX_DESC 8
	79	#define RAVB_NUM_RX_DESC 8
	80
	81	#define RAVB_TX_QUEUE_OFFSET 0
	82	#define RAVB_RX_QUEUE_OFFSET 4
	83
	84	#define RAVB_DESC_DT(n) ((n) << 28)
	85	#define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
	86	#define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
	87	#define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
	88	#define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
	89	#define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
	90	#define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
	91
	92	#define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
	93	#define RAVB_DESC_DS_MASK 0xfff
	94
	95	#define RAVB_RX_DESC_MSC_MC BIT(23)
	96	#define RAVB_RX_DESC_MSC_CEEF BIT(22)
	97	#define RAVB_RX_DESC_MSC_CRL BIT(21)
	98	#define RAVB_RX_DESC_MSC_FRE BIT(20)
	99	#define RAVB_RX_DESC_MSC_RTLF BIT(19)
	100	#define RAVB_RX_DESC_MSC_RTSF BIT(18)
	101	#define RAVB_RX_DESC_MSC_RFE BIT(17)
	102	#define RAVB_RX_DESC_MSC_CRC BIT(16)
	103	#define RAVB_RX_DESC_MSC_MASK (0xff << 16)
	104
	105	#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
	106	(RAVB_RX_DESC_MSC_CRC \| RAVB_RX_DESC_MSC_RFE \| RAVB_RX_DESC_MSC_RTLF \| \
	107	RAVB_RX_DESC_MSC_RTSF \| RAVB_RX_DESC_MSC_CEEF)
	108
	109	#define RAVB_TX_TIMEOUT_MS 1000
	110
	111	struct ravb_desc {
	112	u32 ctrl;
	113	u32 dptr;
	114	};
	115
	116	struct ravb_rxdesc {
	117	struct ravb_desc data;
	118	struct ravb_desc link;
	119	u8 __pad[48];
	120	u8 packet[PKTSIZE_ALIGN];
	121	};
122
123	struct ravb_priv {
124	struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
125	struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
126	struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
127	u32 rx_desc_idx;
128	u32 tx_desc_idx;
129
130	struct phy_device *phydev;
131	struct mii_dev *bus;
132	void __iomem *iobase;
182754f4	133	struct clk_bulk clks;
8ae51b6f MV	134	};
	135
	136	static inline void ravb_flush_dcache(u32 addr, u32 len)
	137	{
	138	flush_dcache_range(addr, addr + len);
	139	}
	140
	141	static inline void ravb_invalidate_dcache(u32 addr, u32 len)
	142	{
	143	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
	144	u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
	145	invalidate_dcache_range(start, end);
	146	}
	147
	148	static int ravb_send(struct udevice dev, void packet, int len)
	149	{
	150	struct ravb_priv *eth = dev_get_priv(dev);
	151	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
	152	unsigned int start;
	153
	154	/* Update TX descriptor */
	155	ravb_flush_dcache((uintptr_t)packet, len);
	156	memset(desc, 0x0, sizeof(*desc));
	157	desc->ctrl = RAVB_DESC_DT_FSINGLE \| RAVB_DESC_DS(len);
	158	desc->dptr = (uintptr_t)packet;
	159	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
	160
	161	/* Restart the transmitter if disabled */
	162	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
	163	setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
	164
	165	/* Wait until packet is transmitted */
	166	start = get_timer(0);
	167	while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
	168	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	169	if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
	170	break;
	171	udelay(10);
	172	};
	173
	174	if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
	175	return -ETIMEDOUT;
	176
	177	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
	178	return 0;
	179	}
	180
	181	static int ravb_recv(struct udevice dev, int flags, uchar *packetp)
	182	{
	183	struct ravb_priv *eth = dev_get_priv(dev);
	184	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
	185	int len;
	186	u8 *packet;
	187
	188	/* Check if the rx descriptor is ready */
	189	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	190	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
	191	return -EAGAIN;
	192
	193	/* Check for errors */
	194	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
	195	desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
	196	return -EAGAIN;
	197	}
198
199	len = desc->data.ctrl & RAVB_DESC_DS_MASK;
200	packet = (u8 *)(uintptr_t)desc->data.dptr;
201	ravb_invalidate_dcache((uintptr_t)packet, len);
202
203	*packetp = packet;
204	return len;
205	}
206
207	static int ravb_free_pkt(struct udevice dev, uchar packet, int length)
208	{
209	struct ravb_priv *eth = dev_get_priv(dev);
210	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
211
212	/* Make current descriptor available again */
213	desc->data.ctrl = RAVB_DESC_DT_FEMPTY \| RAVB_DESC_DS(PKTSIZE_ALIGN);
214	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
215
216	/* Point to the next descriptor */
217	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
218	desc = &eth->rx_desc[eth->rx_desc_idx];
219	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
220
221	return 0;
222	}
223
224	static int ravb_reset(struct udevice *dev)
225	{
226	struct ravb_priv *eth = dev_get_priv(dev);
227
228	/* Set config mode */
229	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
230
231	/* Check the operating mode is changed to the config mode. */
48263504 ÁFR	232	return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
48263504 ÁFR	233	CSR_OPS_CONFIG, true, 100, true);
8ae51b6f MV	234	}
	235
	236	static void ravb_base_desc_init(struct ravb_priv *eth)
	237	{
	238	const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
	239	int i;
	240
	241	/* Initialize all descriptors */
	242	memset(eth->base_desc, 0x0, desc_size);
	243
	244	for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
	245	eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
	246
	247	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
	248
	249	/* Register the descriptor base address table */
	250	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
	251	}
	252
	253	static void ravb_tx_desc_init(struct ravb_priv *eth)
	254	{
	255	const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
	256	int i;
	257
	258	/* Initialize all descriptors */
	259	memset(eth->tx_desc, 0x0, desc_size);
	260	eth->tx_desc_idx = 0;
	261
	262	for (i = 0; i < RAVB_NUM_TX_DESC; i++)
	263	eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
	264
	265	/* Mark the end of the descriptors */
	266	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
	267	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
	268	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
	269
	270	/* Point the controller to the TX descriptor list. */
	271	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	272	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
	273	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
	274	sizeof(struct ravb_desc));
	275	}
	276
	277	static void ravb_rx_desc_init(struct ravb_priv *eth)
	278	{
	279	const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
	280	int i;
	281
	282	/* Initialize all descriptors */
	283	memset(eth->rx_desc, 0x0, desc_size);
	284	eth->rx_desc_idx = 0;
	285
	286	for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
	287	eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY \|
	288	RAVB_DESC_DS(PKTSIZE_ALIGN);
	289	eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
	290
	291	eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
	292	eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
	293	}
	294
	295	/* Mark the end of the descriptors */
	296	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
	297	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
298	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
299
300	/* Point the controller to the rx descriptor list */
301	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
302	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
303	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
304	sizeof(struct ravb_desc));
305	}
306
307	static int ravb_phy_config(struct udevice *dev)
308	{
309	struct ravb_priv *eth = dev_get_priv(dev);
c69cda25	310	struct eth_pdata *pdata = dev_get_plat(dev);
8ae51b6f	311	struct phy_device *phydev;
d797a8cc	312	int reg;
8ae51b6f	313
d797a8cc	314	phydev = phy_connect(eth->bus, -1, dev, pdata->phy_interface);
8ae51b6f MV	315	if (!phydev)
	316	return -ENODEV;
	317
	318	eth->phydev = phydev;
	319
536fb5d4 MV	320	phydev->supported &= SUPPORTED_100baseT_Full \|
	321	SUPPORTED_1000baseT_Full \| SUPPORTED_Autoneg \|
	322	SUPPORTED_TP \| SUPPORTED_MII \| SUPPORTED_Pause \|
	323	SUPPORTED_Asym_Pause;
	324
8ae51b6f	325	if (pdata->max_speed != 1000) {
536fb5d4	326	phydev->supported &= ~SUPPORTED_1000baseT_Full;
8ae51b6f MV	327	reg = phy_read(phydev, -1, MII_CTRL1000);
	328	reg &= ~(BIT(9) \| BIT(8));
	329	phy_write(phydev, -1, MII_CTRL1000, reg);
	330	}
	331
	332	phy_config(phydev);
	333
	334	return 0;
	335	}
	336
	337	/* Set Mac address */
	338	static int ravb_write_hwaddr(struct udevice *dev)
	339	{
	340	struct ravb_priv *eth = dev_get_priv(dev);
c69cda25	341	struct eth_pdata *pdata = dev_get_plat(dev);
8ae51b6f MV	342	unsigned char *mac = pdata->enetaddr;
	343
	344	writel((mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3],
	345	eth->iobase + RAVB_REG_MAHR);
	346
	347	writel((mac[4] << 8) \| mac[5], eth->iobase + RAVB_REG_MALR);
	348
	349	return 0;
	350	}
	351
	352	/* E-MAC init function */
	353	static int ravb_mac_init(struct ravb_priv *eth)
	354	{
	355	/* Disable MAC Interrupt */
	356	writel(0, eth->iobase + RAVB_REG_ECSIPR);
	357
	358	/* Recv frame limit set register */
	359	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
	360
	361	return 0;
	362	}
	363
	364	/* AVB-DMAC init function */
	365	static int ravb_dmac_init(struct udevice *dev)
	366	{
	367	struct ravb_priv *eth = dev_get_priv(dev);
c69cda25	368	struct eth_pdata *pdata = dev_get_plat(dev);
8ae51b6f	369	int ret = 0;
a26c2b15 AF	370	int mode = 0;
	371	unsigned int delay;
	372	bool explicit_delay = false;
8ae51b6f MV	373
	374	/* Set CONFIG mode */
	375	ret = ravb_reset(dev);
	376	if (ret)
	377	return ret;
	378
	379	/* Disable all interrupts */
	380	writel(0, eth->iobase + RAVB_REG_RIC0);
	381	writel(0, eth->iobase + RAVB_REG_RIC1);
	382	writel(0, eth->iobase + RAVB_REG_RIC2);
	383	writel(0, eth->iobase + RAVB_REG_TIC);
	384
	385	/* Set little endian */
	386	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
	387
	388	/* AVB rx set */
	389	writel(0x18000001, eth->iobase + RAVB_REG_RCR);
	390
	391	/* FIFO size set */
	392	writel(0x00222210, eth->iobase + RAVB_REG_TGC);
	393
ef8c8781	394	/* Delay CLK: 2ns (not applicable on R-Car E3/D3) */
c2cffb01 MV	395	if ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77990) \|\|
c2cffb01 MV	396	(renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77995))
ef8c8781 MV	397	return 0;
ef8c8781 MV	398
a26c2b15 AF	399	if (!dev_read_u32(dev, "rx-internal-delay-ps", &delay)) {
	400	/* Valid values are 0 and 1800, according to DT bindings */
	401	if (delay) {
	402	mode \|= APSR_RDM;
	403	explicit_delay = true;
	404	}
	405	}
	406
	407	if (!dev_read_u32(dev, "tx-internal-delay-ps", &delay)) {
	408	/* Valid values are 0 and 2000, according to DT bindings */
	409	if (delay) {
	410	mode \|= APSR_TDM;
	411	explicit_delay = true;
	412	}
	413	}
	414
	415	if (!explicit_delay) {
	416	if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID \|\|
	417	pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
	418	mode \|= APSR_RDM;
	419
	420	if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID \|\|
	421	pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
	422	mode \|= APSR_TDM;
	423	}
	424
	425	writel(mode, eth->iobase + RAVB_REG_APSR);
8ae51b6f MV	426
	427	return 0;
	428	}
	429
	430	static int ravb_config(struct udevice *dev)
	431	{
	432	struct ravb_priv *eth = dev_get_priv(dev);
d64c7894	433	struct phy_device *phy = eth->phydev;
8ae51b6f MV	434	u32 mask = ECMR_CHG_DM \| ECMR_RE \| ECMR_TE;
	435	int ret;
	436
	437	/* Configure AVB-DMAC register */
	438	ravb_dmac_init(dev);
	439
	440	/* Configure E-MAC registers */
	441	ravb_mac_init(eth);
	442	ravb_write_hwaddr(dev);
	443
8ae51b6f MV	444	ret = phy_startup(phy);
	445	if (ret)
	446	return ret;
	447
	448	/* Set the transfer speed */
	449	if (phy->speed == 100)
	450	writel(0, eth->iobase + RAVB_REG_GECMR);
	451	else if (phy->speed == 1000)
	452	writel(1, eth->iobase + RAVB_REG_GECMR);
	453
	454	/* Check if full duplex mode is supported by the phy */
	455	if (phy->duplex)
	456	mask \|= ECMR_DM;
	457
	458	writel(mask, eth->iobase + RAVB_REG_ECMR);
	459
8ae51b6f MV	460	return 0;
	461	}
	462
e3105eac	463	static int ravb_start(struct udevice *dev)
8ae51b6f MV	464	{
	465	struct ravb_priv *eth = dev_get_priv(dev);
	466	int ret;
	467
1fea9e25 MV	468	ret = ravb_reset(dev);
1fea9e25 MV	469	if (ret)
c4a8d9ca	470	return ret;
1fea9e25	471
8ae51b6f MV	472	ravb_base_desc_init(eth);
	473	ravb_tx_desc_init(eth);
	474	ravb_rx_desc_init(eth);
	475
	476	ret = ravb_config(dev);
	477	if (ret)
c4a8d9ca	478	return ret;
8ae51b6f MV	479
	480	/* Setting the control will start the AVB-DMAC process. */
	481	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
	482
	483	return 0;
	484	}
	485
	486	static void ravb_stop(struct udevice *dev)
	487	{
1fea9e25 MV	488	struct ravb_priv *eth = dev_get_priv(dev);
1fea9e25 MV	489
d64c7894	490	phy_shutdown(eth->phydev);
8ae51b6f MV	491	ravb_reset(dev);
	492	}
	493
	494	static int ravb_probe(struct udevice *dev)
	495	{
c69cda25	496	struct eth_pdata *pdata = dev_get_plat(dev);
8ae51b6f MV	497	struct ravb_priv *eth = dev_get_priv(dev);
	498	struct mii_dev *mdiodev;
	499	void __iomem *iobase;
	500	int ret;
	501
	502	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
	503	eth->iobase = iobase;
	504
182754f4	505	ret = clk_get_bulk(dev, &eth->clks);
1fea9e25 MV	506	if (ret < 0)
	507	goto err_mdio_alloc;
	508
8ae51b6f MV	509	mdiodev = mdio_alloc();
	510	if (!mdiodev) {
	511	ret = -ENOMEM;
	512	goto err_mdio_alloc;
	513	}
	514
	515	mdiodev->read = bb_miiphy_read;
	516	mdiodev->write = bb_miiphy_write;
	517	bb_miiphy_buses[0].priv = eth;
	518	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
	519
	520	ret = mdio_register(mdiodev);
	521	if (ret < 0)
	522	goto err_mdio_register;
	523
	524	eth->bus = miiphy_get_dev_by_name(dev->name);
	525
d64c7894	526	/* Bring up PHY */
182754f4	527	ret = clk_enable_bulk(&eth->clks);
d64c7894 MV	528	if (ret)
	529	goto err_mdio_register;
	530
	531	ret = ravb_reset(dev);
	532	if (ret)
	533	goto err_mdio_reset;
	534
	535	ret = ravb_phy_config(dev);
	536	if (ret)
	537	goto err_mdio_reset;
	538
8ae51b6f MV	539	return 0;
8ae51b6f MV	540
d64c7894	541	err_mdio_reset:
182754f4	542	clk_release_bulk(&eth->clks);
8ae51b6f MV	543	err_mdio_register:
	544	mdio_free(mdiodev);
	545	err_mdio_alloc:
	546	unmap_physmem(eth->iobase, MAP_NOCACHE);
	547	return ret;
	548	}
	549
	550	static int ravb_remove(struct udevice *dev)
	551	{
	552	struct ravb_priv *eth = dev_get_priv(dev);
	553
182754f4	554	clk_release_bulk(&eth->clks);
d64c7894	555
8ae51b6f MV	556	free(eth->phydev);
	557	mdio_unregister(eth->bus);
	558	mdio_free(eth->bus);
	559	unmap_physmem(eth->iobase, MAP_NOCACHE);
	560
	561	return 0;
	562	}
	563
	564	int ravb_bb_init(struct bb_miiphy_bus *bus)
	565	{
	566	return 0;
	567	}
	568
	569	int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
	570	{
	571	struct ravb_priv *eth = bus->priv;
	572
	573	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
	574
	575	return 0;
	576	}
	577
	578	int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
	579	{
	580	struct ravb_priv *eth = bus->priv;
	581
	582	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
	583
	584	return 0;
	585	}
	586
	587	int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
	588	{
	589	struct ravb_priv *eth = bus->priv;
	590
	591	if (v)
	592	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	593	else
	594	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	595
	596	return 0;
	597	}
	598
	599	int ravb_bb_get_mdio(struct bb_miiphy_bus bus, int v)
	600	{
	601	struct ravb_priv *eth = bus->priv;
	602
	603	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
	604
	605	return 0;
	606	}
	607
	608	int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
	609	{
	610	struct ravb_priv *eth = bus->priv;
	611
	612	if (v)
	613	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	614	else
	615	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	616
	617	return 0;
	618	}
	619
620	int ravb_bb_delay(struct bb_miiphy_bus *bus)
621	{
622	udelay(10);
623
624	return 0;
625	}
626
627	struct bb_miiphy_bus bb_miiphy_buses[] = {
628	{
629	.name = "ravb",
630	.init = ravb_bb_init,
631	.mdio_active = ravb_bb_mdio_active,
632	.mdio_tristate = ravb_bb_mdio_tristate,
633	.set_mdio = ravb_bb_set_mdio,
634	.get_mdio = ravb_bb_get_mdio,
635	.set_mdc = ravb_bb_set_mdc,
636	.delay = ravb_bb_delay,
637	},
638	};
639	int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
640
641	static const struct eth_ops ravb_ops = {
642	.start = ravb_start,
643	.send = ravb_send,
644	.recv = ravb_recv,
645	.free_pkt = ravb_free_pkt,
646	.stop = ravb_stop,
647	.write_hwaddr = ravb_write_hwaddr,
648	};
649
d1998a9f	650	int ravb_of_to_plat(struct udevice *dev)
5ee8b4d7	651	{
c69cda25	652	struct eth_pdata *pdata = dev_get_plat(dev);
5ee8b4d7	653	const fdt32_t *cell;
5ee8b4d7	654
2548493a	655	pdata->iobase = dev_read_addr(dev);
123ca114 MB	656
123ca114 MB	657	pdata->phy_interface = dev_read_phy_mode(dev);
ffb0f6f4	658	if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
5ee8b4d7	659	return -EINVAL;
5ee8b4d7 MV	660
	661	pdata->max_speed = 1000;
	662	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
	663	if (cell)
	664	pdata->max_speed = fdt32_to_cpu(*cell);
	665
	666	sprintf(bb_miiphy_buses[0].name, dev->name);
	667
123ca114	668	return 0;
5ee8b4d7 MV	669	}
	670
	671	static const struct udevice_id ravb_ids[] = {
5ee8b4d7	672	{ .compatible = "renesas,etheravb-rcar-gen3" },
c2fbaaf3	673	{ .compatible = "renesas,etheravb-rcar-gen4" },
5ee8b4d7 MV	674	{ }
	675	};
	676
8ae51b6f MV	677	U_BOOT_DRIVER(eth_ravb) = {
	678	.name = "ravb",
	679	.id = UCLASS_ETH,
5ee8b4d7	680	.of_match = ravb_ids,
d1998a9f	681	.of_to_plat = ravb_of_to_plat,
8ae51b6f MV	682	.probe = ravb_probe,
	683	.remove = ravb_remove,
	684	.ops = &ravb_ops,
41575d8e	685	.priv_auto = sizeof(struct ravb_priv),
caa4daa2	686	.plat_auto = sizeof(struct eth_pdata),
8ae51b6f MV	687	.flags = DM_FLAG_ALLOC_PRIV_DMA,
8ae51b6f MV	688	};