[J-u-boot.git] / drivers / net / ravb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * drivers/net/ravb.c
 *     This file is driver for Renesas Ethernet AVB.
 *
 * Copyright (C) 2015-2017  Renesas Electronics Corporation
 *
 * Based on the SuperH Ethernet driver.
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <errno.h>
#include <miiphy.h>
#include <malloc.h>
#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>
#include <asm/gpio.h>

/* Registers */
#define RAVB_REG_CCC		0x000
#define RAVB_REG_DBAT		0x004
#define RAVB_REG_CSR		0x00C
#define RAVB_REG_APSR		0x08C
#define RAVB_REG_RCR		0x090
#define RAVB_REG_TGC		0x300
#define RAVB_REG_TCCR		0x304
#define RAVB_REG_RIC0		0x360
#define RAVB_REG_RIC1		0x368
#define RAVB_REG_RIC2		0x370
#define RAVB_REG_TIC		0x378
#define RAVB_REG_ECMR		0x500
#define RAVB_REG_RFLR		0x508
#define RAVB_REG_ECSIPR		0x518
#define RAVB_REG_PIR		0x520
#define RAVB_REG_GECMR		0x5b0
#define RAVB_REG_MAHR		0x5c0
#define RAVB_REG_MALR		0x5c8

#define CCC_OPC_CONFIG		BIT(0)
#define CCC_OPC_OPERATION	BIT(1)
#define CCC_BOC			BIT(20)

#define CSR_OPS			0x0000000F
#define CSR_OPS_CONFIG		BIT(1)

#define TCCR_TSRQ0		BIT(0)

#define RFLR_RFL_MIN		0x05EE

#define PIR_MDI			BIT(3)
#define PIR_MDO			BIT(2)
#define PIR_MMD			BIT(1)
#define PIR_MDC			BIT(0)

#define ECMR_TRCCM		BIT(26)
#define ECMR_RZPF		BIT(20)
#define ECMR_PFR		BIT(18)
#define ECMR_RXF		BIT(17)
#define ECMR_RE			BIT(6)
#define ECMR_TE			BIT(5)
#define ECMR_DM			BIT(1)
#define ECMR_CHG_DM		(ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)

/* DMA Descriptors */
#define RAVB_NUM_BASE_DESC		16
#define RAVB_NUM_TX_DESC		8
#define RAVB_NUM_RX_DESC		8

#define RAVB_TX_QUEUE_OFFSET		0
#define RAVB_RX_QUEUE_OFFSET		4

#define RAVB_DESC_DT(n)			((n) << 28)
#define RAVB_DESC_DT_FSINGLE		RAVB_DESC_DT(0x7)
#define RAVB_DESC_DT_LINKFIX		RAVB_DESC_DT(0x9)
#define RAVB_DESC_DT_EOS		RAVB_DESC_DT(0xa)
#define RAVB_DESC_DT_FEMPTY		RAVB_DESC_DT(0xc)
#define RAVB_DESC_DT_EEMPTY		RAVB_DESC_DT(0x3)
#define RAVB_DESC_DT_MASK		RAVB_DESC_DT(0xf)

#define RAVB_DESC_DS(n)			(((n) & 0xfff) << 0)
#define RAVB_DESC_DS_MASK		0xfff

#define RAVB_RX_DESC_MSC_MC		BIT(23)
#define RAVB_RX_DESC_MSC_CEEF		BIT(22)
#define RAVB_RX_DESC_MSC_CRL		BIT(21)
#define RAVB_RX_DESC_MSC_FRE		BIT(20)
#define RAVB_RX_DESC_MSC_RTLF		BIT(19)
#define RAVB_RX_DESC_MSC_RTSF		BIT(18)
#define RAVB_RX_DESC_MSC_RFE		BIT(17)
#define RAVB_RX_DESC_MSC_CRC		BIT(16)
#define RAVB_RX_DESC_MSC_MASK		(0xff << 16)

#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
	(RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
	 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)

#define RAVB_TX_TIMEOUT_MS		1000

struct ravb_desc {
	u32	ctrl;
	u32	dptr;
};

struct ravb_rxdesc {
	struct ravb_desc	data;
	struct ravb_desc	link;
	u8			__pad[48];
	u8			packet[PKTSIZE_ALIGN];
};

struct ravb_priv {
	struct ravb_desc	base_desc[RAVB_NUM_BASE_DESC];
	struct ravb_desc	tx_desc[RAVB_NUM_TX_DESC];
	struct ravb_rxdesc	rx_desc[RAVB_NUM_RX_DESC];
	u32			rx_desc_idx;
	u32			tx_desc_idx;

	struct phy_device	*phydev;
	struct mii_dev		*bus;
	void __iomem		*iobase;
	struct clk		clk;
	struct gpio_desc	reset_gpio;
};

static inline void ravb_flush_dcache(u32 addr, u32 len)
{
	flush_dcache_range(addr, addr + len);
}

static inline void ravb_invalidate_dcache(u32 addr, u32 len)
{
	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
	u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
	invalidate_dcache_range(start, end);
}

static int ravb_send(struct udevice *dev, void *packet, int len)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
	unsigned int start;

	/* Update TX descriptor */
	ravb_flush_dcache((uintptr_t)packet, len);
	memset(desc, 0x0, sizeof(*desc));
	desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
	desc->dptr = (uintptr_t)packet;
	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));

	/* Restart the transmitter if disabled */
	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
		setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);

	/* Wait until packet is transmitted */
	start = get_timer(0);
	while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
		ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
		if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
			break;
		udelay(10);
	};

	if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
		return -ETIMEDOUT;

	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
	return 0;
}

static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
	int len;
	u8 *packet;

	/* Check if the rx descriptor is ready */
	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
		return -EAGAIN;

	/* Check for errors */
	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
		desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
		return -EAGAIN;
	}

	len = desc->data.ctrl & RAVB_DESC_DS_MASK;
	packet = (u8 *)(uintptr_t)desc->data.dptr;
	ravb_invalidate_dcache((uintptr_t)packet, len);

	*packetp = packet;
	return len;
}

static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];

	/* Make current descriptor available again */
	desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));

	/* Point to the next descriptor */
	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
	desc = &eth->rx_desc[eth->rx_desc_idx];
	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));

	return 0;
}

static int ravb_reset(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	/* Set config mode */
	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);

	/* Check the operating mode is changed to the config mode. */
	return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
				 CSR_OPS_CONFIG, true, 100, true);
}

static void ravb_base_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
	int i;

	/* Initialize all descriptors */
	memset(eth->base_desc, 0x0, desc_size);

	for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
		eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;

	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);

	/* Register the descriptor base address table */
	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
}

static void ravb_tx_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
	int i;

	/* Initialize all descriptors */
	memset(eth->tx_desc, 0x0, desc_size);
	eth->tx_desc_idx = 0;

	for (i = 0; i < RAVB_NUM_TX_DESC; i++)
		eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;

	/* Mark the end of the descriptors */
	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);

	/* Point the controller to the TX descriptor list. */
	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
			  sizeof(struct ravb_desc));
}

static void ravb_rx_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
	int i;

	/* Initialize all descriptors */
	memset(eth->rx_desc, 0x0, desc_size);
	eth->rx_desc_idx = 0;

	for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
		eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
					    RAVB_DESC_DS(PKTSIZE_ALIGN);
		eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;

		eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
		eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
	}

	/* Mark the end of the descriptors */
	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);

	/* Point the controller to the rx descriptor list */
	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
			  sizeof(struct ravb_desc));
}

static int ravb_phy_config(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct phy_device *phydev;
	int mask = 0xffffffff, reg;

	if (dm_gpio_is_valid(&eth->reset_gpio)) {
		dm_gpio_set_value(&eth->reset_gpio, 1);
		mdelay(20);
		dm_gpio_set_value(&eth->reset_gpio, 0);
		mdelay(1);
	}

	phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
	if (!phydev)
		return -ENODEV;

	phy_connect_dev(phydev, dev);

	eth->phydev = phydev;

	/* 10BASE is not supported for Ethernet AVB MAC */
	phydev->supported &= ~(SUPPORTED_10baseT_Full
			       | SUPPORTED_10baseT_Half);
	if (pdata->max_speed != 1000) {
		phydev->supported &= ~(SUPPORTED_1000baseT_Half
				       | SUPPORTED_1000baseT_Full);
		reg = phy_read(phydev, -1, MII_CTRL1000);
		reg &= ~(BIT(9) | BIT(8));
		phy_write(phydev, -1, MII_CTRL1000, reg);
	}

	phy_config(phydev);

	return 0;
}

/* Set Mac address */
static int ravb_write_hwaddr(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	unsigned char *mac = pdata->enetaddr;

	writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
	       eth->iobase + RAVB_REG_MAHR);

	writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);

	return 0;
}

/* E-MAC init function */
static int ravb_mac_init(struct ravb_priv *eth)
{
	/* Disable MAC Interrupt */
	writel(0, eth->iobase + RAVB_REG_ECSIPR);

	/* Recv frame limit set register */
	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);

	return 0;
}

/* AVB-DMAC init function */
static int ravb_dmac_init(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	int ret = 0;

	/* Set CONFIG mode */
	ret = ravb_reset(dev);
	if (ret)
		return ret;

	/* Disable all interrupts */
	writel(0, eth->iobase + RAVB_REG_RIC0);
	writel(0, eth->iobase + RAVB_REG_RIC1);
	writel(0, eth->iobase + RAVB_REG_RIC2);
	writel(0, eth->iobase + RAVB_REG_TIC);

	/* Set little endian */
	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);

	/* AVB rx set */
	writel(0x18000001, eth->iobase + RAVB_REG_RCR);

	/* FIFO size set */
	writel(0x00222210, eth->iobase + RAVB_REG_TGC);

	/* Delay CLK: 2ns */
	if (pdata->max_speed == 1000)
		writel(BIT(14), eth->iobase + RAVB_REG_APSR);

	return 0;
}

static int ravb_config(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct phy_device *phy = eth->phydev;
	u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
	int ret;

	/* Configure AVB-DMAC register */
	ravb_dmac_init(dev);

	/* Configure E-MAC registers */
	ravb_mac_init(eth);
	ravb_write_hwaddr(dev);

	ret = phy_startup(phy);
	if (ret)
		return ret;

	/* Set the transfer speed */
	if (phy->speed == 100)
		writel(0, eth->iobase + RAVB_REG_GECMR);
	else if (phy->speed == 1000)
		writel(1, eth->iobase + RAVB_REG_GECMR);

	/* Check if full duplex mode is supported by the phy */
	if (phy->duplex)
		mask |= ECMR_DM;

	writel(mask, eth->iobase + RAVB_REG_ECMR);

	phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);

	return 0;
}

static int ravb_start(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	int ret;

	ret = ravb_reset(dev);
	if (ret)
		return ret;

	ravb_base_desc_init(eth);
	ravb_tx_desc_init(eth);
	ravb_rx_desc_init(eth);

	ret = ravb_config(dev);
	if (ret)
		return ret;

	/* Setting the control will start the AVB-DMAC process. */
	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);

	return 0;
}

static void ravb_stop(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	phy_shutdown(eth->phydev);
	ravb_reset(dev);
}

static int ravb_probe(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct ravb_priv *eth = dev_get_priv(dev);
	struct mii_dev *mdiodev;
	void __iomem *iobase;
	int ret;

	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
	eth->iobase = iobase;

	ret = clk_get_by_index(dev, 0, &eth->clk);
	if (ret < 0)
		goto err_mdio_alloc;

	gpio_request_by_name(dev, "reset-gpios", 0, &eth->reset_gpio,
			     GPIOD_IS_OUT);

	mdiodev = mdio_alloc();
	if (!mdiodev) {
		ret = -ENOMEM;
		goto err_mdio_alloc;
	}

	mdiodev->read = bb_miiphy_read;
	mdiodev->write = bb_miiphy_write;
	bb_miiphy_buses[0].priv = eth;
	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);

	ret = mdio_register(mdiodev);
	if (ret < 0)
		goto err_mdio_register;

	eth->bus = miiphy_get_dev_by_name(dev->name);

	/* Bring up PHY */
	ret = clk_enable(&eth->clk);
	if (ret)
		goto err_mdio_register;

	ret = ravb_reset(dev);
	if (ret)
		goto err_mdio_reset;

	ret = ravb_phy_config(dev);
	if (ret)
		goto err_mdio_reset;

	return 0;

err_mdio_reset:
	clk_disable(&eth->clk);
err_mdio_register:
	mdio_free(mdiodev);
err_mdio_alloc:
	unmap_physmem(eth->iobase, MAP_NOCACHE);
	return ret;
}

static int ravb_remove(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	clk_disable(&eth->clk);

	free(eth->phydev);
	mdio_unregister(eth->bus);
	mdio_free(eth->bus);
	if (dm_gpio_is_valid(&eth->reset_gpio))
		dm_gpio_free(dev, &eth->reset_gpio);
	unmap_physmem(eth->iobase, MAP_NOCACHE);

	return 0;
}

int ravb_bb_init(struct bb_miiphy_bus *bus)
{
	return 0;
}

int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
{
	struct ravb_priv *eth = bus->priv;

	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);

	return 0;
}

int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
	struct ravb_priv *eth = bus->priv;

	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);

	return 0;
}

int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
	struct ravb_priv *eth = bus->priv;

	if (v)
		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	else
		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);

	return 0;
}

int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
	struct ravb_priv *eth = bus->priv;

	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;

	return 0;
}

int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
	struct ravb_priv *eth = bus->priv;

	if (v)
		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	else
		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);

	return 0;
}

int ravb_bb_delay(struct bb_miiphy_bus *bus)
{
	udelay(10);

	return 0;
}

struct bb_miiphy_bus bb_miiphy_buses[] = {
	{
		.name		= "ravb",
		.init		= ravb_bb_init,
		.mdio_active	= ravb_bb_mdio_active,
		.mdio_tristate	= ravb_bb_mdio_tristate,
		.set_mdio	= ravb_bb_set_mdio,
		.get_mdio	= ravb_bb_get_mdio,
		.set_mdc	= ravb_bb_set_mdc,
		.delay		= ravb_bb_delay,
	},
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);

static const struct eth_ops ravb_ops = {
	.start			= ravb_start,
	.send			= ravb_send,
	.recv			= ravb_recv,
	.free_pkt		= ravb_free_pkt,
	.stop			= ravb_stop,
	.write_hwaddr		= ravb_write_hwaddr,
};

int ravb_ofdata_to_platdata(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	const char *phy_mode;
	const fdt32_t *cell;
	int ret = 0;

	pdata->iobase = devfdt_get_addr(dev);
	pdata->phy_interface = -1;
	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
			       NULL);
	if (phy_mode)
		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
	if (pdata->phy_interface == -1) {
		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
		return -EINVAL;
	}

	pdata->max_speed = 1000;
	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
	if (cell)
		pdata->max_speed = fdt32_to_cpu(*cell);

	sprintf(bb_miiphy_buses[0].name, dev->name);

	return ret;
}

static const struct udevice_id ravb_ids[] = {
	{ .compatible = "renesas,etheravb-r8a7795" },
	{ .compatible = "renesas,etheravb-r8a7796" },
	{ .compatible = "renesas,etheravb-r8a77965" },
	{ .compatible = "renesas,etheravb-r8a77970" },
	{ .compatible = "renesas,etheravb-r8a77990" },
	{ .compatible = "renesas,etheravb-r8a77995" },
	{ .compatible = "renesas,etheravb-rcar-gen3" },
	{ }
};

U_BOOT_DRIVER(eth_ravb) = {
	.name		= "ravb",
	.id		= UCLASS_ETH,
	.of_match	= ravb_ids,
	.ofdata_to_platdata = ravb_ofdata_to_platdata,
	.probe		= ravb_probe,
	.remove		= ravb_remove,
	.ops		= &ravb_ops,
	.priv_auto_alloc_size = sizeof(struct ravb_priv),
	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
8ae51b6f MV	2	/*
	3	* drivers/net/ravb.c
	4	* This file is driver for Renesas Ethernet AVB.
	5	*
	6	* Copyright (C) 2015-2017 Renesas Electronics Corporation
	7	*
	8	* Based on the SuperH Ethernet driver.
8ae51b6f MV	9	*/
	10
	11	#include <common.h>
1fea9e25	12	#include <clk.h>
8ae51b6f MV	13	#include <dm.h>
	14	#include <errno.h>
	15	#include <miiphy.h>
	16	#include <malloc.h>
	17	#include <linux/mii.h>
	18	#include <wait_bit.h>
	19	#include <asm/io.h>
bddb44e9	20	#include <asm/gpio.h>
8ae51b6f MV	21
	22	/* Registers */
	23	#define RAVB_REG_CCC 0x000
	24	#define RAVB_REG_DBAT 0x004
	25	#define RAVB_REG_CSR 0x00C
	26	#define RAVB_REG_APSR 0x08C
	27	#define RAVB_REG_RCR 0x090
	28	#define RAVB_REG_TGC 0x300
	29	#define RAVB_REG_TCCR 0x304
	30	#define RAVB_REG_RIC0 0x360
	31	#define RAVB_REG_RIC1 0x368
	32	#define RAVB_REG_RIC2 0x370
	33	#define RAVB_REG_TIC 0x378
	34	#define RAVB_REG_ECMR 0x500
	35	#define RAVB_REG_RFLR 0x508
	36	#define RAVB_REG_ECSIPR 0x518
	37	#define RAVB_REG_PIR 0x520
	38	#define RAVB_REG_GECMR 0x5b0
	39	#define RAVB_REG_MAHR 0x5c0
	40	#define RAVB_REG_MALR 0x5c8
	41
	42	#define CCC_OPC_CONFIG BIT(0)
	43	#define CCC_OPC_OPERATION BIT(1)
	44	#define CCC_BOC BIT(20)
	45
	46	#define CSR_OPS 0x0000000F
	47	#define CSR_OPS_CONFIG BIT(1)
	48
	49	#define TCCR_TSRQ0 BIT(0)
	50
	51	#define RFLR_RFL_MIN 0x05EE
	52
	53	#define PIR_MDI BIT(3)
	54	#define PIR_MDO BIT(2)
	55	#define PIR_MMD BIT(1)
	56	#define PIR_MDC BIT(0)
	57
	58	#define ECMR_TRCCM BIT(26)
	59	#define ECMR_RZPF BIT(20)
	60	#define ECMR_PFR BIT(18)
	61	#define ECMR_RXF BIT(17)
	62	#define ECMR_RE BIT(6)
	63	#define ECMR_TE BIT(5)
	64	#define ECMR_DM BIT(1)
	65	#define ECMR_CHG_DM (ECMR_TRCCM \| ECMR_RZPF \| ECMR_PFR \| ECMR_RXF)
	66
	67	/* DMA Descriptors */
	68	#define RAVB_NUM_BASE_DESC 16
	69	#define RAVB_NUM_TX_DESC 8
	70	#define RAVB_NUM_RX_DESC 8
	71
	72	#define RAVB_TX_QUEUE_OFFSET 0
	73	#define RAVB_RX_QUEUE_OFFSET 4
	74
	75	#define RAVB_DESC_DT(n) ((n) << 28)
	76	#define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
	77	#define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
	78	#define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
	79	#define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
	80	#define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
	81	#define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
	82
	83	#define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
	84	#define RAVB_DESC_DS_MASK 0xfff
85
86	#define RAVB_RX_DESC_MSC_MC BIT(23)
87	#define RAVB_RX_DESC_MSC_CEEF BIT(22)
88	#define RAVB_RX_DESC_MSC_CRL BIT(21)
89	#define RAVB_RX_DESC_MSC_FRE BIT(20)
90	#define RAVB_RX_DESC_MSC_RTLF BIT(19)
91	#define RAVB_RX_DESC_MSC_RTSF BIT(18)
92	#define RAVB_RX_DESC_MSC_RFE BIT(17)
93	#define RAVB_RX_DESC_MSC_CRC BIT(16)
94	#define RAVB_RX_DESC_MSC_MASK (0xff << 16)
95
96	#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
97	(RAVB_RX_DESC_MSC_CRC \| RAVB_RX_DESC_MSC_RFE \| RAVB_RX_DESC_MSC_RTLF \| \
98	RAVB_RX_DESC_MSC_RTSF \| RAVB_RX_DESC_MSC_CEEF)
99
100	#define RAVB_TX_TIMEOUT_MS 1000
101
102	struct ravb_desc {
103	u32 ctrl;
104	u32 dptr;
105	};
106
107	struct ravb_rxdesc {
108	struct ravb_desc data;
109	struct ravb_desc link;
110	u8 __pad[48];
111	u8 packet[PKTSIZE_ALIGN];
112	};
113
114	struct ravb_priv {
115	struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
116	struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
117	struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
118	u32 rx_desc_idx;
119	u32 tx_desc_idx;
120
121	struct phy_device *phydev;
122	struct mii_dev *bus;
123	void __iomem *iobase;
1fea9e25	124	struct clk clk;
bddb44e9	125	struct gpio_desc reset_gpio;
8ae51b6f MV	126	};
	127
	128	static inline void ravb_flush_dcache(u32 addr, u32 len)
	129	{
	130	flush_dcache_range(addr, addr + len);
	131	}
	132
	133	static inline void ravb_invalidate_dcache(u32 addr, u32 len)
	134	{
	135	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
	136	u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
	137	invalidate_dcache_range(start, end);
	138	}
	139
	140	static int ravb_send(struct udevice dev, void packet, int len)
	141	{
	142	struct ravb_priv *eth = dev_get_priv(dev);
	143	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
	144	unsigned int start;
	145
	146	/* Update TX descriptor */
	147	ravb_flush_dcache((uintptr_t)packet, len);
	148	memset(desc, 0x0, sizeof(*desc));
	149	desc->ctrl = RAVB_DESC_DT_FSINGLE \| RAVB_DESC_DS(len);
	150	desc->dptr = (uintptr_t)packet;
	151	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
	152
	153	/* Restart the transmitter if disabled */
	154	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
	155	setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
	156
	157	/* Wait until packet is transmitted */
	158	start = get_timer(0);
	159	while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
	160	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	161	if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
	162	break;
	163	udelay(10);
	164	};
	165
	166	if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
	167	return -ETIMEDOUT;
	168
	169	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
	170	return 0;
	171	}
	172
	173	static int ravb_recv(struct udevice dev, int flags, uchar *packetp)
	174	{
	175	struct ravb_priv *eth = dev_get_priv(dev);
	176	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
	177	int len;
	178	u8 *packet;
	179
	180	/* Check if the rx descriptor is ready */
	181	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	182	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
	183	return -EAGAIN;
	184
	185	/* Check for errors */
	186	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
	187	desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
	188	return -EAGAIN;
	189	}
190
191	len = desc->data.ctrl & RAVB_DESC_DS_MASK;
192	packet = (u8 *)(uintptr_t)desc->data.dptr;
193	ravb_invalidate_dcache((uintptr_t)packet, len);
194
195	*packetp = packet;
196	return len;
197	}
198
199	static int ravb_free_pkt(struct udevice dev, uchar packet, int length)
200	{
201	struct ravb_priv *eth = dev_get_priv(dev);
202	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
203
204	/* Make current descriptor available again */
205	desc->data.ctrl = RAVB_DESC_DT_FEMPTY \| RAVB_DESC_DS(PKTSIZE_ALIGN);
206	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
207
208	/* Point to the next descriptor */
209	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
210	desc = &eth->rx_desc[eth->rx_desc_idx];
211	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
212
213	return 0;
214	}
215
216	static int ravb_reset(struct udevice *dev)
217	{
218	struct ravb_priv *eth = dev_get_priv(dev);
219
220	/* Set config mode */
221	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
222
223	/* Check the operating mode is changed to the config mode. */
48263504 ÁFR	224	return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
48263504 ÁFR	225	CSR_OPS_CONFIG, true, 100, true);
8ae51b6f MV	226	}
	227
	228	static void ravb_base_desc_init(struct ravb_priv *eth)
	229	{
	230	const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
	231	int i;
	232
	233	/* Initialize all descriptors */
	234	memset(eth->base_desc, 0x0, desc_size);
	235
	236	for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
	237	eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
	238
	239	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
	240
	241	/* Register the descriptor base address table */
	242	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
	243	}
	244
	245	static void ravb_tx_desc_init(struct ravb_priv *eth)
	246	{
	247	const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
	248	int i;
	249
	250	/* Initialize all descriptors */
	251	memset(eth->tx_desc, 0x0, desc_size);
	252	eth->tx_desc_idx = 0;
	253
	254	for (i = 0; i < RAVB_NUM_TX_DESC; i++)
	255	eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
	256
	257	/* Mark the end of the descriptors */
	258	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
	259	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
	260	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
	261
	262	/* Point the controller to the TX descriptor list. */
	263	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	264	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
	265	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
	266	sizeof(struct ravb_desc));
	267	}
	268
	269	static void ravb_rx_desc_init(struct ravb_priv *eth)
	270	{
	271	const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
	272	int i;
	273
	274	/* Initialize all descriptors */
	275	memset(eth->rx_desc, 0x0, desc_size);
	276	eth->rx_desc_idx = 0;
	277
	278	for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
	279	eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY \|
	280	RAVB_DESC_DS(PKTSIZE_ALIGN);
	281	eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
	282
	283	eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
	284	eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
	285	}
	286
	287	/* Mark the end of the descriptors */
	288	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
	289	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
290	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
291
292	/* Point the controller to the rx descriptor list */
293	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
294	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
295	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
296	sizeof(struct ravb_desc));
297	}
298
299	static int ravb_phy_config(struct udevice *dev)
300	{
301	struct ravb_priv *eth = dev_get_priv(dev);
302	struct eth_pdata *pdata = dev_get_platdata(dev);
303	struct phy_device *phydev;
e821a7bd	304	int mask = 0xffffffff, reg;
8ae51b6f	305
bddb44e9 MV	306	if (dm_gpio_is_valid(&eth->reset_gpio)) {
	307	dm_gpio_set_value(&eth->reset_gpio, 1);
	308	mdelay(20);
	309	dm_gpio_set_value(&eth->reset_gpio, 0);
	310	mdelay(1);
	311	}
	312
e821a7bd	313	phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
8ae51b6f MV	314	if (!phydev)
	315	return -ENODEV;
	316
e821a7bd MV	317	phy_connect_dev(phydev, dev);
e821a7bd MV	318
8ae51b6f MV	319	eth->phydev = phydev;
	320
	321	/* 10BASE is not supported for Ethernet AVB MAC */
	322	phydev->supported &= ~(SUPPORTED_10baseT_Full
	323	\| SUPPORTED_10baseT_Half);
	324	if (pdata->max_speed != 1000) {
	325	phydev->supported &= ~(SUPPORTED_1000baseT_Half
	326	\| SUPPORTED_1000baseT_Full);
	327	reg = phy_read(phydev, -1, MII_CTRL1000);
	328	reg &= ~(BIT(9) \| BIT(8));
	329	phy_write(phydev, -1, MII_CTRL1000, reg);
	330	}
	331
	332	phy_config(phydev);
	333
	334	return 0;
	335	}
	336
	337	/* Set Mac address */
	338	static int ravb_write_hwaddr(struct udevice *dev)
	339	{
	340	struct ravb_priv *eth = dev_get_priv(dev);
	341	struct eth_pdata *pdata = dev_get_platdata(dev);
	342	unsigned char *mac = pdata->enetaddr;
	343
	344	writel((mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3],
	345	eth->iobase + RAVB_REG_MAHR);
	346
	347	writel((mac[4] << 8) \| mac[5], eth->iobase + RAVB_REG_MALR);
	348
	349	return 0;
	350	}
	351
	352	/* E-MAC init function */
	353	static int ravb_mac_init(struct ravb_priv *eth)
	354	{
	355	/* Disable MAC Interrupt */
	356	writel(0, eth->iobase + RAVB_REG_ECSIPR);
	357
	358	/* Recv frame limit set register */
	359	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
	360
	361	return 0;
	362	}
	363
	364	/* AVB-DMAC init function */
	365	static int ravb_dmac_init(struct udevice *dev)
	366	{
	367	struct ravb_priv *eth = dev_get_priv(dev);
	368	struct eth_pdata *pdata = dev_get_platdata(dev);
	369	int ret = 0;
	370
	371	/* Set CONFIG mode */
	372	ret = ravb_reset(dev);
	373	if (ret)
	374	return ret;
	375
	376	/* Disable all interrupts */
	377	writel(0, eth->iobase + RAVB_REG_RIC0);
	378	writel(0, eth->iobase + RAVB_REG_RIC1);
	379	writel(0, eth->iobase + RAVB_REG_RIC2);
	380	writel(0, eth->iobase + RAVB_REG_TIC);
	381
	382	/* Set little endian */
383	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
384
385	/* AVB rx set */
386	writel(0x18000001, eth->iobase + RAVB_REG_RCR);
387
388	/* FIFO size set */
389	writel(0x00222210, eth->iobase + RAVB_REG_TGC);
390
391	/* Delay CLK: 2ns */
392	if (pdata->max_speed == 1000)
393	writel(BIT(14), eth->iobase + RAVB_REG_APSR);
394
395	return 0;
396	}
397
398	static int ravb_config(struct udevice *dev)
399	{
400	struct ravb_priv *eth = dev_get_priv(dev);
d64c7894	401	struct phy_device *phy = eth->phydev;
8ae51b6f MV	402	u32 mask = ECMR_CHG_DM \| ECMR_RE \| ECMR_TE;
	403	int ret;
	404
	405	/* Configure AVB-DMAC register */
	406	ravb_dmac_init(dev);
	407
	408	/* Configure E-MAC registers */
	409	ravb_mac_init(eth);
	410	ravb_write_hwaddr(dev);
	411
8ae51b6f MV	412	ret = phy_startup(phy);
	413	if (ret)
	414	return ret;
	415
	416	/* Set the transfer speed */
	417	if (phy->speed == 100)
	418	writel(0, eth->iobase + RAVB_REG_GECMR);
	419	else if (phy->speed == 1000)
	420	writel(1, eth->iobase + RAVB_REG_GECMR);
	421
	422	/* Check if full duplex mode is supported by the phy */
	423	if (phy->duplex)
	424	mask \|= ECMR_DM;
	425
	426	writel(mask, eth->iobase + RAVB_REG_ECMR);
	427
	428	phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) \| 0x19);
	429
	430	return 0;
	431	}
	432
e3105eac	433	static int ravb_start(struct udevice *dev)
8ae51b6f MV	434	{
	435	struct ravb_priv *eth = dev_get_priv(dev);
	436	int ret;
	437
1fea9e25 MV	438	ret = ravb_reset(dev);
1fea9e25 MV	439	if (ret)
c4a8d9ca	440	return ret;
1fea9e25	441
8ae51b6f MV	442	ravb_base_desc_init(eth);
	443	ravb_tx_desc_init(eth);
	444	ravb_rx_desc_init(eth);
	445
	446	ret = ravb_config(dev);
	447	if (ret)
c4a8d9ca	448	return ret;
8ae51b6f MV	449
	450	/* Setting the control will start the AVB-DMAC process. */
	451	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
	452
	453	return 0;
	454	}
	455
	456	static void ravb_stop(struct udevice *dev)
	457	{
1fea9e25 MV	458	struct ravb_priv *eth = dev_get_priv(dev);
1fea9e25 MV	459
d64c7894	460	phy_shutdown(eth->phydev);
8ae51b6f MV	461	ravb_reset(dev);
	462	}
	463
	464	static int ravb_probe(struct udevice *dev)
	465	{
	466	struct eth_pdata *pdata = dev_get_platdata(dev);
	467	struct ravb_priv *eth = dev_get_priv(dev);
	468	struct mii_dev *mdiodev;
	469	void __iomem *iobase;
	470	int ret;
	471
	472	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
	473	eth->iobase = iobase;
	474
1fea9e25 MV	475	ret = clk_get_by_index(dev, 0, &eth->clk);
	476	if (ret < 0)
	477	goto err_mdio_alloc;
	478
90997cda MV	479	gpio_request_by_name(dev, "reset-gpios", 0, &eth->reset_gpio,
90997cda MV	480	GPIOD_IS_OUT);
bddb44e9	481
8ae51b6f MV	482	mdiodev = mdio_alloc();
	483	if (!mdiodev) {
	484	ret = -ENOMEM;
	485	goto err_mdio_alloc;
	486	}
	487
	488	mdiodev->read = bb_miiphy_read;
	489	mdiodev->write = bb_miiphy_write;
	490	bb_miiphy_buses[0].priv = eth;
	491	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
	492
	493	ret = mdio_register(mdiodev);
	494	if (ret < 0)
	495	goto err_mdio_register;
	496
	497	eth->bus = miiphy_get_dev_by_name(dev->name);
	498
d64c7894 MV	499	/* Bring up PHY */
	500	ret = clk_enable(&eth->clk);
	501	if (ret)
	502	goto err_mdio_register;
	503
	504	ret = ravb_reset(dev);
	505	if (ret)
	506	goto err_mdio_reset;
	507
	508	ret = ravb_phy_config(dev);
	509	if (ret)
	510	goto err_mdio_reset;
	511
8ae51b6f MV	512	return 0;
8ae51b6f MV	513
d64c7894 MV	514	err_mdio_reset:
d64c7894 MV	515	clk_disable(&eth->clk);
8ae51b6f MV	516	err_mdio_register:
	517	mdio_free(mdiodev);
	518	err_mdio_alloc:
	519	unmap_physmem(eth->iobase, MAP_NOCACHE);
	520	return ret;
	521	}
	522
	523	static int ravb_remove(struct udevice *dev)
	524	{
	525	struct ravb_priv *eth = dev_get_priv(dev);
	526
d64c7894 MV	527	clk_disable(&eth->clk);
d64c7894 MV	528
8ae51b6f MV	529	free(eth->phydev);
	530	mdio_unregister(eth->bus);
	531	mdio_free(eth->bus);
90997cda MV	532	if (dm_gpio_is_valid(&eth->reset_gpio))
90997cda MV	533	dm_gpio_free(dev, &eth->reset_gpio);
8ae51b6f MV	534	unmap_physmem(eth->iobase, MAP_NOCACHE);
	535
	536	return 0;
	537	}
	538
	539	int ravb_bb_init(struct bb_miiphy_bus *bus)
	540	{
	541	return 0;
	542	}
	543
	544	int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
	545	{
	546	struct ravb_priv *eth = bus->priv;
	547
	548	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
	549
	550	return 0;
	551	}
	552
	553	int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
	554	{
	555	struct ravb_priv *eth = bus->priv;
	556
	557	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
	558
	559	return 0;
	560	}
	561
	562	int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
	563	{
	564	struct ravb_priv *eth = bus->priv;
	565
	566	if (v)
	567	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	568	else
	569	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	570
	571	return 0;
	572	}
	573
	574	int ravb_bb_get_mdio(struct bb_miiphy_bus bus, int v)
	575	{
	576	struct ravb_priv *eth = bus->priv;
	577
	578	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
	579
	580	return 0;
	581	}
	582
	583	int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
	584	{
	585	struct ravb_priv *eth = bus->priv;
	586
	587	if (v)
	588	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	589	else
	590	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	591
	592	return 0;
	593	}
	594
	595	int ravb_bb_delay(struct bb_miiphy_bus *bus)
	596	{
	597	udelay(10);
598
599	return 0;
600	}
601
602	struct bb_miiphy_bus bb_miiphy_buses[] = {
603	{
604	.name = "ravb",
605	.init = ravb_bb_init,
606	.mdio_active = ravb_bb_mdio_active,
607	.mdio_tristate = ravb_bb_mdio_tristate,
608	.set_mdio = ravb_bb_set_mdio,
609	.get_mdio = ravb_bb_get_mdio,
610	.set_mdc = ravb_bb_set_mdc,
611	.delay = ravb_bb_delay,
612	},
613	};
614	int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
615
616	static const struct eth_ops ravb_ops = {
617	.start = ravb_start,
618	.send = ravb_send,
619	.recv = ravb_recv,
620	.free_pkt = ravb_free_pkt,
621	.stop = ravb_stop,
622	.write_hwaddr = ravb_write_hwaddr,
623	};
624
5ee8b4d7 MV	625	int ravb_ofdata_to_platdata(struct udevice *dev)
	626	{
	627	struct eth_pdata *pdata = dev_get_platdata(dev);
	628	const char *phy_mode;
	629	const fdt32_t *cell;
	630	int ret = 0;
	631
	632	pdata->iobase = devfdt_get_addr(dev);
	633	pdata->phy_interface = -1;
	634	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
	635	NULL);
	636	if (phy_mode)
	637	pdata->phy_interface = phy_get_interface_by_name(phy_mode);
	638	if (pdata->phy_interface == -1) {
	639	debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
	640	return -EINVAL;
	641	}
	642
	643	pdata->max_speed = 1000;
	644	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
	645	if (cell)
	646	pdata->max_speed = fdt32_to_cpu(*cell);
	647
	648	sprintf(bb_miiphy_buses[0].name, dev->name);
	649
	650	return ret;
	651	}
	652
	653	static const struct udevice_id ravb_ids[] = {
	654	{ .compatible = "renesas,etheravb-r8a7795" },
	655	{ .compatible = "renesas,etheravb-r8a7796" },
7a7081e6	656	{ .compatible = "renesas,etheravb-r8a77965" },
dc3bb3d4	657	{ .compatible = "renesas,etheravb-r8a77970" },
34f1dba9	658	{ .compatible = "renesas,etheravb-r8a77990" },
9e4a6373	659	{ .compatible = "renesas,etheravb-r8a77995" },
5ee8b4d7 MV	660	{ .compatible = "renesas,etheravb-rcar-gen3" },
	661	{ }
	662	};
	663
8ae51b6f MV	664	U_BOOT_DRIVER(eth_ravb) = {
	665	.name = "ravb",
	666	.id = UCLASS_ETH,
5ee8b4d7 MV	667	.of_match = ravb_ids,
5ee8b4d7 MV	668	.ofdata_to_platdata = ravb_ofdata_to_platdata,
8ae51b6f MV	669	.probe = ravb_probe,
	670	.remove = ravb_remove,
	671	.ops = &ravb_ops,
	672	.priv_auto_alloc_size = sizeof(struct ravb_priv),
	673	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	674	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	675	};