[J-u-boot.git] / drivers / net / ravb.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * drivers/net/ravb.c
 *     This file is driver for Renesas Ethernet AVB.
 *
 * Copyright (C) 2015-2017  Renesas Electronics Corporation
 *
 * Based on the SuperH Ethernet driver.
 */

#include <common.h>
#include <clk.h>
#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <miiphy.h>
#include <malloc.h>
#include <asm/cache.h>
#include <linux/delay.h>
#include <linux/mii.h>
#include <wait_bit.h>
#include <asm/io.h>
#include <asm/gpio.h>

/* Registers */
#define RAVB_REG_CCC		0x000
#define RAVB_REG_DBAT		0x004
#define RAVB_REG_CSR		0x00C
#define RAVB_REG_APSR		0x08C
#define RAVB_REG_RCR		0x090
#define RAVB_REG_TGC		0x300
#define RAVB_REG_TCCR		0x304
#define RAVB_REG_RIC0		0x360
#define RAVB_REG_RIC1		0x368
#define RAVB_REG_RIC2		0x370
#define RAVB_REG_TIC		0x378
#define RAVB_REG_ECMR		0x500
#define RAVB_REG_RFLR		0x508
#define RAVB_REG_ECSIPR		0x518
#define RAVB_REG_PIR		0x520
#define RAVB_REG_GECMR		0x5b0
#define RAVB_REG_MAHR		0x5c0
#define RAVB_REG_MALR		0x5c8

#define CCC_OPC_CONFIG		BIT(0)
#define CCC_OPC_OPERATION	BIT(1)
#define CCC_BOC			BIT(20)

#define CSR_OPS			0x0000000F
#define CSR_OPS_CONFIG		BIT(1)

#define APSR_TDM		BIT(14)

#define TCCR_TSRQ0		BIT(0)

#define RFLR_RFL_MIN		0x05EE

#define PIR_MDI			BIT(3)
#define PIR_MDO			BIT(2)
#define PIR_MMD			BIT(1)
#define PIR_MDC			BIT(0)

#define ECMR_TRCCM		BIT(26)
#define ECMR_RZPF		BIT(20)
#define ECMR_PFR		BIT(18)
#define ECMR_RXF		BIT(17)
#define ECMR_RE			BIT(6)
#define ECMR_TE			BIT(5)
#define ECMR_DM			BIT(1)
#define ECMR_CHG_DM		(ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)

/* DMA Descriptors */
#define RAVB_NUM_BASE_DESC		16
#define RAVB_NUM_TX_DESC		8
#define RAVB_NUM_RX_DESC		8

#define RAVB_TX_QUEUE_OFFSET		0
#define RAVB_RX_QUEUE_OFFSET		4

#define RAVB_DESC_DT(n)			((n) << 28)
#define RAVB_DESC_DT_FSINGLE		RAVB_DESC_DT(0x7)
#define RAVB_DESC_DT_LINKFIX		RAVB_DESC_DT(0x9)
#define RAVB_DESC_DT_EOS		RAVB_DESC_DT(0xa)
#define RAVB_DESC_DT_FEMPTY		RAVB_DESC_DT(0xc)
#define RAVB_DESC_DT_EEMPTY		RAVB_DESC_DT(0x3)
#define RAVB_DESC_DT_MASK		RAVB_DESC_DT(0xf)

#define RAVB_DESC_DS(n)			(((n) & 0xfff) << 0)
#define RAVB_DESC_DS_MASK		0xfff

#define RAVB_RX_DESC_MSC_MC		BIT(23)
#define RAVB_RX_DESC_MSC_CEEF		BIT(22)
#define RAVB_RX_DESC_MSC_CRL		BIT(21)
#define RAVB_RX_DESC_MSC_FRE		BIT(20)
#define RAVB_RX_DESC_MSC_RTLF		BIT(19)
#define RAVB_RX_DESC_MSC_RTSF		BIT(18)
#define RAVB_RX_DESC_MSC_RFE		BIT(17)
#define RAVB_RX_DESC_MSC_CRC		BIT(16)
#define RAVB_RX_DESC_MSC_MASK		(0xff << 16)

#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
	(RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
	 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)

#define RAVB_TX_TIMEOUT_MS		1000

struct ravb_desc {
	u32	ctrl;
	u32	dptr;
};

struct ravb_rxdesc {
	struct ravb_desc	data;
	struct ravb_desc	link;
	u8			__pad[48];
	u8			packet[PKTSIZE_ALIGN];
};

struct ravb_priv {
	struct ravb_desc	base_desc[RAVB_NUM_BASE_DESC];
	struct ravb_desc	tx_desc[RAVB_NUM_TX_DESC];
	struct ravb_rxdesc	rx_desc[RAVB_NUM_RX_DESC];
	u32			rx_desc_idx;
	u32			tx_desc_idx;

	struct phy_device	*phydev;
	struct mii_dev		*bus;
	void __iomem		*iobase;
	struct clk		clk;
	struct gpio_desc	reset_gpio;
};

static inline void ravb_flush_dcache(u32 addr, u32 len)
{
	flush_dcache_range(addr, addr + len);
}

static inline void ravb_invalidate_dcache(u32 addr, u32 len)
{
	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
	u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
	invalidate_dcache_range(start, end);
}

static int ravb_send(struct udevice *dev, void *packet, int len)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
	unsigned int start;

	/* Update TX descriptor */
	ravb_flush_dcache((uintptr_t)packet, len);
	memset(desc, 0x0, sizeof(*desc));
	desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
	desc->dptr = (uintptr_t)packet;
	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));

	/* Restart the transmitter if disabled */
	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
		setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);

	/* Wait until packet is transmitted */
	start = get_timer(0);
	while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
		ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
		if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
			break;
		udelay(10);
	};

	if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
		return -ETIMEDOUT;

	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
	return 0;
}

static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
	int len;
	u8 *packet;

	/* Check if the rx descriptor is ready */
	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
		return -EAGAIN;

	/* Check for errors */
	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
		desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
		return -EAGAIN;
	}

	len = desc->data.ctrl & RAVB_DESC_DS_MASK;
	packet = (u8 *)(uintptr_t)desc->data.dptr;
	ravb_invalidate_dcache((uintptr_t)packet, len);

	*packetp = packet;
	return len;
}

static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];

	/* Make current descriptor available again */
	desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));

	/* Point to the next descriptor */
	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
	desc = &eth->rx_desc[eth->rx_desc_idx];
	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));

	return 0;
}

static int ravb_reset(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	/* Set config mode */
	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);

	/* Check the operating mode is changed to the config mode. */
	return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
				 CSR_OPS_CONFIG, true, 100, true);
}

static void ravb_base_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
	int i;

	/* Initialize all descriptors */
	memset(eth->base_desc, 0x0, desc_size);

	for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
		eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;

	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);

	/* Register the descriptor base address table */
	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
}

static void ravb_tx_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
	int i;

	/* Initialize all descriptors */
	memset(eth->tx_desc, 0x0, desc_size);
	eth->tx_desc_idx = 0;

	for (i = 0; i < RAVB_NUM_TX_DESC; i++)
		eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;

	/* Mark the end of the descriptors */
	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);

	/* Point the controller to the TX descriptor list. */
	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
			  sizeof(struct ravb_desc));
}

static void ravb_rx_desc_init(struct ravb_priv *eth)
{
	const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
	int i;

	/* Initialize all descriptors */
	memset(eth->rx_desc, 0x0, desc_size);
	eth->rx_desc_idx = 0;

	for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
		eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
					    RAVB_DESC_DS(PKTSIZE_ALIGN);
		eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;

		eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
		eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
	}

	/* Mark the end of the descriptors */
	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);

	/* Point the controller to the rx descriptor list */
	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
			  sizeof(struct ravb_desc));
}

static int ravb_phy_config(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct phy_device *phydev;
	int mask = 0xffffffff, reg;

	if (dm_gpio_is_valid(&eth->reset_gpio)) {
		dm_gpio_set_value(&eth->reset_gpio, 1);
		mdelay(20);
		dm_gpio_set_value(&eth->reset_gpio, 0);
		mdelay(1);
	}

	phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
	if (!phydev)
		return -ENODEV;

	phy_connect_dev(phydev, dev);

	eth->phydev = phydev;

	phydev->supported &= SUPPORTED_100baseT_Full |
			     SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
			     SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_Pause |
			     SUPPORTED_Asym_Pause;

	if (pdata->max_speed != 1000) {
		phydev->supported &= ~SUPPORTED_1000baseT_Full;
		reg = phy_read(phydev, -1, MII_CTRL1000);
		reg &= ~(BIT(9) | BIT(8));
		phy_write(phydev, -1, MII_CTRL1000, reg);
	}

	phy_config(phydev);

	return 0;
}

/* Set Mac address */
static int ravb_write_hwaddr(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	unsigned char *mac = pdata->enetaddr;

	writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
	       eth->iobase + RAVB_REG_MAHR);

	writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);

	return 0;
}

/* E-MAC init function */
static int ravb_mac_init(struct ravb_priv *eth)
{
	/* Disable MAC Interrupt */
	writel(0, eth->iobase + RAVB_REG_ECSIPR);

	/* Recv frame limit set register */
	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);

	return 0;
}

/* AVB-DMAC init function */
static int ravb_dmac_init(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	int ret = 0;

	/* Set CONFIG mode */
	ret = ravb_reset(dev);
	if (ret)
		return ret;

	/* Disable all interrupts */
	writel(0, eth->iobase + RAVB_REG_RIC0);
	writel(0, eth->iobase + RAVB_REG_RIC1);
	writel(0, eth->iobase + RAVB_REG_RIC2);
	writel(0, eth->iobase + RAVB_REG_TIC);

	/* Set little endian */
	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);

	/* AVB rx set */
	writel(0x18000001, eth->iobase + RAVB_REG_RCR);

	/* FIFO size set */
	writel(0x00222210, eth->iobase + RAVB_REG_TGC);

	/* Delay CLK: 2ns (not applicable on R-Car E3/D3) */
	if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) ||
	    (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
		return 0;

	if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
	    (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID))
		writel(APSR_TDM, eth->iobase + RAVB_REG_APSR);

	return 0;
}

static int ravb_config(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	struct phy_device *phy = eth->phydev;
	u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
	int ret;

	/* Configure AVB-DMAC register */
	ravb_dmac_init(dev);

	/* Configure E-MAC registers */
	ravb_mac_init(eth);
	ravb_write_hwaddr(dev);

	ret = phy_startup(phy);
	if (ret)
		return ret;

	/* Set the transfer speed */
	if (phy->speed == 100)
		writel(0, eth->iobase + RAVB_REG_GECMR);
	else if (phy->speed == 1000)
		writel(1, eth->iobase + RAVB_REG_GECMR);

	/* Check if full duplex mode is supported by the phy */
	if (phy->duplex)
		mask |= ECMR_DM;

	writel(mask, eth->iobase + RAVB_REG_ECMR);

	phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) | 0x19);

	return 0;
}

static int ravb_start(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);
	int ret;

	ret = ravb_reset(dev);
	if (ret)
		return ret;

	ravb_base_desc_init(eth);
	ravb_tx_desc_init(eth);
	ravb_rx_desc_init(eth);

	ret = ravb_config(dev);
	if (ret)
		return ret;

	/* Setting the control will start the AVB-DMAC process. */
	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);

	return 0;
}

static void ravb_stop(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	phy_shutdown(eth->phydev);
	ravb_reset(dev);
}

static int ravb_probe(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	struct ravb_priv *eth = dev_get_priv(dev);
	struct ofnode_phandle_args phandle_args;
	struct mii_dev *mdiodev;
	void __iomem *iobase;
	int ret;

	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
	eth->iobase = iobase;

	ret = clk_get_by_index(dev, 0, &eth->clk);
	if (ret < 0)
		goto err_mdio_alloc;

	ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args);
	if (!ret) {
		gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
					   &eth->reset_gpio, GPIOD_IS_OUT);
	}

	if (!dm_gpio_is_valid(&eth->reset_gpio)) {
		gpio_request_by_name(dev, "reset-gpios", 0, &eth->reset_gpio,
				     GPIOD_IS_OUT);
	}

	mdiodev = mdio_alloc();
	if (!mdiodev) {
		ret = -ENOMEM;
		goto err_mdio_alloc;
	}

	mdiodev->read = bb_miiphy_read;
	mdiodev->write = bb_miiphy_write;
	bb_miiphy_buses[0].priv = eth;
	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);

	ret = mdio_register(mdiodev);
	if (ret < 0)
		goto err_mdio_register;

	eth->bus = miiphy_get_dev_by_name(dev->name);

	/* Bring up PHY */
	ret = clk_enable(&eth->clk);
	if (ret)
		goto err_mdio_register;

	ret = ravb_reset(dev);
	if (ret)
		goto err_mdio_reset;

	ret = ravb_phy_config(dev);
	if (ret)
		goto err_mdio_reset;

	return 0;

err_mdio_reset:
	clk_disable(&eth->clk);
err_mdio_register:
	mdio_free(mdiodev);
err_mdio_alloc:
	unmap_physmem(eth->iobase, MAP_NOCACHE);
	return ret;
}

static int ravb_remove(struct udevice *dev)
{
	struct ravb_priv *eth = dev_get_priv(dev);

	clk_disable(&eth->clk);

	free(eth->phydev);
	mdio_unregister(eth->bus);
	mdio_free(eth->bus);
	if (dm_gpio_is_valid(&eth->reset_gpio))
		dm_gpio_free(dev, &eth->reset_gpio);
	unmap_physmem(eth->iobase, MAP_NOCACHE);

	return 0;
}

int ravb_bb_init(struct bb_miiphy_bus *bus)
{
	return 0;
}

int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
{
	struct ravb_priv *eth = bus->priv;

	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);

	return 0;
}

int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
{
	struct ravb_priv *eth = bus->priv;

	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);

	return 0;
}

int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
{
	struct ravb_priv *eth = bus->priv;

	if (v)
		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	else
		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);

	return 0;
}

int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
	struct ravb_priv *eth = bus->priv;

	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;

	return 0;
}

int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
{
	struct ravb_priv *eth = bus->priv;

	if (v)
		setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	else
		clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);

	return 0;
}

int ravb_bb_delay(struct bb_miiphy_bus *bus)
{
	udelay(10);

	return 0;
}

struct bb_miiphy_bus bb_miiphy_buses[] = {
	{
		.name		= "ravb",
		.init		= ravb_bb_init,
		.mdio_active	= ravb_bb_mdio_active,
		.mdio_tristate	= ravb_bb_mdio_tristate,
		.set_mdio	= ravb_bb_set_mdio,
		.get_mdio	= ravb_bb_get_mdio,
		.set_mdc	= ravb_bb_set_mdc,
		.delay		= ravb_bb_delay,
	},
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);

static const struct eth_ops ravb_ops = {
	.start			= ravb_start,
	.send			= ravb_send,
	.recv			= ravb_recv,
	.free_pkt		= ravb_free_pkt,
	.stop			= ravb_stop,
	.write_hwaddr		= ravb_write_hwaddr,
};

int ravb_ofdata_to_platdata(struct udevice *dev)
{
	struct eth_pdata *pdata = dev_get_platdata(dev);
	const char *phy_mode;
	const fdt32_t *cell;
	int ret = 0;

	pdata->iobase = devfdt_get_addr(dev);
	pdata->phy_interface = -1;
	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
			       NULL);
	if (phy_mode)
		pdata->phy_interface = phy_get_interface_by_name(phy_mode);
	if (pdata->phy_interface == -1) {
		debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
		return -EINVAL;
	}

	pdata->max_speed = 1000;
	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
	if (cell)
		pdata->max_speed = fdt32_to_cpu(*cell);

	sprintf(bb_miiphy_buses[0].name, dev->name);

	return ret;
}

static const struct udevice_id ravb_ids[] = {
	{ .compatible = "renesas,etheravb-r8a7795" },
	{ .compatible = "renesas,etheravb-r8a7796" },
	{ .compatible = "renesas,etheravb-r8a77965" },
	{ .compatible = "renesas,etheravb-r8a77970" },
	{ .compatible = "renesas,etheravb-r8a77990" },
	{ .compatible = "renesas,etheravb-r8a77995" },
	{ .compatible = "renesas,etheravb-rcar-gen3" },
	{ }
};

U_BOOT_DRIVER(eth_ravb) = {
	.name		= "ravb",
	.id		= UCLASS_ETH,
	.of_match	= ravb_ids,
	.ofdata_to_platdata = ravb_ofdata_to_platdata,
	.probe		= ravb_probe,
	.remove		= ravb_remove,
	.ops		= &ravb_ops,
	.priv_auto_alloc_size = sizeof(struct ravb_priv),
	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	.flags		= DM_FLAG_ALLOC_PRIV_DMA,
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
8ae51b6f MV	2	/*
	3	* drivers/net/ravb.c
	4	* This file is driver for Renesas Ethernet AVB.
	5	*
	6	* Copyright (C) 2015-2017 Renesas Electronics Corporation
	7	*
	8	* Based on the SuperH Ethernet driver.
8ae51b6f MV	9	*/
	10
	11	#include <common.h>
1fea9e25	12	#include <clk.h>
1eb69ae4	13	#include <cpu_func.h>
8ae51b6f MV	14	#include <dm.h>
8ae51b6f MV	15	#include <errno.h>
f7ae49fc	16	#include <log.h>
8ae51b6f MV	17	#include <miiphy.h>
8ae51b6f MV	18	#include <malloc.h>
90526e9f	19	#include <asm/cache.h>
c05ed00a	20	#include <linux/delay.h>
8ae51b6f MV	21	#include <linux/mii.h>
	22	#include <wait_bit.h>
	23	#include <asm/io.h>
bddb44e9	24	#include <asm/gpio.h>
8ae51b6f MV	25
	26	/* Registers */
	27	#define RAVB_REG_CCC 0x000
	28	#define RAVB_REG_DBAT 0x004
	29	#define RAVB_REG_CSR 0x00C
	30	#define RAVB_REG_APSR 0x08C
	31	#define RAVB_REG_RCR 0x090
	32	#define RAVB_REG_TGC 0x300
	33	#define RAVB_REG_TCCR 0x304
	34	#define RAVB_REG_RIC0 0x360
	35	#define RAVB_REG_RIC1 0x368
	36	#define RAVB_REG_RIC2 0x370
	37	#define RAVB_REG_TIC 0x378
	38	#define RAVB_REG_ECMR 0x500
	39	#define RAVB_REG_RFLR 0x508
	40	#define RAVB_REG_ECSIPR 0x518
	41	#define RAVB_REG_PIR 0x520
	42	#define RAVB_REG_GECMR 0x5b0
	43	#define RAVB_REG_MAHR 0x5c0
	44	#define RAVB_REG_MALR 0x5c8
	45
	46	#define CCC_OPC_CONFIG BIT(0)
	47	#define CCC_OPC_OPERATION BIT(1)
	48	#define CCC_BOC BIT(20)
	49
	50	#define CSR_OPS 0x0000000F
	51	#define CSR_OPS_CONFIG BIT(1)
	52
ef8c8781 MV	53	#define APSR_TDM BIT(14)
ef8c8781 MV	54
8ae51b6f MV	55	#define TCCR_TSRQ0 BIT(0)
	56
	57	#define RFLR_RFL_MIN 0x05EE
	58
	59	#define PIR_MDI BIT(3)
	60	#define PIR_MDO BIT(2)
	61	#define PIR_MMD BIT(1)
	62	#define PIR_MDC BIT(0)
	63
	64	#define ECMR_TRCCM BIT(26)
	65	#define ECMR_RZPF BIT(20)
	66	#define ECMR_PFR BIT(18)
	67	#define ECMR_RXF BIT(17)
	68	#define ECMR_RE BIT(6)
	69	#define ECMR_TE BIT(5)
	70	#define ECMR_DM BIT(1)
	71	#define ECMR_CHG_DM (ECMR_TRCCM \| ECMR_RZPF \| ECMR_PFR \| ECMR_RXF)
	72
	73	/* DMA Descriptors */
	74	#define RAVB_NUM_BASE_DESC 16
	75	#define RAVB_NUM_TX_DESC 8
	76	#define RAVB_NUM_RX_DESC 8
	77
	78	#define RAVB_TX_QUEUE_OFFSET 0
	79	#define RAVB_RX_QUEUE_OFFSET 4
	80
	81	#define RAVB_DESC_DT(n) ((n) << 28)
	82	#define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
	83	#define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
	84	#define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
	85	#define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
	86	#define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
	87	#define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
	88
	89	#define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
	90	#define RAVB_DESC_DS_MASK 0xfff
	91
	92	#define RAVB_RX_DESC_MSC_MC BIT(23)
	93	#define RAVB_RX_DESC_MSC_CEEF BIT(22)
	94	#define RAVB_RX_DESC_MSC_CRL BIT(21)
	95	#define RAVB_RX_DESC_MSC_FRE BIT(20)
	96	#define RAVB_RX_DESC_MSC_RTLF BIT(19)
	97	#define RAVB_RX_DESC_MSC_RTSF BIT(18)
	98	#define RAVB_RX_DESC_MSC_RFE BIT(17)
	99	#define RAVB_RX_DESC_MSC_CRC BIT(16)
	100	#define RAVB_RX_DESC_MSC_MASK (0xff << 16)
	101
	102	#define RAVB_RX_DESC_MSC_RX_ERR_MASK \
	103	(RAVB_RX_DESC_MSC_CRC \| RAVB_RX_DESC_MSC_RFE \| RAVB_RX_DESC_MSC_RTLF \| \
	104	RAVB_RX_DESC_MSC_RTSF \| RAVB_RX_DESC_MSC_CEEF)
	105
	106	#define RAVB_TX_TIMEOUT_MS 1000
	107
	108	struct ravb_desc {
	109	u32 ctrl;
	110	u32 dptr;
	111	};
	112
	113	struct ravb_rxdesc {
	114	struct ravb_desc data;
	115	struct ravb_desc link;
	116	u8 __pad[48];
	117	u8 packet[PKTSIZE_ALIGN];
	118	};
119
120	struct ravb_priv {
121	struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
122	struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
123	struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
124	u32 rx_desc_idx;
125	u32 tx_desc_idx;
126
127	struct phy_device *phydev;
128	struct mii_dev *bus;
129	void __iomem *iobase;
1fea9e25	130	struct clk clk;
bddb44e9	131	struct gpio_desc reset_gpio;
8ae51b6f MV	132	};
	133
	134	static inline void ravb_flush_dcache(u32 addr, u32 len)
	135	{
	136	flush_dcache_range(addr, addr + len);
	137	}
	138
	139	static inline void ravb_invalidate_dcache(u32 addr, u32 len)
	140	{
	141	u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
	142	u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
	143	invalidate_dcache_range(start, end);
	144	}
	145
	146	static int ravb_send(struct udevice dev, void packet, int len)
	147	{
	148	struct ravb_priv *eth = dev_get_priv(dev);
	149	struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
	150	unsigned int start;
	151
	152	/* Update TX descriptor */
	153	ravb_flush_dcache((uintptr_t)packet, len);
	154	memset(desc, 0x0, sizeof(*desc));
	155	desc->ctrl = RAVB_DESC_DT_FSINGLE \| RAVB_DESC_DS(len);
	156	desc->dptr = (uintptr_t)packet;
	157	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
	158
	159	/* Restart the transmitter if disabled */
	160	if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
	161	setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
	162
	163	/* Wait until packet is transmitted */
	164	start = get_timer(0);
	165	while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
	166	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	167	if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
	168	break;
	169	udelay(10);
	170	};
	171
	172	if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
	173	return -ETIMEDOUT;
	174
	175	eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
	176	return 0;
	177	}
	178
	179	static int ravb_recv(struct udevice dev, int flags, uchar *packetp)
	180	{
	181	struct ravb_priv *eth = dev_get_priv(dev);
	182	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
	183	int len;
	184	u8 *packet;
	185
	186	/* Check if the rx descriptor is ready */
	187	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
	188	if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
	189	return -EAGAIN;
	190
	191	/* Check for errors */
	192	if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
	193	desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
	194	return -EAGAIN;
	195	}
196
197	len = desc->data.ctrl & RAVB_DESC_DS_MASK;
198	packet = (u8 *)(uintptr_t)desc->data.dptr;
199	ravb_invalidate_dcache((uintptr_t)packet, len);
200
201	*packetp = packet;
202	return len;
203	}
204
205	static int ravb_free_pkt(struct udevice dev, uchar packet, int length)
206	{
207	struct ravb_priv *eth = dev_get_priv(dev);
208	struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
209
210	/* Make current descriptor available again */
211	desc->data.ctrl = RAVB_DESC_DT_FEMPTY \| RAVB_DESC_DS(PKTSIZE_ALIGN);
212	ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
213
214	/* Point to the next descriptor */
215	eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
216	desc = &eth->rx_desc[eth->rx_desc_idx];
217	ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
218
219	return 0;
220	}
221
222	static int ravb_reset(struct udevice *dev)
223	{
224	struct ravb_priv *eth = dev_get_priv(dev);
225
226	/* Set config mode */
227	writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
228
229	/* Check the operating mode is changed to the config mode. */
48263504 ÁFR	230	return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
48263504 ÁFR	231	CSR_OPS_CONFIG, true, 100, true);
8ae51b6f MV	232	}
	233
	234	static void ravb_base_desc_init(struct ravb_priv *eth)
	235	{
	236	const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
	237	int i;
	238
	239	/* Initialize all descriptors */
	240	memset(eth->base_desc, 0x0, desc_size);
	241
	242	for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
	243	eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
	244
	245	ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
	246
	247	/* Register the descriptor base address table */
	248	writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
	249	}
	250
	251	static void ravb_tx_desc_init(struct ravb_priv *eth)
	252	{
	253	const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
	254	int i;
	255
	256	/* Initialize all descriptors */
	257	memset(eth->tx_desc, 0x0, desc_size);
	258	eth->tx_desc_idx = 0;
	259
	260	for (i = 0; i < RAVB_NUM_TX_DESC; i++)
	261	eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
	262
	263	/* Mark the end of the descriptors */
	264	eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
	265	eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
	266	ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
	267
	268	/* Point the controller to the TX descriptor list. */
	269	eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
	270	eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
	271	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
	272	sizeof(struct ravb_desc));
	273	}
	274
	275	static void ravb_rx_desc_init(struct ravb_priv *eth)
	276	{
	277	const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
	278	int i;
	279
	280	/* Initialize all descriptors */
	281	memset(eth->rx_desc, 0x0, desc_size);
	282	eth->rx_desc_idx = 0;
	283
	284	for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
	285	eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY \|
	286	RAVB_DESC_DS(PKTSIZE_ALIGN);
	287	eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
	288
	289	eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
	290	eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
	291	}
	292
	293	/* Mark the end of the descriptors */
	294	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
	295	eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
296	ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
297
298	/* Point the controller to the rx descriptor list */
299	eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
300	eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
301	ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
302	sizeof(struct ravb_desc));
303	}
304
305	static int ravb_phy_config(struct udevice *dev)
306	{
307	struct ravb_priv *eth = dev_get_priv(dev);
308	struct eth_pdata *pdata = dev_get_platdata(dev);
309	struct phy_device *phydev;
e821a7bd	310	int mask = 0xffffffff, reg;
8ae51b6f	311
bddb44e9 MV	312	if (dm_gpio_is_valid(&eth->reset_gpio)) {
	313	dm_gpio_set_value(&eth->reset_gpio, 1);
	314	mdelay(20);
	315	dm_gpio_set_value(&eth->reset_gpio, 0);
	316	mdelay(1);
	317	}
	318
e821a7bd	319	phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
8ae51b6f MV	320	if (!phydev)
	321	return -ENODEV;
	322
e821a7bd MV	323	phy_connect_dev(phydev, dev);
e821a7bd MV	324
8ae51b6f MV	325	eth->phydev = phydev;
8ae51b6f MV	326
536fb5d4 MV	327	phydev->supported &= SUPPORTED_100baseT_Full \|
	328	SUPPORTED_1000baseT_Full \| SUPPORTED_Autoneg \|
	329	SUPPORTED_TP \| SUPPORTED_MII \| SUPPORTED_Pause \|
	330	SUPPORTED_Asym_Pause;
	331
8ae51b6f	332	if (pdata->max_speed != 1000) {
536fb5d4	333	phydev->supported &= ~SUPPORTED_1000baseT_Full;
8ae51b6f MV	334	reg = phy_read(phydev, -1, MII_CTRL1000);
	335	reg &= ~(BIT(9) \| BIT(8));
	336	phy_write(phydev, -1, MII_CTRL1000, reg);
	337	}
	338
	339	phy_config(phydev);
	340
	341	return 0;
	342	}
	343
	344	/* Set Mac address */
	345	static int ravb_write_hwaddr(struct udevice *dev)
	346	{
	347	struct ravb_priv *eth = dev_get_priv(dev);
	348	struct eth_pdata *pdata = dev_get_platdata(dev);
	349	unsigned char *mac = pdata->enetaddr;
	350
	351	writel((mac[0] << 24) \| (mac[1] << 16) \| (mac[2] << 8) \| mac[3],
	352	eth->iobase + RAVB_REG_MAHR);
	353
	354	writel((mac[4] << 8) \| mac[5], eth->iobase + RAVB_REG_MALR);
	355
	356	return 0;
	357	}
	358
	359	/* E-MAC init function */
	360	static int ravb_mac_init(struct ravb_priv *eth)
	361	{
	362	/* Disable MAC Interrupt */
	363	writel(0, eth->iobase + RAVB_REG_ECSIPR);
	364
	365	/* Recv frame limit set register */
	366	writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
	367
	368	return 0;
	369	}
	370
	371	/* AVB-DMAC init function */
	372	static int ravb_dmac_init(struct udevice *dev)
	373	{
	374	struct ravb_priv *eth = dev_get_priv(dev);
	375	struct eth_pdata *pdata = dev_get_platdata(dev);
	376	int ret = 0;
	377
	378	/* Set CONFIG mode */
	379	ret = ravb_reset(dev);
	380	if (ret)
	381	return ret;
	382
	383	/* Disable all interrupts */
	384	writel(0, eth->iobase + RAVB_REG_RIC0);
	385	writel(0, eth->iobase + RAVB_REG_RIC1);
	386	writel(0, eth->iobase + RAVB_REG_RIC2);
	387	writel(0, eth->iobase + RAVB_REG_TIC);
	388
	389	/* Set little endian */
	390	clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
	391
	392	/* AVB rx set */
	393	writel(0x18000001, eth->iobase + RAVB_REG_RCR);
	394
	395	/* FIFO size set */
	396	writel(0x00222210, eth->iobase + RAVB_REG_TGC);
	397
ef8c8781 MV	398	/* Delay CLK: 2ns (not applicable on R-Car E3/D3) */
	399	if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) \|\|
	400	(rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
	401	return 0;
	402
	403	if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) \|\|
	404	(pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID))
	405	writel(APSR_TDM, eth->iobase + RAVB_REG_APSR);
8ae51b6f MV	406
	407	return 0;
	408	}
	409
	410	static int ravb_config(struct udevice *dev)
	411	{
	412	struct ravb_priv *eth = dev_get_priv(dev);
d64c7894	413	struct phy_device *phy = eth->phydev;
8ae51b6f MV	414	u32 mask = ECMR_CHG_DM \| ECMR_RE \| ECMR_TE;
	415	int ret;
	416
	417	/* Configure AVB-DMAC register */
	418	ravb_dmac_init(dev);
	419
	420	/* Configure E-MAC registers */
	421	ravb_mac_init(eth);
	422	ravb_write_hwaddr(dev);
	423
8ae51b6f MV	424	ret = phy_startup(phy);
	425	if (ret)
	426	return ret;
	427
	428	/* Set the transfer speed */
	429	if (phy->speed == 100)
	430	writel(0, eth->iobase + RAVB_REG_GECMR);
	431	else if (phy->speed == 1000)
	432	writel(1, eth->iobase + RAVB_REG_GECMR);
	433
	434	/* Check if full duplex mode is supported by the phy */
	435	if (phy->duplex)
	436	mask \|= ECMR_DM;
	437
	438	writel(mask, eth->iobase + RAVB_REG_ECMR);
	439
	440	phy->drv->writeext(phy, -1, 0x02, 0x08, (0x0f << 5) \| 0x19);
	441
	442	return 0;
	443	}
	444
e3105eac	445	static int ravb_start(struct udevice *dev)
8ae51b6f MV	446	{
	447	struct ravb_priv *eth = dev_get_priv(dev);
	448	int ret;
	449
1fea9e25 MV	450	ret = ravb_reset(dev);
1fea9e25 MV	451	if (ret)
c4a8d9ca	452	return ret;
1fea9e25	453
8ae51b6f MV	454	ravb_base_desc_init(eth);
	455	ravb_tx_desc_init(eth);
	456	ravb_rx_desc_init(eth);
	457
	458	ret = ravb_config(dev);
	459	if (ret)
c4a8d9ca	460	return ret;
8ae51b6f MV	461
	462	/* Setting the control will start the AVB-DMAC process. */
	463	writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
	464
	465	return 0;
	466	}
	467
	468	static void ravb_stop(struct udevice *dev)
	469	{
1fea9e25 MV	470	struct ravb_priv *eth = dev_get_priv(dev);
1fea9e25 MV	471
d64c7894	472	phy_shutdown(eth->phydev);
8ae51b6f MV	473	ravb_reset(dev);
	474	}
	475
	476	static int ravb_probe(struct udevice *dev)
	477	{
	478	struct eth_pdata *pdata = dev_get_platdata(dev);
	479	struct ravb_priv *eth = dev_get_priv(dev);
701db6e9	480	struct ofnode_phandle_args phandle_args;
8ae51b6f MV	481	struct mii_dev *mdiodev;
	482	void __iomem *iobase;
	483	int ret;
	484
	485	iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
	486	eth->iobase = iobase;
	487
1fea9e25 MV	488	ret = clk_get_by_index(dev, 0, &eth->clk);
	489	if (ret < 0)
	490	goto err_mdio_alloc;
	491
701db6e9 MV	492	ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args);
	493	if (!ret) {
	494	gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
	495	&eth->reset_gpio, GPIOD_IS_OUT);
	496	}
	497
	498	if (!dm_gpio_is_valid(&eth->reset_gpio)) {
	499	gpio_request_by_name(dev, "reset-gpios", 0, &eth->reset_gpio,
	500	GPIOD_IS_OUT);
	501	}
bddb44e9	502
8ae51b6f MV	503	mdiodev = mdio_alloc();
	504	if (!mdiodev) {
	505	ret = -ENOMEM;
	506	goto err_mdio_alloc;
	507	}
	508
	509	mdiodev->read = bb_miiphy_read;
	510	mdiodev->write = bb_miiphy_write;
	511	bb_miiphy_buses[0].priv = eth;
	512	snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
	513
	514	ret = mdio_register(mdiodev);
	515	if (ret < 0)
	516	goto err_mdio_register;
	517
	518	eth->bus = miiphy_get_dev_by_name(dev->name);
	519
d64c7894 MV	520	/* Bring up PHY */
	521	ret = clk_enable(&eth->clk);
	522	if (ret)
	523	goto err_mdio_register;
	524
	525	ret = ravb_reset(dev);
	526	if (ret)
	527	goto err_mdio_reset;
	528
	529	ret = ravb_phy_config(dev);
	530	if (ret)
	531	goto err_mdio_reset;
	532
8ae51b6f MV	533	return 0;
8ae51b6f MV	534
d64c7894 MV	535	err_mdio_reset:
d64c7894 MV	536	clk_disable(&eth->clk);
8ae51b6f MV	537	err_mdio_register:
	538	mdio_free(mdiodev);
	539	err_mdio_alloc:
	540	unmap_physmem(eth->iobase, MAP_NOCACHE);
	541	return ret;
	542	}
	543
	544	static int ravb_remove(struct udevice *dev)
	545	{
	546	struct ravb_priv *eth = dev_get_priv(dev);
	547
d64c7894 MV	548	clk_disable(&eth->clk);
d64c7894 MV	549
8ae51b6f MV	550	free(eth->phydev);
	551	mdio_unregister(eth->bus);
	552	mdio_free(eth->bus);
90997cda MV	553	if (dm_gpio_is_valid(&eth->reset_gpio))
90997cda MV	554	dm_gpio_free(dev, &eth->reset_gpio);
8ae51b6f MV	555	unmap_physmem(eth->iobase, MAP_NOCACHE);
	556
	557	return 0;
	558	}
	559
	560	int ravb_bb_init(struct bb_miiphy_bus *bus)
	561	{
	562	return 0;
	563	}
	564
	565	int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
	566	{
	567	struct ravb_priv *eth = bus->priv;
	568
	569	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
	570
	571	return 0;
	572	}
	573
	574	int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
	575	{
	576	struct ravb_priv *eth = bus->priv;
	577
	578	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
	579
	580	return 0;
	581	}
	582
	583	int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
	584	{
	585	struct ravb_priv *eth = bus->priv;
	586
	587	if (v)
	588	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	589	else
	590	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
	591
	592	return 0;
	593	}
	594
	595	int ravb_bb_get_mdio(struct bb_miiphy_bus bus, int v)
	596	{
	597	struct ravb_priv *eth = bus->priv;
	598
	599	*v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
	600
	601	return 0;
	602	}
	603
	604	int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
	605	{
	606	struct ravb_priv *eth = bus->priv;
	607
	608	if (v)
	609	setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	610	else
	611	clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
	612
	613	return 0;
	614	}
	615
	616	int ravb_bb_delay(struct bb_miiphy_bus *bus)
	617	{
	618	udelay(10);
619
620	return 0;
621	}
622
623	struct bb_miiphy_bus bb_miiphy_buses[] = {
624	{
625	.name = "ravb",
626	.init = ravb_bb_init,
627	.mdio_active = ravb_bb_mdio_active,
628	.mdio_tristate = ravb_bb_mdio_tristate,
629	.set_mdio = ravb_bb_set_mdio,
630	.get_mdio = ravb_bb_get_mdio,
631	.set_mdc = ravb_bb_set_mdc,
632	.delay = ravb_bb_delay,
633	},
634	};
635	int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
636
637	static const struct eth_ops ravb_ops = {
638	.start = ravb_start,
639	.send = ravb_send,
640	.recv = ravb_recv,
641	.free_pkt = ravb_free_pkt,
642	.stop = ravb_stop,
643	.write_hwaddr = ravb_write_hwaddr,
644	};
645
5ee8b4d7 MV	646	int ravb_ofdata_to_platdata(struct udevice *dev)
	647	{
	648	struct eth_pdata *pdata = dev_get_platdata(dev);
	649	const char *phy_mode;
	650	const fdt32_t *cell;
	651	int ret = 0;
	652
	653	pdata->iobase = devfdt_get_addr(dev);
	654	pdata->phy_interface = -1;
	655	phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
	656	NULL);
	657	if (phy_mode)
	658	pdata->phy_interface = phy_get_interface_by_name(phy_mode);
	659	if (pdata->phy_interface == -1) {
	660	debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
	661	return -EINVAL;
	662	}
	663
	664	pdata->max_speed = 1000;
	665	cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
	666	if (cell)
	667	pdata->max_speed = fdt32_to_cpu(*cell);
	668
	669	sprintf(bb_miiphy_buses[0].name, dev->name);
	670
	671	return ret;
	672	}
	673
	674	static const struct udevice_id ravb_ids[] = {
	675	{ .compatible = "renesas,etheravb-r8a7795" },
	676	{ .compatible = "renesas,etheravb-r8a7796" },
7a7081e6	677	{ .compatible = "renesas,etheravb-r8a77965" },
dc3bb3d4	678	{ .compatible = "renesas,etheravb-r8a77970" },
34f1dba9	679	{ .compatible = "renesas,etheravb-r8a77990" },
9e4a6373	680	{ .compatible = "renesas,etheravb-r8a77995" },
5ee8b4d7 MV	681	{ .compatible = "renesas,etheravb-rcar-gen3" },
	682	{ }
	683	};
	684
8ae51b6f MV	685	U_BOOT_DRIVER(eth_ravb) = {
	686	.name = "ravb",
	687	.id = UCLASS_ETH,
5ee8b4d7 MV	688	.of_match = ravb_ids,
5ee8b4d7 MV	689	.ofdata_to_platdata = ravb_ofdata_to_platdata,
8ae51b6f MV	690	.probe = ravb_probe,
	691	.remove = ravb_remove,
	692	.ops = &ravb_ops,
	693	.priv_auto_alloc_size = sizeof(struct ravb_priv),
	694	.platdata_auto_alloc_size = sizeof(struct eth_pdata),
	695	.flags = DM_FLAG_ALLOC_PRIV_DMA,
	696	};