[J-u-boot.git] / cmd / reginfo.c

/*
 * (C) Copyright 2000
 * Subodh Nijsure, SkyStream Networks, [email protected]
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#if defined(CONFIG_8xx)
#include <mpc8xx.h>
#elif defined (CONFIG_4xx)
extern void ppc4xx_reginfo(void);
#elif defined (CONFIG_5xx)
#include <mpc5xx.h>
#elif defined (CONFIG_MPC5200)
#include <mpc5xxx.h>
#elif defined (CONFIG_MPC86xx)
extern void mpc86xx_reginfo(void);
#elif defined(CONFIG_MPC85xx)
extern void mpc85xx_reginfo(void);
#endif

static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
		       char * const argv[])
{
#if defined(CONFIG_8xx)
	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
	volatile sit8xx_t *timers = &immap->im_sit;

	/* Hopefully more PowerPC  knowledgable people will add code to display
	 * other useful registers
	 */

	printf ("\nSystem Configuration registers\n"

		"\tIMMR\t0x%08X\n", get_immr(0));

	printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
	printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);

	printf("\tSWT\t0x%08X",    sysconf->sc_swt);
	printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);

	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
		sysconf->sc_sipend, sysconf->sc_simask);
	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
		sysconf->sc_siel, sysconf->sc_sivec);
	printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
		sysconf->sc_tesr, sysconf->sc_sdcr);

	printf ("Memory Controller Registers\n"

		"\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
	printf ("\n"
		"\tmamr\t0x%08X\tmbmr\t0x%08X \n",
		memctl->memc_mamr, memctl->memc_mbmr );
	printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
		memctl->memc_mstat, memctl->memc_mptpr );
	printf("\tmdr\t0x%08X \n", memctl->memc_mdr);

	printf ("\nSystem Integration Timers\n"
		"\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
		timers->sit_tbscr, timers->sit_rtcsc);
	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);

	/*
	 * May be some CPM info here?
	 */

#elif defined (CONFIG_4xx)
	ppc4xx_reginfo();
#elif defined(CONFIG_5xx)

	volatile immap_t	*immap  = (immap_t *)CONFIG_SYS_IMMR;
	volatile memctl5xx_t	*memctl = &immap->im_memctl;
	volatile sysconf5xx_t	*sysconf = &immap->im_siu_conf;
	volatile sit5xx_t	*timers = &immap->im_sit;
	volatile car5xx_t	*car = &immap->im_clkrst;
	volatile uimb5xx_t	*uimb = &immap->im_uimb;

	puts ("\nSystem Configuration registers\n");
	printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
	printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
	printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);

	puts ("\nMemory Controller Registers\n");
	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
	printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);

	puts ("\nSystem Integration Timers\n");
	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);

	puts ("\nClocks and Reset\n");
	printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);

	puts ("\nU-Bus to IMB3 Bus Interface\n");
	printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
	puts ("\n\n");

#elif defined(CONFIG_MPC5200)
	puts ("\nMPC5200 registers\n");
	printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
	puts ("Memory map registers\n");
	printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS0_START,
		*(volatile ulong*)MPC5XXX_CS0_STOP,
		*(volatile ulong*)MPC5XXX_CS0_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
	printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS1_START,
		*(volatile ulong*)MPC5XXX_CS1_STOP,
		*(volatile ulong*)MPC5XXX_CS1_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
	printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS2_START,
		*(volatile ulong*)MPC5XXX_CS2_STOP,
		*(volatile ulong*)MPC5XXX_CS2_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
	printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS3_START,
		*(volatile ulong*)MPC5XXX_CS3_STOP,
		*(volatile ulong*)MPC5XXX_CS3_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
	printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS4_START,
		*(volatile ulong*)MPC5XXX_CS4_STOP,
		*(volatile ulong*)MPC5XXX_CS4_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
	printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS5_START,
		*(volatile ulong*)MPC5XXX_CS5_STOP,
		*(volatile ulong*)MPC5XXX_CS5_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
	printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS6_START,
		*(volatile ulong*)MPC5XXX_CS6_STOP,
		*(volatile ulong*)MPC5XXX_CS6_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
	printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_CS7_START,
		*(volatile ulong*)MPC5XXX_CS7_STOP,
		*(volatile ulong*)MPC5XXX_CS7_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
	printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
		*(volatile ulong*)MPC5XXX_BOOTCS_START,
		*(volatile ulong*)MPC5XXX_BOOTCS_STOP,
		*(volatile ulong*)MPC5XXX_BOOTCS_CFG,
		(*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
	printf ("\tSDRAMCS0: %08lX\n",
		*(volatile ulong*)MPC5XXX_SDRAM_CS0CFG);
	printf ("\tSDRAMCS1: %08lX\n",
		*(volatile ulong*)MPC5XXX_SDRAM_CS1CFG);
#elif defined(CONFIG_MPC86xx)
	mpc86xx_reginfo();

#elif defined(CONFIG_MPC85xx)
	mpc85xx_reginfo();

#elif defined(CONFIG_BLACKFIN)
	puts("\nSystem Configuration registers\n");
#ifndef __ADSPBF60x__
	puts("\nPLL Registers\n");
	printf("\tPLL_DIV:   0x%04x   PLL_CTL:      0x%04x\n",
		bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
	printf("\tPLL_STAT:  0x%04x   PLL_LOCKCNT:  0x%04x\n",
		bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
	printf("\tVR_CTL:    0x%04x\n", bfin_read_VR_CTL());

	puts("\nEBIU AMC Registers\n");
	printf("\tEBIU_AMGCTL:   0x%04x\n", bfin_read_EBIU_AMGCTL());
	printf("\tEBIU_AMBCTL0:  0x%08x   EBIU_AMBCTL1:  0x%08x\n",
		bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
# ifdef EBIU_MODE
	printf("\tEBIU_MBSCTL:   0x%08x   EBIU_ARBSTAT:  0x%08x\n",
		bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
	printf("\tEBIU_MODE:     0x%08x   EBIU_FCTL:     0x%08x\n",
		bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
# endif

# ifdef EBIU_RSTCTL
	puts("\nEBIU DDR Registers\n");
	printf("\tEBIU_DDRCTL0:  0x%08x   EBIU_DDRCTL1:  0x%08x\n",
		bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
	printf("\tEBIU_DDRCTL2:  0x%08x   EBIU_DDRCTL3:  0x%08x\n",
		bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
	printf("\tEBIU_DDRQUE:   0x%08x   EBIU_RSTCTL    0x%04x\n",
		bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
	printf("\tEBIU_ERRADD:   0x%08x   EBIU_ERRMST:   0x%04x\n",
		bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
# else
	puts("\nEBIU SDC Registers\n");
	printf("\tEBIU_SDRRC:   0x%04x   EBIU_SDBCTL:  0x%04x\n",
		bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
	printf("\tEBIU_SDSTAT:  0x%04x   EBIU_SDGCTL:  0x%08x\n",
		bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
# endif
#else
	puts("\nCGU Registers\n");
	printf("\tCGU_DIV:   0x%08x   CGU_CTL:      0x%08x\n",
		bfin_read_CGU_DIV(), bfin_read_CGU_CTL());
	printf("\tCGU_STAT:  0x%08x   CGU_LOCKCNT:  0x%08x\n",
		bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL());

	puts("\nSMC DDR Registers\n");
	printf("\tDDR_CFG:   0x%08x   DDR_TR0:      0x%08x\n",
		bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0());
	printf("\tDDR_TR1:   0x%08x   DDR_TR2:      0x%08x\n",
		bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2());
	printf("\tDDR_MR:    0x%08x   DDR_EMR1:     0x%08x\n",
		bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1());
	printf("\tDDR_CTL:   0x%08x   DDR_STAT:     0x%08x\n",
		bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT());
	printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL());
#endif
#endif /* CONFIG_BLACKFIN */

	return 0;
}

 /**************************************************/

#if defined(CONFIG_CMD_REGINFO)
U_BOOT_CMD(
	reginfo,	2,	1,	do_reginfo,
	"print register information",
	""
);
#endif
Commit	Line	Data
e887afc9 WD	1	/*
	2	* (C) Copyright 2000
	3	* Subodh Nijsure, SkyStream Networks, [email protected]
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
e887afc9 WD	6	*/
	7
	8	#include <common.h>
	9	#include <command.h>
e887afc9 WD	10	#if defined(CONFIG_8xx)
e887afc9 WD	11	#include <mpc8xx.h>
78d2a641 NG	12	#elif defined (CONFIG_4xx)
78d2a641 NG	13	extern void ppc4xx_reginfo(void);
0db5bca8 WD	14	#elif defined (CONFIG_5xx)
0db5bca8 WD	15	#include <mpc5xx.h>
56523f12 WD	16	#elif defined (CONFIG_MPC5200)
56523f12 WD	17	#include <mpc5xxx.h>
4f93f8b1 BB	18	#elif defined (CONFIG_MPC86xx)
4f93f8b1 BB	19	extern void mpc86xx_reginfo(void);
199e262e BB	20	#elif defined(CONFIG_MPC85xx)
199e262e BB	21	extern void mpc85xx_reginfo(void);
e887afc9	22	#endif
65c450b4	23
088f1b19 KP	24	static int do_reginfo(cmd_tbl_t *cmdtp, int flag, int argc,
088f1b19 KP	25	char * const argv[])
e887afc9 WD	26	{
e887afc9 WD	27	#if defined(CONFIG_8xx)
6d0f6bcf	28	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
e887afc9 WD	29	volatile memctl8xx_t *memctl = &immap->im_memctl;
	30	volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
	31	volatile sit8xx_t *timers = &immap->im_sit;
	32
	33	/* Hopefully more PowerPC knowledgable people will add code to display
	34	* other useful registers
	35	*/
	36
4b9206ed	37	printf ("\nSystem Configuration registers\n"
e887afc9	38
4b9206ed	39	"\tIMMR\t0x%08X\n", get_immr(0));
e887afc9 WD	40
	41	printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
	42	printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
	43
	44	printf("\tSWT\t0x%08X", sysconf->sc_swt);
	45	printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
	46
	47	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
	48	sysconf->sc_sipend, sysconf->sc_simask);
	49	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
	50	sysconf->sc_siel, sysconf->sc_sivec);
	51	printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
	52	sysconf->sc_tesr, sysconf->sc_sdcr);
	53
4b9206ed	54	printf ("Memory Controller Registers\n"
e887afc9	55
4b9206ed	56	"\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
e887afc9 WD	57	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	58	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	59	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	60	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
	61	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
	62	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
	63	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
4b9206ed WD	64	printf ("\n"
4b9206ed WD	65	"\tmamr\t0x%08X\tmbmr\t0x%08X \n",
e887afc9 WD	66	memctl->memc_mamr, memctl->memc_mbmr );
	67	printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
	68	memctl->memc_mstat, memctl->memc_mptpr );
	69	printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
	70
4b9206ed WD	71	printf ("\nSystem Integration Timers\n"
4b9206ed WD	72	"\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
e887afc9 WD	73	timers->sit_tbscr, timers->sit_rtcsc);
	74	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
	75
	76	/*
	77	* May be some CPM info here?
	78	*/
	79
78d2a641 NG	80	#elif defined (CONFIG_4xx)
78d2a641 NG	81	ppc4xx_reginfo();
0db5bca8	82	#elif defined(CONFIG_5xx)
e887afc9	83
6d0f6bcf	84	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
0db5bca8 WD	85	volatile memctl5xx_t *memctl = &immap->im_memctl;
	86	volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
	87	volatile sit5xx_t *timers = &immap->im_sit;
	88	volatile car5xx_t *car = &immap->im_clkrst;
	89	volatile uimb5xx_t *uimb = &immap->im_uimb;
	90
4b9206ed	91	puts ("\nSystem Configuration registers\n");
0db5bca8 WD	92	printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
	93	printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
	94	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
	95	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
	96	printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
	97
4b9206ed	98	puts ("\nMemory Controller Registers\n");
0db5bca8 WD	99	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	100	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	101	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	102	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	103	printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
	104	printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
	105
4b9206ed	106	puts ("\nSystem Integration Timers\n");
0db5bca8 WD	107	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
	108	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
	109
4b9206ed	110	puts ("\nClocks and Reset\n");
0db5bca8 WD	111	printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
0db5bca8 WD	112
4b9206ed	113	puts ("\nU-Bus to IMB3 Bus Interface\n");
0db5bca8	114	printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
4b9206ed	115	puts ("\n\n");
56523f12 WD	116
	117	#elif defined(CONFIG_MPC5200)
	118	puts ("\nMPC5200 registers\n");
6d0f6bcf	119	printf ("MBAR=%08x\n", CONFIG_SYS_MBAR);
56523f12	120	puts ("Memory map registers\n");
9b55a253	121	printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	122	(volatile ulong)MPC5XXX_CS0_START,
	123	(volatile ulong)MPC5XXX_CS0_STOP,
	124	(volatile ulong)MPC5XXX_CS0_CFG,
	125	((volatile ulong)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0);
9b55a253	126	printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	127	(volatile ulong)MPC5XXX_CS1_START,
	128	(volatile ulong)MPC5XXX_CS1_STOP,
	129	(volatile ulong)MPC5XXX_CS1_CFG,
	130	((volatile ulong)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0);
9b55a253	131	printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	132	(volatile ulong)MPC5XXX_CS2_START,
	133	(volatile ulong)MPC5XXX_CS2_STOP,
	134	(volatile ulong)MPC5XXX_CS2_CFG,
	135	((volatile ulong)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0);
9b55a253	136	printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	137	(volatile ulong)MPC5XXX_CS3_START,
	138	(volatile ulong)MPC5XXX_CS3_STOP,
	139	(volatile ulong)MPC5XXX_CS3_CFG,
	140	((volatile ulong)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0);
9b55a253	141	printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	142	(volatile ulong)MPC5XXX_CS4_START,
	143	(volatile ulong)MPC5XXX_CS4_STOP,
	144	(volatile ulong)MPC5XXX_CS4_CFG,
	145	((volatile ulong)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0);
9b55a253	146	printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	147	(volatile ulong)MPC5XXX_CS5_START,
	148	(volatile ulong)MPC5XXX_CS5_STOP,
	149	(volatile ulong)MPC5XXX_CS5_CFG,
	150	((volatile ulong)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0);
9b55a253	151	printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	152	(volatile ulong)MPC5XXX_CS6_START,
	153	(volatile ulong)MPC5XXX_CS6_STOP,
	154	(volatile ulong)MPC5XXX_CS6_CFG,
	155	((volatile ulong)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0);
9b55a253	156	printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	157	(volatile ulong)MPC5XXX_CS7_START,
	158	(volatile ulong)MPC5XXX_CS7_STOP,
	159	(volatile ulong)MPC5XXX_CS7_CFG,
	160	((volatile ulong)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0);
9b55a253	161	printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n",
56523f12 WD	162	(volatile ulong)MPC5XXX_BOOTCS_START,
	163	(volatile ulong)MPC5XXX_BOOTCS_STOP,
	164	(volatile ulong)MPC5XXX_BOOTCS_CFG,
	165	((volatile ulong)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0);
9b55a253	166	printf ("\tSDRAMCS0: %08lX\n",
56523f12	167	(volatile ulong)MPC5XXX_SDRAM_CS0CFG);
9b55a253	168	printf ("\tSDRAMCS1: %08lX\n",
56523f12	169	(volatile ulong)MPC5XXX_SDRAM_CS1CFG);
4f93f8b1 BB	170	#elif defined(CONFIG_MPC86xx)
4f93f8b1 BB	171	mpc86xx_reginfo();
97c26e00	172
199e262e BB	173	#elif defined(CONFIG_MPC85xx)
	174	mpc85xx_reginfo();
	175
97c26e00 MF	176	#elif defined(CONFIG_BLACKFIN)
97c26e00 MF	177	puts("\nSystem Configuration registers\n");
a2979dcd	178	#ifndef __ADSPBF60x__
97c26e00 MF	179	puts("\nPLL Registers\n");
	180	printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n",
	181	bfin_read_PLL_DIV(), bfin_read_PLL_CTL());
	182	printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n",
	183	bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT());
	184	printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL());
	185
	186	puts("\nEBIU AMC Registers\n");
	187	printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL());
	188	printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n",
	189	bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1());
	190	# ifdef EBIU_MODE
	191	printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n",
	192	bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT());
	193	printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n",
	194	bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL());
	195	# endif
	196
	197	# ifdef EBIU_RSTCTL
	198	puts("\nEBIU DDR Registers\n");
	199	printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n",
	200	bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1());
	201	printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n",
	202	bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3());
	203	printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n",
	204	bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL());
	205	printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n",
	206	bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST());
	207	# else
	208	puts("\nEBIU SDC Registers\n");
	209	printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n",
	210	bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL());
	211	printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n",
	212	bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL());
	213	# endif
a2979dcd SZ	214	#else
	215	puts("\nCGU Registers\n");
	216	printf("\tCGU_DIV: 0x%08x CGU_CTL: 0x%08x\n",
	217	bfin_read_CGU_DIV(), bfin_read_CGU_CTL());
	218	printf("\tCGU_STAT: 0x%08x CGU_LOCKCNT: 0x%08x\n",
	219	bfin_read_CGU_STAT(), bfin_read_CGU_CLKOUTSEL());
97c26e00	220
a2979dcd SZ	221	puts("\nSMC DDR Registers\n");
	222	printf("\tDDR_CFG: 0x%08x DDR_TR0: 0x%08x\n",
	223	bfin_read_DMC0_CFG(), bfin_read_DMC0_TR0());
	224	printf("\tDDR_TR1: 0x%08x DDR_TR2: 0x%08x\n",
	225	bfin_read_DMC0_TR1(), bfin_read_DMC0_TR2());
	226	printf("\tDDR_MR: 0x%08x DDR_EMR1: 0x%08x\n",
	227	bfin_read_DMC0_MR(), bfin_read_DMC0_EMR1());
	228	printf("\tDDR_CTL: 0x%08x DDR_STAT: 0x%08x\n",
	229	bfin_read_DMC0_CTL(), bfin_read_DMC0_STAT());
	230	printf("\tDDR_DLLCTL:0x%08x\n", bfin_read_DMC0_DLLCTL());
	231	#endif
9e04a813	232	#endif /* CONFIG_BLACKFIN */
4f93f8b1	233
e887afc9 WD	234	return 0;
	235	}
	236
8bde7f77 WD	237	/**************************************************/
8bde7f77 WD	238
97c26e00	239	#if defined(CONFIG_CMD_REGINFO)
0d498393	240	U_BOOT_CMD(
53677ef1	241	reginfo, 2, 1, do_reginfo,
2fb2604d	242	"print register information",
a89c33db	243	""
8bde7f77 WD	244	);
8bde7f77 WD	245	#endif