projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| e887afc9 WD |
1 | /* |
| 2 | * (C) Copyright 2000 | |
| 3 | * Subodh Nijsure, SkyStream Networks, [email protected] | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | #include <common.h> | |
| 25 | #include <command.h> | |
| e887afc9 WD |
26 | #if defined(CONFIG_8xx) |
| 27 | #include <mpc8xx.h> | |
| e075fbe6 | 28 | #elif defined (CONFIG_405GP) || defined(CONFIG_405EP) |
| e887afc9 | 29 | #include <asm/processor.h> |
| 0db5bca8 WD |
30 | #elif defined (CONFIG_5xx) |
| 31 | #include <mpc5xx.h> | |
| 56523f12 WD |
32 | #elif defined (CONFIG_MPC5200) |
| 33 | #include <mpc5xxx.h> | |
| 4f93f8b1 BB |
34 | #elif defined (CONFIG_MPC86xx) |
| 35 | extern void mpc86xx_reginfo(void); | |
| e887afc9 | 36 | #endif |
| 65c450b4 | 37 | |
| e887afc9 WD |
38 | int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) |
| 39 | { | |
| 40 | #if defined(CONFIG_8xx) | |
| 6d0f6bcf | 41 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
| e887afc9 WD |
42 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
| 43 | volatile sysconf8xx_t *sysconf = &immap->im_siu_conf; | |
| 44 | volatile sit8xx_t *timers = &immap->im_sit; | |
| 45 | ||
| 46 | /* Hopefully more PowerPC knowledgable people will add code to display | |
| 47 | * other useful registers | |
| 48 | */ | |
| 49 | ||
| 4b9206ed | 50 | printf ("\nSystem Configuration registers\n" |
| e887afc9 | 51 | |
| 4b9206ed | 52 | "\tIMMR\t0x%08X\n", get_immr(0)); |
| e887afc9 WD |
53 | |
| 54 | printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr); | |
| 55 | printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr); | |
| 56 | ||
| 57 | printf("\tSWT\t0x%08X", sysconf->sc_swt); | |
| 58 | printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr); | |
| 59 | ||
| 60 | printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n", | |
| 61 | sysconf->sc_sipend, sysconf->sc_simask); | |
| 62 | printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n", | |
| 63 | sysconf->sc_siel, sysconf->sc_sivec); | |
| 64 | printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n", | |
| 65 | sysconf->sc_tesr, sysconf->sc_sdcr); | |
| 66 | ||
| 4b9206ed | 67 | printf ("Memory Controller Registers\n" |
| e887afc9 | 68 | |
| 4b9206ed | 69 | "\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); |
| e887afc9 WD |
70 | printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); |
| 71 | printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); | |
| 72 | printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); | |
| 73 | printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4); | |
| 74 | printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5); | |
| 75 | printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6); | |
| 76 | printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7); | |
| 4b9206ed WD |
77 | printf ("\n" |
| 78 | "\tmamr\t0x%08X\tmbmr\t0x%08X \n", | |
| e887afc9 WD |
79 | memctl->memc_mamr, memctl->memc_mbmr ); |
| 80 | printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n", | |
| 81 | memctl->memc_mstat, memctl->memc_mptpr ); | |
| 82 | printf("\tmdr\t0x%08X \n", memctl->memc_mdr); | |
| 83 | ||
| 4b9206ed WD |
84 | printf ("\nSystem Integration Timers\n" |
| 85 | "\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", | |
| e887afc9 WD |
86 | timers->sit_tbscr, timers->sit_rtcsc); |
| 87 | printf("\tPISCR\t0x%08X \n", timers->sit_piscr); | |
| 88 | ||
| 89 | /* | |
| 90 | * May be some CPM info here? | |
| 91 | */ | |
| 92 | ||
| e075fbe6 | 93 | #elif defined (CONFIG_405GP) |
| 50015ab3 WD |
94 | printf ("\n405GP registers; MSR=%08x\n",mfmsr()); |
| 95 | printf ("\nUniversal Interrupt Controller Regs\n" | |
| 952e7760 | 96 | "UIC0SR UIC0ER UIC0CR UIC0PR UIC0TR UIC0MSR UIC0VR UIC0VCR" |
| 50015ab3 | 97 | "\n" |
| d1631fe1 | 98 | "%08x %08x %08x %08x %08x %08x %08x %08x\n", |
| 952e7760 SR |
99 | mfdcr(UIC0SR), |
| 100 | mfdcr(UIC0ER), | |
| 101 | mfdcr(UIC0CR), | |
| 102 | mfdcr(UIC0PR), | |
| 103 | mfdcr(UIC0TR), | |
| 104 | mfdcr(UIC0MSR), | |
| 105 | mfdcr(UIC0VR), | |
| 106 | mfdcr(UIC0VCR)); | |
| e887afc9 | 107 | |
| 4b9206ed | 108 | puts ("\nMemory (SDRAM) Configuration\n" |
| 50015ab3 | 109 | "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n"); |
| e887afc9 | 110 | |
| 95b602ba SR |
111 | mtdcr(SDRAM0_CFGADDR,SDRAM0_BESR0); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); |
| 112 | mtdcr(SDRAM0_CFGADDR,SDRAM0_BESRS0); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 113 | mtdcr(SDRAM0_CFGADDR,SDRAM0_BESR1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 114 | mtdcr(SDRAM0_CFGADDR,SDRAM0_BESRS1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 115 | mtdcr(SDRAM0_CFGADDR,SDRAM0_BEAR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 116 | mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 117 | mtdcr(SDRAM0_CFGADDR,SDRAM0_RTR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 118 | mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| e887afc9 | 119 | |
| 4b9206ed | 120 | puts ("\n" |
| 50015ab3 | 121 | "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n"); |
| 95b602ba SR |
122 | mtdcr(SDRAM0_CFGADDR,SDRAM0_B0CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); |
| 123 | mtdcr(SDRAM0_CFGADDR,SDRAM0_B1CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 124 | mtdcr(SDRAM0_CFGADDR,SDRAM0_B2CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 125 | mtdcr(SDRAM0_CFGADDR,SDRAM0_B3CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 126 | mtdcr(SDRAM0_CFGADDR,SDRAM0_TR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 127 | mtdcr(SDRAM0_CFGADDR,SDRAM0_ECCCFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 128 | mtdcr(SDRAM0_CFGADDR,SDRAM0_ECCESR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| e887afc9 WD |
129 | |
| 130 | printf ("\n\n" | |
| 50015ab3 | 131 | "DMA Channels\n" |
| d1c3b275 | 132 | "DMASR DMASGC DMAADR\n" |
| 50015ab3 WD |
133 | "%08x %08x %08x\n" |
| 134 | "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" | |
| 135 | "%08x %08x %08x %08x %08x\n" | |
| 136 | "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" | |
| 137 | "%08x %08x %08x %08x %08x\n", | |
| d1c3b275 SR |
138 | mfdcr(DMASR), mfdcr(DMASGC),mfdcr(DMAADR), |
| 139 | mfdcr(DMACR0), mfdcr(DMACT0),mfdcr(DMADA0), mfdcr(DMASA0), mfdcr(DMASB0), | |
| 140 | mfdcr(DMACR1), mfdcr(DMACT1),mfdcr(DMADA1), mfdcr(DMASA1), mfdcr(DMASB1)); | |
| e887afc9 WD |
141 | |
| 142 | printf ( | |
| 50015ab3 WD |
143 | "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" |
| 144 | "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", | |
| d1c3b275 SR |
145 | mfdcr(DMACR2), mfdcr(DMACT2),mfdcr(DMADA2), mfdcr(DMASA2), mfdcr(DMASB2), |
| 146 | mfdcr(DMACR3), mfdcr(DMACT3),mfdcr(DMADA3), mfdcr(DMASA3), mfdcr(DMASB3) ); | |
| e887afc9 | 147 | |
| 4b9206ed | 148 | puts ("\n" |
| 50015ab3 | 149 | "External Bus\n" |
| d1c3b275 SR |
150 | "PBEAR PBESR0 PBESR1 EBC0_CFG\n"); |
| 151 | mtdcr(EBC0_CFGADDR,PBEAR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 152 | mtdcr(EBC0_CFGADDR,PBESR0); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 153 | mtdcr(EBC0_CFGADDR,PBESR1); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 154 | mtdcr(EBC0_CFGADDR,EBC0_CFG); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| e887afc9 | 155 | |
| 4b9206ed | 156 | puts ("\n" |
| d1c3b275 SR |
157 | "PB0CR PB0AP PB1CR PB1AP PB2CR PB2AP PB3CR PB3AP\n"); |
| 158 | mtdcr(EBC0_CFGADDR,PB0CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 159 | mtdcr(EBC0_CFGADDR,PB0AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 160 | mtdcr(EBC0_CFGADDR,PB1CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 161 | mtdcr(EBC0_CFGADDR,PB1AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 162 | mtdcr(EBC0_CFGADDR,PB2CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 163 | mtdcr(EBC0_CFGADDR,PB2AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 164 | mtdcr(EBC0_CFGADDR,PB3CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 165 | mtdcr(EBC0_CFGADDR,PB3AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| e887afc9 | 166 | |
| 4b9206ed | 167 | puts ("\n" |
| d1c3b275 SR |
168 | "PB4CR PB4AP PB5CR bp5ap PB6CR PB6AP PB7CR PB7AP\n"); |
| 169 | mtdcr(EBC0_CFGADDR,PB4CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 170 | mtdcr(EBC0_CFGADDR,PB4AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 171 | mtdcr(EBC0_CFGADDR,PB5CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 172 | mtdcr(EBC0_CFGADDR,PB5AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 173 | mtdcr(EBC0_CFGADDR,PB6CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 174 | mtdcr(EBC0_CFGADDR,PB6AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 175 | mtdcr(EBC0_CFGADDR,PB7CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 176 | mtdcr(EBC0_CFGADDR,PB7AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| e887afc9 | 177 | |
| 4b9206ed | 178 | puts ("\n\n"); |
| 56523f12 | 179 | |
| e075fbe6 | 180 | #elif defined(CONFIG_405EP) |
| 50015ab3 WD |
181 | printf ("\n405EP registers; MSR=%08x\n",mfmsr()); |
| 182 | printf ("\nUniversal Interrupt Controller Regs\n" | |
| 952e7760 | 183 | "UIC0SR UIC0ER UIC0CR UIC0PR UIC0TR UIC0MSR UIC0VR UIC0VCR" |
| 50015ab3 WD |
184 | "\n" |
| 185 | "%08x %08x %08x %08x %08x %08x %08x %08x\n", | |
| 952e7760 SR |
186 | mfdcr(UIC0SR), |
| 187 | mfdcr(UIC0ER), | |
| 188 | mfdcr(UIC0CR), | |
| 189 | mfdcr(UIC0PR), | |
| 190 | mfdcr(UIC0TR), | |
| 191 | mfdcr(UIC0MSR), | |
| 192 | mfdcr(UIC0VR), | |
| 193 | mfdcr(UIC0VCR)); | |
| e075fbe6 | 194 | |
| 4b9206ed | 195 | puts ("\nMemory (SDRAM) Configuration\n" |
| 50015ab3 | 196 | "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n"); |
| e075fbe6 | 197 | |
| 95b602ba SR |
198 | mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); |
| 199 | mtdcr(SDRAM0_CFGADDR,SDRAM0_RTR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 200 | mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 201 | mtdcr(SDRAM0_CFGADDR,SDRAM0_B0CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 202 | mtdcr(SDRAM0_CFGADDR,SDRAM0_B1CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| 203 | mtdcr(SDRAM0_CFGADDR,SDRAM0_TR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); | |
| e075fbe6 SR |
204 | |
| 205 | printf ("\n\n" | |
| 50015ab3 | 206 | "DMA Channels\n" |
| d1c3b275 | 207 | "DMASR DMASGC DMAADR\n" "%08x %08x %08x\n" |
| 50015ab3 WD |
208 | "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n" |
| 209 | "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n", | |
| d1c3b275 SR |
210 | mfdcr(DMASR), mfdcr(DMASGC),mfdcr(DMAADR), |
| 211 | mfdcr(DMACR0), mfdcr(DMACT0),mfdcr(DMADA0), mfdcr(DMASA0), mfdcr(DMASB0), | |
| 212 | mfdcr(DMACR1), mfdcr(DMACT1),mfdcr(DMADA1), mfdcr(DMASA1), mfdcr(DMASB1)); | |
| e075fbe6 SR |
213 | |
| 214 | printf ( | |
| 50015ab3 WD |
215 | "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" |
| 216 | "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", | |
| d1c3b275 SR |
217 | mfdcr(DMACR2), mfdcr(DMACT2),mfdcr(DMADA2), mfdcr(DMASA2), mfdcr(DMASB2), |
| 218 | mfdcr(DMACR3), mfdcr(DMACT3),mfdcr(DMADA3), mfdcr(DMASA3), mfdcr(DMASB3) ); | |
| e075fbe6 | 219 | |
| 4b9206ed | 220 | puts ("\n" |
| 50015ab3 | 221 | "External Bus\n" |
| d1c3b275 SR |
222 | "PBEAR PBESR0 PBESR1 EBC0_CFG\n"); |
| 223 | mtdcr(EBC0_CFGADDR,PBEAR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 224 | mtdcr(EBC0_CFGADDR,PBESR0); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 225 | mtdcr(EBC0_CFGADDR,PBESR1); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 226 | mtdcr(EBC0_CFGADDR,EBC0_CFG); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| e075fbe6 | 227 | |
| 4b9206ed | 228 | puts ("\n" |
| d1c3b275 SR |
229 | "PB0CR PB0AP PB1CR PB1AP PB2CR PB2AP PB3CR PB3AP\n"); |
| 230 | mtdcr(EBC0_CFGADDR,PB0CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 231 | mtdcr(EBC0_CFGADDR,PB0AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 232 | mtdcr(EBC0_CFGADDR,PB1CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 233 | mtdcr(EBC0_CFGADDR,PB1AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 234 | mtdcr(EBC0_CFGADDR,PB2CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 235 | mtdcr(EBC0_CFGADDR,PB2AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 236 | mtdcr(EBC0_CFGADDR,PB3CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 237 | mtdcr(EBC0_CFGADDR,PB3AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| e075fbe6 | 238 | |
| 4b9206ed | 239 | puts ("\n" |
| d1c3b275 SR |
240 | "PB4CR PB4AP\n"); |
| 241 | mtdcr(EBC0_CFGADDR,PB4CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| 242 | mtdcr(EBC0_CFGADDR,PB4AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); | |
| e075fbe6 | 243 | |
| 4b9206ed | 244 | puts ("\n\n"); |
| 0db5bca8 | 245 | #elif defined(CONFIG_5xx) |
| e887afc9 | 246 | |
| 6d0f6bcf | 247 | volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
| 0db5bca8 WD |
248 | volatile memctl5xx_t *memctl = &immap->im_memctl; |
| 249 | volatile sysconf5xx_t *sysconf = &immap->im_siu_conf; | |
| 250 | volatile sit5xx_t *timers = &immap->im_sit; | |
| 251 | volatile car5xx_t *car = &immap->im_clkrst; | |
| 252 | volatile uimb5xx_t *uimb = &immap->im_uimb; | |
| 253 | ||
| 4b9206ed | 254 | puts ("\nSystem Configuration registers\n"); |
| 0db5bca8 WD |
255 | printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr); |
| 256 | printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr); | |
| 257 | printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask); | |
| 258 | printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec); | |
| 259 | printf("\tTESR\t0x%08X\n", sysconf->sc_tesr); | |
| 260 | ||
| 4b9206ed | 261 | puts ("\nMemory Controller Registers\n"); |
| 0db5bca8 WD |
262 | printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0); |
| 263 | printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1); | |
| 264 | printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2); | |
| 265 | printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3); | |
| 266 | printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor ); | |
| 267 | printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat); | |
| 268 | ||
| 4b9206ed | 269 | puts ("\nSystem Integration Timers\n"); |
| 0db5bca8 WD |
270 | printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc); |
| 271 | printf("\tPISCR\t0x%08X \n", timers->sit_piscr); | |
| 272 | ||
| 4b9206ed | 273 | puts ("\nClocks and Reset\n"); |
| 0db5bca8 WD |
274 | printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr); |
| 275 | ||
| 4b9206ed | 276 | puts ("\nU-Bus to IMB3 Bus Interface\n"); |
| 0db5bca8 | 277 | printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend); |
| 4b9206ed | 278 | puts ("\n\n"); |
| 56523f12 WD |
279 | |
| 280 | #elif defined(CONFIG_MPC5200) | |
| 281 | puts ("\nMPC5200 registers\n"); | |
| 6d0f6bcf | 282 | printf ("MBAR=%08x\n", CONFIG_SYS_MBAR); |
| 56523f12 | 283 | puts ("Memory map registers\n"); |
| 9b55a253 | 284 | printf ("\tCS0: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", |
| 56523f12 WD |
285 | *(volatile ulong*)MPC5XXX_CS0_START, |
| 286 | *(volatile ulong*)MPC5XXX_CS0_STOP, | |
| 287 | *(volatile ulong*)MPC5XXX_CS0_CFG, | |
| 288 | (*(volatile ulong*)MPC5XXX_ADDECR & 0x00010000) ? 1 : 0); | |
| 9b55a253 | 289 | printf ("\tCS1: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", |
| 56523f12 WD |
290 | *(volatile ulong*)MPC5XXX_CS1_START, |
| 291 | *(volatile ulong*)MPC5XXX_CS1_STOP, | |
| 292 | *(volatile ulong*)MPC5XXX_CS1_CFG, | |
| 293 | (*(volatile ulong*)MPC5XXX_ADDECR & 0x00020000) ? 1 : 0); | |
| 9b55a253 | 294 | printf ("\tCS2: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", |
| 56523f12 WD |
295 | *(volatile ulong*)MPC5XXX_CS2_START, |
| 296 | *(volatile ulong*)MPC5XXX_CS2_STOP, | |
| 297 | *(volatile ulong*)MPC5XXX_CS2_CFG, | |
| 298 | (*(volatile ulong*)MPC5XXX_ADDECR & 0x00040000) ? 1 : 0); | |
| 9b55a253 | 299 | printf ("\tCS3: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", |
| 56523f12 WD |
300 | *(volatile ulong*)MPC5XXX_CS3_START, |
| 301 | *(volatile ulong*)MPC5XXX_CS3_STOP, | |
| 302 | *(volatile ulong*)MPC5XXX_CS3_CFG, | |
| 303 | (*(volatile ulong*)MPC5XXX_ADDECR & 0x00080000) ? 1 : 0); | |
| 9b55a253 | 304 | printf ("\tCS4: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", |
| 56523f12 WD |
305 | *(volatile ulong*)MPC5XXX_CS4_START, |
| 306 | *(volatile ulong*)MPC5XXX_CS4_STOP, | |
| 307 | *(volatile ulong*)MPC5XXX_CS4_CFG, | |
| 308 | (*(volatile ulong*)MPC5XXX_ADDECR & 0x00100000) ? 1 : 0); | |
| 9b55a253 | 309 | printf ("\tCS5: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", |
| 56523f12 WD |
310 | *(volatile ulong*)MPC5XXX_CS5_START, |
| 311 | *(volatile ulong*)MPC5XXX_CS5_STOP, | |
| 312 | *(volatile ulong*)MPC5XXX_CS5_CFG, | |
| 313 | (*(volatile ulong*)MPC5XXX_ADDECR & 0x00200000) ? 1 : 0); | |
| 9b55a253 | 314 | printf ("\tCS6: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", |
| 56523f12 WD |
315 | *(volatile ulong*)MPC5XXX_CS6_START, |
| 316 | *(volatile ulong*)MPC5XXX_CS6_STOP, | |
| 317 | *(volatile ulong*)MPC5XXX_CS6_CFG, | |
| 318 | (*(volatile ulong*)MPC5XXX_ADDECR & 0x04000000) ? 1 : 0); | |
| 9b55a253 | 319 | printf ("\tCS7: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", |
| 56523f12 WD |
320 | *(volatile ulong*)MPC5XXX_CS7_START, |
| 321 | *(volatile ulong*)MPC5XXX_CS7_STOP, | |
| 322 | *(volatile ulong*)MPC5XXX_CS7_CFG, | |
| 323 | (*(volatile ulong*)MPC5XXX_ADDECR & 0x08000000) ? 1 : 0); | |
| 9b55a253 | 324 | printf ("\tBOOTCS: start %08lX\tstop %08lX\tconfig %08lX\ten %d\n", |
| 56523f12 WD |
325 | *(volatile ulong*)MPC5XXX_BOOTCS_START, |
| 326 | *(volatile ulong*)MPC5XXX_BOOTCS_STOP, | |
| 327 | *(volatile ulong*)MPC5XXX_BOOTCS_CFG, | |
| 328 | (*(volatile ulong*)MPC5XXX_ADDECR & 0x02000000) ? 1 : 0); | |
| 9b55a253 | 329 | printf ("\tSDRAMCS0: %08lX\n", |
| 56523f12 | 330 | *(volatile ulong*)MPC5XXX_SDRAM_CS0CFG); |
| 9b55a253 | 331 | printf ("\tSDRAMCS1: %08lX\n", |
| 56523f12 | 332 | *(volatile ulong*)MPC5XXX_SDRAM_CS1CFG); |
| 4f93f8b1 BB |
333 | #elif defined(CONFIG_MPC86xx) |
| 334 | mpc86xx_reginfo(); | |
| 97c26e00 MF |
335 | |
| 336 | #elif defined(CONFIG_BLACKFIN) | |
| 337 | puts("\nSystem Configuration registers\n"); | |
| 338 | ||
| 339 | puts("\nPLL Registers\n"); | |
| 340 | printf("\tPLL_DIV: 0x%04x PLL_CTL: 0x%04x\n", | |
| 341 | bfin_read_PLL_DIV(), bfin_read_PLL_CTL()); | |
| 342 | printf("\tPLL_STAT: 0x%04x PLL_LOCKCNT: 0x%04x\n", | |
| 343 | bfin_read_PLL_STAT(), bfin_read_PLL_LOCKCNT()); | |
| 344 | printf("\tVR_CTL: 0x%04x\n", bfin_read_VR_CTL()); | |
| 345 | ||
| 346 | puts("\nEBIU AMC Registers\n"); | |
| 347 | printf("\tEBIU_AMGCTL: 0x%04x\n", bfin_read_EBIU_AMGCTL()); | |
| 348 | printf("\tEBIU_AMBCTL0: 0x%08x EBIU_AMBCTL1: 0x%08x\n", | |
| 349 | bfin_read_EBIU_AMBCTL0(), bfin_read_EBIU_AMBCTL1()); | |
| 350 | # ifdef EBIU_MODE | |
| 351 | printf("\tEBIU_MBSCTL: 0x%08x EBIU_ARBSTAT: 0x%08x\n", | |
| 352 | bfin_read_EBIU_MBSCTL(), bfin_read_EBIU_ARBSTAT()); | |
| 353 | printf("\tEBIU_MODE: 0x%08x EBIU_FCTL: 0x%08x\n", | |
| 354 | bfin_read_EBIU_MODE(), bfin_read_EBIU_FCTL()); | |
| 355 | # endif | |
| 356 | ||
| 357 | # ifdef EBIU_RSTCTL | |
| 358 | puts("\nEBIU DDR Registers\n"); | |
| 359 | printf("\tEBIU_DDRCTL0: 0x%08x EBIU_DDRCTL1: 0x%08x\n", | |
| 360 | bfin_read_EBIU_DDRCTL0(), bfin_read_EBIU_DDRCTL1()); | |
| 361 | printf("\tEBIU_DDRCTL2: 0x%08x EBIU_DDRCTL3: 0x%08x\n", | |
| 362 | bfin_read_EBIU_DDRCTL2(), bfin_read_EBIU_DDRCTL3()); | |
| 363 | printf("\tEBIU_DDRQUE: 0x%08x EBIU_RSTCTL 0x%04x\n", | |
| 364 | bfin_read_EBIU_DDRQUE(), bfin_read_EBIU_RSTCTL()); | |
| 365 | printf("\tEBIU_ERRADD: 0x%08x EBIU_ERRMST: 0x%04x\n", | |
| 366 | bfin_read_EBIU_ERRADD(), bfin_read_EBIU_ERRMST()); | |
| 367 | # else | |
| 368 | puts("\nEBIU SDC Registers\n"); | |
| 369 | printf("\tEBIU_SDRRC: 0x%04x EBIU_SDBCTL: 0x%04x\n", | |
| 370 | bfin_read_EBIU_SDRRC(), bfin_read_EBIU_SDBCTL()); | |
| 371 | printf("\tEBIU_SDSTAT: 0x%04x EBIU_SDGCTL: 0x%08x\n", | |
| 372 | bfin_read_EBIU_SDSTAT(), bfin_read_EBIU_SDGCTL()); | |
| 373 | # endif | |
| 374 | ||
| 9e04a813 | 375 | #endif /* CONFIG_BLACKFIN */ |
| 4f93f8b1 | 376 | |
| e887afc9 WD |
377 | return 0; |
| 378 | } | |
| 379 | ||
| 8bde7f77 WD |
380 | /**************************************************/ |
| 381 | ||
| 97c26e00 | 382 | #if defined(CONFIG_CMD_REGINFO) |
| 0d498393 | 383 | U_BOOT_CMD( |
| 53677ef1 | 384 | reginfo, 2, 1, do_reginfo, |
| 2fb2604d | 385 | "print register information", |
| a89c33db | 386 | "" |
| 8bde7f77 WD |
387 | ); |
| 388 | #endif |