[J-u-boot.git] / common / cmd_reginfo.c

/*
 * (C) Copyright 2000
 * Subodh Nijsure, SkyStream Networks, [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <command.h>
#if defined(CONFIG_8xx)
#include <mpc8xx.h>
#elif defined (CONFIG_405GP) || defined(CONFIG_405EP)
#include <asm/processor.h>
#elif defined (CONFIG_5xx)
#include <mpc5xx.h>
#endif
#if (CONFIG_COMMANDS & CFG_CMD_REGINFO)

int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
#if defined(CONFIG_8xx)
	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
	volatile sit8xx_t *timers = &immap->im_sit;

	/* Hopefully more PowerPC  knowledgable people will add code to display
	 * other useful registers
	 */

	printf ("\nSystem Configuration registers\n"

		"\tIMMR\t0x%08X\n", get_immr(0));

	printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
	printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);

	printf("\tSWT\t0x%08X",    sysconf->sc_swt);
	printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);

	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
		sysconf->sc_sipend, sysconf->sc_simask);
	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
		sysconf->sc_siel, sysconf->sc_sivec);
	printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
		sysconf->sc_tesr, sysconf->sc_sdcr);

	printf ("Memory Controller Registers\n"

		"\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
	printf ("\n"
		"\tmamr\t0x%08X\tmbmr\t0x%08X \n",
		memctl->memc_mamr, memctl->memc_mbmr );
	printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
		memctl->memc_mstat, memctl->memc_mptpr );
	printf("\tmdr\t0x%08X \n", memctl->memc_mdr);

	printf ("\nSystem Integration Timers\n"
		"\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
		timers->sit_tbscr, timers->sit_rtcsc);
	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);

	/*
	 * May be some CPM info here?
	 */

/* DBU[[email protected]]   For the CRAY-L1, but should be generically 405gp */
#elif defined (CONFIG_405GP)
	printf ("\n405GP registers; MSR=%08x\n",mfmsr());
	printf ("\nUniversal Interrupt Controller Regs\n"
	    "uicsr    uicsrs   uicer    uiccr    uicpr    uictr    uicmsr   uicvr    uicvcr"
	    "\n"
	    "%08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
	mfdcr(uicsr),
	mfdcr(uicsrs),
	mfdcr(uicer),
	mfdcr(uiccr),
	mfdcr(uicpr),
	mfdcr(uictr),
	mfdcr(uicmsr),
	mfdcr(uicvr),
	mfdcr(uicvcr));

	puts ("\nMemory (SDRAM) Configuration\n"
	    "besra    besrsa   besrb    besrsb   bear     mcopt1   rtr      pmit\n");

	mtdcr(memcfga,mem_besra); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_besrsa);	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_besrb); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_besrsb); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_bear); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mcopt1); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_rtr); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_pmit); 	printf ("%08x ", mfdcr(memcfgd));

	puts ("\n"
	    "mb0cf    mb1cf    mb2cf    mb3cf    sdtr1    ecccf    eccerr\n");
	mtdcr(memcfga,mem_mb0cf); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb1cf); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb2cf); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb3cf); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_sdtr1); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_ecccf); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_eccerr); 	printf ("%08x ", mfdcr(memcfgd));

	printf ("\n\n"
	    "DMA Channels\n"
	    "dmasr    dmasgc   dmaadr\n"
	    "%08x %08x %08x\n"
	    "dmacr_0  dmact_0  dmada_0  dmasa_0  dmasb_0\n"
	    "%08x %08x %08x %08x %08x\n"
	    "dmacr_1  dmact_1  dmada_1  dmasa_1  dmasb_1\n"
	    "%08x %08x %08x %08x %08x\n",
	mfdcr(dmasr),  mfdcr(dmasgc),mfdcr(dmaadr),
	mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
	mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));

	printf (
	    "dmacr_2  dmact_2  dmada_2  dmasa_2  dmasb_2\n"	"%08x %08x %08x %08x %08x\n"
	    "dmacr_3  dmact_3  dmada_3  dmasa_3  dmasb_3\n"	"%08x %08x %08x %08x %08x\n",
	mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
	mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );

	puts ("\n"
	    "External Bus\n"
	    "pbear    pbesr0   pbesr1   epcr\n");
	mtdcr(ebccfga,pbear); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pbesr0); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pbesr1); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,epcr); 	printf ("%08x ", mfdcr(ebccfgd));

	puts ("\n"
	    "pb0cr    pb0ap    pb1cr    pb1ap    pb2cr    pb2ap    pb3cr    pb3ap\n");
	mtdcr(ebccfga,pb0cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb0ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb1cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb1ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb2cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb2ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb3cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb3ap); 	printf ("%08x ", mfdcr(ebccfgd));

	puts ("\n"
	    "pb4cr    pb4ap    pb5cr    bp5ap    pb6cr    pb6ap    pb7cr    pb7ap\n");
	mtdcr(ebccfga,pb4cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb4ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb5cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb5ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb6cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb6ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb7cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb7ap); 	printf ("%08x ", mfdcr(ebccfgd));

	puts ("\n\n");
/* For the BUBINGA (IBM 405EP eval) but should be generically 405ep */
#elif defined(CONFIG_405EP)
	printf ("\n405EP registers; MSR=%08x\n",mfmsr());
	printf ("\nUniversal Interrupt Controller Regs\n"
	    "uicsr    uicer    uiccr    uicpr    uictr    uicmsr   uicvr    uicvcr"
	    "\n"
	    "%08x %08x %08x %08x %08x %08x %08x %08x\n",
	mfdcr(uicsr),
	mfdcr(uicer),
	mfdcr(uiccr),
	mfdcr(uicpr),
	mfdcr(uictr),
	mfdcr(uicmsr),
	mfdcr(uicvr),
	mfdcr(uicvcr));

	puts ("\nMemory (SDRAM) Configuration\n"
	    "mcopt1   rtr      pmit     mb0cf    mb1cf    sdtr1\n");

	mtdcr(memcfga,mem_mcopt1); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_rtr); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_pmit); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb0cf); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_mb1cf); 	printf ("%08x ", mfdcr(memcfgd));
	mtdcr(memcfga,mem_sdtr1); 	printf ("%08x ", mfdcr(memcfgd));

	printf ("\n\n"
	    "DMA Channels\n"
	    "dmasr    dmasgc   dmaadr\n"			"%08x %08x %08x\n"
	    "dmacr_0  dmact_0  dmada_0  dmasa_0  dmasb_0\n"	"%08x %08x %08x %08x %08x\n"
	    "dmacr_1  dmact_1  dmada_1  dmasa_1  dmasb_1\n"	"%08x %08x %08x %08x %08x\n",
	mfdcr(dmasr),  mfdcr(dmasgc),mfdcr(dmaadr),
	mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
	mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));

	printf (
	    "dmacr_2  dmact_2  dmada_2  dmasa_2  dmasb_2\n"	"%08x %08x %08x %08x %08x\n"
	    "dmacr_3  dmact_3  dmada_3  dmasa_3  dmasb_3\n"	"%08x %08x %08x %08x %08x\n",
	mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
	mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );

	puts ("\n"
	    "External Bus\n"
	    "pbear    pbesr0   pbesr1   epcr\n");
	mtdcr(ebccfga,pbear); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pbesr0); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pbesr1); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,epcr); 	printf ("%08x ", mfdcr(ebccfgd));

	puts ("\n"
	    "pb0cr    pb0ap    pb1cr    pb1ap    pb2cr    pb2ap    pb3cr    pb3ap\n");
	mtdcr(ebccfga,pb0cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb0ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb1cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb1ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb2cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb2ap); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb3cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb3ap); 	printf ("%08x ", mfdcr(ebccfgd));

	puts ("\n"
	    "pb4cr    pb4ap\n");
	mtdcr(ebccfga,pb4cr); 	printf ("%08x ", mfdcr(ebccfgd));
	mtdcr(ebccfga,pb4ap); 	printf ("%08x ", mfdcr(ebccfgd));

	puts ("\n\n");
#elif defined(CONFIG_5xx)

	volatile immap_t     	*immap  = (immap_t *)CFG_IMMR;
	volatile memctl5xx_t	*memctl = &immap->im_memctl;
	volatile sysconf5xx_t	*sysconf = &immap->im_siu_conf;
	volatile sit5xx_t	*timers = &immap->im_sit;
	volatile car5xx_t	*car = &immap->im_clkrst;
	volatile uimb5xx_t	*uimb = &immap->im_uimb;

	puts ("\nSystem Configuration registers\n");
	printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
	printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
	printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);

	puts ("\nMemory Controller Registers\n");
	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
	printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);

	puts ("\nSystem Integration Timers\n");
	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);

	puts ("\nClocks and Reset\n");
	printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);

	puts ("\nU-Bus to IMB3 Bus Interface\n");
	printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
	puts ("\n\n");
#endif /* CONFIG_5xx */
	return 0;
}

#endif	/* CONFIG_COMMANDS & CFG_CMD_REGINFO */


 /**************************************************/

#if (defined(CONFIG_8xx) || defined(CONFIG_405GP) || defined(CONFIG_405EP)) && \
     (CONFIG_COMMANDS & CFG_CMD_REGINFO)

U_BOOT_CMD(
 	reginfo,	2,	1,	do_reginfo,
	"reginfo - print register information\n",
);
#endif
Commit	Line	Data
e887afc9 WD	1	/*
	2	* (C) Copyright 2000
	3	* Subodh Nijsure, SkyStream Networks, [email protected]
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <common.h>
	25	#include <command.h>
e887afc9 WD	26	#if defined(CONFIG_8xx)
e887afc9 WD	27	#include <mpc8xx.h>
e075fbe6	28	#elif defined (CONFIG_405GP) \|\| defined(CONFIG_405EP)
e887afc9	29	#include <asm/processor.h>
0db5bca8 WD	30	#elif defined (CONFIG_5xx)
0db5bca8 WD	31	#include <mpc5xx.h>
e887afc9 WD	32	#endif
	33	#if (CONFIG_COMMANDS & CFG_CMD_REGINFO)
	34
	35	int do_reginfo (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	36	{
	37	#if defined(CONFIG_8xx)
	38	volatile immap_t immap = (immap_t )CFG_IMMR;
	39	volatile memctl8xx_t *memctl = &immap->im_memctl;
	40	volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
	41	volatile sit8xx_t *timers = &immap->im_sit;
	42
	43	/* Hopefully more PowerPC knowledgable people will add code to display
	44	* other useful registers
	45	*/
	46
4b9206ed	47	printf ("\nSystem Configuration registers\n"
e887afc9	48
4b9206ed	49	"\tIMMR\t0x%08X\n", get_immr(0));
e887afc9 WD	50
	51	printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
	52	printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
	53
	54	printf("\tSWT\t0x%08X", sysconf->sc_swt);
	55	printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
	56
	57	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
	58	sysconf->sc_sipend, sysconf->sc_simask);
	59	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
	60	sysconf->sc_siel, sysconf->sc_sivec);
	61	printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
	62	sysconf->sc_tesr, sysconf->sc_sdcr);
	63
4b9206ed	64	printf ("Memory Controller Registers\n"
e887afc9	65
4b9206ed	66	"\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
e887afc9 WD	67	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	68	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	69	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	70	printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
	71	printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
	72	printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
	73	printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
4b9206ed WD	74	printf ("\n"
4b9206ed WD	75	"\tmamr\t0x%08X\tmbmr\t0x%08X \n",
e887afc9 WD	76	memctl->memc_mamr, memctl->memc_mbmr );
	77	printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
	78	memctl->memc_mstat, memctl->memc_mptpr );
	79	printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
	80
4b9206ed WD	81	printf ("\nSystem Integration Timers\n"
4b9206ed WD	82	"\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
e887afc9 WD	83	timers->sit_tbscr, timers->sit_rtcsc);
	84	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
	85
	86	/*
	87	* May be some CPM info here?
	88	*/
	89
	90	/* DBU[[email protected]] For the CRAY-L1, but should be generically 405gp */
e075fbe6	91	#elif defined (CONFIG_405GP)
50015ab3 WD	92	printf ("\n405GP registers; MSR=%08x\n",mfmsr());
	93	printf ("\nUniversal Interrupt Controller Regs\n"
	94	"uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
	95	"\n"
	96	"%08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
e887afc9 WD	97	mfdcr(uicsr),
	98	mfdcr(uicsrs),
	99	mfdcr(uicer),
	100	mfdcr(uiccr),
	101	mfdcr(uicpr),
	102	mfdcr(uictr),
	103	mfdcr(uicmsr),
	104	mfdcr(uicvr),
	105	mfdcr(uicvcr));
	106
4b9206ed	107	puts ("\nMemory (SDRAM) Configuration\n"
50015ab3	108	"besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
e887afc9 WD	109
	110	mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd));
	111	mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd));
	112	mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd));
	113	mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd));
	114	mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd));
	115	mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
	116	mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
	117	mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
	118
4b9206ed	119	puts ("\n"
50015ab3	120	"mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n");
e887afc9 WD	121	mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
	122	mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
	123	mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd));
	124	mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd));
	125	mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
	126	mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd));
	127	mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd));
	128
	129	printf ("\n\n"
50015ab3 WD	130	"DMA Channels\n"
	131	"dmasr dmasgc dmaadr\n"
	132	"%08x %08x %08x\n"
	133	"dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n"
	134	"%08x %08x %08x %08x %08x\n"
	135	"dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n"
	136	"%08x %08x %08x %08x %08x\n",
	137	mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
	138	mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
	139	mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
e887afc9 WD	140
e887afc9 WD	141	printf (
50015ab3 WD	142	"dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
	143	"dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
	144	mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
	145	mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
e887afc9	146
4b9206ed	147	puts ("\n"
50015ab3 WD	148	"External Bus\n"
50015ab3 WD	149	"pbear pbesr0 pbesr1 epcr\n");
e887afc9 WD	150	mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
	151	mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
	152	mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
	153	mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
	154
4b9206ed	155	puts ("\n"
50015ab3	156	"pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
e887afc9 WD	157	mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
	158	mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
	159	mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
	160	mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
	161	mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
	162	mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
	163	mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
	164	mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
	165
4b9206ed	166	puts ("\n"
50015ab3	167	"pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n");
e887afc9 WD	168	mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
	169	mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
	170	mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd));
	171	mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd));
	172	mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd));
	173	mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd));
	174	mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd));
	175	mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd));
	176
4b9206ed	177	puts ("\n\n");
e075fbe6 SR	178	/* For the BUBINGA (IBM 405EP eval) but should be generically 405ep */
e075fbe6 SR	179	#elif defined(CONFIG_405EP)
50015ab3 WD	180	printf ("\n405EP registers; MSR=%08x\n",mfmsr());
	181	printf ("\nUniversal Interrupt Controller Regs\n"
	182	"uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
	183	"\n"
	184	"%08x %08x %08x %08x %08x %08x %08x %08x\n",
e075fbe6 SR	185	mfdcr(uicsr),
	186	mfdcr(uicer),
	187	mfdcr(uiccr),
	188	mfdcr(uicpr),
	189	mfdcr(uictr),
	190	mfdcr(uicmsr),
	191	mfdcr(uicvr),
	192	mfdcr(uicvcr));
	193
4b9206ed	194	puts ("\nMemory (SDRAM) Configuration\n"
50015ab3	195	"mcopt1 rtr pmit mb0cf mb1cf sdtr1\n");
e075fbe6 SR	196
	197	mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
	198	mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
	199	mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
	200	mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
	201	mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
	202	mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
	203
	204	printf ("\n\n"
50015ab3 WD	205	"DMA Channels\n"
	206	"dmasr dmasgc dmaadr\n" "%08x %08x %08x\n"
	207	"dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n"
	208	"dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n",
	209	mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
	210	mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
	211	mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
e075fbe6 SR	212
e075fbe6 SR	213	printf (
50015ab3 WD	214	"dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
	215	"dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
	216	mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
	217	mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
e075fbe6	218
4b9206ed	219	puts ("\n"
50015ab3 WD	220	"External Bus\n"
50015ab3 WD	221	"pbear pbesr0 pbesr1 epcr\n");
e075fbe6 SR	222	mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
	223	mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
	224	mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
	225	mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
	226
4b9206ed	227	puts ("\n"
50015ab3	228	"pb0cr pb0ap pb1cr pb1ap pb2cr pb2ap pb3cr pb3ap\n");
e075fbe6 SR	229	mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
	230	mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
	231	mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
	232	mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
	233	mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
	234	mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
	235	mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
	236	mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
	237
4b9206ed	238	puts ("\n"
50015ab3	239	"pb4cr pb4ap\n");
e075fbe6 SR	240	mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
	241	mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
	242
4b9206ed	243	puts ("\n\n");
0db5bca8	244	#elif defined(CONFIG_5xx)
e887afc9	245
0db5bca8 WD	246	volatile immap_t immap = (immap_t )CFG_IMMR;
	247	volatile memctl5xx_t *memctl = &immap->im_memctl;
	248	volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
	249	volatile sit5xx_t *timers = &immap->im_sit;
	250	volatile car5xx_t *car = &immap->im_clkrst;
	251	volatile uimb5xx_t *uimb = &immap->im_uimb;
	252
4b9206ed	253	puts ("\nSystem Configuration registers\n");
0db5bca8 WD	254	printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
	255	printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
	256	printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
	257	printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
	258	printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
	259
4b9206ed	260	puts ("\nMemory Controller Registers\n");
0db5bca8 WD	261	printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
	262	printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
	263	printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
	264	printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
	265	printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
	266	printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
	267
4b9206ed	268	puts ("\nSystem Integration Timers\n");
0db5bca8 WD	269	printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
	270	printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
	271
4b9206ed	272	puts ("\nClocks and Reset\n");
0db5bca8 WD	273	printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
0db5bca8 WD	274
4b9206ed	275	puts ("\nU-Bus to IMB3 Bus Interface\n");
0db5bca8	276	printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
4b9206ed	277	puts ("\n\n");
0db5bca8	278	#endif /* CONFIG_5xx */
e887afc9 WD	279	return 0;
	280	}
	281
0db5bca8	282	#endif /* CONFIG_COMMANDS & CFG_CMD_REGINFO */
8bde7f77 WD	283
	284
	285	/**************************************************/
	286
e075fbe6	287	#if (defined(CONFIG_8xx) \|\| defined(CONFIG_405GP) \|\| defined(CONFIG_405EP)) && \
8bde7f77 WD	288	(CONFIG_COMMANDS & CFG_CMD_REGINFO)
8bde7f77 WD	289
0d498393 WD	290	U_BOOT_CMD(
0d498393 WD	291	reginfo, 2, 1, do_reginfo,
8bde7f77 WD	292	"reginfo - print register information\n",
	293	);
	294	#endif