[J-u-boot.git] / include / phy.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 *	Andy Fleming <[email protected]>
 *
 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
 */

#ifndef _PHY_H
#define _PHY_H

#include <log.h>
#include <phy_interface.h>
#include <dm/ofnode.h>
#include <dm/read.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>

struct udevice;

#define PHY_FIXED_ID		0xa5a55a5a
#define PHY_NCSI_ID            0xbeefcafe

/*
 * There is no actual id for this.
 * This is just a dummy id for gmii2rgmmi converter.
 */
#define PHY_GMII2RGMII_ID	0x5a5a5a5a

#define PHY_MAX_ADDR 32

#define PHY_FLAG_BROKEN_RESET	(1 << 0) /* soft reset not supported */

#define PHY_DEFAULT_FEATURES	(SUPPORTED_Autoneg | \
				 SUPPORTED_TP | \
				 SUPPORTED_MII)

#define PHY_10BT_FEATURES	(SUPPORTED_10baseT_Half | \
				 SUPPORTED_10baseT_Full)

#define PHY_100BT_FEATURES	(SUPPORTED_100baseT_Half | \
				 SUPPORTED_100baseT_Full)

#define PHY_1000BT_FEATURES	(SUPPORTED_1000baseT_Half | \
				 SUPPORTED_1000baseT_Full)

#define PHY_BASIC_FEATURES	(PHY_10BT_FEATURES | \
				 PHY_100BT_FEATURES | \
				 PHY_DEFAULT_FEATURES)

#define PHY_GBIT_FEATURES	(PHY_BASIC_FEATURES | \
				 PHY_1000BT_FEATURES)

#define PHY_10G_FEATURES	(PHY_GBIT_FEATURES | \
				SUPPORTED_10000baseT_Full)

#ifndef PHY_ANEG_TIMEOUT
#define PHY_ANEG_TIMEOUT	4000
#endif


struct phy_device;

#define MDIO_NAME_LEN 32

struct mii_dev {
	struct list_head link;
	char name[MDIO_NAME_LEN];
	void *priv;
	int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
	int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
			u16 val);
	int (*reset)(struct mii_dev *bus);
	struct phy_device *phymap[PHY_MAX_ADDR];
	u32 phy_mask;
};

/* struct phy_driver: a structure which defines PHY behavior
 *
 * uid will contain a number which represents the PHY.  During
 * startup, the driver will poll the PHY to find out what its
 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 * gotten from the PHY will be masked to
 * discard any bits which may change based on revision numbers
 * unimportant to functionality
 *
 */
struct phy_driver {
	char *name;
	unsigned int uid;
	unsigned int mask;
	unsigned int mmds;

	u32 features;

	/* Called to do any driver startup necessities */
	/* Will be called during phy_connect */
	int (*probe)(struct phy_device *phydev);

	/* Called to configure the PHY, and modify the controller
	 * based on the results.  Should be called after phy_connect */
	int (*config)(struct phy_device *phydev);

	/* Called when starting up the controller */
	int (*startup)(struct phy_device *phydev);

	/* Called when bringing down the controller */
	int (*shutdown)(struct phy_device *phydev);

	int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
	int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
			u16 val);

	/* Phy specific driver override for reading a MMD register */
	int (*read_mmd)(struct phy_device *phydev, int devad, int reg);

	/* Phy specific driver override for writing a MMD register */
	int (*write_mmd)(struct phy_device *phydev, int devad, int reg,
			 u16 val);

	struct list_head list;

	/* driver private data */
	ulong data;
};

struct phy_device {
	/* Information about the PHY type */
	/* And management functions */
	struct mii_dev *bus;
	struct phy_driver *drv;
	void *priv;

#ifdef CONFIG_DM_ETH
	struct udevice *dev;
	ofnode node;
#else
	struct eth_device *dev;
#endif

	/* forced speed & duplex (no autoneg)
	 * partner speed & duplex & pause (autoneg)
	 */
	int speed;
	int duplex;

	/* The most recently read link state */
	int link;
	int port;
	phy_interface_t interface;

	u32 advertising;
	u32 supported;
	u32 mmds;

	int autoneg;
	int addr;
	int pause;
	int asym_pause;
	u32 phy_id;
	bool is_c45;
	u32 flags;
};

struct fixed_link {
	int phy_id;
	int duplex;
	int link_speed;
	int pause;
	int asym_pause;
};

/**
 * phy_read - Convenience function for reading a given PHY register
 * @phydev: the phy_device struct
 * @devad: The MMD to read from
 * @regnum: register number to read
 * @return: value for success or negative errno for failure
 */
static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
	struct mii_dev *bus = phydev->bus;

	if (!bus || !bus->read) {
		debug("%s: No bus configured\n", __func__);
		return -1;
	}

	return bus->read(bus, phydev->addr, devad, regnum);
}

/**
 * phy_write - Convenience function for writing a given PHY register
 * @phydev: the phy_device struct
 * @devad: The MMD to read from
 * @regnum: register number to write
 * @val: value to write to @regnum
 * @return: 0 for success or negative errno for failure
 */
static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
			u16 val)
{
	struct mii_dev *bus = phydev->bus;

	if (!bus || !bus->write) {
		debug("%s: No bus configured\n", __func__);
		return -1;
	}

	return bus->write(bus, phydev->addr, devad, regnum, val);
}

/**
 * phy_mmd_start_indirect - Convenience function for writing MMD registers
 * @phydev: the phy_device struct
 * @devad: The MMD to read from
 * @regnum: register number to write
 * @return: None
 */
static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
					  int regnum)
{
	/* Write the desired MMD Devad */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);

	/* Write the desired MMD register address */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);

	/* Select the Function : DATA with no post increment */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL,
		  (devad | MII_MMD_CTRL_NOINCR));
}

/**
 * phy_read_mmd - Convenience function for reading a register
 * from an MMD on a given PHY.
 * @phydev: The phy_device struct
 * @devad: The MMD to read from
 * @regnum: The register on the MMD to read
 * @return: Value for success or negative errno for failure
 */
static inline int phy_read_mmd(struct phy_device *phydev, int devad,
			       int regnum)
{
	struct phy_driver *drv = phydev->drv;

	if (regnum > (u16)~0 || devad > 32)
		return -EINVAL;

	/* driver-specific access */
	if (drv->read_mmd)
		return drv->read_mmd(phydev, devad, regnum);

	/* direct C45 / C22 access */
	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
	    devad == MDIO_DEVAD_NONE || !devad)
		return phy_read(phydev, devad, regnum);

	/* indirect C22 access */
	phy_mmd_start_indirect(phydev, devad, regnum);

	/* Read the content of the MMD's selected register */
	return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
}

/**
 * phy_write_mmd - Convenience function for writing a register
 * on an MMD on a given PHY.
 * @phydev: The phy_device struct
 * @devad: The MMD to read from
 * @regnum: The register on the MMD to read
 * @val: value to write to @regnum
 * @return: 0 for success or negative errno for failure
 */
static inline int phy_write_mmd(struct phy_device *phydev, int devad,
				int regnum, u16 val)
{
	struct phy_driver *drv = phydev->drv;

	if (regnum > (u16)~0 || devad > 32)
		return -EINVAL;

	/* driver-specific access */
	if (drv->write_mmd)
		return drv->write_mmd(phydev, devad, regnum, val);

	/* direct C45 / C22 access */
	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
	    devad == MDIO_DEVAD_NONE || !devad)
		return phy_write(phydev, devad, regnum, val);

	/* indirect C22 access */
	phy_mmd_start_indirect(phydev, devad, regnum);

	/* Write the data into MMD's selected register */
	return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
}

/**
 * phy_set_bits_mmd - Convenience function for setting bits in a register
 * on MMD
 * @phydev: the phy_device struct
 * @devad: the MMD containing register to modify
 * @regnum: register number to modify
 * @val: bits to set
 * @return: 0 for success or negative errno for failure
 */
static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
				   u32 regnum, u16 val)
{
	int value, ret;

	value = phy_read_mmd(phydev, devad, regnum);
	if (value < 0)
		return value;

	value |= val;

	ret = phy_write_mmd(phydev, devad, regnum, value);
	if (ret < 0)
		return ret;

	return 0;
}

/**
 * phy_clear_bits_mmd - Convenience function for clearing bits in a register
 * on MMD
 * @phydev: the phy_device struct
 * @devad: the MMD containing register to modify
 * @regnum: register number to modify
 * @val: bits to clear
 * @return: 0 for success or negative errno for failure
 */
static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
				     u32 regnum, u16 val)
{
	int value, ret;

	value = phy_read_mmd(phydev, devad, regnum);
	if (value < 0)
		return value;

	value &= ~val;

	ret = phy_write_mmd(phydev, devad, regnum, value);
	if (ret < 0)
		return ret;

	return 0;
}

#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;

/*
 * List all 10G interfaces here, the assumption being that PHYs on these
 * interfaces are C45
 */
static inline int is_10g_interface(phy_interface_t interface)
{
	return interface == PHY_INTERFACE_MODE_XGMII ||
	       interface == PHY_INTERFACE_MODE_USXGMII ||
	       interface == PHY_INTERFACE_MODE_XFI;
}

#endif

/**
 * phy_init() - Initializes the PHY drivers
 * This function registers all available PHY drivers
 *
 * @return: 0 if OK, -ve on error
 */
int phy_init(void);

/**
 * phy_reset() - Resets the specified PHY
 * Issues a reset of the PHY and waits for it to complete
 *
 * @phydev:	PHY to reset
 * @return: 0 if OK, -ve on error
 */
int phy_reset(struct phy_device *phydev);

/**
 * phy_find_by_mask() - Searches for a PHY on the specified MDIO bus
 * The function checks the PHY addresses flagged in phy_mask and returns a
 * phy_device pointer if it detects a PHY.
 * This function should only be called if just one PHY is expected to be present
 * in the set of addresses flagged in phy_mask.  If multiple PHYs are present,
 * it is undefined which of these PHYs is returned.
 *
 * @bus:	MII/MDIO bus to scan
 * @phy_mask:	bitmap of PYH addresses to scan
 * @interface:	type of MAC-PHY interface
 * @return: pointer to phy_device if a PHY is found, or NULL otherwise
 */
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
		phy_interface_t interface);

#ifdef CONFIG_PHY_FIXED

/**
 * fixed_phy_create() - create an unconnected fixed-link pseudo-PHY device
 * @node: OF node for the container of the fixed-link node
 *
 * Description: Creates a struct phy_device based on a fixed-link of_node
 * description. Can be used without phy_connect by drivers which do not expose
 * a UCLASS_ETH udevice.
 */
struct phy_device *fixed_phy_create(ofnode node);

#else

static inline struct phy_device *fixed_phy_create(ofnode node)
{
	return NULL;
}

#endif

#ifdef CONFIG_DM_ETH

/**
 * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
 * @phydev:	PHY device
 * @dev:	Ethernet device
 */
void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);

/**
 * phy_connect() - Creates a PHY device for the Ethernet interface
 * Creates a PHY device for the PHY at the given address, if one doesn't exist
 * already, and associates it with the Ethernet device.
 * The function may be called with addr <= 0, in this case addr value is ignored
 * and the bus is scanned to detect a PHY.  Scanning should only be used if only
 * one PHY is expected to be present on the MDIO bus, otherwise it is undefined
 * which PHY is returned.
 *
 * @bus:	MII/MDIO bus that hosts the PHY
 * @addr:	PHY address on MDIO bus
 * @dev:	Ethernet device to associate to the PHY
 * @interface:	type of MAC-PHY interface
 * @return: pointer to phy_device if a PHY is found, or NULL otherwise
 */
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct udevice *dev,
				phy_interface_t interface);

static inline ofnode phy_get_ofnode(struct phy_device *phydev)
{
	if (ofnode_valid(phydev->node))
		return phydev->node;
	else
		return dev_ofnode(phydev->dev);
}
#else

/**
 * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
 * @phydev:	PHY device
 * @dev:	Ethernet device
 */
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);

/**
 * phy_connect() - Creates a PHY device for the Ethernet interface
 * Creates a PHY device for the PHY at the given address, if one doesn't exist
 * already, and associates it with the Ethernet device.
 * The function may be called with addr <= 0, in this case addr value is ignored
 * and the bus is scanned to detect a PHY.  Scanning should only be used if only
 * one PHY is expected to be present on the MDIO bus, otherwise it is undefined
 * which PHY is returned.
 *
 * @bus:	MII/MDIO bus that hosts the PHY
 * @addr:	PHY address on MDIO bus
 * @dev:	Ethernet device to associate to the PHY
 * @interface:	type of MAC-PHY interface
 * @return: pointer to phy_device if a PHY is found, or NULL otherwise
 */
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct eth_device *dev,
				phy_interface_t interface);

static inline ofnode phy_get_ofnode(struct phy_device *phydev)
{
	return ofnode_null();
}
#endif
int phy_startup(struct phy_device *phydev);
int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int phy_set_supported(struct phy_device *phydev, u32 max_speed);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_restart_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
int genphy_parse_link(struct phy_device *phydev);
int genphy_config(struct phy_device *phydev);
int genphy_startup(struct phy_device *phydev);
int genphy_shutdown(struct phy_device *phydev);
int gen10g_config(struct phy_device *phydev);
int gen10g_startup(struct phy_device *phydev);
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);

int phy_b53_init(void);
int phy_mv88e61xx_init(void);
int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_cortina_init(void);
int phy_cortina_access_init(void);
int phy_davicom_init(void);
int phy_et1011c_init(void);
int phy_lxt_init(void);
int phy_marvell_init(void);
int phy_micrel_ksz8xxx_init(void);
int phy_micrel_ksz90x1_init(void);
int phy_meson_gxl_init(void);
int phy_natsemi_init(void);
int phy_realtek_init(void);
int phy_smsc_init(void);
int phy_teranetics_init(void);
int phy_ti_init(void);
int phy_vitesse_init(void);
int phy_xilinx_init(void);
int phy_mscc_init(void);
int phy_fixed_init(void);
int phy_ncsi_init(void);
int phy_xilinx_gmii2rgmii_init(void);

int board_phy_config(struct phy_device *phydev);
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);

/**
 * phy_get_interface_by_name() - Look up a PHY interface name
 *
 * @str:	PHY interface name, e.g. "mii"
 * @return: PHY_INTERFACE_MODE_... value, or -1 if not found
 */
int phy_get_interface_by_name(const char *str);

/**
 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
 * is RGMII (all variants)
 * @phydev: the phy_device struct
 * @return: true if MII bus is RGMII or false if it is not
 */
static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
{
	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
}

/**
 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
 * is SGMII (all variants)
 * @phydev: the phy_device struct
 * @return: true if MII bus is SGMII or false if it is not
 */
static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
{
	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
		phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
}

/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_CS4340  	0x13e51002
#define PHY_UID_CS4223  	0x03e57003
#define PHY_UID_TN2020		0x00a19410
#define PHY_UID_IN112525_S03	0x02107440

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
5f184715 AF	2	/*
5f184715 AF	3	* Copyright 2011 Freescale Semiconductor, Inc.
b21f87a3	4	* Andy Fleming <[email protected]>
5f184715	5	*
5f184715 AF	6	* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
	7	*/
	8
	9	#ifndef _PHY_H
	10	#define _PHY_H
	11
2a64ada7 SG	12	#include <log.h>
	13	#include <phy_interface.h>
	14	#include <dm/ofnode.h>
	15	#include <dm/read.h>
f2176515	16	#include <linux/errno.h>
5f184715 AF	17	#include <linux/list.h>
	18	#include <linux/mii.h>
	19	#include <linux/ethtool.h>
	20	#include <linux/mdio.h>
2a64ada7 SG	21
2a64ada7 SG	22	struct udevice;
5f184715	23
db40c1aa	24	#define PHY_FIXED_ID 0xa5a55a5a
f641a8ac SMJ	25	#define PHY_NCSI_ID 0xbeefcafe
f641a8ac SMJ	26
f41e588c SDPP	27	/*
	28	* There is no actual id for this.
	29	* This is just a dummy id for gmii2rgmmi converter.
	30	*/
	31	#define PHY_GMII2RGMII_ID 0x5a5a5a5a
db40c1aa	32
5f184715 AF	33	#define PHY_MAX_ADDR 32
5f184715 AF	34
ddcd1f30 SX	35	#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */
ddcd1f30 SX	36
4dae610b	37	#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg \| \
5f184715 AF	38	SUPPORTED_TP \| \
	39	SUPPORTED_MII)
	40
4dae610b FF	41	#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half \| \
	42	SUPPORTED_10baseT_Full)
	43
	44	#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half \| \
	45	SUPPORTED_100baseT_Full)
	46
	47	#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half \| \
5f184715 AF	48	SUPPORTED_1000baseT_Full)
5f184715 AF	49
4dae610b FF	50	#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES \| \
	51	PHY_100BT_FEATURES \| \
	52	PHY_DEFAULT_FEATURES)
	53
	54	#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES \| \
	55	PHY_1000BT_FEATURES)
	56
5f184715 AF	57	#define PHY_10G_FEATURES (PHY_GBIT_FEATURES \| \
	58	SUPPORTED_10000baseT_Full)
	59
4fb3f0c8	60	#ifndef PHY_ANEG_TIMEOUT
5f184715	61	#define PHY_ANEG_TIMEOUT 4000
4fb3f0c8	62	#endif
5f184715 AF	63
5f184715 AF	64
5f184715 AF	65	struct phy_device;
	66
	67	#define MDIO_NAME_LEN 32
	68
	69	struct mii_dev {
	70	struct list_head link;
	71	char name[MDIO_NAME_LEN];
	72	void *priv;
	73	int (read)(struct mii_dev bus, int addr, int devad, int reg);
	74	int (write)(struct mii_dev bus, int addr, int devad, int reg,
	75	u16 val);
	76	int (reset)(struct mii_dev bus);
	77	struct phy_device *phymap[PHY_MAX_ADDR];
	78	u32 phy_mask;
	79	};
	80
	81	/* struct phy_driver: a structure which defines PHY behavior
	82	*
	83	* uid will contain a number which represents the PHY. During
	84	* startup, the driver will poll the PHY to find out what its
	85	* UID--as defined by registers 2 and 3--is. The 32-bit result
	86	* gotten from the PHY will be masked to
	87	* discard any bits which may change based on revision numbers
	88	* unimportant to functionality
	89	*
	90	*/
	91	struct phy_driver {
	92	char *name;
	93	unsigned int uid;
	94	unsigned int mask;
	95	unsigned int mmds;
	96
	97	u32 features;
	98
	99	/* Called to do any driver startup necessities */
	100	/* Will be called during phy_connect */
	101	int (probe)(struct phy_device phydev);
	102
	103	/* Called to configure the PHY, and modify the controller
	104	* based on the results. Should be called after phy_connect */
	105	int (config)(struct phy_device phydev);
	106
	107	/* Called when starting up the controller */
	108	int (startup)(struct phy_device phydev);
	109
	110	/* Called when bringing down the controller */
	111	int (shutdown)(struct phy_device phydev);
	112
b71841b9 SB	113	int (readext)(struct phy_device phydev, int addr, int devad, int reg);
	114	int (writeext)(struct phy_device phydev, int addr, int devad, int reg,
	115	u16 val);
4f6746dc CC	116
	117	/* Phy specific driver override for reading a MMD register */
	118	int (read_mmd)(struct phy_device phydev, int devad, int reg);
	119
	120	/* Phy specific driver override for writing a MMD register */
	121	int (write_mmd)(struct phy_device phydev, int devad, int reg,
	122	u16 val);
	123
5f184715	124	struct list_head list;
d718b697 AM	125
	126	/* driver private data */
	127	ulong data;
5f184715 AF	128	};
	129
	130	struct phy_device {
	131	/* Information about the PHY type */
	132	/* And management functions */
	133	struct mii_dev *bus;
	134	struct phy_driver *drv;
	135	void *priv;
	136
c74c8e66 SG	137	#ifdef CONFIG_DM_ETH
c74c8e66 SG	138	struct udevice *dev;
eef0b8a9	139	ofnode node;
c74c8e66	140	#else
5f184715	141	struct eth_device *dev;
c74c8e66	142	#endif
5f184715 AF	143
	144	/* forced speed & duplex (no autoneg)
	145	* partner speed & duplex & pause (autoneg)
	146	*/
	147	int speed;
	148	int duplex;
	149
	150	/* The most recently read link state */
	151	int link;
	152	int port;
	153	phy_interface_t interface;
	154
	155	u32 advertising;
	156	u32 supported;
	157	u32 mmds;
	158
	159	int autoneg;
	160	int addr;
	161	int pause;
	162	int asym_pause;
	163	u32 phy_id;
b3eabd82	164	bool is_c45;
5f184715 AF	165	u32 flags;
	166	};
	167
f55a776c SX	168	struct fixed_link {
	169	int phy_id;
	170	int duplex;
	171	int link_speed;
	172	int pause;
	173	int asym_pause;
	174	};
	175
6325c8bc DM	176	/**
	177	* phy_read - Convenience function for reading a given PHY register
	178	* @phydev: the phy_device struct
	179	* @devad: The MMD to read from
	180	* @regnum: register number to read
	181	* @return: value for success or negative errno for failure
	182	*/
5f184715 AF	183	static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
	184	{
	185	struct mii_dev *bus = phydev->bus;
	186
e2ffeaa1 SMJ	187	if (!bus \|\| !bus->read) {
	188	debug("%s: No bus configured\n", __func__);
	189	return -1;
	190	}
	191
5f184715 AF	192	return bus->read(bus, phydev->addr, devad, regnum);
	193	}
	194
6325c8bc DM	195	/**
	196	* phy_write - Convenience function for writing a given PHY register
	197	* @phydev: the phy_device struct
	198	* @devad: The MMD to read from
	199	* @regnum: register number to write
	200	* @val: value to write to @regnum
	201	* @return: 0 for success or negative errno for failure
	202	*/
5f184715 AF	203	static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
	204	u16 val)
	205	{
	206	struct mii_dev *bus = phydev->bus;
	207
7def4e62	208	if (!bus \|\| !bus->write) {
e2ffeaa1 SMJ	209	debug("%s: No bus configured\n", __func__);
	210	return -1;
	211	}
	212
5f184715 AF	213	return bus->write(bus, phydev->addr, devad, regnum, val);
	214	}
	215
6325c8bc DM	216	/**
	217	* phy_mmd_start_indirect - Convenience function for writing MMD registers
	218	* @phydev: the phy_device struct
	219	* @devad: The MMD to read from
	220	* @regnum: register number to write
	221	* @return: None
	222	*/
4f6746dc CC	223	static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
	224	int regnum)
	225	{
	226	/* Write the desired MMD Devad */
	227	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);
	228
	229	/* Write the desired MMD register address */
	230	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);
	231
	232	/* Select the Function : DATA with no post increment */
	233	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL,
	234	(devad \| MII_MMD_CTRL_NOINCR));
	235	}
	236
6325c8bc DM	237	/**
	238	* phy_read_mmd - Convenience function for reading a register
	239	* from an MMD on a given PHY.
	240	* @phydev: The phy_device struct
	241	* @devad: The MMD to read from
	242	* @regnum: The register on the MMD to read
	243	* @return: Value for success or negative errno for failure
	244	*/
4f6746dc CC	245	static inline int phy_read_mmd(struct phy_device *phydev, int devad,
	246	int regnum)
	247	{
	248	struct phy_driver *drv = phydev->drv;
	249
	250	if (regnum > (u16)~0 \|\| devad > 32)
	251	return -EINVAL;
	252
	253	/* driver-specific access */
	254	if (drv->read_mmd)
	255	return drv->read_mmd(phydev, devad, regnum);
	256
	257	/* direct C45 / C22 access */
	258	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES \|\|
	259	devad == MDIO_DEVAD_NONE \|\| !devad)
	260	return phy_read(phydev, devad, regnum);
	261
	262	/* indirect C22 access */
	263	phy_mmd_start_indirect(phydev, devad, regnum);
	264
	265	/* Read the content of the MMD's selected register */
	266	return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
	267	}
	268
6325c8bc DM	269	/**
	270	* phy_write_mmd - Convenience function for writing a register
	271	* on an MMD on a given PHY.
	272	* @phydev: The phy_device struct
	273	* @devad: The MMD to read from
	274	* @regnum: The register on the MMD to read
	275	* @val: value to write to @regnum
	276	* @return: 0 for success or negative errno for failure
	277	*/
4f6746dc CC	278	static inline int phy_write_mmd(struct phy_device *phydev, int devad,
	279	int regnum, u16 val)
	280	{
	281	struct phy_driver *drv = phydev->drv;
	282
	283	if (regnum > (u16)~0 \|\| devad > 32)
	284	return -EINVAL;
	285
	286	/* driver-specific access */
	287	if (drv->write_mmd)
	288	return drv->write_mmd(phydev, devad, regnum, val);
	289
	290	/* direct C45 / C22 access */
	291	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES \|\|
	292	devad == MDIO_DEVAD_NONE \|\| !devad)
	293	return phy_write(phydev, devad, regnum, val);
	294
	295	/* indirect C22 access */
	296	phy_mmd_start_indirect(phydev, devad, regnum);
	297
	298	/* Write the data into MMD's selected register */
	299	return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
	300	}
	301
535247a9 DM	302	/**
	303	* phy_set_bits_mmd - Convenience function for setting bits in a register
	304	* on MMD
	305	* @phydev: the phy_device struct
	306	* @devad: the MMD containing register to modify
	307	* @regnum: register number to modify
	308	* @val: bits to set
	309	* @return: 0 for success or negative errno for failure
	310	*/
	311	static inline int phy_set_bits_mmd(struct phy_device *phydev, int devad,
	312	u32 regnum, u16 val)
	313	{
	314	int value, ret;
	315
	316	value = phy_read_mmd(phydev, devad, regnum);
	317	if (value < 0)
	318	return value;
	319
	320	value \|= val;
	321
	322	ret = phy_write_mmd(phydev, devad, regnum, value);
	323	if (ret < 0)
	324	return ret;
	325
	326	return 0;
	327	}
	328
	329	/**
	330	* phy_clear_bits_mmd - Convenience function for clearing bits in a register
	331	* on MMD
	332	* @phydev: the phy_device struct
	333	* @devad: the MMD containing register to modify
	334	* @regnum: register number to modify
	335	* @val: bits to clear
	336	* @return: 0 for success or negative errno for failure
	337	*/
	338	static inline int phy_clear_bits_mmd(struct phy_device *phydev, int devad,
	339	u32 regnum, u16 val)
	340	{
	341	int value, ret;
	342
	343	value = phy_read_mmd(phydev, devad, regnum);
	344	if (value < 0)
	345	return value;
	346
	347	value &= ~val;
	348
	349	ret = phy_write_mmd(phydev, devad, regnum, value);
	350	if (ret < 0)
	351	return ret;
	352
	353	return 0;
	354	}
	355
5f184715 AF	356	#ifdef CONFIG_PHYLIB_10G
	357	extern struct phy_driver gen10g_driver;
	358
9810489c AM	359	/*
	360	* List all 10G interfaces here, the assumption being that PHYs on these
	361	* interfaces are C45
	362	*/
5f184715 AF	363	static inline int is_10g_interface(phy_interface_t interface)
5f184715 AF	364	{
9810489c AM	365	return interface == PHY_INTERFACE_MODE_XGMII \|\|
	366	interface == PHY_INTERFACE_MODE_USXGMII \|\|
	367	interface == PHY_INTERFACE_MODE_XFI;
5f184715 AF	368	}
	369
	370	#endif
	371
c38ac289 AM	372	/**
c38ac289 AM	373	* phy_init() - Initializes the PHY drivers
c38ac289 AM	374	* This function registers all available PHY drivers
c38ac289 AM	375	*
ea756fb8	376	* @return: 0 if OK, -ve on error
c38ac289	377	*/
5f184715	378	int phy_init(void);
c38ac289 AM	379
	380	/**
	381	* phy_reset() - Resets the specified PHY
c38ac289 AM	382	* Issues a reset of the PHY and waits for it to complete
	383	*
	384	* @phydev: PHY to reset
ea756fb8	385	* @return: 0 if OK, -ve on error
c38ac289	386	*/
5f184715	387	int phy_reset(struct phy_device *phydev);
c38ac289 AM	388
	389	/**
	390	* phy_find_by_mask() - Searches for a PHY on the specified MDIO bus
c38ac289 AM	391	* The function checks the PHY addresses flagged in phy_mask and returns a
	392	* phy_device pointer if it detects a PHY.
	393	* This function should only be called if just one PHY is expected to be present
	394	* in the set of addresses flagged in phy_mask. If multiple PHYs are present,
	395	* it is undefined which of these PHYs is returned.
	396	*
	397	* @bus: MII/MDIO bus to scan
	398	* @phy_mask: bitmap of PYH addresses to scan
	399	* @interface: type of MAC-PHY interface
ea756fb8	400	* @return: pointer to phy_device if a PHY is found, or NULL otherwise
c38ac289	401	*/
1adb406b TK	402	struct phy_device phy_find_by_mask(struct mii_dev bus, unsigned phy_mask,
1adb406b TK	403	phy_interface_t interface);
c38ac289	404
d0781c95 VO	405	#ifdef CONFIG_PHY_FIXED
	406
	407	/**
	408	* fixed_phy_create() - create an unconnected fixed-link pseudo-PHY device
	409	* @node: OF node for the container of the fixed-link node
	410	*
	411	* Description: Creates a struct phy_device based on a fixed-link of_node
	412	* description. Can be used without phy_connect by drivers which do not expose
	413	* a UCLASS_ETH udevice.
	414	*/
	415	struct phy_device *fixed_phy_create(ofnode node);
	416
	417	#else
	418
	419	static inline struct phy_device *fixed_phy_create(ofnode node)
	420	{
	421	return NULL;
	422	}
	423
	424	#endif
	425
c74c8e66	426	#ifdef CONFIG_DM_ETH
c38ac289 AM	427
	428	/**
	429	* phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
	430	* @phydev: PHY device
	431	* @dev: Ethernet device
	432	*/
c74c8e66	433	void phy_connect_dev(struct phy_device phydev, struct udevice dev);
c38ac289 AM	434
	435	/**
	436	* phy_connect() - Creates a PHY device for the Ethernet interface
c38ac289 AM	437	* Creates a PHY device for the PHY at the given address, if one doesn't exist
	438	* already, and associates it with the Ethernet device.
	439	* The function may be called with addr <= 0, in this case addr value is ignored
	440	* and the bus is scanned to detect a PHY. Scanning should only be used if only
	441	* one PHY is expected to be present on the MDIO bus, otherwise it is undefined
	442	* which PHY is returned.
	443	*
	444	* @bus: MII/MDIO bus that hosts the PHY
	445	* @addr: PHY address on MDIO bus
	446	* @dev: Ethernet device to associate to the PHY
	447	* @interface: type of MAC-PHY interface
ea756fb8	448	* @return: pointer to phy_device if a PHY is found, or NULL otherwise
c38ac289	449	*/
c74c8e66 SG	450	struct phy_device phy_connect(struct mii_dev bus, int addr,
	451	struct udevice *dev,
	452	phy_interface_t interface);
c38ac289	453
eef0b8a9 GS	454	static inline ofnode phy_get_ofnode(struct phy_device *phydev)
	455	{
	456	if (ofnode_valid(phydev->node))
	457	return phydev->node;
	458	else
	459	return dev_ofnode(phydev->dev);
	460	}
c74c8e66	461	#else
c38ac289 AM	462
	463	/**
	464	* phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
	465	* @phydev: PHY device
	466	* @dev: Ethernet device
	467	*/
1adb406b	468	void phy_connect_dev(struct phy_device phydev, struct eth_device dev);
c38ac289 AM	469
	470	/**
	471	* phy_connect() - Creates a PHY device for the Ethernet interface
c38ac289 AM	472	* Creates a PHY device for the PHY at the given address, if one doesn't exist
	473	* already, and associates it with the Ethernet device.
	474	* The function may be called with addr <= 0, in this case addr value is ignored
	475	* and the bus is scanned to detect a PHY. Scanning should only be used if only
	476	* one PHY is expected to be present on the MDIO bus, otherwise it is undefined
	477	* which PHY is returned.
	478	*
	479	* @bus: MII/MDIO bus that hosts the PHY
	480	* @addr: PHY address on MDIO bus
	481	* @dev: Ethernet device to associate to the PHY
	482	* @interface: type of MAC-PHY interface
ea756fb8	483	* @return: pointer to phy_device if a PHY is found, or NULL otherwise
c38ac289	484	*/
5f184715 AF	485	struct phy_device phy_connect(struct mii_dev bus, int addr,
	486	struct eth_device *dev,
	487	phy_interface_t interface);
c38ac289	488
eef0b8a9 GS	489	static inline ofnode phy_get_ofnode(struct phy_device *phydev)
	490	{
	491	return ofnode_null();
	492	}
c74c8e66	493	#endif
5f184715 AF	494	int phy_startup(struct phy_device *phydev);
	495	int phy_config(struct phy_device *phydev);
	496	int phy_shutdown(struct phy_device *phydev);
	497	int phy_register(struct phy_driver *drv);
b18acb0a	498	int phy_set_supported(struct phy_device *phydev, u32 max_speed);
5f184715	499	int genphy_config_aneg(struct phy_device *phydev);
8682aba7	500	int genphy_restart_aneg(struct phy_device *phydev);
5f184715	501	int genphy_update_link(struct phy_device *phydev);
e2043f5c	502	int genphy_parse_link(struct phy_device *phydev);
5f184715 AF	503	int genphy_config(struct phy_device *phydev);
	504	int genphy_startup(struct phy_device *phydev);
	505	int genphy_shutdown(struct phy_device *phydev);
	506	int gen10g_config(struct phy_device *phydev);
	507	int gen10g_startup(struct phy_device *phydev);
	508	int gen10g_shutdown(struct phy_device *phydev);
	509	int gen10g_discover_mmds(struct phy_device *phydev);
	510
137963d7	511	int phy_b53_init(void);
24ae3961	512	int phy_mv88e61xx_init(void);
f7c38cf8	513	int phy_aquantia_init(void);
9082eeac AF	514	int phy_atheros_init(void);
9082eeac AF	515	int phy_broadcom_init(void);
9b18e519	516	int phy_cortina_init(void);
a70d7b01	517	int phy_cortina_access_init(void);
9082eeac	518	int phy_davicom_init(void);
f485c8a3	519	int phy_et1011c_init(void);
9082eeac AF	520	int phy_lxt_init(void);
9082eeac AF	521	int phy_marvell_init(void);
d397f7c4 AG	522	int phy_micrel_ksz8xxx_init(void);
d397f7c4 AG	523	int phy_micrel_ksz90x1_init(void);
8995a96d	524	int phy_meson_gxl_init(void);
9082eeac AF	525	int phy_natsemi_init(void);
9082eeac AF	526	int phy_realtek_init(void);
b6abf555	527	int phy_smsc_init(void);
9082eeac	528	int phy_teranetics_init(void);
721aed79	529	int phy_ti_init(void);
9082eeac	530	int phy_vitesse_init(void);
ed6fad3e	531	int phy_xilinx_init(void);
a5fd13ad	532	int phy_mscc_init(void);
db40c1aa	533	int phy_fixed_init(void);
e2ffeaa1	534	int phy_ncsi_init(void);
f41e588c	535	int phy_xilinx_gmii2rgmii_init(void);
a836626c	536
2fb63964	537	int board_phy_config(struct phy_device *phydev);
5707d5ff	538	int get_phy_id(struct mii_dev bus, int addr, int devad, u32 phy_id);
2fb63964	539
c74c8e66 SG	540	/**
	541	* phy_get_interface_by_name() - Look up a PHY interface name
	542	*
	543	* @str: PHY interface name, e.g. "mii"
ea756fb8	544	* @return: PHY_INTERFACE_MODE_... value, or -1 if not found
c74c8e66 SG	545	*/
	546	int phy_get_interface_by_name(const char *str);
	547
3ab72fe8 DM	548	/**
	549	* phy_interface_is_rgmii - Convenience function for testing if a PHY interface
	550	* is RGMII (all variants)
	551	* @phydev: the phy_device struct
ea756fb8	552	* @return: true if MII bus is RGMII or false if it is not
3ab72fe8 DM	553	*/
	554	static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
	555	{
	556	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
	557	phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
	558	}
	559
3c221af3 DM	560	/**
	561	* phy_interface_is_sgmii - Convenience function for testing if a PHY interface
	562	* is SGMII (all variants)
	563	* @phydev: the phy_device struct
ea756fb8	564	* @return: true if MII bus is SGMII or false if it is not
3c221af3 DM	565	*/
	566	static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
	567	{
	568	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
	569	phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
	570	}
	571
a836626c	572	/* PHY UIDs for various PHYs that are referenced in external code */
1ddcf5ed PJ	573	#define PHY_UID_CS4340 0x13e51002
	574	#define PHY_UID_CS4223 0x03e57003
	575	#define PHY_UID_TN2020 0x00a19410
	576	#define PHY_UID_IN112525_S03 0x02107440
a836626c	577
5f184715	578	#endif