[J-u-boot.git] / include / phy.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 *	Andy Fleming <[email protected]>
 *
 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
 */

#ifndef _PHY_H
#define _PHY_H

#include <linux/list.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>
#include <phy_interface.h>

#define PHY_FIXED_ID		0xa5a55a5a

#define PHY_MAX_ADDR 32

#define PHY_FLAG_BROKEN_RESET	(1 << 0) /* soft reset not supported */

#define PHY_DEFAULT_FEATURES	(SUPPORTED_Autoneg | \
				 SUPPORTED_TP | \
				 SUPPORTED_MII)

#define PHY_10BT_FEATURES	(SUPPORTED_10baseT_Half | \
				 SUPPORTED_10baseT_Full)

#define PHY_100BT_FEATURES	(SUPPORTED_100baseT_Half | \
				 SUPPORTED_100baseT_Full)

#define PHY_1000BT_FEATURES	(SUPPORTED_1000baseT_Half | \
				 SUPPORTED_1000baseT_Full)

#define PHY_BASIC_FEATURES	(PHY_10BT_FEATURES | \
				 PHY_100BT_FEATURES | \
				 PHY_DEFAULT_FEATURES)

#define PHY_GBIT_FEATURES	(PHY_BASIC_FEATURES | \
				 PHY_1000BT_FEATURES)

#define PHY_10G_FEATURES	(PHY_GBIT_FEATURES | \
				SUPPORTED_10000baseT_Full)

#ifndef PHY_ANEG_TIMEOUT
#define PHY_ANEG_TIMEOUT	4000
#endif


struct phy_device;

#define MDIO_NAME_LEN 32

struct mii_dev {
	struct list_head link;
	char name[MDIO_NAME_LEN];
	void *priv;
	int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
	int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
			u16 val);
	int (*reset)(struct mii_dev *bus);
	struct phy_device *phymap[PHY_MAX_ADDR];
	u32 phy_mask;
};

/* struct phy_driver: a structure which defines PHY behavior
 *
 * uid will contain a number which represents the PHY.  During
 * startup, the driver will poll the PHY to find out what its
 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 * gotten from the PHY will be masked to
 * discard any bits which may change based on revision numbers
 * unimportant to functionality
 *
 */
struct phy_driver {
	char *name;
	unsigned int uid;
	unsigned int mask;
	unsigned int mmds;

	u32 features;

	/* Called to do any driver startup necessities */
	/* Will be called during phy_connect */
	int (*probe)(struct phy_device *phydev);

	/* Called to configure the PHY, and modify the controller
	 * based on the results.  Should be called after phy_connect */
	int (*config)(struct phy_device *phydev);

	/* Called when starting up the controller */
	int (*startup)(struct phy_device *phydev);

	/* Called when bringing down the controller */
	int (*shutdown)(struct phy_device *phydev);

	int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
	int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
			u16 val);
	struct list_head list;
};

struct phy_device {
	/* Information about the PHY type */
	/* And management functions */
	struct mii_dev *bus;
	struct phy_driver *drv;
	void *priv;

#ifdef CONFIG_DM_ETH
	struct udevice *dev;
#else
	struct eth_device *dev;
#endif

	/* forced speed & duplex (no autoneg)
	 * partner speed & duplex & pause (autoneg)
	 */
	int speed;
	int duplex;

	/* The most recently read link state */
	int link;
	int port;
	phy_interface_t interface;

	u32 advertising;
	u32 supported;
	u32 mmds;

	int autoneg;
	int addr;
	int pause;
	int asym_pause;
	u32 phy_id;
	u32 flags;
};

struct fixed_link {
	int phy_id;
	int duplex;
	int link_speed;
	int pause;
	int asym_pause;
};

static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
	struct mii_dev *bus = phydev->bus;

	return bus->read(bus, phydev->addr, devad, regnum);
}

static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
			u16 val)
{
	struct mii_dev *bus = phydev->bus;

	return bus->write(bus, phydev->addr, devad, regnum, val);
}

#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;

/* For now, XGMII is the only 10G interface */
static inline int is_10g_interface(phy_interface_t interface)
{
	return interface == PHY_INTERFACE_MODE_XGMII;
}

#endif

int phy_init(void);
int phy_reset(struct phy_device *phydev);
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
		phy_interface_t interface);
#ifdef CONFIG_DM_ETH
void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct udevice *dev,
				phy_interface_t interface);
#else
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct eth_device *dev,
				phy_interface_t interface);
#endif
int phy_startup(struct phy_device *phydev);
int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int phy_set_supported(struct phy_device *phydev, u32 max_speed);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_restart_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
int genphy_parse_link(struct phy_device *phydev);
int genphy_config(struct phy_device *phydev);
int genphy_startup(struct phy_device *phydev);
int genphy_shutdown(struct phy_device *phydev);
int gen10g_config(struct phy_device *phydev);
int gen10g_startup(struct phy_device *phydev);
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);

int phy_b53_init(void);
int phy_mv88e61xx_init(void);
int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_cortina_init(void);
int phy_davicom_init(void);
int phy_et1011c_init(void);
int phy_lxt_init(void);
int phy_marvell_init(void);
int phy_micrel_ksz8xxx_init(void);
int phy_micrel_ksz90x1_init(void);
int phy_meson_gxl_init(void);
int phy_natsemi_init(void);
int phy_realtek_init(void);
int phy_smsc_init(void);
int phy_teranetics_init(void);
int phy_ti_init(void);
int phy_vitesse_init(void);
int phy_xilinx_init(void);
int phy_mscc_init(void);
int phy_fixed_init(void);

int board_phy_config(struct phy_device *phydev);
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);

/**
 * phy_get_interface_by_name() - Look up a PHY interface name
 *
 * @str:	PHY interface name, e.g. "mii"
 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
 */
int phy_get_interface_by_name(const char *str);

/**
 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
 * is RGMII (all variants)
 * @phydev: the phy_device struct
 */
static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
{
	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
}

/**
 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
 * is SGMII (all variants)
 * @phydev: the phy_device struct
 */
static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
{
	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
		phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
}

/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_CS4340  0x13e51002
#define PHY_UID_CS4223  0x03e57003
#define PHY_UID_TN2020	0x00a19410

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
5f184715 AF	2	/*
5f184715 AF	3	* Copyright 2011 Freescale Semiconductor, Inc.
b21f87a3	4	* Andy Fleming <[email protected]>
5f184715	5	*
5f184715 AF	6	* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
	7	*/
	8
	9	#ifndef _PHY_H
	10	#define _PHY_H
	11
	12	#include <linux/list.h>
	13	#include <linux/mii.h>
	14	#include <linux/ethtool.h>
	15	#include <linux/mdio.h>
f070b1a2	16	#include <phy_interface.h>
5f184715	17
db40c1aa HS	18	#define PHY_FIXED_ID 0xa5a55a5a
db40c1aa HS	19
5f184715 AF	20	#define PHY_MAX_ADDR 32
5f184715 AF	21
ddcd1f30 SX	22	#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */
ddcd1f30 SX	23
4dae610b	24	#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg \| \
5f184715 AF	25	SUPPORTED_TP \| \
	26	SUPPORTED_MII)
	27
4dae610b FF	28	#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half \| \
	29	SUPPORTED_10baseT_Full)
	30
	31	#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half \| \
	32	SUPPORTED_100baseT_Full)
	33
	34	#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half \| \
5f184715 AF	35	SUPPORTED_1000baseT_Full)
5f184715 AF	36
4dae610b FF	37	#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES \| \
	38	PHY_100BT_FEATURES \| \
	39	PHY_DEFAULT_FEATURES)
	40
	41	#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES \| \
	42	PHY_1000BT_FEATURES)
	43
5f184715 AF	44	#define PHY_10G_FEATURES (PHY_GBIT_FEATURES \| \
	45	SUPPORTED_10000baseT_Full)
	46
4fb3f0c8	47	#ifndef PHY_ANEG_TIMEOUT
5f184715	48	#define PHY_ANEG_TIMEOUT 4000
4fb3f0c8	49	#endif
5f184715 AF	50
5f184715 AF	51
5f184715 AF	52	struct phy_device;
	53
	54	#define MDIO_NAME_LEN 32
	55
	56	struct mii_dev {
	57	struct list_head link;
	58	char name[MDIO_NAME_LEN];
	59	void *priv;
	60	int (read)(struct mii_dev bus, int addr, int devad, int reg);
	61	int (write)(struct mii_dev bus, int addr, int devad, int reg,
	62	u16 val);
	63	int (reset)(struct mii_dev bus);
	64	struct phy_device *phymap[PHY_MAX_ADDR];
	65	u32 phy_mask;
	66	};
	67
	68	/* struct phy_driver: a structure which defines PHY behavior
	69	*
	70	* uid will contain a number which represents the PHY. During
	71	* startup, the driver will poll the PHY to find out what its
	72	* UID--as defined by registers 2 and 3--is. The 32-bit result
	73	* gotten from the PHY will be masked to
	74	* discard any bits which may change based on revision numbers
	75	* unimportant to functionality
	76	*
	77	*/
	78	struct phy_driver {
	79	char *name;
	80	unsigned int uid;
	81	unsigned int mask;
	82	unsigned int mmds;
	83
	84	u32 features;
	85
	86	/* Called to do any driver startup necessities */
	87	/* Will be called during phy_connect */
	88	int (probe)(struct phy_device phydev);
	89
	90	/* Called to configure the PHY, and modify the controller
	91	* based on the results. Should be called after phy_connect */
	92	int (config)(struct phy_device phydev);
	93
	94	/* Called when starting up the controller */
	95	int (startup)(struct phy_device phydev);
	96
	97	/* Called when bringing down the controller */
	98	int (shutdown)(struct phy_device phydev);
	99
b71841b9 SB	100	int (readext)(struct phy_device phydev, int addr, int devad, int reg);
	101	int (writeext)(struct phy_device phydev, int addr, int devad, int reg,
	102	u16 val);
5f184715 AF	103	struct list_head list;
	104	};
	105
	106	struct phy_device {
	107	/* Information about the PHY type */
	108	/* And management functions */
	109	struct mii_dev *bus;
	110	struct phy_driver *drv;
	111	void *priv;
	112
c74c8e66 SG	113	#ifdef CONFIG_DM_ETH
	114	struct udevice *dev;
	115	#else
5f184715	116	struct eth_device *dev;
c74c8e66	117	#endif
5f184715 AF	118
	119	/* forced speed & duplex (no autoneg)
	120	* partner speed & duplex & pause (autoneg)
	121	*/
	122	int speed;
	123	int duplex;
	124
	125	/* The most recently read link state */
	126	int link;
	127	int port;
	128	phy_interface_t interface;
	129
	130	u32 advertising;
	131	u32 supported;
	132	u32 mmds;
	133
	134	int autoneg;
	135	int addr;
	136	int pause;
	137	int asym_pause;
	138	u32 phy_id;
	139	u32 flags;
	140	};
	141
f55a776c SX	142	struct fixed_link {
	143	int phy_id;
	144	int duplex;
	145	int link_speed;
	146	int pause;
	147	int asym_pause;
	148	};
	149
5f184715 AF	150	static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
	151	{
	152	struct mii_dev *bus = phydev->bus;
	153
	154	return bus->read(bus, phydev->addr, devad, regnum);
	155	}
	156
	157	static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
	158	u16 val)
	159	{
	160	struct mii_dev *bus = phydev->bus;
	161
	162	return bus->write(bus, phydev->addr, devad, regnum, val);
	163	}
	164
	165	#ifdef CONFIG_PHYLIB_10G
	166	extern struct phy_driver gen10g_driver;
	167
	168	/* For now, XGMII is the only 10G interface */
	169	static inline int is_10g_interface(phy_interface_t interface)
	170	{
	171	return interface == PHY_INTERFACE_MODE_XGMII;
	172	}
	173
	174	#endif
	175
	176	int phy_init(void);
	177	int phy_reset(struct phy_device *phydev);
1adb406b TK	178	struct phy_device phy_find_by_mask(struct mii_dev bus, unsigned phy_mask,
1adb406b TK	179	phy_interface_t interface);
c74c8e66 SG	180	#ifdef CONFIG_DM_ETH
	181	void phy_connect_dev(struct phy_device phydev, struct udevice dev);
	182	struct phy_device phy_connect(struct mii_dev bus, int addr,
	183	struct udevice *dev,
	184	phy_interface_t interface);
	185	#else
1adb406b	186	void phy_connect_dev(struct phy_device phydev, struct eth_device dev);
5f184715 AF	187	struct phy_device phy_connect(struct mii_dev bus, int addr,
	188	struct eth_device *dev,
	189	phy_interface_t interface);
c74c8e66	190	#endif
5f184715 AF	191	int phy_startup(struct phy_device *phydev);
	192	int phy_config(struct phy_device *phydev);
	193	int phy_shutdown(struct phy_device *phydev);
	194	int phy_register(struct phy_driver *drv);
b18acb0a	195	int phy_set_supported(struct phy_device *phydev, u32 max_speed);
5f184715	196	int genphy_config_aneg(struct phy_device *phydev);
8682aba7	197	int genphy_restart_aneg(struct phy_device *phydev);
5f184715	198	int genphy_update_link(struct phy_device *phydev);
e2043f5c	199	int genphy_parse_link(struct phy_device *phydev);
5f184715 AF	200	int genphy_config(struct phy_device *phydev);
	201	int genphy_startup(struct phy_device *phydev);
	202	int genphy_shutdown(struct phy_device *phydev);
	203	int gen10g_config(struct phy_device *phydev);
	204	int gen10g_startup(struct phy_device *phydev);
	205	int gen10g_shutdown(struct phy_device *phydev);
	206	int gen10g_discover_mmds(struct phy_device *phydev);
	207
137963d7	208	int phy_b53_init(void);
24ae3961	209	int phy_mv88e61xx_init(void);
f7c38cf8	210	int phy_aquantia_init(void);
9082eeac AF	211	int phy_atheros_init(void);
9082eeac AF	212	int phy_broadcom_init(void);
9b18e519	213	int phy_cortina_init(void);
9082eeac	214	int phy_davicom_init(void);
f485c8a3	215	int phy_et1011c_init(void);
9082eeac AF	216	int phy_lxt_init(void);
9082eeac AF	217	int phy_marvell_init(void);
d397f7c4 AG	218	int phy_micrel_ksz8xxx_init(void);
d397f7c4 AG	219	int phy_micrel_ksz90x1_init(void);
8995a96d	220	int phy_meson_gxl_init(void);
9082eeac AF	221	int phy_natsemi_init(void);
9082eeac AF	222	int phy_realtek_init(void);
b6abf555	223	int phy_smsc_init(void);
9082eeac	224	int phy_teranetics_init(void);
721aed79	225	int phy_ti_init(void);
9082eeac	226	int phy_vitesse_init(void);
ed6fad3e	227	int phy_xilinx_init(void);
a5fd13ad	228	int phy_mscc_init(void);
db40c1aa	229	int phy_fixed_init(void);
a836626c	230
2fb63964	231	int board_phy_config(struct phy_device *phydev);
5707d5ff	232	int get_phy_id(struct mii_dev bus, int addr, int devad, u32 phy_id);
2fb63964	233
c74c8e66 SG	234	/**
	235	* phy_get_interface_by_name() - Look up a PHY interface name
	236	*
	237	* @str: PHY interface name, e.g. "mii"
	238	* @return PHY_INTERFACE_MODE_... value, or -1 if not found
	239	*/
	240	int phy_get_interface_by_name(const char *str);
	241
3ab72fe8 DM	242	/**
	243	* phy_interface_is_rgmii - Convenience function for testing if a PHY interface
	244	* is RGMII (all variants)
	245	* @phydev: the phy_device struct
	246	*/
	247	static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
	248	{
	249	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
	250	phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
	251	}
	252
3c221af3 DM	253	/**
	254	* phy_interface_is_sgmii - Convenience function for testing if a PHY interface
	255	* is SGMII (all variants)
	256	* @phydev: the phy_device struct
	257	*/
	258	static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
	259	{
	260	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
	261	phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
	262	}
	263
a836626c	264	/* PHY UIDs for various PHYs that are referenced in external code */
9b18e519	265	#define PHY_UID_CS4340 0x13e51002
552e7c57	266	#define PHY_UID_CS4223 0x03e57003
a836626c TT	267	#define PHY_UID_TN2020 0x00a19410
a836626c TT	268
5f184715	269	#endif