[J-u-boot.git] / include / phy.h

/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 *	Andy Fleming <[email protected]>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
 */

#ifndef _PHY_H
#define _PHY_H

#include <linux/list.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>

#define PHY_MAX_ADDR 32

#define PHY_BASIC_FEATURES	(SUPPORTED_10baseT_Half | \
				 SUPPORTED_10baseT_Full | \
				 SUPPORTED_100baseT_Half | \
				 SUPPORTED_100baseT_Full | \
				 SUPPORTED_Autoneg | \
				 SUPPORTED_TP | \
				 SUPPORTED_MII)

#define PHY_GBIT_FEATURES	(PHY_BASIC_FEATURES | \
				 SUPPORTED_1000baseT_Half | \
				 SUPPORTED_1000baseT_Full)

#define PHY_10G_FEATURES	(PHY_GBIT_FEATURES | \
				SUPPORTED_10000baseT_Full)

#define PHY_ANEG_TIMEOUT	4000


typedef enum {
	PHY_INTERFACE_MODE_MII,
	PHY_INTERFACE_MODE_GMII,
	PHY_INTERFACE_MODE_SGMII,
	PHY_INTERFACE_MODE_TBI,
	PHY_INTERFACE_MODE_RMII,
	PHY_INTERFACE_MODE_RGMII,
	PHY_INTERFACE_MODE_RGMII_ID,
	PHY_INTERFACE_MODE_RGMII_RXID,
	PHY_INTERFACE_MODE_RGMII_TXID,
	PHY_INTERFACE_MODE_RTBI,
	PHY_INTERFACE_MODE_XGMII,
	PHY_INTERFACE_MODE_NONE	/* Must be last */
} phy_interface_t;

static const char *phy_interface_strings[] = {
	[PHY_INTERFACE_MODE_MII]		= "mii",
	[PHY_INTERFACE_MODE_GMII]		= "gmii",
	[PHY_INTERFACE_MODE_SGMII]		= "sgmii",
	[PHY_INTERFACE_MODE_TBI]		= "tbi",
	[PHY_INTERFACE_MODE_RMII]		= "rmii",
	[PHY_INTERFACE_MODE_RGMII]		= "rgmii",
	[PHY_INTERFACE_MODE_RGMII_ID]		= "rgmii-id",
	[PHY_INTERFACE_MODE_RGMII_RXID]		= "rgmii-rxid",
	[PHY_INTERFACE_MODE_RGMII_TXID]		= "rgmii-txid",
	[PHY_INTERFACE_MODE_RTBI]		= "rtbi",
	[PHY_INTERFACE_MODE_XGMII]		= "xgmii",
	[PHY_INTERFACE_MODE_NONE]		= "",
};

static inline const char *phy_string_for_interface(phy_interface_t i)
{
	/* Default to unknown */
	if (i > PHY_INTERFACE_MODE_NONE)
		i = PHY_INTERFACE_MODE_NONE;

	return phy_interface_strings[i];
}


struct phy_device;

#define MDIO_NAME_LEN 32

struct mii_dev {
	struct list_head link;
	char name[MDIO_NAME_LEN];
	void *priv;
	int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
	int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
			u16 val);
	int (*reset)(struct mii_dev *bus);
	struct phy_device *phymap[PHY_MAX_ADDR];
	u32 phy_mask;
};

/* struct phy_driver: a structure which defines PHY behavior
 *
 * uid will contain a number which represents the PHY.  During
 * startup, the driver will poll the PHY to find out what its
 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 * gotten from the PHY will be masked to
 * discard any bits which may change based on revision numbers
 * unimportant to functionality
 *
 */
struct phy_driver {
	char *name;
	unsigned int uid;
	unsigned int mask;
	unsigned int mmds;

	u32 features;

	/* Called to do any driver startup necessities */
	/* Will be called during phy_connect */
	int (*probe)(struct phy_device *phydev);

	/* Called to configure the PHY, and modify the controller
	 * based on the results.  Should be called after phy_connect */
	int (*config)(struct phy_device *phydev);

	/* Called when starting up the controller */
	int (*startup)(struct phy_device *phydev);

	/* Called when bringing down the controller */
	int (*shutdown)(struct phy_device *phydev);

	struct list_head list;
};

struct phy_device {
	/* Information about the PHY type */
	/* And management functions */
	struct mii_dev *bus;
	struct phy_driver *drv;
	void *priv;

	struct eth_device *dev;

	/* forced speed & duplex (no autoneg)
	 * partner speed & duplex & pause (autoneg)
	 */
	int speed;
	int duplex;

	/* The most recently read link state */
	int link;
	int port;
	phy_interface_t interface;

	u32 advertising;
	u32 supported;
	u32 mmds;

	int autoneg;
	int addr;
	int pause;
	int asym_pause;
	u32 phy_id;
	u32 flags;
};

static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
	struct mii_dev *bus = phydev->bus;

	return bus->read(bus, phydev->addr, devad, regnum);
}

static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
			u16 val)
{
	struct mii_dev *bus = phydev->bus;

	return bus->write(bus, phydev->addr, devad, regnum, val);
}

#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;

/* For now, XGMII is the only 10G interface */
static inline int is_10g_interface(phy_interface_t interface)
{
	return interface == PHY_INTERFACE_MODE_XGMII;
}

#endif

int phy_init(void);
int phy_reset(struct phy_device *phydev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct eth_device *dev,
				phy_interface_t interface);
int phy_startup(struct phy_device *phydev);
int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
int genphy_config(struct phy_device *phydev);
int genphy_startup(struct phy_device *phydev);
int genphy_shutdown(struct phy_device *phydev);
int gen10g_config(struct phy_device *phydev);
int gen10g_startup(struct phy_device *phydev);
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);

int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_davicom_init(void);
int phy_lxt_init(void);
int phy_marvell_init(void);
int phy_micrel_init(void);
int phy_natsemi_init(void);
int phy_realtek_init(void);
int phy_teranetics_init(void);
int phy_vitesse_init(void);

/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_TN2020	0x00a19410

#endif
Commit	Line	Data
5f184715 AF	1	/*
	2	* Copyright 2011 Freescale Semiconductor, Inc.
	3	* Andy Fleming <[email protected]>
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	* MA 02111-1307 USA
	19	*
	20	* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
	21	*/
	22
	23	#ifndef _PHY_H
	24	#define _PHY_H
	25
	26	#include <linux/list.h>
	27	#include <linux/mii.h>
	28	#include <linux/ethtool.h>
	29	#include <linux/mdio.h>
	30
	31	#define PHY_MAX_ADDR 32
	32
	33	#define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half \| \
	34	SUPPORTED_10baseT_Full \| \
	35	SUPPORTED_100baseT_Half \| \
	36	SUPPORTED_100baseT_Full \| \
	37	SUPPORTED_Autoneg \| \
	38	SUPPORTED_TP \| \
	39	SUPPORTED_MII)
	40
	41	#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES \| \
	42	SUPPORTED_1000baseT_Half \| \
	43	SUPPORTED_1000baseT_Full)
	44
	45	#define PHY_10G_FEATURES (PHY_GBIT_FEATURES \| \
	46	SUPPORTED_10000baseT_Full)
	47
	48	#define PHY_ANEG_TIMEOUT 4000
	49
	50
	51	typedef enum {
	52	PHY_INTERFACE_MODE_MII,
	53	PHY_INTERFACE_MODE_GMII,
	54	PHY_INTERFACE_MODE_SGMII,
	55	PHY_INTERFACE_MODE_TBI,
	56	PHY_INTERFACE_MODE_RMII,
	57	PHY_INTERFACE_MODE_RGMII,
	58	PHY_INTERFACE_MODE_RGMII_ID,
	59	PHY_INTERFACE_MODE_RGMII_RXID,
	60	PHY_INTERFACE_MODE_RGMII_TXID,
	61	PHY_INTERFACE_MODE_RTBI,
	62	PHY_INTERFACE_MODE_XGMII,
	63	PHY_INTERFACE_MODE_NONE /* Must be last */
	64	} phy_interface_t;
65
66	static const char *phy_interface_strings[] = {
67	[PHY_INTERFACE_MODE_MII] = "mii",
68	[PHY_INTERFACE_MODE_GMII] = "gmii",
69	[PHY_INTERFACE_MODE_SGMII] = "sgmii",
70	[PHY_INTERFACE_MODE_TBI] = "tbi",
71	[PHY_INTERFACE_MODE_RMII] = "rmii",
72	[PHY_INTERFACE_MODE_RGMII] = "rgmii",
73	[PHY_INTERFACE_MODE_RGMII_ID] = "rgmii-id",
74	[PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
75	[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
76	[PHY_INTERFACE_MODE_RTBI] = "rtbi",
77	[PHY_INTERFACE_MODE_XGMII] = "xgmii",
78	[PHY_INTERFACE_MODE_NONE] = "",
79	};
80
81	static inline const char *phy_string_for_interface(phy_interface_t i)
82	{
83	/* Default to unknown */
84	if (i > PHY_INTERFACE_MODE_NONE)
85	i = PHY_INTERFACE_MODE_NONE;
86
87	return phy_interface_strings[i];
88	}
89
90
91	struct phy_device;
92
93	#define MDIO_NAME_LEN 32
94
95	struct mii_dev {
96	struct list_head link;
97	char name[MDIO_NAME_LEN];
98	void *priv;
99	int (read)(struct mii_dev bus, int addr, int devad, int reg);
100	int (write)(struct mii_dev bus, int addr, int devad, int reg,
101	u16 val);
102	int (reset)(struct mii_dev bus);
103	struct phy_device *phymap[PHY_MAX_ADDR];
104	u32 phy_mask;
105	};
106
107	/* struct phy_driver: a structure which defines PHY behavior
108	*
109	* uid will contain a number which represents the PHY. During
110	* startup, the driver will poll the PHY to find out what its
111	* UID--as defined by registers 2 and 3--is. The 32-bit result
112	* gotten from the PHY will be masked to
113	* discard any bits which may change based on revision numbers
114	* unimportant to functionality
115	*
116	*/
117	struct phy_driver {
118	char *name;
119	unsigned int uid;
120	unsigned int mask;
121	unsigned int mmds;
122
123	u32 features;
124
125	/* Called to do any driver startup necessities */
126	/* Will be called during phy_connect */
127	int (probe)(struct phy_device phydev);
128
129	/* Called to configure the PHY, and modify the controller
130	* based on the results. Should be called after phy_connect */
131	int (config)(struct phy_device phydev);
132
133	/* Called when starting up the controller */
134	int (startup)(struct phy_device phydev);
135
136	/* Called when bringing down the controller */
137	int (shutdown)(struct phy_device phydev);
138
139	struct list_head list;
140	};
141
142	struct phy_device {
143	/* Information about the PHY type */
144	/* And management functions */
145	struct mii_dev *bus;
146	struct phy_driver *drv;
147	void *priv;
148
149	struct eth_device *dev;
150
151	/* forced speed & duplex (no autoneg)
152	* partner speed & duplex & pause (autoneg)
153	*/
154	int speed;
155	int duplex;
156
157	/* The most recently read link state */
158	int link;
159	int port;
160	phy_interface_t interface;
161
162	u32 advertising;
163	u32 supported;
164	u32 mmds;
165
166	int autoneg;
167	int addr;
168	int pause;
169	int asym_pause;
170	u32 phy_id;
171	u32 flags;
172	};
173
174	static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
175	{
176	struct mii_dev *bus = phydev->bus;
177
178	return bus->read(bus, phydev->addr, devad, regnum);
179	}
180
181	static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
182	u16 val)
183	{
184	struct mii_dev *bus = phydev->bus;
185
186	return bus->write(bus, phydev->addr, devad, regnum, val);
187	}
188
189	#ifdef CONFIG_PHYLIB_10G
190	extern struct phy_driver gen10g_driver;
191
192	/* For now, XGMII is the only 10G interface */
193	static inline int is_10g_interface(phy_interface_t interface)
194	{
195	return interface == PHY_INTERFACE_MODE_XGMII;
196	}
197
198	#endif
199
200	int phy_init(void);
201	int phy_reset(struct phy_device *phydev);
202	struct phy_device phy_connect(struct mii_dev bus, int addr,
203	struct eth_device *dev,
204	phy_interface_t interface);
205	int phy_startup(struct phy_device *phydev);
206	int phy_config(struct phy_device *phydev);
207	int phy_shutdown(struct phy_device *phydev);
208	int phy_register(struct phy_driver *drv);
209	int genphy_config_aneg(struct phy_device *phydev);
210	int genphy_update_link(struct phy_device *phydev);
211	int genphy_config(struct phy_device *phydev);
212	int genphy_startup(struct phy_device *phydev);
213	int genphy_shutdown(struct phy_device *phydev);
214	int gen10g_config(struct phy_device *phydev);
215	int gen10g_startup(struct phy_device *phydev);
216	int gen10g_shutdown(struct phy_device *phydev);
217	int gen10g_discover_mmds(struct phy_device *phydev);
218
9082eeac AF	219	int phy_atheros_init(void);
	220	int phy_broadcom_init(void);
	221	int phy_davicom_init(void);
	222	int phy_lxt_init(void);
	223	int phy_marvell_init(void);
	224	int phy_micrel_init(void);
	225	int phy_natsemi_init(void);
	226	int phy_realtek_init(void);
	227	int phy_teranetics_init(void);
	228	int phy_vitesse_init(void);
a836626c TT	229
	230	/* PHY UIDs for various PHYs that are referenced in external code */
	231	#define PHY_UID_TN2020 0x00a19410
	232
5f184715	233	#endif