[J-u-boot.git] / include / phy.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2011 Freescale Semiconductor, Inc.
 *	Andy Fleming <[email protected]>
 *
 * This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
 */

#ifndef _PHY_H
#define _PHY_H

#include <dm.h>
#include <linux/list.h>
#include <linux/mii.h>
#include <linux/ethtool.h>
#include <linux/mdio.h>
#include <phy_interface.h>

#define PHY_FIXED_ID		0xa5a55a5a
/*
 * There is no actual id for this.
 * This is just a dummy id for gmii2rgmmi converter.
 */
#define PHY_GMII2RGMII_ID	0x5a5a5a5a

#define PHY_MAX_ADDR 32

#define PHY_FLAG_BROKEN_RESET	(1 << 0) /* soft reset not supported */

#define PHY_DEFAULT_FEATURES	(SUPPORTED_Autoneg | \
				 SUPPORTED_TP | \
				 SUPPORTED_MII)

#define PHY_10BT_FEATURES	(SUPPORTED_10baseT_Half | \
				 SUPPORTED_10baseT_Full)

#define PHY_100BT_FEATURES	(SUPPORTED_100baseT_Half | \
				 SUPPORTED_100baseT_Full)

#define PHY_1000BT_FEATURES	(SUPPORTED_1000baseT_Half | \
				 SUPPORTED_1000baseT_Full)

#define PHY_BASIC_FEATURES	(PHY_10BT_FEATURES | \
				 PHY_100BT_FEATURES | \
				 PHY_DEFAULT_FEATURES)

#define PHY_GBIT_FEATURES	(PHY_BASIC_FEATURES | \
				 PHY_1000BT_FEATURES)

#define PHY_10G_FEATURES	(PHY_GBIT_FEATURES | \
				SUPPORTED_10000baseT_Full)

#ifndef PHY_ANEG_TIMEOUT
#define PHY_ANEG_TIMEOUT	4000
#endif


struct phy_device;

#define MDIO_NAME_LEN 32

struct mii_dev {
	struct list_head link;
	char name[MDIO_NAME_LEN];
	void *priv;
	int (*read)(struct mii_dev *bus, int addr, int devad, int reg);
	int (*write)(struct mii_dev *bus, int addr, int devad, int reg,
			u16 val);
	int (*reset)(struct mii_dev *bus);
	struct phy_device *phymap[PHY_MAX_ADDR];
	u32 phy_mask;
};

/* struct phy_driver: a structure which defines PHY behavior
 *
 * uid will contain a number which represents the PHY.  During
 * startup, the driver will poll the PHY to find out what its
 * UID--as defined by registers 2 and 3--is.  The 32-bit result
 * gotten from the PHY will be masked to
 * discard any bits which may change based on revision numbers
 * unimportant to functionality
 *
 */
struct phy_driver {
	char *name;
	unsigned int uid;
	unsigned int mask;
	unsigned int mmds;

	u32 features;

	/* Called to do any driver startup necessities */
	/* Will be called during phy_connect */
	int (*probe)(struct phy_device *phydev);

	/* Called to configure the PHY, and modify the controller
	 * based on the results.  Should be called after phy_connect */
	int (*config)(struct phy_device *phydev);

	/* Called when starting up the controller */
	int (*startup)(struct phy_device *phydev);

	/* Called when bringing down the controller */
	int (*shutdown)(struct phy_device *phydev);

	int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
	int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
			u16 val);

	/* Phy specific driver override for reading a MMD register */
	int (*read_mmd)(struct phy_device *phydev, int devad, int reg);

	/* Phy specific driver override for writing a MMD register */
	int (*write_mmd)(struct phy_device *phydev, int devad, int reg,
			 u16 val);

	struct list_head list;
};

struct phy_device {
	/* Information about the PHY type */
	/* And management functions */
	struct mii_dev *bus;
	struct phy_driver *drv;
	void *priv;

#ifdef CONFIG_DM_ETH
	struct udevice *dev;
	ofnode node;
#else
	struct eth_device *dev;
#endif

	/* forced speed & duplex (no autoneg)
	 * partner speed & duplex & pause (autoneg)
	 */
	int speed;
	int duplex;

	/* The most recently read link state */
	int link;
	int port;
	phy_interface_t interface;

	u32 advertising;
	u32 supported;
	u32 mmds;

	int autoneg;
	int addr;
	int pause;
	int asym_pause;
	u32 phy_id;
	bool is_c45;
	u32 flags;
};

struct fixed_link {
	int phy_id;
	int duplex;
	int link_speed;
	int pause;
	int asym_pause;
};

static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
{
	struct mii_dev *bus = phydev->bus;

	return bus->read(bus, phydev->addr, devad, regnum);
}

static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
			u16 val)
{
	struct mii_dev *bus = phydev->bus;

	return bus->write(bus, phydev->addr, devad, regnum, val);
}

static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
					  int regnum)
{
	/* Write the desired MMD Devad */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);

	/* Write the desired MMD register address */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);

	/* Select the Function : DATA with no post increment */
	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL,
		  (devad | MII_MMD_CTRL_NOINCR));
}

static inline int phy_read_mmd(struct phy_device *phydev, int devad,
			       int regnum)
{
	struct phy_driver *drv = phydev->drv;

	if (regnum > (u16)~0 || devad > 32)
		return -EINVAL;

	/* driver-specific access */
	if (drv->read_mmd)
		return drv->read_mmd(phydev, devad, regnum);

	/* direct C45 / C22 access */
	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
	    devad == MDIO_DEVAD_NONE || !devad)
		return phy_read(phydev, devad, regnum);

	/* indirect C22 access */
	phy_mmd_start_indirect(phydev, devad, regnum);

	/* Read the content of the MMD's selected register */
	return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
}

static inline int phy_write_mmd(struct phy_device *phydev, int devad,
				int regnum, u16 val)
{
	struct phy_driver *drv = phydev->drv;

	if (regnum > (u16)~0 || devad > 32)
		return -EINVAL;

	/* driver-specific access */
	if (drv->write_mmd)
		return drv->write_mmd(phydev, devad, regnum, val);

	/* direct C45 / C22 access */
	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES ||
	    devad == MDIO_DEVAD_NONE || !devad)
		return phy_write(phydev, devad, regnum, val);

	/* indirect C22 access */
	phy_mmd_start_indirect(phydev, devad, regnum);

	/* Write the data into MMD's selected register */
	return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
}

#ifdef CONFIG_PHYLIB_10G
extern struct phy_driver gen10g_driver;

/* For now, XGMII is the only 10G interface */
static inline int is_10g_interface(phy_interface_t interface)
{
	return interface == PHY_INTERFACE_MODE_XGMII;
}

#endif

/**
 * phy_init() - Initializes the PHY drivers
 *
 * This function registers all available PHY drivers
 *
 * @return 0 if OK, -ve on error
 */
int phy_init(void);

/**
 * phy_reset() - Resets the specified PHY
 *
 * Issues a reset of the PHY and waits for it to complete
 *
 * @phydev:	PHY to reset
 * @return 0 if OK, -ve on error
 */
int phy_reset(struct phy_device *phydev);

/**
 * phy_find_by_mask() - Searches for a PHY on the specified MDIO bus
 *
 * The function checks the PHY addresses flagged in phy_mask and returns a
 * phy_device pointer if it detects a PHY.
 * This function should only be called if just one PHY is expected to be present
 * in the set of addresses flagged in phy_mask.  If multiple PHYs are present,
 * it is undefined which of these PHYs is returned.
 *
 * @bus:	MII/MDIO bus to scan
 * @phy_mask:	bitmap of PYH addresses to scan
 * @interface:	type of MAC-PHY interface
 * @return pointer to phy_device if a PHY is found, or NULL otherwise
 */
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
		phy_interface_t interface);

#ifdef CONFIG_DM_ETH

/**
 * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
 * @phydev:	PHY device
 * @dev:	Ethernet device
 */
void phy_connect_dev(struct phy_device *phydev, struct udevice *dev);

/**
 * phy_connect() - Creates a PHY device for the Ethernet interface
 *
 * Creates a PHY device for the PHY at the given address, if one doesn't exist
 * already, and associates it with the Ethernet device.
 * The function may be called with addr <= 0, in this case addr value is ignored
 * and the bus is scanned to detect a PHY.  Scanning should only be used if only
 * one PHY is expected to be present on the MDIO bus, otherwise it is undefined
 * which PHY is returned.
 *
 * @bus:	MII/MDIO bus that hosts the PHY
 * @addr:	PHY address on MDIO bus
 * @dev:	Ethernet device to associate to the PHY
 * @interface:	type of MAC-PHY interface
 * @return pointer to phy_device if a PHY is found, or NULL otherwise
 */
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct udevice *dev,
				phy_interface_t interface);

static inline ofnode phy_get_ofnode(struct phy_device *phydev)
{
	if (ofnode_valid(phydev->node))
		return phydev->node;
	else
		return dev_ofnode(phydev->dev);
}
#else

/**
 * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
 * @phydev:	PHY device
 * @dev:	Ethernet device
 */
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);

/**
 * phy_connect() - Creates a PHY device for the Ethernet interface
 *
 * Creates a PHY device for the PHY at the given address, if one doesn't exist
 * already, and associates it with the Ethernet device.
 * The function may be called with addr <= 0, in this case addr value is ignored
 * and the bus is scanned to detect a PHY.  Scanning should only be used if only
 * one PHY is expected to be present on the MDIO bus, otherwise it is undefined
 * which PHY is returned.
 *
 * @bus:	MII/MDIO bus that hosts the PHY
 * @addr:	PHY address on MDIO bus
 * @dev:	Ethernet device to associate to the PHY
 * @interface:	type of MAC-PHY interface
 * @return pointer to phy_device if a PHY is found, or NULL otherwise
 */
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
				struct eth_device *dev,
				phy_interface_t interface);

static inline ofnode phy_get_ofnode(struct phy_device *phydev)
{
	return ofnode_null();
}
#endif
int phy_startup(struct phy_device *phydev);
int phy_config(struct phy_device *phydev);
int phy_shutdown(struct phy_device *phydev);
int phy_register(struct phy_driver *drv);
int phy_set_supported(struct phy_device *phydev, u32 max_speed);
int genphy_config_aneg(struct phy_device *phydev);
int genphy_restart_aneg(struct phy_device *phydev);
int genphy_update_link(struct phy_device *phydev);
int genphy_parse_link(struct phy_device *phydev);
int genphy_config(struct phy_device *phydev);
int genphy_startup(struct phy_device *phydev);
int genphy_shutdown(struct phy_device *phydev);
int gen10g_config(struct phy_device *phydev);
int gen10g_startup(struct phy_device *phydev);
int gen10g_shutdown(struct phy_device *phydev);
int gen10g_discover_mmds(struct phy_device *phydev);

int phy_b53_init(void);
int phy_mv88e61xx_init(void);
int phy_aquantia_init(void);
int phy_atheros_init(void);
int phy_broadcom_init(void);
int phy_cortina_init(void);
int phy_davicom_init(void);
int phy_et1011c_init(void);
int phy_lxt_init(void);
int phy_marvell_init(void);
int phy_micrel_ksz8xxx_init(void);
int phy_micrel_ksz90x1_init(void);
int phy_meson_gxl_init(void);
int phy_natsemi_init(void);
int phy_realtek_init(void);
int phy_smsc_init(void);
int phy_teranetics_init(void);
int phy_ti_init(void);
int phy_vitesse_init(void);
int phy_xilinx_init(void);
int phy_mscc_init(void);
int phy_fixed_init(void);
int phy_xilinx_gmii2rgmii_init(void);

int board_phy_config(struct phy_device *phydev);
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);

/**
 * phy_get_interface_by_name() - Look up a PHY interface name
 *
 * @str:	PHY interface name, e.g. "mii"
 * @return PHY_INTERFACE_MODE_... value, or -1 if not found
 */
int phy_get_interface_by_name(const char *str);

/**
 * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
 * is RGMII (all variants)
 * @phydev: the phy_device struct
 */
static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
{
	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
		phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
}

/**
 * phy_interface_is_sgmii - Convenience function for testing if a PHY interface
 * is SGMII (all variants)
 * @phydev: the phy_device struct
 */
static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
{
	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
		phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
}

/* PHY UIDs for various PHYs that are referenced in external code */
#define PHY_UID_CS4340  	0x13e51002
#define PHY_UID_CS4223  	0x03e57003
#define PHY_UID_TN2020		0x00a19410
#define PHY_UID_IN112525_S03	0x02107440

#endif
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
5f184715 AF	2	/*
5f184715 AF	3	* Copyright 2011 Freescale Semiconductor, Inc.
b21f87a3	4	* Andy Fleming <[email protected]>
5f184715	5	*
5f184715 AF	6	* This file pretty much stolen from Linux's mii.h/ethtool.h/phy.h
	7	*/
	8
	9	#ifndef _PHY_H
	10	#define _PHY_H
	11
eef0b8a9	12	#include <dm.h>
5f184715 AF	13	#include <linux/list.h>
	14	#include <linux/mii.h>
	15	#include <linux/ethtool.h>
	16	#include <linux/mdio.h>
f070b1a2	17	#include <phy_interface.h>
5f184715	18
db40c1aa	19	#define PHY_FIXED_ID 0xa5a55a5a
f41e588c SDPP	20	/*
	21	* There is no actual id for this.
	22	* This is just a dummy id for gmii2rgmmi converter.
	23	*/
	24	#define PHY_GMII2RGMII_ID 0x5a5a5a5a
db40c1aa	25
5f184715 AF	26	#define PHY_MAX_ADDR 32
5f184715 AF	27
ddcd1f30 SX	28	#define PHY_FLAG_BROKEN_RESET (1 << 0) /* soft reset not supported */
ddcd1f30 SX	29
4dae610b	30	#define PHY_DEFAULT_FEATURES (SUPPORTED_Autoneg \| \
5f184715 AF	31	SUPPORTED_TP \| \
	32	SUPPORTED_MII)
	33
4dae610b FF	34	#define PHY_10BT_FEATURES (SUPPORTED_10baseT_Half \| \
	35	SUPPORTED_10baseT_Full)
	36
	37	#define PHY_100BT_FEATURES (SUPPORTED_100baseT_Half \| \
	38	SUPPORTED_100baseT_Full)
	39
	40	#define PHY_1000BT_FEATURES (SUPPORTED_1000baseT_Half \| \
5f184715 AF	41	SUPPORTED_1000baseT_Full)
5f184715 AF	42
4dae610b FF	43	#define PHY_BASIC_FEATURES (PHY_10BT_FEATURES \| \
	44	PHY_100BT_FEATURES \| \
	45	PHY_DEFAULT_FEATURES)
	46
	47	#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES \| \
	48	PHY_1000BT_FEATURES)
	49
5f184715 AF	50	#define PHY_10G_FEATURES (PHY_GBIT_FEATURES \| \
	51	SUPPORTED_10000baseT_Full)
	52
4fb3f0c8	53	#ifndef PHY_ANEG_TIMEOUT
5f184715	54	#define PHY_ANEG_TIMEOUT 4000
4fb3f0c8	55	#endif
5f184715 AF	56
5f184715 AF	57
5f184715 AF	58	struct phy_device;
	59
	60	#define MDIO_NAME_LEN 32
	61
	62	struct mii_dev {
	63	struct list_head link;
	64	char name[MDIO_NAME_LEN];
	65	void *priv;
	66	int (read)(struct mii_dev bus, int addr, int devad, int reg);
	67	int (write)(struct mii_dev bus, int addr, int devad, int reg,
	68	u16 val);
	69	int (reset)(struct mii_dev bus);
	70	struct phy_device *phymap[PHY_MAX_ADDR];
	71	u32 phy_mask;
	72	};
	73
	74	/* struct phy_driver: a structure which defines PHY behavior
	75	*
	76	* uid will contain a number which represents the PHY. During
	77	* startup, the driver will poll the PHY to find out what its
	78	* UID--as defined by registers 2 and 3--is. The 32-bit result
	79	* gotten from the PHY will be masked to
	80	* discard any bits which may change based on revision numbers
	81	* unimportant to functionality
	82	*
	83	*/
	84	struct phy_driver {
	85	char *name;
	86	unsigned int uid;
	87	unsigned int mask;
	88	unsigned int mmds;
	89
	90	u32 features;
	91
	92	/* Called to do any driver startup necessities */
	93	/* Will be called during phy_connect */
	94	int (probe)(struct phy_device phydev);
	95
	96	/* Called to configure the PHY, and modify the controller
	97	* based on the results. Should be called after phy_connect */
	98	int (config)(struct phy_device phydev);
	99
	100	/* Called when starting up the controller */
	101	int (startup)(struct phy_device phydev);
	102
	103	/* Called when bringing down the controller */
	104	int (shutdown)(struct phy_device phydev);
	105
b71841b9 SB	106	int (readext)(struct phy_device phydev, int addr, int devad, int reg);
	107	int (writeext)(struct phy_device phydev, int addr, int devad, int reg,
	108	u16 val);
4f6746dc CC	109
	110	/* Phy specific driver override for reading a MMD register */
	111	int (read_mmd)(struct phy_device phydev, int devad, int reg);
	112
	113	/* Phy specific driver override for writing a MMD register */
	114	int (write_mmd)(struct phy_device phydev, int devad, int reg,
	115	u16 val);
	116
5f184715 AF	117	struct list_head list;
	118	};
	119
	120	struct phy_device {
	121	/* Information about the PHY type */
	122	/* And management functions */
	123	struct mii_dev *bus;
	124	struct phy_driver *drv;
	125	void *priv;
	126
c74c8e66 SG	127	#ifdef CONFIG_DM_ETH
c74c8e66 SG	128	struct udevice *dev;
eef0b8a9	129	ofnode node;
c74c8e66	130	#else
5f184715	131	struct eth_device *dev;
c74c8e66	132	#endif
5f184715 AF	133
	134	/* forced speed & duplex (no autoneg)
	135	* partner speed & duplex & pause (autoneg)
	136	*/
	137	int speed;
	138	int duplex;
	139
	140	/* The most recently read link state */
	141	int link;
	142	int port;
	143	phy_interface_t interface;
	144
	145	u32 advertising;
	146	u32 supported;
	147	u32 mmds;
	148
	149	int autoneg;
	150	int addr;
	151	int pause;
	152	int asym_pause;
	153	u32 phy_id;
b3eabd82	154	bool is_c45;
5f184715 AF	155	u32 flags;
	156	};
	157
f55a776c SX	158	struct fixed_link {
	159	int phy_id;
	160	int duplex;
	161	int link_speed;
	162	int pause;
	163	int asym_pause;
	164	};
	165
5f184715 AF	166	static inline int phy_read(struct phy_device *phydev, int devad, int regnum)
	167	{
	168	struct mii_dev *bus = phydev->bus;
	169
	170	return bus->read(bus, phydev->addr, devad, regnum);
	171	}
	172
	173	static inline int phy_write(struct phy_device *phydev, int devad, int regnum,
	174	u16 val)
	175	{
	176	struct mii_dev *bus = phydev->bus;
	177
	178	return bus->write(bus, phydev->addr, devad, regnum, val);
	179	}
	180
4f6746dc CC	181	static inline void phy_mmd_start_indirect(struct phy_device *phydev, int devad,
	182	int regnum)
	183	{
	184	/* Write the desired MMD Devad */
	185	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL, devad);
	186
	187	/* Write the desired MMD register address */
	188	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, regnum);
	189
	190	/* Select the Function : DATA with no post increment */
	191	phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_CTRL,
	192	(devad \| MII_MMD_CTRL_NOINCR));
	193	}
	194
	195	static inline int phy_read_mmd(struct phy_device *phydev, int devad,
	196	int regnum)
	197	{
	198	struct phy_driver *drv = phydev->drv;
	199
	200	if (regnum > (u16)~0 \|\| devad > 32)
	201	return -EINVAL;
	202
	203	/* driver-specific access */
	204	if (drv->read_mmd)
	205	return drv->read_mmd(phydev, devad, regnum);
	206
	207	/* direct C45 / C22 access */
	208	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES \|\|
	209	devad == MDIO_DEVAD_NONE \|\| !devad)
	210	return phy_read(phydev, devad, regnum);
	211
	212	/* indirect C22 access */
	213	phy_mmd_start_indirect(phydev, devad, regnum);
	214
	215	/* Read the content of the MMD's selected register */
	216	return phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA);
	217	}
	218
	219	static inline int phy_write_mmd(struct phy_device *phydev, int devad,
	220	int regnum, u16 val)
	221	{
	222	struct phy_driver *drv = phydev->drv;
	223
	224	if (regnum > (u16)~0 \|\| devad > 32)
	225	return -EINVAL;
	226
	227	/* driver-specific access */
	228	if (drv->write_mmd)
	229	return drv->write_mmd(phydev, devad, regnum, val);
	230
	231	/* direct C45 / C22 access */
	232	if ((drv->features & PHY_10G_FEATURES) == PHY_10G_FEATURES \|\|
	233	devad == MDIO_DEVAD_NONE \|\| !devad)
	234	return phy_write(phydev, devad, regnum, val);
	235
	236	/* indirect C22 access */
	237	phy_mmd_start_indirect(phydev, devad, regnum);
	238
	239	/* Write the data into MMD's selected register */
	240	return phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_DATA, val);
	241	}
	242
5f184715 AF	243	#ifdef CONFIG_PHYLIB_10G
	244	extern struct phy_driver gen10g_driver;
	245
	246	/* For now, XGMII is the only 10G interface */
	247	static inline int is_10g_interface(phy_interface_t interface)
	248	{
	249	return interface == PHY_INTERFACE_MODE_XGMII;
	250	}
	251
	252	#endif
	253
c38ac289 AM	254	/**
	255	* phy_init() - Initializes the PHY drivers
	256	*
	257	* This function registers all available PHY drivers
	258	*
	259	* @return 0 if OK, -ve on error
	260	*/
5f184715	261	int phy_init(void);
c38ac289 AM	262
	263	/**
	264	* phy_reset() - Resets the specified PHY
	265	*
	266	* Issues a reset of the PHY and waits for it to complete
	267	*
	268	* @phydev: PHY to reset
	269	* @return 0 if OK, -ve on error
	270	*/
5f184715	271	int phy_reset(struct phy_device *phydev);
c38ac289 AM	272
	273	/**
	274	* phy_find_by_mask() - Searches for a PHY on the specified MDIO bus
	275	*
	276	* The function checks the PHY addresses flagged in phy_mask and returns a
	277	* phy_device pointer if it detects a PHY.
	278	* This function should only be called if just one PHY is expected to be present
	279	* in the set of addresses flagged in phy_mask. If multiple PHYs are present,
	280	* it is undefined which of these PHYs is returned.
	281	*
	282	* @bus: MII/MDIO bus to scan
	283	* @phy_mask: bitmap of PYH addresses to scan
	284	* @interface: type of MAC-PHY interface
	285	* @return pointer to phy_device if a PHY is found, or NULL otherwise
	286	*/
1adb406b TK	287	struct phy_device phy_find_by_mask(struct mii_dev bus, unsigned phy_mask,
1adb406b TK	288	phy_interface_t interface);
c38ac289	289
c74c8e66	290	#ifdef CONFIG_DM_ETH
c38ac289 AM	291
	292	/**
	293	* phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
	294	* @phydev: PHY device
	295	* @dev: Ethernet device
	296	*/
c74c8e66	297	void phy_connect_dev(struct phy_device phydev, struct udevice dev);
c38ac289 AM	298
	299	/**
	300	* phy_connect() - Creates a PHY device for the Ethernet interface
	301	*
	302	* Creates a PHY device for the PHY at the given address, if one doesn't exist
	303	* already, and associates it with the Ethernet device.
	304	* The function may be called with addr <= 0, in this case addr value is ignored
	305	* and the bus is scanned to detect a PHY. Scanning should only be used if only
	306	* one PHY is expected to be present on the MDIO bus, otherwise it is undefined
	307	* which PHY is returned.
	308	*
	309	* @bus: MII/MDIO bus that hosts the PHY
	310	* @addr: PHY address on MDIO bus
	311	* @dev: Ethernet device to associate to the PHY
	312	* @interface: type of MAC-PHY interface
	313	* @return pointer to phy_device if a PHY is found, or NULL otherwise
	314	*/
c74c8e66 SG	315	struct phy_device phy_connect(struct mii_dev bus, int addr,
	316	struct udevice *dev,
	317	phy_interface_t interface);
c38ac289	318
eef0b8a9 GS	319	static inline ofnode phy_get_ofnode(struct phy_device *phydev)
	320	{
	321	if (ofnode_valid(phydev->node))
	322	return phydev->node;
	323	else
	324	return dev_ofnode(phydev->dev);
	325	}
c74c8e66	326	#else
c38ac289 AM	327
	328	/**
	329	* phy_connect_dev() - Associates the given pair of PHY and Ethernet devices
	330	* @phydev: PHY device
	331	* @dev: Ethernet device
	332	*/
1adb406b	333	void phy_connect_dev(struct phy_device phydev, struct eth_device dev);
c38ac289 AM	334
	335	/**
	336	* phy_connect() - Creates a PHY device for the Ethernet interface
	337	*
	338	* Creates a PHY device for the PHY at the given address, if one doesn't exist
	339	* already, and associates it with the Ethernet device.
	340	* The function may be called with addr <= 0, in this case addr value is ignored
	341	* and the bus is scanned to detect a PHY. Scanning should only be used if only
	342	* one PHY is expected to be present on the MDIO bus, otherwise it is undefined
	343	* which PHY is returned.
	344	*
	345	* @bus: MII/MDIO bus that hosts the PHY
	346	* @addr: PHY address on MDIO bus
	347	* @dev: Ethernet device to associate to the PHY
	348	* @interface: type of MAC-PHY interface
	349	* @return pointer to phy_device if a PHY is found, or NULL otherwise
	350	*/
5f184715 AF	351	struct phy_device phy_connect(struct mii_dev bus, int addr,
	352	struct eth_device *dev,
	353	phy_interface_t interface);
c38ac289	354
eef0b8a9 GS	355	static inline ofnode phy_get_ofnode(struct phy_device *phydev)
	356	{
	357	return ofnode_null();
	358	}
c74c8e66	359	#endif
5f184715 AF	360	int phy_startup(struct phy_device *phydev);
	361	int phy_config(struct phy_device *phydev);
	362	int phy_shutdown(struct phy_device *phydev);
	363	int phy_register(struct phy_driver *drv);
b18acb0a	364	int phy_set_supported(struct phy_device *phydev, u32 max_speed);
5f184715	365	int genphy_config_aneg(struct phy_device *phydev);
8682aba7	366	int genphy_restart_aneg(struct phy_device *phydev);
5f184715	367	int genphy_update_link(struct phy_device *phydev);
e2043f5c	368	int genphy_parse_link(struct phy_device *phydev);
5f184715 AF	369	int genphy_config(struct phy_device *phydev);
	370	int genphy_startup(struct phy_device *phydev);
	371	int genphy_shutdown(struct phy_device *phydev);
	372	int gen10g_config(struct phy_device *phydev);
	373	int gen10g_startup(struct phy_device *phydev);
	374	int gen10g_shutdown(struct phy_device *phydev);
	375	int gen10g_discover_mmds(struct phy_device *phydev);
	376
137963d7	377	int phy_b53_init(void);
24ae3961	378	int phy_mv88e61xx_init(void);
f7c38cf8	379	int phy_aquantia_init(void);
9082eeac AF	380	int phy_atheros_init(void);
9082eeac AF	381	int phy_broadcom_init(void);
9b18e519	382	int phy_cortina_init(void);
9082eeac	383	int phy_davicom_init(void);
f485c8a3	384	int phy_et1011c_init(void);
9082eeac AF	385	int phy_lxt_init(void);
9082eeac AF	386	int phy_marvell_init(void);
d397f7c4 AG	387	int phy_micrel_ksz8xxx_init(void);
d397f7c4 AG	388	int phy_micrel_ksz90x1_init(void);
8995a96d	389	int phy_meson_gxl_init(void);
9082eeac AF	390	int phy_natsemi_init(void);
9082eeac AF	391	int phy_realtek_init(void);
b6abf555	392	int phy_smsc_init(void);
9082eeac	393	int phy_teranetics_init(void);
721aed79	394	int phy_ti_init(void);
9082eeac	395	int phy_vitesse_init(void);
ed6fad3e	396	int phy_xilinx_init(void);
a5fd13ad	397	int phy_mscc_init(void);
db40c1aa	398	int phy_fixed_init(void);
f41e588c	399	int phy_xilinx_gmii2rgmii_init(void);
a836626c	400
2fb63964	401	int board_phy_config(struct phy_device *phydev);
5707d5ff	402	int get_phy_id(struct mii_dev bus, int addr, int devad, u32 phy_id);
2fb63964	403
c74c8e66 SG	404	/**
	405	* phy_get_interface_by_name() - Look up a PHY interface name
	406	*
	407	* @str: PHY interface name, e.g. "mii"
	408	* @return PHY_INTERFACE_MODE_... value, or -1 if not found
	409	*/
	410	int phy_get_interface_by_name(const char *str);
	411
3ab72fe8 DM	412	/**
	413	* phy_interface_is_rgmii - Convenience function for testing if a PHY interface
	414	* is RGMII (all variants)
	415	* @phydev: the phy_device struct
	416	*/
	417	static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
	418	{
	419	return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
	420	phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
	421	}
	422
3c221af3 DM	423	/**
	424	* phy_interface_is_sgmii - Convenience function for testing if a PHY interface
	425	* is SGMII (all variants)
	426	* @phydev: the phy_device struct
	427	*/
	428	static inline bool phy_interface_is_sgmii(struct phy_device *phydev)
	429	{
	430	return phydev->interface >= PHY_INTERFACE_MODE_SGMII &&
	431	phydev->interface <= PHY_INTERFACE_MODE_QSGMII;
	432	}
	433
a836626c	434	/* PHY UIDs for various PHYs that are referenced in external code */
1ddcf5ed PJ	435	#define PHY_UID_CS4340 0x13e51002
	436	#define PHY_UID_CS4223 0x03e57003
	437	#define PHY_UID_TN2020 0x00a19410
	438	#define PHY_UID_IN112525_S03 0x02107440
a836626c	439
5f184715	440	#endif