[J-u-boot.git] / include / configs / MPC8540ADS.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright 2004, 2011 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <[email protected]>
 */

/*
 * mpc8540ads board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_SERVERIP, etc in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * default CCARBAR is at 0xff700000
 * assume U-Boot is less than 0.5MB
 */

#ifndef CONFIG_HAS_FEC
#define CONFIG_HAS_FEC		1	/* 8540 has FEC */
#endif

#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 *
 * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
 * 33MHz to accommodate, based on a PCI pin.
 * Note that PCI-X won't work at 33MHz.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33000000
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
#define CONFIG_SYS_DDR_TIMING_1	0x37344321
#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */

#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_SYS_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Local Bus Definitions
 */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CONFIG_SYS_BR2_PRELIM		0xf0001861

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/

#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
				| LSDMR_RFCR5		\
				| LSDMR_PRETOACT3	\
				| LSDMR_ACTTORW3	\
				| LSDMR_BL8		\
				| LSDMR_WRC2		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * SDRAM Controller configuration sequence.
 */
#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)

/*
 * 32KB, 8-bit wide for ADS config reg
 */
#define CONFIG_SYS_BR4_PRELIM          0xf8000801
#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* RapidIO MMU */
#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */

#if defined(CONFIG_PCI)
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

#if CONFIG_HAS_FEC
#define CONFIG_MPC85XX_FEC	1
#define CONFIG_MPC85XX_FEC_NAME		"FEC"
#define FEC_PHY_ADDR		3
#define FEC_PHYIDX		0
#define FEC_FLAGS		0
#endif

/* Options are: TSEC[0-1], FEC */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME		"unknown"
#define CONFIG_ROOTPATH		"/nfsroot"
#define CONFIG_BOOTFILE		"your.uImage"

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS0\0"                                                 \
   "ramdiskaddr=1000000\0"						\
   "ramdiskfile=your.ramdisk.u-boot\0"					\
   "fdtaddr=400000\0"							\
   "fdtfile=your.fdt.dtb\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
42d1f039	2	/*
7c57f3e8	3	* Copyright 2004, 2011 Freescale Semiconductor.
42d1f039 WD	4	* (C) Copyright 2002,2003 Motorola,Inc.
42d1f039 WD	5	* Xianghua Xiao <[email protected]>
42d1f039 WD	6	*/
42d1f039 WD	7
0ac6f8b7 WD	8	/*
	9	* mpc8540ads board configuration file
	10	*
	11	* Please refer to doc/README.mpc85xx for more info.
	12	*
	13	* Make sure you change the MAC address and other network params first,
92ac5208	14	* search for CONFIG_SERVERIP, etc in this file.
42d1f039 WD	15	*/
	16
	17	#ifndef __CONFIG_H
	18	#define __CONFIG_H
	19
2ae18241 WD	20	/*
	21	* default CCARBAR is at 0xff700000
	22	* assume U-Boot is less than 0.5MB
	23	*/
2ae18241	24
288693ab JL	25	#ifndef CONFIG_HAS_FEC
	26	#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
	27	#endif
	28
842033e6	29	#define CONFIG_PCI_INDIRECT_BRIDGE
0151cbac	30	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
42d1f039	31	#define CONFIG_ENV_OVERWRITE
42d1f039	32
0ac6f8b7 WD	33	/*
	34	* sysclk for MPC85xx
	35	*
	36	* Two valid values are:
	37	* 33000000
	38	* 66000000
	39	*
	40	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
9aea9530 WD	41	* is likely the desired value here, so that is now the default.
	42	* The board, however, can run at 66MHz. In any event, this value
	43	* must match the settings of some switches. Details can be found
	44	* in the README.mpc85xxads.
34c3c0e0 MM	45	*
	46	* XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
	47	* 33MHz to accommodate, based on a PCI pin.
	48	* Note that PCI-X won't work at 33MHz.
0ac6f8b7 WD	49	*/
0ac6f8b7 WD	50
9aea9530	51	#ifndef CONFIG_SYS_CLK_FREQ
34c3c0e0	52	#define CONFIG_SYS_CLK_FREQ 33000000
42d1f039 WD	53	#endif
42d1f039 WD	54
0ac6f8b7 WD	55	/*
	56	* These can be toggled for performance analysis, otherwise use default.
	57	*/
	58	#define CONFIG_L2_CACHE /* toggle L2 cache */
	59	#define CONFIG_BTB /* toggle branch predition */
42d1f039	60
6d0f6bcf JCPV	61	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
6d0f6bcf JCPV	62	#define CONFIG_SYS_MEMTEST_END 0x00400000
42d1f039	63
e46fedfe TT	64	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	65	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
42d1f039	66
9617c8d4	67	/* DDR Setup */
9617c8d4 KG	68	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
9617c8d4 KG	69	#define CONFIG_DDR_SPD
9617c8d4 KG	70
9617c8d4 KG	71	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
9aea9530	72
6d0f6bcf JCPV	73	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	74	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
9aea9530	75
9617c8d4 KG	76	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	77	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
	78
	79	/* I2C addresses of SPD EEPROMs */
	80	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	81
	82	/* These are used when DDR doesn't use SPD. */
6d0f6bcf JCPV	83	#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
	84	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
	85	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
	86	#define CONFIG_SYS_DDR_TIMING_1 0x37344321
	87	#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	88	#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	89	#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	90	#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
42d1f039	91
0ac6f8b7 WD	92	/*
	93	* SDRAM on the Local Bus
	94	*/
6d0f6bcf JCPV	95	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	96	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
42d1f039	97
6d0f6bcf JCPV	98	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
6d0f6bcf JCPV	99	#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
42d1f039	100
6d0f6bcf JCPV	101	#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
	102	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	103	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
	104	#undef CONFIG_SYS_FLASH_CHECKSUM
	105	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	106	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
0ac6f8b7	107
14d0a02a	108	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
42d1f039	109
6d0f6bcf JCPV	110	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	111	#define CONFIG_SYS_RAMBOOT
42d1f039	112	#else
6d0f6bcf	113	#undef CONFIG_SYS_RAMBOOT
42d1f039 WD	114	#endif
42d1f039 WD	115
6d0f6bcf	116	#define CONFIG_SYS_FLASH_EMPTY_INFO
42d1f039	117
0ac6f8b7 WD	118	#undef CONFIG_CLOCKS_IN_MHZ
0ac6f8b7 WD	119
0ac6f8b7 WD	120	/*
	121	* Local Bus Definitions
	122	*/
	123
	124	/*
	125	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	126	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
0ac6f8b7 WD	127	*
	128	* For BR2, need:
	129	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	130	* port-size = 32-bits = BR2[19:20] = 11
	131	* no parity checking = BR2[21:22] = 00
	132	* SDRAM for MSEL = BR2[24:26] = 011
	133	* Valid = BR[31] = 1
	134	*
	135	* 0 4 8 12 16 20 24 28
	136	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	137	*
6d0f6bcf	138	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
0ac6f8b7 WD	139	* FIXME: the top 17 bits of BR2.
	140	*/
	141
6d0f6bcf	142	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
0ac6f8b7 WD	143
0ac6f8b7 WD	144	/*
6d0f6bcf	145	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
0ac6f8b7 WD	146	*
	147	* For OR2, need:
	148	* 64MB mask for AM, OR2[0:7] = 1111 1100
	149	* XAM, OR2[17:18] = 11
	150	* 9 columns OR2[19-21] = 010
	151	* 13 rows OR2[23-25] = 100
	152	* EAD set for extra time OR[31] = 1
	153	*
	154	* 0 4 8 12 16 20 24 28
	155	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	156	*/
	157
6d0f6bcf	158	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
0ac6f8b7	159
6d0f6bcf JCPV	160	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	161	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	162	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	163	#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
0ac6f8b7	164
b0fe93ed KG	165	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
	166	\| LSDMR_RFCR5 \
	167	\| LSDMR_PRETOACT3 \
	168	\| LSDMR_ACTTORW3 \
	169	\| LSDMR_BL8 \
	170	\| LSDMR_WRC2 \
	171	\| LSDMR_CL3 \
	172	\| LSDMR_RFEN \
0ac6f8b7 WD	173	)
	174
	175	/*
	176	* SDRAM Controller configuration sequence.
	177	*/
b0fe93ed KG	178	#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_PCHALL)
	179	#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	180	#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	181	#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_MRW)
	182	#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_NORMAL)
0ac6f8b7	183
9aea9530 WD	184	/*
	185	* 32KB, 8-bit wide for ADS config reg
	186	*/
6d0f6bcf JCPV	187	#define CONFIG_SYS_BR4_PRELIM 0xf8000801
	188	#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
	189	#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
42d1f039	190
6d0f6bcf JCPV	191	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	192	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	193	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
42d1f039	194
25ddd1fb	195	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	196	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
42d1f039	197
6d0f6bcf JCPV	198	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	199	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
42d1f039 WD	200
42d1f039 WD	201	/* Serial Port */
6d0f6bcf JCPV	202	#define CONFIG_SYS_NS16550_SERIAL
	203	#define CONFIG_SYS_NS16550_REG_SIZE 1
	204	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
42d1f039	205
6d0f6bcf	206	#define CONFIG_SYS_BAUDRATE_TABLE \
42d1f039 WD	207	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
42d1f039 WD	208
6d0f6bcf JCPV	209	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	210	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
42d1f039	211
20476726 JL	212	/*
	213	* I2C
	214	*/
00f792e0 HS	215	#define CONFIG_SYS_I2C
	216	#define CONFIG_SYS_I2C_FSL
	217	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	218	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	219	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	220	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
0ac6f8b7 WD	221
0ac6f8b7 WD	222	/* RapidIO MMU */
5af0fdd8	223	#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
10795f42	224	#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
5af0fdd8	225	#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
6d0f6bcf	226	#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
0ac6f8b7 WD	227
	228	/*
	229	* General PCI
362dd830	230	* Memory space is mapped 1-1, but I/O space must start from 0.
0ac6f8b7	231	*/
5af0fdd8	232	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	233	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	234	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	235	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	236	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	237	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	238	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
6d0f6bcf JCPV	239	#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
42d1f039	240
42d1f039	241	#if defined(CONFIG_PCI)
42d1f039	242	#undef CONFIG_EEPRO100
0ac6f8b7 WD	243	#undef CONFIG_TULIP
	244
	245	#if !defined(CONFIG_PCI_PNP)
	246	#define PCI_ENET0_IOADDR 0xe0000000
	247	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	248	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
42d1f039	249	#endif
0ac6f8b7 WD	250
0ac6f8b7 WD	251	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	252	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
0ac6f8b7 WD	253
	254	#endif /* CONFIG_PCI */
	255
0ac6f8b7 WD	256	#if defined(CONFIG_TSEC_ENET)
0ac6f8b7 WD	257
255a3577 KP	258	#define CONFIG_TSEC1 1
	259	#define CONFIG_TSEC1_NAME "TSEC0"
	260	#define CONFIG_TSEC2 1
	261	#define CONFIG_TSEC2_NAME "TSEC1"
0ac6f8b7 WD	262	#define TSEC1_PHY_ADDR 0
0ac6f8b7 WD	263	#define TSEC2_PHY_ADDR 1
0ac6f8b7 WD	264	#define TSEC1_PHYIDX 0
0ac6f8b7 WD	265	#define TSEC2_PHYIDX 0
3a79013e AF	266	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	267	#define TSEC2_FLAGS TSEC_GIGABIT
9aea9530	268
288693ab	269	#if CONFIG_HAS_FEC
9aea9530	270	#define CONFIG_MPC85XX_FEC 1
d9b94f28	271	#define CONFIG_MPC85XX_FEC_NAME "FEC"
9aea9530	272	#define FEC_PHY_ADDR 3
0ac6f8b7	273	#define FEC_PHYIDX 0
3a79013e	274	#define FEC_FLAGS 0
288693ab	275	#endif
9aea9530	276
d9b94f28 JL	277	/* Options are: TSEC[0-1], FEC */
d9b94f28 JL	278	#define CONFIG_ETHPRIME "TSEC0"
0ac6f8b7 WD	279
	280	#endif /* CONFIG_TSEC_ENET */
	281
0ac6f8b7 WD	282	/*
	283	* Environment
	284	*/
42d1f039	285
0ac6f8b7	286	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	287	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
42d1f039	288
659e2f67 JL	289	/*
	290	* BOOTP options
	291	*/
	292	#define CONFIG_BOOTP_BOOTFILESIZE
659e2f67	293
2835e518 JL	294	/*
	295	* Command line configuration.
	296	*/
2835e518	297
0ac6f8b7	298	#undef CONFIG_WATCHDOG /* watchdog disabled */
42d1f039 WD	299
	300	/*
	301	* Miscellaneous configurable options
	302	*/
6d0f6bcf	303	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
0ac6f8b7	304
42d1f039 WD	305	/*
42d1f039 WD	306	* For booting Linux, the board info and command line data
a832ac41	307	* have to be in the first 64 MB of memory, since this is
42d1f039 WD	308	* the maximum mapped by the Linux kernel during initialization.
42d1f039 WD	309	*/
a832ac41 KG	310	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	311	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
42d1f039	312
2835e518	313	#if defined(CONFIG_CMD_KGDB)
42d1f039	314	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
42d1f039 WD	315	#endif
42d1f039 WD	316
9aea9530 WD	317	/*
	318	* Environment Configuration
	319	*/
0ac6f8b7 WD	320
0ac6f8b7 WD	321	/* The mac addresses for all ethernet interface */
42d1f039	322	#if defined(CONFIG_TSEC_ENET)
10327dc5	323	#define CONFIG_HAS_ETH0
e2ffd59b	324	#define CONFIG_HAS_ETH1
e2ffd59b	325	#define CONFIG_HAS_ETH2
42d1f039 WD	326	#endif
42d1f039 WD	327
0ac6f8b7 WD	328	#define CONFIG_IPADDR 192.168.1.253
0ac6f8b7 WD	329
5bc0543d	330	#define CONFIG_HOSTNAME "unknown"
8b3637c6	331	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	332	#define CONFIG_BOOTFILE "your.uImage"
0ac6f8b7 WD	333
	334	#define CONFIG_SERVERIP 192.168.1.1
	335	#define CONFIG_GATEWAYIP 192.168.1.1
	336	#define CONFIG_NETMASK 255.255.255.0
	337
	338	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	339
9aea9530	340	#define CONFIG_EXTRA_ENV_SETTINGS \
0ac6f8b7 WD	341	"netdev=eth0\0" \
0ac6f8b7 WD	342	"consoledev=ttyS0\0" \
d3ec0d94	343	"ramdiskaddr=1000000\0" \
8272dc2f AF	344	"ramdiskfile=your.ramdisk.u-boot\0" \
	345	"fdtaddr=400000\0" \
	346	"fdtfile=your.fdt.dtb\0"
0ac6f8b7	347
9aea9530	348	#define CONFIG_NFSBOOTCOMMAND \
0ac6f8b7 WD	349	"setenv bootargs root=/dev/nfs rw " \
	350	"nfsroot=$serverip:$rootpath " \
	351	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	352	"console=$consoledev,$baudrate $othbootargs;" \
	353	"tftp $loadaddr $bootfile;" \
8272dc2f AF	354	"tftp $fdtaddr $fdtfile;" \
8272dc2f AF	355	"bootm $loadaddr - $fdtaddr"
0ac6f8b7 WD	356
	357	#define CONFIG_RAMBOOTCOMMAND \
	358	"setenv bootargs root=/dev/ram rw " \
	359	"console=$consoledev,$baudrate $othbootargs;" \
	360	"tftp $ramdiskaddr $ramdiskfile;" \
	361	"tftp $loadaddr $bootfile;" \
8272dc2f	362	"tftp $fdtaddr $fdtfile;" \
d3ec0d94	363	"bootm $loadaddr $ramdiskaddr $fdtaddr"
0ac6f8b7 WD	364
0ac6f8b7 WD	365	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
42d1f039 WD	366
42d1f039 WD	367	#endif /* __CONFIG_H */