[J-u-boot.git] / include / configs / MPC8540ADS.h

/*
 * Copyright 2004, 2011 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * mpc8540ads board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_SERVERIP, etc in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * default CCARBAR is at 0xff700000
 * assume U-Boot is less than 0.5MB
 */

#ifndef CONFIG_HAS_FEC
#define CONFIG_HAS_FEC		1	/* 8540 has FEC */
#endif

#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 *
 * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
 * 33MHz to accommodate, based on a PCI pin.
 * Note that PCI-X won't work at 33MHz.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33000000
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
#define CONFIG_SYS_DDR_TIMING_1	0x37344321
#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */

#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Local Bus Definitions
 */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CONFIG_SYS_BR2_PRELIM		0xf0001861

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/

#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
				| LSDMR_RFCR5		\
				| LSDMR_PRETOACT3	\
				| LSDMR_ACTTORW3	\
				| LSDMR_BL8		\
				| LSDMR_WRC2		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * SDRAM Controller configuration sequence.
 */
#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)

/*
 * 32KB, 8-bit wide for ADS config reg
 */
#define CONFIG_SYS_BR4_PRELIM          0xf8000801
#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* RapidIO MMU */
#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */

#if defined(CONFIG_PCI)
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

#if CONFIG_HAS_FEC
#define CONFIG_MPC85XX_FEC	1
#define CONFIG_MPC85XX_FEC_NAME		"FEC"
#define FEC_PHY_ADDR		3
#define FEC_PHYIDX		0
#define FEC_FLAGS		0
#endif

/* Options are: TSEC[0-1], FEC */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
  #define CONFIG_ENV_SIZE		0x2000
#else
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
  #define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME		"unknown"
#define CONFIG_ROOTPATH		"/nfsroot"
#define CONFIG_BOOTFILE		"your.uImage"

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS0\0"                                                 \
   "ramdiskaddr=1000000\0"						\
   "ramdiskfile=your.ramdisk.u-boot\0"					\
   "fdtaddr=400000\0"							\
   "fdtfile=your.fdt.dtb\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
42d1f039	1	/*
7c57f3e8	2	* Copyright 2004, 2011 Freescale Semiconductor.
42d1f039 WD	3	* (C) Copyright 2002,2003 Motorola,Inc.
	4	* Xianghua Xiao <[email protected]>
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
42d1f039 WD	7	*/
42d1f039 WD	8
0ac6f8b7 WD	9	/*
	10	* mpc8540ads board configuration file
	11	*
	12	* Please refer to doc/README.mpc85xx for more info.
	13	*
	14	* Make sure you change the MAC address and other network params first,
92ac5208	15	* search for CONFIG_SERVERIP, etc in this file.
42d1f039 WD	16	*/
	17
	18	#ifndef __CONFIG_H
	19	#define __CONFIG_H
	20
2ae18241 WD	21	/*
	22	* default CCARBAR is at 0xff700000
	23	* assume U-Boot is less than 0.5MB
	24	*/
2ae18241	25
288693ab JL	26	#ifndef CONFIG_HAS_FEC
	27	#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
	28	#endif
	29
842033e6	30	#define CONFIG_PCI_INDIRECT_BRIDGE
0151cbac	31	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
42d1f039	32	#define CONFIG_ENV_OVERWRITE
42d1f039	33
0ac6f8b7 WD	34	/*
	35	* sysclk for MPC85xx
	36	*
	37	* Two valid values are:
	38	* 33000000
	39	* 66000000
	40	*
	41	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
9aea9530 WD	42	* is likely the desired value here, so that is now the default.
	43	* The board, however, can run at 66MHz. In any event, this value
	44	* must match the settings of some switches. Details can be found
	45	* in the README.mpc85xxads.
34c3c0e0 MM	46	*
	47	* XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
	48	* 33MHz to accommodate, based on a PCI pin.
	49	* Note that PCI-X won't work at 33MHz.
0ac6f8b7 WD	50	*/
0ac6f8b7 WD	51
9aea9530	52	#ifndef CONFIG_SYS_CLK_FREQ
34c3c0e0	53	#define CONFIG_SYS_CLK_FREQ 33000000
42d1f039 WD	54	#endif
42d1f039 WD	55
0ac6f8b7 WD	56	/*
	57	* These can be toggled for performance analysis, otherwise use default.
	58	*/
	59	#define CONFIG_L2_CACHE /* toggle L2 cache */
	60	#define CONFIG_BTB /* toggle branch predition */
42d1f039	61
6d0f6bcf JCPV	62	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
6d0f6bcf JCPV	63	#define CONFIG_SYS_MEMTEST_END 0x00400000
42d1f039	64
e46fedfe TT	65	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	66	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
42d1f039	67
9617c8d4	68	/* DDR Setup */
9617c8d4 KG	69	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	70	#define CONFIG_DDR_SPD
	71	#undef CONFIG_FSL_DDR_INTERACTIVE
	72
	73	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
9aea9530	74
6d0f6bcf JCPV	75	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	76	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
9aea9530	77
9617c8d4 KG	78	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	79	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
	80
	81	/* I2C addresses of SPD EEPROMs */
	82	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	83
	84	/* These are used when DDR doesn't use SPD. */
6d0f6bcf JCPV	85	#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
	86	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
	87	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
	88	#define CONFIG_SYS_DDR_TIMING_1 0x37344321
	89	#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	90	#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	91	#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	92	#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
42d1f039	93
0ac6f8b7 WD	94	/*
	95	* SDRAM on the Local Bus
	96	*/
6d0f6bcf JCPV	97	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	98	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
42d1f039	99
6d0f6bcf JCPV	100	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
6d0f6bcf JCPV	101	#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
42d1f039	102
6d0f6bcf JCPV	103	#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
	104	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	105	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
	106	#undef CONFIG_SYS_FLASH_CHECKSUM
	107	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	108	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
0ac6f8b7	109
14d0a02a	110	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
42d1f039	111
6d0f6bcf JCPV	112	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	113	#define CONFIG_SYS_RAMBOOT
42d1f039	114	#else
6d0f6bcf	115	#undef CONFIG_SYS_RAMBOOT
42d1f039 WD	116	#endif
42d1f039 WD	117
00b1883a	118	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	119	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	120	#define CONFIG_SYS_FLASH_EMPTY_INFO
42d1f039	121
0ac6f8b7 WD	122	#undef CONFIG_CLOCKS_IN_MHZ
0ac6f8b7 WD	123
0ac6f8b7 WD	124	/*
	125	* Local Bus Definitions
	126	*/
	127
	128	/*
	129	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	130	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
0ac6f8b7 WD	131	*
	132	* For BR2, need:
	133	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	134	* port-size = 32-bits = BR2[19:20] = 11
	135	* no parity checking = BR2[21:22] = 00
	136	* SDRAM for MSEL = BR2[24:26] = 011
	137	* Valid = BR[31] = 1
	138	*
	139	* 0 4 8 12 16 20 24 28
	140	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	141	*
6d0f6bcf	142	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
0ac6f8b7 WD	143	* FIXME: the top 17 bits of BR2.
	144	*/
	145
6d0f6bcf	146	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
0ac6f8b7 WD	147
0ac6f8b7 WD	148	/*
6d0f6bcf	149	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
0ac6f8b7 WD	150	*
	151	* For OR2, need:
	152	* 64MB mask for AM, OR2[0:7] = 1111 1100
	153	* XAM, OR2[17:18] = 11
	154	* 9 columns OR2[19-21] = 010
	155	* 13 rows OR2[23-25] = 100
	156	* EAD set for extra time OR[31] = 1
	157	*
	158	* 0 4 8 12 16 20 24 28
	159	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	160	*/
	161
6d0f6bcf	162	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
0ac6f8b7	163
6d0f6bcf JCPV	164	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	165	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	166	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	167	#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
0ac6f8b7	168
b0fe93ed KG	169	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
	170	\| LSDMR_RFCR5 \
	171	\| LSDMR_PRETOACT3 \
	172	\| LSDMR_ACTTORW3 \
	173	\| LSDMR_BL8 \
	174	\| LSDMR_WRC2 \
	175	\| LSDMR_CL3 \
	176	\| LSDMR_RFEN \
0ac6f8b7 WD	177	)
	178
	179	/*
	180	* SDRAM Controller configuration sequence.
	181	*/
b0fe93ed KG	182	#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_PCHALL)
	183	#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	184	#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	185	#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_MRW)
	186	#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_NORMAL)
0ac6f8b7	187
9aea9530 WD	188	/*
	189	* 32KB, 8-bit wide for ADS config reg
	190	*/
6d0f6bcf JCPV	191	#define CONFIG_SYS_BR4_PRELIM 0xf8000801
	192	#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
	193	#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
42d1f039	194
6d0f6bcf JCPV	195	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	196	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	197	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
42d1f039	198
25ddd1fb	199	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	200	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
42d1f039	201
6d0f6bcf JCPV	202	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	203	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
42d1f039 WD	204
42d1f039 WD	205	/* Serial Port */
6d0f6bcf JCPV	206	#define CONFIG_SYS_NS16550_SERIAL
	207	#define CONFIG_SYS_NS16550_REG_SIZE 1
	208	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
42d1f039	209
6d0f6bcf	210	#define CONFIG_SYS_BAUDRATE_TABLE \
42d1f039 WD	211	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
42d1f039 WD	212
6d0f6bcf JCPV	213	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	214	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
42d1f039	215
20476726 JL	216	/*
	217	* I2C
	218	*/
00f792e0 HS	219	#define CONFIG_SYS_I2C
	220	#define CONFIG_SYS_I2C_FSL
	221	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	222	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	223	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	224	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
0ac6f8b7 WD	225
0ac6f8b7 WD	226	/* RapidIO MMU */
5af0fdd8	227	#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
10795f42	228	#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
5af0fdd8	229	#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
6d0f6bcf	230	#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
0ac6f8b7 WD	231
	232	/*
	233	* General PCI
362dd830	234	* Memory space is mapped 1-1, but I/O space must start from 0.
0ac6f8b7	235	*/
5af0fdd8	236	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	237	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	238	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	239	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	240	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	241	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	242	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
6d0f6bcf JCPV	243	#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
42d1f039	244
42d1f039	245	#if defined(CONFIG_PCI)
42d1f039	246	#undef CONFIG_EEPRO100
0ac6f8b7 WD	247	#undef CONFIG_TULIP
	248
	249	#if !defined(CONFIG_PCI_PNP)
	250	#define PCI_ENET0_IOADDR 0xe0000000
	251	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	252	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
42d1f039	253	#endif
0ac6f8b7 WD	254
0ac6f8b7 WD	255	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	256	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
0ac6f8b7 WD	257
	258	#endif /* CONFIG_PCI */
	259
0ac6f8b7 WD	260	#if defined(CONFIG_TSEC_ENET)
0ac6f8b7 WD	261
0ac6f8b7	262	#define CONFIG_MII 1 /* MII PHY management */
255a3577 KP	263	#define CONFIG_TSEC1 1
	264	#define CONFIG_TSEC1_NAME "TSEC0"
	265	#define CONFIG_TSEC2 1
	266	#define CONFIG_TSEC2_NAME "TSEC1"
0ac6f8b7 WD	267	#define TSEC1_PHY_ADDR 0
0ac6f8b7 WD	268	#define TSEC2_PHY_ADDR 1
0ac6f8b7 WD	269	#define TSEC1_PHYIDX 0
0ac6f8b7 WD	270	#define TSEC2_PHYIDX 0
3a79013e AF	271	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	272	#define TSEC2_FLAGS TSEC_GIGABIT
9aea9530	273
288693ab	274	#if CONFIG_HAS_FEC
9aea9530	275	#define CONFIG_MPC85XX_FEC 1
d9b94f28	276	#define CONFIG_MPC85XX_FEC_NAME "FEC"
9aea9530	277	#define FEC_PHY_ADDR 3
0ac6f8b7	278	#define FEC_PHYIDX 0
3a79013e	279	#define FEC_FLAGS 0
288693ab	280	#endif
9aea9530	281
d9b94f28 JL	282	/* Options are: TSEC[0-1], FEC */
d9b94f28 JL	283	#define CONFIG_ETHPRIME "TSEC0"
0ac6f8b7 WD	284
	285	#endif /* CONFIG_TSEC_ENET */
	286
0ac6f8b7 WD	287	/*
	288	* Environment
	289	*/
6d0f6bcf	290	#ifndef CONFIG_SYS_RAMBOOT
6d0f6bcf	291	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586 JCPV	292	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
0e8d1586 JCPV	293	#define CONFIG_ENV_SIZE 0x2000
42d1f039	294	#else
6d0f6bcf	295	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	296	#define CONFIG_ENV_SIZE 0x2000
42d1f039 WD	297	#endif
42d1f039 WD	298
0ac6f8b7	299	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	300	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
42d1f039	301
659e2f67 JL	302	/*
	303	* BOOTP options
	304	*/
	305	#define CONFIG_BOOTP_BOOTFILESIZE
659e2f67	306
2835e518 JL	307	/*
	308	* Command line configuration.
	309	*/
2835e518	310
0ac6f8b7	311	#undef CONFIG_WATCHDOG /* watchdog disabled */
42d1f039 WD	312
	313	/*
	314	* Miscellaneous configurable options
	315	*/
6d0f6bcf	316	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
0ac6f8b7	317
42d1f039 WD	318	/*
42d1f039 WD	319	* For booting Linux, the board info and command line data
a832ac41	320	* have to be in the first 64 MB of memory, since this is
42d1f039 WD	321	* the maximum mapped by the Linux kernel during initialization.
42d1f039 WD	322	*/
a832ac41 KG	323	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	324	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
42d1f039	325
2835e518	326	#if defined(CONFIG_CMD_KGDB)
42d1f039	327	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
42d1f039 WD	328	#endif
42d1f039 WD	329
9aea9530 WD	330	/*
	331	* Environment Configuration
	332	*/
0ac6f8b7 WD	333
0ac6f8b7 WD	334	/* The mac addresses for all ethernet interface */
42d1f039	335	#if defined(CONFIG_TSEC_ENET)
10327dc5	336	#define CONFIG_HAS_ETH0
e2ffd59b	337	#define CONFIG_HAS_ETH1
e2ffd59b	338	#define CONFIG_HAS_ETH2
42d1f039 WD	339	#endif
42d1f039 WD	340
0ac6f8b7 WD	341	#define CONFIG_IPADDR 192.168.1.253
0ac6f8b7 WD	342
5bc0543d	343	#define CONFIG_HOSTNAME "unknown"
8b3637c6	344	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	345	#define CONFIG_BOOTFILE "your.uImage"
0ac6f8b7 WD	346
	347	#define CONFIG_SERVERIP 192.168.1.1
	348	#define CONFIG_GATEWAYIP 192.168.1.1
	349	#define CONFIG_NETMASK 255.255.255.0
	350
	351	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	352
9aea9530	353	#define CONFIG_EXTRA_ENV_SETTINGS \
0ac6f8b7 WD	354	"netdev=eth0\0" \
0ac6f8b7 WD	355	"consoledev=ttyS0\0" \
d3ec0d94	356	"ramdiskaddr=1000000\0" \
8272dc2f AF	357	"ramdiskfile=your.ramdisk.u-boot\0" \
	358	"fdtaddr=400000\0" \
	359	"fdtfile=your.fdt.dtb\0"
0ac6f8b7	360
9aea9530	361	#define CONFIG_NFSBOOTCOMMAND \
0ac6f8b7 WD	362	"setenv bootargs root=/dev/nfs rw " \
	363	"nfsroot=$serverip:$rootpath " \
	364	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	365	"console=$consoledev,$baudrate $othbootargs;" \
	366	"tftp $loadaddr $bootfile;" \
8272dc2f AF	367	"tftp $fdtaddr $fdtfile;" \
8272dc2f AF	368	"bootm $loadaddr - $fdtaddr"
0ac6f8b7 WD	369
	370	#define CONFIG_RAMBOOTCOMMAND \
	371	"setenv bootargs root=/dev/ram rw " \
	372	"console=$consoledev,$baudrate $othbootargs;" \
	373	"tftp $ramdiskaddr $ramdiskfile;" \
	374	"tftp $loadaddr $bootfile;" \
8272dc2f	375	"tftp $fdtaddr $fdtfile;" \
d3ec0d94	376	"bootm $loadaddr $ramdiskaddr $fdtaddr"
0ac6f8b7 WD	377
0ac6f8b7 WD	378	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
42d1f039 WD	379
42d1f039 WD	380	#endif /* __CONFIG_H */