[J-u-boot.git] / include / configs / MPC8540ADS.h

/*
 * Copyright 2004 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <[email protected]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * mpc8540ads board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560 */
#define CONFIG_MPC8540		1	/* MPC8540 specific */
#define CONFIG_MPC8540ADS	1	/* MPC8540ADS board specific */

#define CONFIG_PCI
#define CONFIG_TSEC_ENET 		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_DDR_DLL			/* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */


/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33000000
#endif


/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */
#define CONFIG_ADDR_STREAMING		/* toggle addr streaming */

#define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init */

#undef	CFG_DRAM_TEST			/* memory test, takes time */
#define CFG_MEMTEST_START	0x00200000	/* memtest region */
#define CFG_MEMTEST_END		0x00400000


/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */


/*
 * DDR Setup
 */
#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE

#if defined(CONFIG_SPD_EEPROM)
    /*
     * Determine DDR configuration from I2C interface.
     */
    #define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */

#else
    /*
     * Manually set up DDR parameters
     */
    #define CFG_SDRAM_SIZE	128		/* DDR is 128MB */
    #define CFG_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
    #define CFG_DDR_CS0_CONFIG	0x80000002
    #define CFG_DDR_TIMING_1	0x37344321
    #define CFG_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
    #define CFG_DDR_CONTROL	0xc2000000	/* unbuffered,no DYN_PWR */
    #define CFG_DDR_MODE	0x00000062	/* DLL,normal,seq,4/2.5 */
    #define CFG_DDR_INTERVAL	0x05200100	/* autocharge,no open page */
#endif


/*
 * SDRAM on the Local Bus
 */
#define CFG_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CFG_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#define CFG_BR0_PRELIM		0xff001801	/* port size 32bit */

#define CFG_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
#define CFG_MAX_FLASH_SECT	64		/* sectors per device */
#undef	CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CFG_MONITOR_BASE    	TEXT_BASE	/* start of monitor */

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef  CFG_RAMBOOT
#endif

#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ


/*
 * Local Bus Definitions
 */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CFG_BR2_PRELIM		0xf0001861

/*
 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CFG_OR2_PRELIM		0xfc006901

#define CFG_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CFG_LBC_LBCR		0x00000000    /* LB config reg */
#define CFG_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CFG_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/

/*
 * LSDMR masks
 */
#define CFG_LBC_LSDMR_RFEN	(1 << (31 -  1))
#define CFG_LBC_LSDMR_BSMA1516	(3 << (31 - 10))
#define CFG_LBC_LSDMR_BSMA1617	(4 << (31 - 10))
#define CFG_LBC_LSDMR_RFCR5	(3 << (31 - 16))
#define CFG_LBC_LSDMR_RFCR16	(7 << (31 - 16))
#define CFG_LBC_LSDMR_PRETOACT3	(3 << (31 - 19))
#define CFG_LBC_LSDMR_PRETOACT7	(7 << (31 - 19))
#define CFG_LBC_LSDMR_ACTTORW3	(3 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW7	(7 << (31 - 22))
#define CFG_LBC_LSDMR_ACTTORW6	(6 << (31 - 22))
#define CFG_LBC_LSDMR_BL8	(1 << (31 - 23))
#define CFG_LBC_LSDMR_WRC2	(2 << (31 - 27))
#define CFG_LBC_LSDMR_WRC4	(0 << (31 - 27))
#define CFG_LBC_LSDMR_BUFCMD	(1 << (31 - 29))
#define CFG_LBC_LSDMR_CL3	(3 << (31 - 31))

#define CFG_LBC_LSDMR_OP_NORMAL	(0 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ARFRSH	(1 << (31 - 4))
#define CFG_LBC_LSDMR_OP_SRFRSH	(2 << (31 - 4))
#define CFG_LBC_LSDMR_OP_MRW	(3 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PRECH	(4 << (31 - 4))
#define CFG_LBC_LSDMR_OP_PCHALL	(5 << (31 - 4))
#define CFG_LBC_LSDMR_OP_ACTBNK	(6 << (31 - 4))
#define CFG_LBC_LSDMR_OP_RWINV	(7 << (31 - 4))

#define CFG_LBC_LSDMR_COMMON	( CFG_LBC_LSDMR_BSMA1516	\
				| CFG_LBC_LSDMR_RFCR5		\
				| CFG_LBC_LSDMR_PRETOACT3	\
				| CFG_LBC_LSDMR_ACTTORW3	\
				| CFG_LBC_LSDMR_BL8		\
				| CFG_LBC_LSDMR_WRC2		\
				| CFG_LBC_LSDMR_CL3		\
				| CFG_LBC_LSDMR_RFEN		\
				)

/*
 * SDRAM Controller configuration sequence.
 */
#define CFG_LBC_LSDMR_1		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_PCHALL)
#define CFG_LBC_LSDMR_2		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_3		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_ARFRSH)
#define CFG_LBC_LSDMR_4		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5		( CFG_LBC_LSDMR_COMMON \
				| CFG_LBC_LSDMR_OP_NORMAL)


/*
 * 32KB, 8-bit wide for ADS config reg
 */
#define CFG_BR4_PRELIM          0xf8000801
#define CFG_OR4_PRELIM		0xffffe1f1
#define CFG_BCSR		(CFG_BR4_PRELIM & 0xffff8000)

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 	1
#define CFG_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CFG_INIT_RAM_END    	0x4000	    	/* End of used area in RAM */

#define CFG_GBL_DATA_SIZE  	128		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN	    	(512 * 1024)    /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN	    	(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE    1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CFG_NS16550_COM1        (CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2        (CFG_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#ifdef  CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* I2C */
#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES        {0x69}	/* Don't probe these addrs */

/* RapidIO MMU */
#define CFG_RIO_MEM_BASE	0xc0000000	/* base address */
#define CFG_RIO_MEM_PHYS	CFG_RIO_MEM_BASE
#define CFG_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI1_IO_BASE	0xe2000000
#define CFG_PCI1_IO_PHYS	CFG_PCI1_IO_BASE
#define CFG_PCI1_IO_SIZE	0x1000000	/* 16M */

#if defined(CONFIG_PCI)

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP	               	/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c 	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */


#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 	1
#endif

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_MPC85XX_TSEC1	1
#define CONFIG_MPC85XX_TSEC2	1
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0

#define CONFIG_MPC85XX_FEC	1
#define FEC_PHY_ADDR		3
#define FEC_PHYIDX		0

#define CONFIG_ETHPRIME		"MOTO ENET0"

#endif	/* CONFIG_TSEC_ENET */


/*
 * Environment
 */
#ifndef CFG_RAMBOOT
  #define CFG_ENV_IS_IN_FLASH	1
  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
  #define CFG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
  #define CFG_ENV_SIZE		0x2000
#else
  #define CFG_NO_FLASH		1	/* Flash is not usable now */
  #define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
  #define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
  #define CFG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

#if defined(CFG_RAMBOOT)
  #if defined(CONFIG_PCI)
    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
				 | CFG_CMD_PING		\
				 | CFG_CMD_PCI		\
				 | CFG_CMD_I2C)		\
				&			\
				 ~(CFG_CMD_ENV		\
				  | CFG_CMD_LOADS))
  #else
    #define  CONFIG_COMMANDS	((CONFIG_CMD_DFL	\
				 | CFG_CMD_PING		\
				 | CFG_CMD_I2C)		\
				&			\
				 ~(CFG_CMD_ENV		\
				  | CFG_CMD_LOADS))
  #endif
#else
  #if defined(CONFIG_PCI)
    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
				| CFG_CMD_PCI		\
				| CFG_CMD_PING		\
				| CFG_CMD_I2C)
  #else
    #define  CONFIG_COMMANDS	(CONFIG_CMD_DFL		\
				| CFG_CMD_PING		\
				| CFG_CMD_I2C)
  #endif
#endif

#include <cmd_confdefs.h>

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory	*/
#define CFG_LOAD_ADDR	0x2000000	/* default load address */
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
    #define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
    #define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

/* Cache Configuration */
#define CFG_DCACHE_SIZE		32768
#define CFG_CACHELINE_SIZE	32
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot */

#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif


/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_ETHADDR   00:E0:0C:00:00:FD
#define CONFIG_ETH1ADDR  00:E0:0C:00:01:FD
#define CONFIG_ETH2ADDR  00:E0:0C:00:02:FD
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		/nfsroot
#define CONFIG_BOOTFILE		your.uImage

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS0\0"                                                 \
   "ramdiskaddr=400000\0"						\
   "ramdiskfile=your.ramdisk.u-boot\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr $ramdiskaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
42d1f039	1	/*
0ac6f8b7	2	* Copyright 2004 Freescale Semiconductor.
42d1f039 WD	3	* (C) Copyright 2002,2003 Motorola,Inc.
	4	* Xianghua Xiao <[email protected]>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
0ac6f8b7 WD	25	/*
	26	* mpc8540ads board configuration file
	27	*
	28	* Please refer to doc/README.mpc85xx for more info.
	29	*
	30	* Make sure you change the MAC address and other network params first,
	31	* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
42d1f039 WD	32	*/
	33
	34	#ifndef __CONFIG_H
	35	#define __CONFIG_H
	36
	37	/* High Level Configuration Options */
0ac6f8b7 WD	38	#define CONFIG_BOOKE 1 /* BOOKE */
	39	#define CONFIG_E500 1 /* BOOKE e500 family */
	40	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
	41	#define CONFIG_MPC8540 1 /* MPC8540 specific */
	42	#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
	43
	44	#define CONFIG_PCI
	45	#define CONFIG_TSEC_ENET /* tsec ethernet support */
42d1f039	46	#define CONFIG_ENV_OVERWRITE
0ac6f8b7 WD	47	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	48	#define CONFIG_DDR_ECC /* only for ECC DDR module */
	49	#define CONFIG_DDR_DLL /* possible DLL fix needed */
	50	#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
42d1f039	51
42d1f039	52
0ac6f8b7 WD	53	/*
	54	* sysclk for MPC85xx
	55	*
	56	* Two valid values are:
	57	* 33000000
	58	* 66000000
	59	*
	60	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
9aea9530 WD	61	* is likely the desired value here, so that is now the default.
	62	* The board, however, can run at 66MHz. In any event, this value
	63	* must match the settings of some switches. Details can be found
	64	* in the README.mpc85xxads.
0ac6f8b7 WD	65	*/
0ac6f8b7 WD	66
9aea9530 WD	67	#ifndef CONFIG_SYS_CLK_FREQ
9aea9530 WD	68	#define CONFIG_SYS_CLK_FREQ 33000000
42d1f039 WD	69	#endif
42d1f039 WD	70
9aea9530	71
0ac6f8b7 WD	72	/*
	73	* These can be toggled for performance analysis, otherwise use default.
	74	*/
	75	#define CONFIG_L2_CACHE /* toggle L2 cache */
	76	#define CONFIG_BTB /* toggle branch predition */
	77	#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
42d1f039	78
0ac6f8b7	79	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
42d1f039	80
0ac6f8b7 WD	81	#undef CFG_DRAM_TEST /* memory test, takes time */
0ac6f8b7 WD	82	#define CFG_MEMTEST_START 0x00200000 /* memtest region */
42d1f039 WD	83	#define CFG_MEMTEST_END 0x00400000
42d1f039 WD	84
42d1f039 WD	85
	86	/*
	87	* Base addresses -- Note these are effective addresses where the
	88	* actual resources get mapped (not physical addresses)
	89	*/
0ac6f8b7 WD	90	#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
	91	#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
	92	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
42d1f039	93
9aea9530 WD	94
	95	/*
	96	* DDR Setup
	97	*/
0ac6f8b7	98	#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
42d1f039	99	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
9aea9530 WD	100
	101	#if defined(CONFIG_SPD_EEPROM)
	102	/*
	103	* Determine DDR configuration from I2C interface.
	104	*/
	105	#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
	106
	107	#else
	108	/*
	109	* Manually set up DDR parameters
	110	*/
	111	#define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
	112	#define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
	113	#define CFG_DDR_CS0_CONFIG 0x80000002
	114	#define CFG_DDR_TIMING_1 0x37344321
	115	#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	116	#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	117	#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	118	#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
	119	#endif
	120
42d1f039	121
0ac6f8b7 WD	122	/*
	123	* SDRAM on the Local Bus
	124	*/
0ac6f8b7	125	#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
0ac6f8b7	126	#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
42d1f039	127
0ac6f8b7 WD	128	#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
0ac6f8b7 WD	129	#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
42d1f039	130
0ac6f8b7 WD	131	#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
	132	#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
	133	#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
42d1f039	134	#undef CFG_FLASH_CHECKSUM
0ac6f8b7 WD	135	#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	136	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	137
	138	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
42d1f039	139
42d1f039 WD	140	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	141	#define CFG_RAMBOOT
	142	#else
0ac6f8b7	143	#undef CFG_RAMBOOT
42d1f039 WD	144	#endif
42d1f039 WD	145
cf33678e WD	146	#define CFG_FLASH_CFI_DRIVER
	147	#define CFG_FLASH_CFI
	148	#define CFG_FLASH_EMPTY_INFO
42d1f039	149
0ac6f8b7 WD	150	#undef CONFIG_CLOCKS_IN_MHZ
0ac6f8b7 WD	151
42d1f039	152
0ac6f8b7 WD	153	/*
	154	* Local Bus Definitions
	155	*/
	156
	157	/*
	158	* Base Register 2 and Option Register 2 configure SDRAM.
	159	* The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
	160	*
	161	* For BR2, need:
	162	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	163	* port-size = 32-bits = BR2[19:20] = 11
	164	* no parity checking = BR2[21:22] = 00
	165	* SDRAM for MSEL = BR2[24:26] = 011
	166	* Valid = BR[31] = 1
	167	*
	168	* 0 4 8 12 16 20 24 28
	169	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	170	*
	171	* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
	172	* FIXME: the top 17 bits of BR2.
	173	*/
	174
	175	#define CFG_BR2_PRELIM 0xf0001861
	176
	177	/*
	178	* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
	179	*
	180	* For OR2, need:
	181	* 64MB mask for AM, OR2[0:7] = 1111 1100
	182	* XAM, OR2[17:18] = 11
	183	* 9 columns OR2[19-21] = 010
	184	* 13 rows OR2[23-25] = 100
	185	* EAD set for extra time OR[31] = 1
	186	*
	187	* 0 4 8 12 16 20 24 28
	188	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	189	*/
	190
42d1f039	191	#define CFG_OR2_PRELIM 0xfc006901
0ac6f8b7 WD	192
	193	#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	194	#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
	195	#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	196	#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
	197
	198	/*
	199	* LSDMR masks
	200	*/
	201	#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
	202	#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
	203	#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
	204	#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
	205	#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
	206	#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
	207	#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
	208	#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
	209	#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
	210	#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
	211	#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
	212	#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
	213	#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
	214	#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
	215	#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
	216
	217	#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
	218	#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
	219	#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
	220	#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
	221	#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
	222	#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
	223	#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
	224	#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
	225
	226	#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
	227	\| CFG_LBC_LSDMR_RFCR5 \
	228	\| CFG_LBC_LSDMR_PRETOACT3 \
	229	\| CFG_LBC_LSDMR_ACTTORW3 \
	230	\| CFG_LBC_LSDMR_BL8 \
	231	\| CFG_LBC_LSDMR_WRC2 \
	232	\| CFG_LBC_LSDMR_CL3 \
	233	\| CFG_LBC_LSDMR_RFEN \
	234	)
	235
	236	/*
	237	* SDRAM Controller configuration sequence.
	238	*/
	239	#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
9aea9530	240	\| CFG_LBC_LSDMR_OP_PCHALL)
0ac6f8b7	241	#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
9aea9530	242	\| CFG_LBC_LSDMR_OP_ARFRSH)
0ac6f8b7	243	#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
9aea9530	244	\| CFG_LBC_LSDMR_OP_ARFRSH)
0ac6f8b7	245	#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
9aea9530	246	\| CFG_LBC_LSDMR_OP_MRW)
0ac6f8b7	247	#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
9aea9530	248	\| CFG_LBC_LSDMR_OP_NORMAL)
0ac6f8b7	249
42d1f039	250
9aea9530 WD	251	/*
	252	* 32KB, 8-bit wide for ADS config reg
	253	*/
	254	#define CFG_BR4_PRELIM 0xf8000801
c837dcb1 WD	255	#define CFG_OR4_PRELIM 0xffffe1f1
c837dcb1 WD	256	#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
42d1f039 WD	257
42d1f039 WD	258	#define CONFIG_L1_INIT_RAM
0ac6f8b7	259	#define CFG_INIT_RAM_LOCK 1
9aea9530	260	#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
0ac6f8b7	261	#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
42d1f039	262
0ac6f8b7	263	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
42d1f039 WD	264	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	265	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	266
cf33678e	267	#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 256 kB for Mon */
0ac6f8b7	268	#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
42d1f039 WD	269
	270	/* Serial Port */
	271	#define CONFIG_CONS_INDEX 1
	272	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	273	#define CFG_NS16550
	274	#define CFG_NS16550_SERIAL
0ac6f8b7	275	#define CFG_NS16550_REG_SIZE 1
42d1f039	276	#define CFG_NS16550_CLK get_bus_freq(0)
42d1f039 WD	277
	278	#define CFG_BAUDRATE_TABLE \
	279	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
	280
0ac6f8b7 WD	281	#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
0ac6f8b7 WD	282	#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
42d1f039 WD	283
	284	/* Use the HUSH parser */
	285	#define CFG_HUSH_PARSER
0ac6f8b7	286	#ifdef CFG_HUSH_PARSER
42d1f039 WD	287	#define CFG_PROMPT_HUSH_PS2 "> "
	288	#endif
	289
	290	/* I2C */
0ac6f8b7 WD	291	#define CONFIG_HARD_I2C /* I2C with hardware support*/
	292	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	293	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
42d1f039	294	#define CFG_I2C_SLAVE 0x7F
0ac6f8b7 WD	295	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
	296
	297	/* RapidIO MMU */
	298	#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
	299	#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
	300	#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
	301
	302	/*
	303	* General PCI
	304	* Addresses are mapped 1-1.
	305	*/
	306	#define CFG_PCI1_MEM_BASE 0x80000000
	307	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
	308	#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
	309	#define CFG_PCI1_IO_BASE 0xe2000000
	310	#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
	311	#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
42d1f039	312
42d1f039	313	#if defined(CONFIG_PCI)
0ac6f8b7	314
42d1f039	315	#define CONFIG_NET_MULTI
9aea9530	316	#define CONFIG_PCI_PNP /* do pci plug-and-play */
0ac6f8b7	317
42d1f039	318	#undef CONFIG_EEPRO100
0ac6f8b7 WD	319	#undef CONFIG_TULIP
	320
	321	#if !defined(CONFIG_PCI_PNP)
	322	#define PCI_ENET0_IOADDR 0xe0000000
	323	#define PCI_ENET0_MEMADDR 0xe0000000
	324	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
42d1f039	325	#endif
0ac6f8b7 WD	326
	327	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	328	#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
	329
	330	#endif /* CONFIG_PCI */
	331
	332
	333	#if defined(CONFIG_TSEC_ENET)
	334
	335	#ifndef CONFIG_NET_MULTI
	336	#define CONFIG_NET_MULTI 1
42d1f039 WD	337	#endif
42d1f039 WD	338
0ac6f8b7 WD	339	#define CONFIG_MII 1 /* MII PHY management */
	340	#define CONFIG_MPC85XX_TSEC1 1
	341	#define CONFIG_MPC85XX_TSEC2 1
0ac6f8b7 WD	342	#define TSEC1_PHY_ADDR 0
0ac6f8b7 WD	343	#define TSEC2_PHY_ADDR 1
0ac6f8b7 WD	344	#define TSEC1_PHYIDX 0
0ac6f8b7 WD	345	#define TSEC2_PHYIDX 0
9aea9530 WD	346
	347	#define CONFIG_MPC85XX_FEC 1
	348	#define FEC_PHY_ADDR 3
0ac6f8b7	349	#define FEC_PHYIDX 0
9aea9530	350
0ac6f8b7 WD	351	#define CONFIG_ETHPRIME "MOTO ENET0"
	352
	353	#endif /* CONFIG_TSEC_ENET */
	354
	355
	356	/*
	357	* Environment
	358	*/
42d1f039	359	#ifndef CFG_RAMBOOT
42d1f039 WD	360	#define CFG_ENV_IS_IN_FLASH 1
42d1f039 WD	361	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
0ac6f8b7	362	#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
42d1f039 WD	363	#define CFG_ENV_SIZE 0x2000
42d1f039 WD	364	#else
9aea9530 WD	365	#define CFG_NO_FLASH 1 /* Flash is not usable now */
	366	#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	367	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
	368	#define CFG_ENV_SIZE 0x2000
42d1f039 WD	369	#endif
42d1f039 WD	370
0ac6f8b7 WD	371	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
0ac6f8b7 WD	372	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
42d1f039	373
9aea9530	374	#if defined(CFG_RAMBOOT)
42d1f039	375	#if defined(CONFIG_PCI)
0ac6f8b7 WD	376	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
	377	\| CFG_CMD_PING \
	378	\| CFG_CMD_PCI \
	379	\| CFG_CMD_I2C) \
	380	& \
	381	~(CFG_CMD_ENV \
	382	\| CFG_CMD_LOADS))
42d1f039	383	#else
0ac6f8b7 WD	384	#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
	385	\| CFG_CMD_PING \
	386	\| CFG_CMD_I2C) \
	387	& \
	388	~(CFG_CMD_ENV \
	389	\| CFG_CMD_LOADS))
42d1f039 WD	390	#endif
	391	#else
	392	#if defined(CONFIG_PCI)
0ac6f8b7 WD	393	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
	394	\| CFG_CMD_PCI \
	395	\| CFG_CMD_PING \
	396	\| CFG_CMD_I2C)
42d1f039	397	#else
0ac6f8b7 WD	398	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
	399	\| CFG_CMD_PING \
	400	\| CFG_CMD_I2C)
42d1f039 WD	401	#endif
42d1f039 WD	402	#endif
0ac6f8b7	403
42d1f039 WD	404	#include <cmd_confdefs.h>
42d1f039 WD	405
0ac6f8b7	406	#undef CONFIG_WATCHDOG /* watchdog disabled */
42d1f039 WD	407
	408	/*
	409	* Miscellaneous configurable options
	410	*/
0ac6f8b7 WD	411	#define CFG_LONGHELP /* undef to save memory */
	412	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
	413	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	414
42d1f039	415	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
0ac6f8b7	416	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
42d1f039	417	#else
0ac6f8b7	418	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
42d1f039	419	#endif
0ac6f8b7	420
42d1f039	421	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
0ac6f8b7 WD	422	#define CFG_MAXARGS 16 /* max number of command args */
	423	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	424	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
42d1f039 WD	425
	426	/*
	427	* For booting Linux, the board info and command line data
	428	* have to be in the first 8 MB of memory, since this is
	429	* the maximum mapped by the Linux kernel during initialization.
	430	*/
0ac6f8b7	431	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
42d1f039 WD	432
42d1f039 WD	433	/* Cache Configuration */
0ac6f8b7	434	#define CFG_DCACHE_SIZE 32768
42d1f039 WD	435	#define CFG_CACHELINE_SIZE 32
42d1f039 WD	436	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
0ac6f8b7	437	#define CFG_CACHELINE_SHIFT 5 /log base 2 of the above value/
42d1f039 WD	438	#endif
	439
	440	/*
	441	* Internal Definitions
	442	*
	443	* Boot Flags
	444	*/
	445	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
0ac6f8b7	446	#define BOOTFLAG_WARM 0x02 /* Software reboot */
42d1f039 WD	447
	448	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	449	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	450	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	451	#endif
	452
9aea9530 WD	453
	454	/*
	455	* Environment Configuration
	456	*/
0ac6f8b7 WD	457
0ac6f8b7 WD	458	/* The mac addresses for all ethernet interface */
42d1f039	459	#if defined(CONFIG_TSEC_ENET)
0ac6f8b7 WD	460	#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
	461	#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
	462	#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
42d1f039 WD	463	#endif
42d1f039 WD	464
0ac6f8b7 WD	465	#define CONFIG_IPADDR 192.168.1.253
	466
	467	#define CONFIG_HOSTNAME unknown
	468	#define CONFIG_ROOTPATH /nfsroot
	469	#define CONFIG_BOOTFILE your.uImage
	470
	471	#define CONFIG_SERVERIP 192.168.1.1
	472	#define CONFIG_GATEWAYIP 192.168.1.1
	473	#define CONFIG_NETMASK 255.255.255.0
	474
	475	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	476
	477	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
	478	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	479
	480	#define CONFIG_BAUDRATE 115200
	481
9aea9530	482	#define CONFIG_EXTRA_ENV_SETTINGS \
0ac6f8b7 WD	483	"netdev=eth0\0" \
	484	"consoledev=ttyS0\0" \
	485	"ramdiskaddr=400000\0" \
	486	"ramdiskfile=your.ramdisk.u-boot\0"
	487
9aea9530	488	#define CONFIG_NFSBOOTCOMMAND \
0ac6f8b7 WD	489	"setenv bootargs root=/dev/nfs rw " \
	490	"nfsroot=$serverip:$rootpath " \
	491	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	492	"console=$consoledev,$baudrate $othbootargs;" \
	493	"tftp $loadaddr $bootfile;" \
	494	"bootm $loadaddr"
	495
	496	#define CONFIG_RAMBOOTCOMMAND \
	497	"setenv bootargs root=/dev/ram rw " \
	498	"console=$consoledev,$baudrate $othbootargs;" \
	499	"tftp $ramdiskaddr $ramdiskfile;" \
	500	"tftp $loadaddr $bootfile;" \
	501	"bootm $loadaddr $ramdiskaddr"
	502
	503	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
42d1f039 WD	504
42d1f039 WD	505	#endif /* __CONFIG_H */