[J-u-boot.git] / arch / arm / mach-stm32mp / bsec.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
 */

#define LOG_CATEGORY UCLASS_MISC

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
#include <misc.h>
#include <asm/io.h>
#include <asm/arch/bsec.h>
#include <asm/arch/stm32mp1_smc.h>
#include <dm/device_compat.h>
#include <linux/arm-smccc.h>
#include <linux/iopoll.h>

#define BSEC_OTP_MAX_VALUE		95
#define BSEC_OTP_UPPER_START		32
#define BSEC_TIMEOUT_US			10000

/* BSEC REGISTER OFFSET (base relative) */
#define BSEC_OTP_CONF_OFF		0x000
#define BSEC_OTP_CTRL_OFF		0x004
#define BSEC_OTP_WRDATA_OFF		0x008
#define BSEC_OTP_STATUS_OFF		0x00C
#define BSEC_OTP_LOCK_OFF		0x010
#define BSEC_DENABLE_OFF		0x014
#define BSEC_DISTURBED_OFF		0x01C
#define BSEC_ERROR_OFF			0x034
#define BSEC_WRLOCK_OFF			0x04C /* OTP write permananet lock */
#define BSEC_SPLOCK_OFF			0x064 /* OTP write sticky lock */
#define BSEC_SWLOCK_OFF			0x07C /* shadow write sticky lock */
#define BSEC_SRLOCK_OFF			0x094 /* shadow read sticky lock */
#define BSEC_OTP_DATA_OFF		0x200

/* BSEC_CONFIGURATION Register MASK */
#define BSEC_CONF_POWER_UP		0x001

/* BSEC_CONTROL Register */
#define BSEC_READ			0x000
#define BSEC_WRITE			0x100
#define BSEC_LOCK			0x200

/* LOCK Register */
#define OTP_LOCK_MASK			0x1F
#define OTP_LOCK_BANK_SHIFT		0x05
#define OTP_LOCK_BIT_MASK		0x01

/* STATUS Register */
#define BSEC_MODE_BUSY_MASK		0x08
#define BSEC_MODE_PROGFAIL_MASK		0x10
#define BSEC_MODE_PWR_MASK		0x20

/* DENABLE Register */
#define BSEC_DENABLE_DBGSWENABLE	BIT(10)

/*
 * OTP Lock services definition
 * Value must corresponding to the bit number in the register
 */
#define BSEC_LOCK_PROGRAM		0x04

/*
 * OTP status: bit 0 permanent lock
 */
#define BSEC_LOCK_PERM			BIT(0)

/**
 * bsec_lock() - manage lock for each type SR/SP/SW
 * @address: address of bsec IP register
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: true if locked else false
 */
static bool bsec_read_lock(u32 address, u32 otp)
{
	u32 bit;
	u32 bank;

	bit = 1 << (otp & OTP_LOCK_MASK);
	bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);

	return !!(readl(address + bank) & bit);
}

/**
 * bsec_check_error() - Check status of one otp
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error, -EAGAIN or -ENOTSUPP
 */
static u32 bsec_check_error(u32 base, u32 otp)
{
	u32 bit;
	u32 bank;

	bit = 1 << (otp & OTP_LOCK_MASK);
	bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);

	if (readl(base + BSEC_DISTURBED_OFF + bank) & bit)
		return -EAGAIN;
	else if (readl(base + BSEC_ERROR_OFF + bank) & bit)
		return -ENOTSUPP;

	return 0;
}

/**
 * bsec_read_SR_lock() - read SR lock (Shadowing)
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: true if locked else false
 */
static bool bsec_read_SR_lock(u32 base, u32 otp)
{
	return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
}

/**
 * bsec_read_SP_lock() - read SP lock (program Lock)
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: true if locked else false
 */
static bool bsec_read_SP_lock(u32 base, u32 otp)
{
	return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
}

/**
 * bsec_SW_lock() - manage SW lock (Write in Shadow)
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: true if locked else false
 */
static bool bsec_read_SW_lock(u32 base, u32 otp)
{
	return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
}

/**
 * bsec_power_safmem() - Activate or deactivate safmem power
 * @base: base address of bsec IP
 * @power: true to power up , false to power down
 * Return: 0 if succeed
 */
static int bsec_power_safmem(u32 base, bool power)
{
	u32 val;
	u32 mask;

	if (power) {
		setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
		mask = BSEC_MODE_PWR_MASK;
	} else {
		clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
		mask = 0;
	}

	/* waiting loop */
	return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
				  val, (val & BSEC_MODE_PWR_MASK) == mask,
				  BSEC_TIMEOUT_US);
}

/**
 * bsec_shadow_register() - copy safmen otp to bsec data
 * @dev: bsec IP device
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error
 */
static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
{
	u32 val;
	int ret;
	bool power_up = false;

	/* check if shadowing of otp is locked */
	if (bsec_read_SR_lock(base, otp))
		dev_dbg(dev, "OTP %d is locked and refreshed with 0\n",
			otp);

	/* check if safemem is power up */
	val = readl(base + BSEC_OTP_STATUS_OFF);
	if (!(val & BSEC_MODE_PWR_MASK)) {
		ret = bsec_power_safmem(base, true);
		if (ret)
			return ret;
		power_up = true;
	}
	/* set BSEC_OTP_CTRL_OFF with the otp value*/
	writel(otp | BSEC_READ, base + BSEC_OTP_CTRL_OFF);

	/* check otp status*/
	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
				 val, (val & BSEC_MODE_BUSY_MASK) == 0,
				 BSEC_TIMEOUT_US);
	if (ret)
		return ret;

	ret = bsec_check_error(base, otp);

	if (power_up)
		bsec_power_safmem(base, false);

	return ret;
}

/**
 * bsec_read_shadow() - read an otp data value from shadow
 * @dev: bsec IP device
 * @base: base address of bsec IP
 * @val: read value
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error
 */
static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp)
{
	*val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));

	return bsec_check_error(base, otp);
}

/**
 * bsec_write_shadow() - write value in BSEC data register in shadow
 * @dev: bsec IP device
 * @base: base address of bsec IP
 * @val: value to write
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error
 */
static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
{
	/* check if programming of otp is locked */
	if (bsec_read_SW_lock(base, otp))
		dev_dbg(dev, "OTP %d is lock, write will be ignore\n", otp);

	writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));

	return bsec_check_error(base, otp);
}

/**
 * bsec_program_otp() - program a bit in SAFMEM
 * @dev: bsec IP device
 * @base: base address of bsec IP
 * @val: value to program
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * after the function the otp data is not refreshed in shadow
 * Return: 0 if no error
 */
static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
{
	u32 ret;
	bool power_up = false;

	if (bsec_read_SP_lock(base, otp))
		dev_dbg(dev, "OTP %d locked, prog will be ignore\n", otp);

	if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
		dev_dbg(dev, "Global lock, prog will be ignore\n");

	/* check if safemem is power up */
	if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
		ret = bsec_power_safmem(base, true);
		if (ret)
			return ret;

		power_up = true;
	}
	/* set value in write register*/
	writel(val, base + BSEC_OTP_WRDATA_OFF);

	/* set BSEC_OTP_CTRL_OFF with the otp value */
	writel(otp | BSEC_WRITE, base + BSEC_OTP_CTRL_OFF);

	/* check otp status*/
	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
				 val, (val & BSEC_MODE_BUSY_MASK) == 0,
				 BSEC_TIMEOUT_US);
	if (ret)
		return ret;

	if (val & BSEC_MODE_PROGFAIL_MASK)
		ret = -EACCES;
	else
		ret = bsec_check_error(base, otp);

	if (power_up)
		bsec_power_safmem(base, false);

	return ret;
}

/**
 * bsec_permanent_lock_otp() - permanent lock of OTP in SAFMEM
 * @dev: bsec IP device
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error
 */
static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp)
{
	int ret;
	bool power_up = false;
	u32 val, addr;

	/* check if safemem is power up */
	if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
		ret = bsec_power_safmem(base, true);
		if (ret)
			return ret;

		power_up = true;
	}

	/*
	 * low OTPs = 2 bits word for low OTPs, 1 bits per word for upper OTP
	 * and only 16 bits used in WRDATA
	 */
	if (otp < BSEC_OTP_UPPER_START) {
		addr = otp / 8;
		val = 0x03 << ((otp * 2) & 0xF);
	} else {
		addr = BSEC_OTP_UPPER_START / 8 +
		       ((otp - BSEC_OTP_UPPER_START) / 16);
		val = 0x01 << (otp & 0xF);
	}

	/* set value in write register*/
	writel(val, base + BSEC_OTP_WRDATA_OFF);

	/* set BSEC_OTP_CTRL_OFF with the otp addr and lock request*/
	writel(addr | BSEC_WRITE | BSEC_LOCK, base + BSEC_OTP_CTRL_OFF);

	/* check otp status*/
	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
				 val, (val & BSEC_MODE_BUSY_MASK) == 0,
				 BSEC_TIMEOUT_US);
	if (ret)
		return ret;

	if (val & BSEC_MODE_PROGFAIL_MASK)
		ret = -EACCES;
	else
		ret = bsec_check_error(base, otp);

	if (power_up)
		bsec_power_safmem(base, false);

	return ret;
}

/* BSEC MISC driver *******************************************************/
struct stm32mp_bsec_plat {
	u32 base;
};

static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;
	u32 tmp_data = 0;
	int ret;

	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
		return stm32_smc(STM32_SMC_BSEC,
				 STM32_SMC_READ_OTP,
				 otp, 0, val);

	plat = dev_get_plat(dev);

	/* read current shadow value */
	ret = bsec_read_shadow(dev, plat->base, &tmp_data, otp);
	if (ret)
		return ret;

	/* copy otp in shadow */
	ret = bsec_shadow_register(dev, plat->base, otp);
	if (ret)
		return ret;

	ret = bsec_read_shadow(dev, plat->base, val, otp);
	if (ret)
		return ret;

	/* restore shadow value */
	ret = bsec_write_shadow(dev, plat->base, tmp_data, otp);

	return ret;
}

static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;

	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
		return stm32_smc(STM32_SMC_BSEC,
				 STM32_SMC_READ_SHADOW,
				 otp, 0, val);

	plat = dev_get_plat(dev);

	return bsec_read_shadow(dev, plat->base, val, otp);
}

static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
{
	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
	u32 wrlock;

	/* return OTP permanent write lock status */
	wrlock = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);

	*val = 0;
	if (wrlock)
		*val = BSEC_LOCK_PERM;

	return 0;
}

static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;

	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
		return stm32_smc_exec(STM32_SMC_BSEC,
				      STM32_SMC_PROG_OTP,
				      otp, val);

	plat = dev_get_plat(dev);

	return bsec_program_otp(dev, plat->base, val, otp);

}

static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;

	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
		return stm32_smc_exec(STM32_SMC_BSEC,
				      STM32_SMC_WRITE_SHADOW,
				      otp, val);

	plat = dev_get_plat(dev);

	return bsec_write_shadow(dev, plat->base, val, otp);
}

static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;

	/* only permanent write lock is supported in U-Boot */
	if (!(val & BSEC_LOCK_PERM)) {
		dev_dbg(dev, "lock option without BSEC_LOCK_PERM: %x\n", val);
		return 0; /* nothing to do */
	}

	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
		return stm32_smc_exec(STM32_SMC_BSEC,
				      STM32_SMC_WRLOCK_OTP,
				      otp, 0);

	plat = dev_get_plat(dev);

	return bsec_permanent_lock_otp(dev, plat->base, otp);

	return -EINVAL;
}

static int stm32mp_bsec_read(struct udevice *dev, int offset,
			     void *buf, int size)
{
	int ret;
	int i;
	bool shadow = true, lock = false;
	int nb_otp = size / sizeof(u32);
	int otp;
	unsigned int offs = offset;

	if (offs >= STM32_BSEC_LOCK_OFFSET) {
		offs -= STM32_BSEC_LOCK_OFFSET;
		lock = true;
	} else if (offs >= STM32_BSEC_OTP_OFFSET) {
		offs -= STM32_BSEC_OTP_OFFSET;
		shadow = false;
	}

	if ((offs % 4) || (size % 4))
		return -EINVAL;

	otp = offs / sizeof(u32);

	for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
		u32 *addr = &((u32 *)buf)[i - otp];

		if (lock)
			ret = stm32mp_bsec_read_lock(dev, addr, i);
		else if (shadow)
			ret = stm32mp_bsec_read_shadow(dev, addr, i);
		else
			ret = stm32mp_bsec_read_otp(dev, addr, i);

		if (ret)
			break;
	}
	if (ret)
		return ret;
	else
		return (i - otp) * 4;
}

static int stm32mp_bsec_write(struct udevice *dev, int offset,
			      const void *buf, int size)
{
	int ret = 0;
	int i;
	bool shadow = true, lock = false;
	int nb_otp = size / sizeof(u32);
	int otp;
	unsigned int offs = offset;

	if (offs >= STM32_BSEC_LOCK_OFFSET) {
		offs -= STM32_BSEC_LOCK_OFFSET;
		lock = true;
	} else if (offs >= STM32_BSEC_OTP_OFFSET) {
		offs -= STM32_BSEC_OTP_OFFSET;
		shadow = false;
	}

	if ((offs % 4) || (size % 4))
		return -EINVAL;

	otp = offs / sizeof(u32);

	for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
		u32 *val = &((u32 *)buf)[i - otp];

		if (lock)
			ret = stm32mp_bsec_write_lock(dev, *val, i);
		else if (shadow)
			ret = stm32mp_bsec_write_shadow(dev, *val, i);
		else
			ret = stm32mp_bsec_write_otp(dev, *val, i);
		if (ret)
			break;
	}
	if (ret)
		return ret;
	else
		return (i - otp) * 4;
}

static const struct misc_ops stm32mp_bsec_ops = {
	.read = stm32mp_bsec_read,
	.write = stm32mp_bsec_write,
};

static int stm32mp_bsec_of_to_plat(struct udevice *dev)
{
	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);

	plat->base = (u32)dev_read_addr_ptr(dev);

	return 0;
}

static int stm32mp_bsec_probe(struct udevice *dev)
{
	int otp;
	struct stm32mp_bsec_plat *plat;
	struct clk_bulk clk_bulk;
	int ret;

	ret = clk_get_bulk(dev, &clk_bulk);
	if (!ret) {
		ret = clk_enable_bulk(&clk_bulk);
		if (ret)
			return ret;
	}

	/*
	 * update unlocked shadow for OTP cleared by the rom code
	 * only executed in SPL, it is done in TF-A for TFABOOT
	 */
	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
		plat = dev_get_plat(dev);

		for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
			if (!bsec_read_SR_lock(plat->base, otp))
				bsec_shadow_register(dev, plat->base, otp);
	}

	return 0;
}

static const struct udevice_id stm32mp_bsec_ids[] = {
	{ .compatible = "st,stm32mp15-bsec" },
	{}
};

U_BOOT_DRIVER(stm32mp_bsec) = {
	.name = "stm32mp_bsec",
	.id = UCLASS_MISC,
	.of_match = stm32mp_bsec_ids,
	.of_to_plat = stm32mp_bsec_of_to_plat,
	.plat_auto	= sizeof(struct stm32mp_bsec_plat),
	.ops = &stm32mp_bsec_ops,
	.probe = stm32mp_bsec_probe,
};

bool bsec_dbgswenable(void)
{
	struct udevice *dev;
	struct stm32mp_bsec_plat *plat;
	int ret;

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_DRIVER_GET(stm32mp_bsec), &dev);
	if (ret || !dev) {
		log_debug("bsec driver not available\n");
		return false;
	}

	plat = dev_get_plat(dev);
	if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
		return true;

	return false;
}

u32 get_otp(int index, int shift, int mask)
{
	int ret;
	struct udevice *dev;
	u32 otp = 0;

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_DRIVER_GET(stm32mp_bsec),
					  &dev);

	if (!ret)
		ret = misc_read(dev, STM32_BSEC_SHADOW(index),
				&otp, sizeof(otp));

	return (otp >> shift) & mask;
}
Commit	Line	Data
19f58992 PD	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
	4	*/
	5
b66bfdf2 PD	6	#define LOG_CATEGORY UCLASS_MISC
b66bfdf2 PD	7
19f58992	8	#include <common.h>
622c956c	9	#include <clk.h>
19f58992	10	#include <dm.h>
f7ae49fc	11	#include <log.h>
19f58992 PD	12	#include <misc.h>
19f58992 PD	13	#include <asm/io.h>
bd3f60d2	14	#include <asm/arch/bsec.h>
d859c611	15	#include <asm/arch/stm32mp1_smc.h>
b66bfdf2	16	#include <dm/device_compat.h>
d859c611	17	#include <linux/arm-smccc.h>
ee7d7723	18	#include <linux/iopoll.h>
19f58992 PD	19
19f58992 PD	20	#define BSEC_OTP_MAX_VALUE 95
0c20f53b	21	#define BSEC_OTP_UPPER_START 32
19f58992 PD	22	#define BSEC_TIMEOUT_US 10000
	23
	24	/* BSEC REGISTER OFFSET (base relative) */
	25	#define BSEC_OTP_CONF_OFF 0x000
	26	#define BSEC_OTP_CTRL_OFF 0x004
	27	#define BSEC_OTP_WRDATA_OFF 0x008
	28	#define BSEC_OTP_STATUS_OFF 0x00C
	29	#define BSEC_OTP_LOCK_OFF 0x010
bd3f60d2	30	#define BSEC_DENABLE_OFF 0x014
19f58992 PD	31	#define BSEC_DISTURBED_OFF 0x01C
19f58992 PD	32	#define BSEC_ERROR_OFF 0x034
7ae22d72 PD	33	#define BSEC_WRLOCK_OFF 0x04C /* OTP write permananet lock */
	34	#define BSEC_SPLOCK_OFF 0x064 /* OTP write sticky lock */
	35	#define BSEC_SWLOCK_OFF 0x07C /* shadow write sticky lock */
	36	#define BSEC_SRLOCK_OFF 0x094 /* shadow read sticky lock */
19f58992 PD	37	#define BSEC_OTP_DATA_OFF 0x200
	38
	39	/* BSEC_CONFIGURATION Register MASK */
	40	#define BSEC_CONF_POWER_UP 0x001
	41
	42	/* BSEC_CONTROL Register */
	43	#define BSEC_READ 0x000
	44	#define BSEC_WRITE 0x100
0c20f53b	45	#define BSEC_LOCK 0x200
19f58992 PD	46
	47	/* LOCK Register */
	48	#define OTP_LOCK_MASK 0x1F
	49	#define OTP_LOCK_BANK_SHIFT 0x05
	50	#define OTP_LOCK_BIT_MASK 0x01
	51
	52	/* STATUS Register */
	53	#define BSEC_MODE_BUSY_MASK 0x08
	54	#define BSEC_MODE_PROGFAIL_MASK 0x10
	55	#define BSEC_MODE_PWR_MASK 0x20
	56
bd3f60d2 PD	57	/* DENABLE Register */
	58	#define BSEC_DENABLE_DBGSWENABLE BIT(10)
	59
19f58992 PD	60	/*
	61	* OTP Lock services definition
	62	* Value must corresponding to the bit number in the register
	63	*/
	64	#define BSEC_LOCK_PROGRAM 0x04
	65
0c20f53b PD	66	/*
	67	* OTP status: bit 0 permanent lock
	68	*/
	69	#define BSEC_LOCK_PERM BIT(0)
	70
19f58992	71	/**
7ae22d72 PD	72	* bsec_lock() - manage lock for each type SR/SP/SW
7ae22d72 PD	73	* @address: address of bsec IP register
19f58992	74	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
7ae22d72	75	* Return: true if locked else false
19f58992	76	*/
7ae22d72	77	static bool bsec_read_lock(u32 address, u32 otp)
19f58992 PD	78	{
	79	u32 bit;
	80	u32 bank;
	81
	82	bit = 1 << (otp & OTP_LOCK_MASK);
	83	bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
	84
7ae22d72	85	return !!(readl(address + bank) & bit);
19f58992 PD	86	}
	87
	88	/**
7ae22d72 PD	89	* bsec_check_error() - Check status of one otp
7ae22d72 PD	90	* @base: base address of bsec IP
19f58992	91	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
7ae22d72	92	* Return: 0 if no error, -EAGAIN or -ENOTSUPP
19f58992	93	*/
7ae22d72	94	static u32 bsec_check_error(u32 base, u32 otp)
19f58992 PD	95	{
	96	u32 bit;
	97	u32 bank;
	98
	99	bit = 1 << (otp & OTP_LOCK_MASK);
	100	bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
	101
7ae22d72 PD	102	if (readl(base + BSEC_DISTURBED_OFF + bank) & bit)
	103	return -EAGAIN;
	104	else if (readl(base + BSEC_ERROR_OFF + bank) & bit)
	105	return -ENOTSUPP;
	106
	107	return 0;
19f58992 PD	108	}
	109
	110	/**
	111	* bsec_read_SR_lock() - read SR lock (Shadowing)
	112	* @base: base address of bsec IP
	113	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	114	* Return: true if locked else false
	115	*/
	116	static bool bsec_read_SR_lock(u32 base, u32 otp)
	117	{
	118	return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
	119	}
	120
	121	/**
	122	* bsec_read_SP_lock() - read SP lock (program Lock)
	123	* @base: base address of bsec IP
	124	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	125	* Return: true if locked else false
	126	*/
	127	static bool bsec_read_SP_lock(u32 base, u32 otp)
	128	{
	129	return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
	130	}
	131
	132	/**
	133	* bsec_SW_lock() - manage SW lock (Write in Shadow)
	134	* @base: base address of bsec IP
	135	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	136	* Return: true if locked else false
	137	*/
	138	static bool bsec_read_SW_lock(u32 base, u32 otp)
	139	{
	140	return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
	141	}
	142
	143	/**
	144	* bsec_power_safmem() - Activate or deactivate safmem power
	145	* @base: base address of bsec IP
	146	* @power: true to power up , false to power down
	147	* Return: 0 if succeed
	148	*/
	149	static int bsec_power_safmem(u32 base, bool power)
	150	{
	151	u32 val;
	152	u32 mask;
	153
	154	if (power) {
	155	setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
	156	mask = BSEC_MODE_PWR_MASK;
	157	} else {
	158	clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
	159	mask = 0;
	160	}
	161
	162	/* waiting loop */
	163	return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
	164	val, (val & BSEC_MODE_PWR_MASK) == mask,
	165	BSEC_TIMEOUT_US);
	166	}
	167
	168	/**
	169	* bsec_shadow_register() - copy safmen otp to bsec data
2d48d99c	170	* @dev: bsec IP device
19f58992 PD	171	* @base: base address of bsec IP
	172	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	173	* Return: 0 if no error
	174	*/
b66bfdf2	175	static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
19f58992 PD	176	{
	177	u32 val;
	178	int ret;
	179	bool power_up = false;
	180
	181	/* check if shadowing of otp is locked */
	182	if (bsec_read_SR_lock(base, otp))
b66bfdf2 PD	183	dev_dbg(dev, "OTP %d is locked and refreshed with 0\n",
b66bfdf2 PD	184	otp);
19f58992 PD	185
	186	/* check if safemem is power up */
	187	val = readl(base + BSEC_OTP_STATUS_OFF);
	188	if (!(val & BSEC_MODE_PWR_MASK)) {
	189	ret = bsec_power_safmem(base, true);
	190	if (ret)
	191	return ret;
815bc8bc	192	power_up = true;
19f58992 PD	193	}
	194	/* set BSEC_OTP_CTRL_OFF with the otp value*/
	195	writel(otp \| BSEC_READ, base + BSEC_OTP_CTRL_OFF);
	196
	197	/* check otp status*/
	198	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
	199	val, (val & BSEC_MODE_BUSY_MASK) == 0,
	200	BSEC_TIMEOUT_US);
	201	if (ret)
	202	return ret;
	203
	204	ret = bsec_check_error(base, otp);
	205
	206	if (power_up)
	207	bsec_power_safmem(base, false);
	208
	209	return ret;
	210	}
	211
	212	/**
	213	* bsec_read_shadow() - read an otp data value from shadow
2d48d99c	214	* @dev: bsec IP device
19f58992 PD	215	* @base: base address of bsec IP
	216	* @val: read value
	217	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	218	* Return: 0 if no error
	219	*/
b66bfdf2	220	static int bsec_read_shadow(struct udevice dev, u32 base, u32 val, u32 otp)
19f58992 PD	221	{
	222	val = readl(base + BSEC_OTP_DATA_OFF + otp sizeof(u32));
	223
	224	return bsec_check_error(base, otp);
	225	}
	226
	227	/**
	228	* bsec_write_shadow() - write value in BSEC data register in shadow
2d48d99c	229	* @dev: bsec IP device
19f58992 PD	230	* @base: base address of bsec IP
	231	* @val: value to write
	232	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	233	* Return: 0 if no error
	234	*/
b66bfdf2	235	static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
19f58992 PD	236	{
	237	/* check if programming of otp is locked */
	238	if (bsec_read_SW_lock(base, otp))
b66bfdf2	239	dev_dbg(dev, "OTP %d is lock, write will be ignore\n", otp);
19f58992 PD	240
	241	writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
	242
	243	return bsec_check_error(base, otp);
	244	}
	245
	246	/**
	247	* bsec_program_otp() - program a bit in SAFMEM
2d48d99c	248	* @dev: bsec IP device
19f58992 PD	249	* @base: base address of bsec IP
	250	* @val: value to program
	251	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	252	* after the function the otp data is not refreshed in shadow
	253	* Return: 0 if no error
	254	*/
b66bfdf2	255	static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
19f58992 PD	256	{
	257	u32 ret;
	258	bool power_up = false;
	259
	260	if (bsec_read_SP_lock(base, otp))
b66bfdf2	261	dev_dbg(dev, "OTP %d locked, prog will be ignore\n", otp);
19f58992 PD	262
19f58992 PD	263	if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
b66bfdf2	264	dev_dbg(dev, "Global lock, prog will be ignore\n");
19f58992 PD	265
	266	/* check if safemem is power up */
	267	if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
	268	ret = bsec_power_safmem(base, true);
	269	if (ret)
	270	return ret;
	271
	272	power_up = true;
	273	}
	274	/* set value in write register*/
	275	writel(val, base + BSEC_OTP_WRDATA_OFF);
	276
	277	/* set BSEC_OTP_CTRL_OFF with the otp value */
	278	writel(otp \| BSEC_WRITE, base + BSEC_OTP_CTRL_OFF);
	279
	280	/* check otp status*/
	281	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
	282	val, (val & BSEC_MODE_BUSY_MASK) == 0,
	283	BSEC_TIMEOUT_US);
	284	if (ret)
	285	return ret;
	286
	287	if (val & BSEC_MODE_PROGFAIL_MASK)
	288	ret = -EACCES;
	289	else
	290	ret = bsec_check_error(base, otp);
	291
	292	if (power_up)
	293	bsec_power_safmem(base, false);
	294
	295	return ret;
	296	}
	297
0c20f53b PD	298	/**
	299	* bsec_permanent_lock_otp() - permanent lock of OTP in SAFMEM
	300	* @dev: bsec IP device
	301	* @base: base address of bsec IP
	302	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	303	* Return: 0 if no error
	304	*/
	305	static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp)
	306	{
	307	int ret;
	308	bool power_up = false;
	309	u32 val, addr;
	310
	311	/* check if safemem is power up */
	312	if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
	313	ret = bsec_power_safmem(base, true);
	314	if (ret)
	315	return ret;
	316
	317	power_up = true;
	318	}
	319
	320	/*
	321	* low OTPs = 2 bits word for low OTPs, 1 bits per word for upper OTP
	322	* and only 16 bits used in WRDATA
	323	*/
	324	if (otp < BSEC_OTP_UPPER_START) {
	325	addr = otp / 8;
	326	val = 0x03 << ((otp * 2) & 0xF);
	327	} else {
	328	addr = BSEC_OTP_UPPER_START / 8 +
	329	((otp - BSEC_OTP_UPPER_START) / 16);
	330	val = 0x01 << (otp & 0xF);
	331	}
	332
	333	/* set value in write register*/
	334	writel(val, base + BSEC_OTP_WRDATA_OFF);
	335
	336	/* set BSEC_OTP_CTRL_OFF with the otp addr and lock request*/
	337	writel(addr \| BSEC_WRITE \| BSEC_LOCK, base + BSEC_OTP_CTRL_OFF);
	338
	339	/* check otp status*/
	340	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
	341	val, (val & BSEC_MODE_BUSY_MASK) == 0,
	342	BSEC_TIMEOUT_US);
	343	if (ret)
	344	return ret;
	345
	346	if (val & BSEC_MODE_PROGFAIL_MASK)
	347	ret = -EACCES;
	348	else
	349	ret = bsec_check_error(base, otp);
	350
	351	if (power_up)
	352	bsec_power_safmem(base, false);
	353
	354	return ret;
	355	}
	356
19f58992	357	/* BSEC MISC driver *******************************************************/
8a8d24bd	358	struct stm32mp_bsec_plat {
19f58992 PD	359	u32 base;
	360	};
	361
	362	static int stm32mp_bsec_read_otp(struct udevice dev, u32 val, u32 otp)
	363	{
8a8d24bd	364	struct stm32mp_bsec_plat *plat;
19f58992 PD	365	u32 tmp_data = 0;
	366	int ret;
	367
f42045b2	368	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
4e9e358f PD	369	return stm32_smc(STM32_SMC_BSEC,
	370	STM32_SMC_READ_OTP,
	371	otp, 0, val);
	372
c69cda25	373	plat = dev_get_plat(dev);
4e9e358f	374
19f58992	375	/* read current shadow value */
b66bfdf2	376	ret = bsec_read_shadow(dev, plat->base, &tmp_data, otp);
19f58992 PD	377	if (ret)
	378	return ret;
	379
	380	/* copy otp in shadow */
b66bfdf2	381	ret = bsec_shadow_register(dev, plat->base, otp);
19f58992 PD	382	if (ret)
	383	return ret;
	384
b66bfdf2	385	ret = bsec_read_shadow(dev, plat->base, val, otp);
19f58992 PD	386	if (ret)
	387	return ret;
	388
	389	/* restore shadow value */
b66bfdf2	390	ret = bsec_write_shadow(dev, plat->base, tmp_data, otp);
4e9e358f	391
19f58992 PD	392	return ret;
	393	}
	394
	395	static int stm32mp_bsec_read_shadow(struct udevice dev, u32 val, u32 otp)
	396	{
8a8d24bd	397	struct stm32mp_bsec_plat *plat;
4e9e358f	398
f42045b2	399	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
4e9e358f PD	400	return stm32_smc(STM32_SMC_BSEC,
	401	STM32_SMC_READ_SHADOW,
	402	otp, 0, val);
	403
c69cda25	404	plat = dev_get_plat(dev);
19f58992	405
b66bfdf2	406	return bsec_read_shadow(dev, plat->base, val, otp);
19f58992 PD	407	}
19f58992 PD	408
7ae22d72 PD	409	static int stm32mp_bsec_read_lock(struct udevice dev, u32 val, u32 otp)
7ae22d72 PD	410	{
8a8d24bd	411	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
0c20f53b	412	u32 wrlock;
7ae22d72 PD	413
7ae22d72 PD	414	/* return OTP permanent write lock status */
0c20f53b PD	415	wrlock = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
	416
	417	*val = 0;
	418	if (wrlock)
	419	*val = BSEC_LOCK_PERM;
7ae22d72 PD	420
	421	return 0;
	422	}
	423
19f58992 PD	424	static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
19f58992 PD	425	{
8a8d24bd	426	struct stm32mp_bsec_plat *plat;
4e9e358f	427
f42045b2	428	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
4e9e358f PD	429	return stm32_smc_exec(STM32_SMC_BSEC,
	430	STM32_SMC_PROG_OTP,
	431	otp, val);
	432
c69cda25	433	plat = dev_get_plat(dev);
19f58992	434
b66bfdf2	435	return bsec_program_otp(dev, plat->base, val, otp);
4e9e358f	436
19f58992 PD	437	}
	438
	439	static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
	440	{
8a8d24bd	441	struct stm32mp_bsec_plat *plat;
4e9e358f	442
f42045b2	443	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
4e9e358f PD	444	return stm32_smc_exec(STM32_SMC_BSEC,
	445	STM32_SMC_WRITE_SHADOW,
	446	otp, val);
	447
c69cda25	448	plat = dev_get_plat(dev);
19f58992	449
b66bfdf2	450	return bsec_write_shadow(dev, plat->base, val, otp);
19f58992 PD	451	}
19f58992 PD	452
7ae22d72 PD	453	static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
7ae22d72 PD	454	{
0c20f53b PD	455	struct stm32mp_bsec_plat *plat;
	456
	457	/* only permanent write lock is supported in U-Boot */
	458	if (!(val & BSEC_LOCK_PERM)) {
	459	dev_dbg(dev, "lock option without BSEC_LOCK_PERM: %x\n", val);
	460	return 0; /* nothing to do */
	461	}
4e9e358f	462
0c20f53b	463	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
7ae22d72 PD	464	return stm32_smc_exec(STM32_SMC_BSEC,
	465	STM32_SMC_WRLOCK_OTP,
	466	otp, 0);
0c20f53b PD	467
	468	plat = dev_get_plat(dev);
	469
	470	return bsec_permanent_lock_otp(dev, plat->base, otp);
7ae22d72 PD	471
7ae22d72 PD	472	return -EINVAL;
7ae22d72 PD	473	}
7ae22d72 PD	474
19f58992 PD	475	static int stm32mp_bsec_read(struct udevice *dev, int offset,
	476	void *buf, int size)
	477	{
	478	int ret;
	479	int i;
7ae22d72	480	bool shadow = true, lock = false;
19f58992 PD	481	int nb_otp = size / sizeof(u32);
19f58992 PD	482	int otp;
745b676d	483	unsigned int offs = offset;
19f58992	484
7ae22d72 PD	485	if (offs >= STM32_BSEC_LOCK_OFFSET) {
	486	offs -= STM32_BSEC_LOCK_OFFSET;
	487	lock = true;
	488	} else if (offs >= STM32_BSEC_OTP_OFFSET) {
745b676d	489	offs -= STM32_BSEC_OTP_OFFSET;
19f58992 PD	490	shadow = false;
19f58992 PD	491	}
19f58992	492
df2d1b8f	493	if ((offs % 4) \|\| (size % 4))
19f58992	494	return -EINVAL;
19f58992	495
0c8620d2 PD	496	otp = offs / sizeof(u32);
	497
	498	for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
19f58992 PD	499	u32 addr = &((u32 )buf)[i - otp];
19f58992 PD	500
7ae22d72 PD	501	if (lock)
	502	ret = stm32mp_bsec_read_lock(dev, addr, i);
	503	else if (shadow)
19f58992 PD	504	ret = stm32mp_bsec_read_shadow(dev, addr, i);
	505	else
	506	ret = stm32mp_bsec_read_otp(dev, addr, i);
	507
	508	if (ret)
	509	break;
	510	}
0c8620d2 PD	511	if (ret)
	512	return ret;
	513	else
	514	return (i - otp) * 4;
19f58992 PD	515	}
	516
	517	static int stm32mp_bsec_write(struct udevice *dev, int offset,
	518	const void *buf, int size)
	519	{
	520	int ret = 0;
	521	int i;
7ae22d72	522	bool shadow = true, lock = false;
19f58992 PD	523	int nb_otp = size / sizeof(u32);
19f58992 PD	524	int otp;
745b676d	525	unsigned int offs = offset;
19f58992	526
7ae22d72 PD	527	if (offs >= STM32_BSEC_LOCK_OFFSET) {
	528	offs -= STM32_BSEC_LOCK_OFFSET;
	529	lock = true;
	530	} else if (offs >= STM32_BSEC_OTP_OFFSET) {
745b676d	531	offs -= STM32_BSEC_OTP_OFFSET;
19f58992 PD	532	shadow = false;
19f58992 PD	533	}
19f58992	534
df2d1b8f	535	if ((offs % 4) \|\| (size % 4))
19f58992	536	return -EINVAL;
19f58992	537
0c8620d2 PD	538	otp = offs / sizeof(u32);
	539
	540	for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
19f58992 PD	541	u32 val = &((u32 )buf)[i - otp];
19f58992 PD	542
7ae22d72 PD	543	if (lock)
	544	ret = stm32mp_bsec_write_lock(dev, *val, i);
	545	else if (shadow)
19f58992 PD	546	ret = stm32mp_bsec_write_shadow(dev, *val, i);
	547	else
	548	ret = stm32mp_bsec_write_otp(dev, *val, i);
	549	if (ret)
	550	break;
	551	}
0c8620d2 PD	552	if (ret)
	553	return ret;
	554	else
	555	return (i - otp) * 4;
19f58992 PD	556	}
	557
	558	static const struct misc_ops stm32mp_bsec_ops = {
	559	.read = stm32mp_bsec_read,
	560	.write = stm32mp_bsec_write,
	561	};
	562
d1998a9f	563	static int stm32mp_bsec_of_to_plat(struct udevice *dev)
19f58992	564	{
8a8d24bd	565	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
19f58992 PD	566
	567	plat->base = (u32)dev_read_addr_ptr(dev);
	568
	569	return 0;
	570	}
	571
815bc8bc PD	572	static int stm32mp_bsec_probe(struct udevice *dev)
	573	{
	574	int otp;
8a8d24bd	575	struct stm32mp_bsec_plat *plat;
622c956c PD	576	struct clk_bulk clk_bulk;
	577	int ret;
	578
	579	ret = clk_get_bulk(dev, &clk_bulk);
	580	if (!ret) {
	581	ret = clk_enable_bulk(&clk_bulk);
	582	if (ret)
	583	return ret;
	584	}
815bc8bc	585
95bd49a5 PD	586	/*
95bd49a5 PD	587	* update unlocked shadow for OTP cleared by the rom code
9788708f	588	* only executed in SPL, it is done in TF-A for TFABOOT
95bd49a5	589	*/
9788708f	590	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
c69cda25	591	plat = dev_get_plat(dev);
4e9e358f PD	592
	593	for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
	594	if (!bsec_read_SR_lock(plat->base, otp))
b66bfdf2	595	bsec_shadow_register(dev, plat->base, otp);
4e9e358f	596	}
815bc8bc PD	597
	598	return 0;
	599	}
815bc8bc	600
19f58992	601	static const struct udevice_id stm32mp_bsec_ids[] = {
bfe1f08f	602	{ .compatible = "st,stm32mp15-bsec" },
19f58992 PD	603	{}
	604	};
	605
	606	U_BOOT_DRIVER(stm32mp_bsec) = {
	607	.name = "stm32mp_bsec",
	608	.id = UCLASS_MISC,
	609	.of_match = stm32mp_bsec_ids,
d1998a9f	610	.of_to_plat = stm32mp_bsec_of_to_plat,
8a8d24bd	611	.plat_auto = sizeof(struct stm32mp_bsec_plat),
19f58992	612	.ops = &stm32mp_bsec_ops,
815bc8bc	613	.probe = stm32mp_bsec_probe,
19f58992	614	};
bd3f60d2 PD	615
	616	bool bsec_dbgswenable(void)
	617	{
	618	struct udevice *dev;
8a8d24bd	619	struct stm32mp_bsec_plat *plat;
bd3f60d2 PD	620	int ret;
	621
	622	ret = uclass_get_device_by_driver(UCLASS_MISC,
65e25bea	623	DM_DRIVER_GET(stm32mp_bsec), &dev);
bd3f60d2	624	if (ret \|\| !dev) {
b66bfdf2	625	log_debug("bsec driver not available\n");
bd3f60d2 PD	626	return false;
	627	}
	628
c69cda25	629	plat = dev_get_plat(dev);
bd3f60d2 PD	630	if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
	631	return true;
	632
	633	return false;
	634	}
3865a7ec PD	635
	636	u32 get_otp(int index, int shift, int mask)
	637	{
	638	int ret;
	639	struct udevice *dev;
	640	u32 otp = 0;
	641
	642	ret = uclass_get_device_by_driver(UCLASS_MISC,
	643	DM_DRIVER_GET(stm32mp_bsec),
	644	&dev);
	645
	646	if (!ret)
	647	ret = misc_read(dev, STM32_BSEC_SHADOW(index),
	648	&otp, sizeof(otp));
	649
	650	return (otp >> shift) & mask;
	651	}