[J-u-boot.git] / arch / arm / mach-stm32mp / bsec.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
 */

#define LOG_CATEGORY UCLASS_MISC

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
#include <misc.h>
#include <asm/io.h>
#include <asm/arch/bsec.h>
#include <asm/arch/stm32mp1_smc.h>
#include <dm/device_compat.h>
#include <linux/arm-smccc.h>
#include <linux/iopoll.h>

#define BSEC_OTP_MAX_VALUE		95
#define BSEC_TIMEOUT_US			10000

/* BSEC REGISTER OFFSET (base relative) */
#define BSEC_OTP_CONF_OFF		0x000
#define BSEC_OTP_CTRL_OFF		0x004
#define BSEC_OTP_WRDATA_OFF		0x008
#define BSEC_OTP_STATUS_OFF		0x00C
#define BSEC_OTP_LOCK_OFF		0x010
#define BSEC_DENABLE_OFF		0x014
#define BSEC_DISTURBED_OFF		0x01C
#define BSEC_ERROR_OFF			0x034
#define BSEC_WRLOCK_OFF			0x04C /* OTP write permananet lock */
#define BSEC_SPLOCK_OFF			0x064 /* OTP write sticky lock */
#define BSEC_SWLOCK_OFF			0x07C /* shadow write sticky lock */
#define BSEC_SRLOCK_OFF			0x094 /* shadow read sticky lock */
#define BSEC_OTP_DATA_OFF		0x200

/* BSEC_CONFIGURATION Register MASK */
#define BSEC_CONF_POWER_UP		0x001

/* BSEC_CONTROL Register */
#define BSEC_READ			0x000
#define BSEC_WRITE			0x100

/* LOCK Register */
#define OTP_LOCK_MASK			0x1F
#define OTP_LOCK_BANK_SHIFT		0x05
#define OTP_LOCK_BIT_MASK		0x01

/* STATUS Register */
#define BSEC_MODE_BUSY_MASK		0x08
#define BSEC_MODE_PROGFAIL_MASK		0x10
#define BSEC_MODE_PWR_MASK		0x20

/* DENABLE Register */
#define BSEC_DENABLE_DBGSWENABLE	BIT(10)

/*
 * OTP Lock services definition
 * Value must corresponding to the bit number in the register
 */
#define BSEC_LOCK_PROGRAM		0x04

/**
 * bsec_lock() - manage lock for each type SR/SP/SW
 * @address: address of bsec IP register
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: true if locked else false
 */
static bool bsec_read_lock(u32 address, u32 otp)
{
	u32 bit;
	u32 bank;

	bit = 1 << (otp & OTP_LOCK_MASK);
	bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);

	return !!(readl(address + bank) & bit);
}

/**
 * bsec_check_error() - Check status of one otp
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error, -EAGAIN or -ENOTSUPP
 */
static u32 bsec_check_error(u32 base, u32 otp)
{
	u32 bit;
	u32 bank;

	bit = 1 << (otp & OTP_LOCK_MASK);
	bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);

	if (readl(base + BSEC_DISTURBED_OFF + bank) & bit)
		return -EAGAIN;
	else if (readl(base + BSEC_ERROR_OFF + bank) & bit)
		return -ENOTSUPP;

	return 0;
}

/**
 * bsec_read_SR_lock() - read SR lock (Shadowing)
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: true if locked else false
 */
static bool bsec_read_SR_lock(u32 base, u32 otp)
{
	return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
}

/**
 * bsec_read_SP_lock() - read SP lock (program Lock)
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: true if locked else false
 */
static bool bsec_read_SP_lock(u32 base, u32 otp)
{
	return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
}

/**
 * bsec_SW_lock() - manage SW lock (Write in Shadow)
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: true if locked else false
 */
static bool bsec_read_SW_lock(u32 base, u32 otp)
{
	return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
}

/**
 * bsec_power_safmem() - Activate or deactivate safmem power
 * @base: base address of bsec IP
 * @power: true to power up , false to power down
 * Return: 0 if succeed
 */
static int bsec_power_safmem(u32 base, bool power)
{
	u32 val;
	u32 mask;

	if (power) {
		setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
		mask = BSEC_MODE_PWR_MASK;
	} else {
		clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
		mask = 0;
	}

	/* waiting loop */
	return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
				  val, (val & BSEC_MODE_PWR_MASK) == mask,
				  BSEC_TIMEOUT_US);
}

/**
 * bsec_shadow_register() - copy safmen otp to bsec data
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error
 */
static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
{
	u32 val;
	int ret;
	bool power_up = false;

	/* check if shadowing of otp is locked */
	if (bsec_read_SR_lock(base, otp))
		dev_dbg(dev, "OTP %d is locked and refreshed with 0\n",
			otp);

	/* check if safemem is power up */
	val = readl(base + BSEC_OTP_STATUS_OFF);
	if (!(val & BSEC_MODE_PWR_MASK)) {
		ret = bsec_power_safmem(base, true);
		if (ret)
			return ret;
		power_up = true;
	}
	/* set BSEC_OTP_CTRL_OFF with the otp value*/
	writel(otp | BSEC_READ, base + BSEC_OTP_CTRL_OFF);

	/* check otp status*/
	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
				 val, (val & BSEC_MODE_BUSY_MASK) == 0,
				 BSEC_TIMEOUT_US);
	if (ret)
		return ret;

	ret = bsec_check_error(base, otp);

	if (power_up)
		bsec_power_safmem(base, false);

	return ret;
}

/**
 * bsec_read_shadow() - read an otp data value from shadow
 * @base: base address of bsec IP
 * @val: read value
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error
 */
static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp)
{
	*val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));

	return bsec_check_error(base, otp);
}

/**
 * bsec_write_shadow() - write value in BSEC data register in shadow
 * @base: base address of bsec IP
 * @val: value to write
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error
 */
static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
{
	/* check if programming of otp is locked */
	if (bsec_read_SW_lock(base, otp))
		dev_dbg(dev, "OTP %d is lock, write will be ignore\n", otp);

	writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));

	return bsec_check_error(base, otp);
}

/**
 * bsec_program_otp() - program a bit in SAFMEM
 * @base: base address of bsec IP
 * @val: value to program
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * after the function the otp data is not refreshed in shadow
 * Return: 0 if no error
 */
static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
{
	u32 ret;
	bool power_up = false;

	if (bsec_read_SP_lock(base, otp))
		dev_dbg(dev, "OTP %d locked, prog will be ignore\n", otp);

	if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
		dev_dbg(dev, "Global lock, prog will be ignore\n");

	/* check if safemem is power up */
	if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
		ret = bsec_power_safmem(base, true);
		if (ret)
			return ret;

		power_up = true;
	}
	/* set value in write register*/
	writel(val, base + BSEC_OTP_WRDATA_OFF);

	/* set BSEC_OTP_CTRL_OFF with the otp value */
	writel(otp | BSEC_WRITE, base + BSEC_OTP_CTRL_OFF);

	/* check otp status*/
	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
				 val, (val & BSEC_MODE_BUSY_MASK) == 0,
				 BSEC_TIMEOUT_US);
	if (ret)
		return ret;

	if (val & BSEC_MODE_PROGFAIL_MASK)
		ret = -EACCES;
	else
		ret = bsec_check_error(base, otp);

	if (power_up)
		bsec_power_safmem(base, false);

	return ret;
}

/* BSEC MISC driver *******************************************************/
struct stm32mp_bsec_plat {
	u32 base;
};

static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;
	u32 tmp_data = 0;
	int ret;

	if (IS_ENABLED(CONFIG_TFABOOT))
		return stm32_smc(STM32_SMC_BSEC,
				 STM32_SMC_READ_OTP,
				 otp, 0, val);

	plat = dev_get_plat(dev);

	/* read current shadow value */
	ret = bsec_read_shadow(dev, plat->base, &tmp_data, otp);
	if (ret)
		return ret;

	/* copy otp in shadow */
	ret = bsec_shadow_register(dev, plat->base, otp);
	if (ret)
		return ret;

	ret = bsec_read_shadow(dev, plat->base, val, otp);
	if (ret)
		return ret;

	/* restore shadow value */
	ret = bsec_write_shadow(dev, plat->base, tmp_data, otp);

	return ret;
}

static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;

	if (IS_ENABLED(CONFIG_TFABOOT))
		return stm32_smc(STM32_SMC_BSEC,
				 STM32_SMC_READ_SHADOW,
				 otp, 0, val);

	plat = dev_get_plat(dev);

	return bsec_read_shadow(dev, plat->base, val, otp);
}

static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
{
	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);

	/* return OTP permanent write lock status */
	*val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);

	return 0;
}

static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;

	if (IS_ENABLED(CONFIG_TFABOOT))
		return stm32_smc_exec(STM32_SMC_BSEC,
				      STM32_SMC_PROG_OTP,
				      otp, val);

	plat = dev_get_plat(dev);

	return bsec_program_otp(dev, plat->base, val, otp);

}

static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;

	if (IS_ENABLED(CONFIG_TFABOOT))
		return stm32_smc_exec(STM32_SMC_BSEC,
				      STM32_SMC_WRITE_SHADOW,
				      otp, val);

	plat = dev_get_plat(dev);

	return bsec_write_shadow(dev, plat->base, val, otp);
}

static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
{
	if (!IS_ENABLED(CONFIG_TFABOOT))
		return -ENOTSUPP;

	if (val == 1)
		return stm32_smc_exec(STM32_SMC_BSEC,
				      STM32_SMC_WRLOCK_OTP,
				      otp, 0);
	if (val == 0)
		return 0; /* nothing to do */

	return -EINVAL;
}

static int stm32mp_bsec_read(struct udevice *dev, int offset,
			     void *buf, int size)
{
	int ret;
	int i;
	bool shadow = true, lock = false;
	int nb_otp = size / sizeof(u32);
	int otp;
	unsigned int offs = offset;

	if (offs >= STM32_BSEC_LOCK_OFFSET) {
		offs -= STM32_BSEC_LOCK_OFFSET;
		lock = true;
	} else if (offs >= STM32_BSEC_OTP_OFFSET) {
		offs -= STM32_BSEC_OTP_OFFSET;
		shadow = false;
	}

	if ((offs % 4) || (size % 4))
		return -EINVAL;

	otp = offs / sizeof(u32);

	for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
		u32 *addr = &((u32 *)buf)[i - otp];

		if (lock)
			ret = stm32mp_bsec_read_lock(dev, addr, i);
		else if (shadow)
			ret = stm32mp_bsec_read_shadow(dev, addr, i);
		else
			ret = stm32mp_bsec_read_otp(dev, addr, i);

		if (ret)
			break;
	}
	if (ret)
		return ret;
	else
		return (i - otp) * 4;
}

static int stm32mp_bsec_write(struct udevice *dev, int offset,
			      const void *buf, int size)
{
	int ret = 0;
	int i;
	bool shadow = true, lock = false;
	int nb_otp = size / sizeof(u32);
	int otp;
	unsigned int offs = offset;

	if (offs >= STM32_BSEC_LOCK_OFFSET) {
		offs -= STM32_BSEC_LOCK_OFFSET;
		lock = true;
	} else if (offs >= STM32_BSEC_OTP_OFFSET) {
		offs -= STM32_BSEC_OTP_OFFSET;
		shadow = false;
	}

	if ((offs % 4) || (size % 4))
		return -EINVAL;

	otp = offs / sizeof(u32);

	for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
		u32 *val = &((u32 *)buf)[i - otp];

		if (lock)
			ret = stm32mp_bsec_write_lock(dev, *val, i);
		else if (shadow)
			ret = stm32mp_bsec_write_shadow(dev, *val, i);
		else
			ret = stm32mp_bsec_write_otp(dev, *val, i);
		if (ret)
			break;
	}
	if (ret)
		return ret;
	else
		return (i - otp) * 4;
}

static const struct misc_ops stm32mp_bsec_ops = {
	.read = stm32mp_bsec_read,
	.write = stm32mp_bsec_write,
};

static int stm32mp_bsec_of_to_plat(struct udevice *dev)
{
	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);

	plat->base = (u32)dev_read_addr_ptr(dev);

	return 0;
}

static int stm32mp_bsec_probe(struct udevice *dev)
{
	int otp;
	struct stm32mp_bsec_plat *plat;
	struct clk_bulk clk_bulk;
	int ret;

	ret = clk_get_bulk(dev, &clk_bulk);
	if (!ret) {
		ret = clk_enable_bulk(&clk_bulk);
		if (ret)
			return ret;
	}

	/*
	 * update unlocked shadow for OTP cleared by the rom code
	 * only executed in U-Boot proper when TF-A is not used
	 */

	if (!IS_ENABLED(CONFIG_TFABOOT) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
		plat = dev_get_plat(dev);

		for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
			if (!bsec_read_SR_lock(plat->base, otp))
				bsec_shadow_register(dev, plat->base, otp);
	}

	return 0;
}

static const struct udevice_id stm32mp_bsec_ids[] = {
	{ .compatible = "st,stm32mp15-bsec" },
	{}
};

U_BOOT_DRIVER(stm32mp_bsec) = {
	.name = "stm32mp_bsec",
	.id = UCLASS_MISC,
	.of_match = stm32mp_bsec_ids,
	.of_to_plat = stm32mp_bsec_of_to_plat,
	.plat_auto	= sizeof(struct stm32mp_bsec_plat),
	.ops = &stm32mp_bsec_ops,
	.probe = stm32mp_bsec_probe,
};

bool bsec_dbgswenable(void)
{
	struct udevice *dev;
	struct stm32mp_bsec_plat *plat;
	int ret;

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_DRIVER_GET(stm32mp_bsec), &dev);
	if (ret || !dev) {
		log_debug("bsec driver not available\n");
		return false;
	}

	plat = dev_get_plat(dev);
	if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
		return true;

	return false;
}
Commit	Line	Data
19f58992 PD	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
	4	*/
	5
b66bfdf2 PD	6	#define LOG_CATEGORY UCLASS_MISC
b66bfdf2 PD	7
19f58992	8	#include <common.h>
622c956c	9	#include <clk.h>
19f58992	10	#include <dm.h>
f7ae49fc	11	#include <log.h>
19f58992 PD	12	#include <misc.h>
19f58992 PD	13	#include <asm/io.h>
bd3f60d2	14	#include <asm/arch/bsec.h>
d859c611	15	#include <asm/arch/stm32mp1_smc.h>
b66bfdf2	16	#include <dm/device_compat.h>
d859c611	17	#include <linux/arm-smccc.h>
ee7d7723	18	#include <linux/iopoll.h>
19f58992 PD	19
19f58992 PD	20	#define BSEC_OTP_MAX_VALUE 95
19f58992 PD	21	#define BSEC_TIMEOUT_US 10000
	22
	23	/* BSEC REGISTER OFFSET (base relative) */
	24	#define BSEC_OTP_CONF_OFF 0x000
	25	#define BSEC_OTP_CTRL_OFF 0x004
	26	#define BSEC_OTP_WRDATA_OFF 0x008
	27	#define BSEC_OTP_STATUS_OFF 0x00C
	28	#define BSEC_OTP_LOCK_OFF 0x010
bd3f60d2	29	#define BSEC_DENABLE_OFF 0x014
19f58992 PD	30	#define BSEC_DISTURBED_OFF 0x01C
19f58992 PD	31	#define BSEC_ERROR_OFF 0x034
7ae22d72 PD	32	#define BSEC_WRLOCK_OFF 0x04C /* OTP write permananet lock */
	33	#define BSEC_SPLOCK_OFF 0x064 /* OTP write sticky lock */
	34	#define BSEC_SWLOCK_OFF 0x07C /* shadow write sticky lock */
	35	#define BSEC_SRLOCK_OFF 0x094 /* shadow read sticky lock */
19f58992 PD	36	#define BSEC_OTP_DATA_OFF 0x200
	37
	38	/* BSEC_CONFIGURATION Register MASK */
	39	#define BSEC_CONF_POWER_UP 0x001
	40
	41	/* BSEC_CONTROL Register */
	42	#define BSEC_READ 0x000
	43	#define BSEC_WRITE 0x100
	44
	45	/* LOCK Register */
	46	#define OTP_LOCK_MASK 0x1F
	47	#define OTP_LOCK_BANK_SHIFT 0x05
	48	#define OTP_LOCK_BIT_MASK 0x01
	49
	50	/* STATUS Register */
	51	#define BSEC_MODE_BUSY_MASK 0x08
	52	#define BSEC_MODE_PROGFAIL_MASK 0x10
	53	#define BSEC_MODE_PWR_MASK 0x20
	54
bd3f60d2 PD	55	/* DENABLE Register */
	56	#define BSEC_DENABLE_DBGSWENABLE BIT(10)
	57
19f58992 PD	58	/*
	59	* OTP Lock services definition
	60	* Value must corresponding to the bit number in the register
	61	*/
	62	#define BSEC_LOCK_PROGRAM 0x04
	63
	64	/**
7ae22d72 PD	65	* bsec_lock() - manage lock for each type SR/SP/SW
7ae22d72 PD	66	* @address: address of bsec IP register
19f58992	67	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
7ae22d72	68	* Return: true if locked else false
19f58992	69	*/
7ae22d72	70	static bool bsec_read_lock(u32 address, u32 otp)
19f58992 PD	71	{
	72	u32 bit;
	73	u32 bank;
	74
	75	bit = 1 << (otp & OTP_LOCK_MASK);
	76	bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
	77
7ae22d72	78	return !!(readl(address + bank) & bit);
19f58992 PD	79	}
	80
	81	/**
7ae22d72 PD	82	* bsec_check_error() - Check status of one otp
7ae22d72 PD	83	* @base: base address of bsec IP
19f58992	84	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
7ae22d72	85	* Return: 0 if no error, -EAGAIN or -ENOTSUPP
19f58992	86	*/
7ae22d72	87	static u32 bsec_check_error(u32 base, u32 otp)
19f58992 PD	88	{
	89	u32 bit;
	90	u32 bank;
	91
	92	bit = 1 << (otp & OTP_LOCK_MASK);
	93	bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
	94
7ae22d72 PD	95	if (readl(base + BSEC_DISTURBED_OFF + bank) & bit)
	96	return -EAGAIN;
	97	else if (readl(base + BSEC_ERROR_OFF + bank) & bit)
	98	return -ENOTSUPP;
	99
	100	return 0;
19f58992 PD	101	}
	102
	103	/**
	104	* bsec_read_SR_lock() - read SR lock (Shadowing)
	105	* @base: base address of bsec IP
	106	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	107	* Return: true if locked else false
	108	*/
	109	static bool bsec_read_SR_lock(u32 base, u32 otp)
	110	{
	111	return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
	112	}
	113
	114	/**
	115	* bsec_read_SP_lock() - read SP lock (program Lock)
	116	* @base: base address of bsec IP
	117	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	118	* Return: true if locked else false
	119	*/
	120	static bool bsec_read_SP_lock(u32 base, u32 otp)
	121	{
	122	return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
	123	}
	124
	125	/**
	126	* bsec_SW_lock() - manage SW lock (Write in Shadow)
	127	* @base: base address of bsec IP
	128	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	129	* Return: true if locked else false
	130	*/
	131	static bool bsec_read_SW_lock(u32 base, u32 otp)
	132	{
	133	return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
	134	}
	135
	136	/**
	137	* bsec_power_safmem() - Activate or deactivate safmem power
	138	* @base: base address of bsec IP
	139	* @power: true to power up , false to power down
	140	* Return: 0 if succeed
	141	*/
	142	static int bsec_power_safmem(u32 base, bool power)
	143	{
	144	u32 val;
	145	u32 mask;
	146
	147	if (power) {
	148	setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
	149	mask = BSEC_MODE_PWR_MASK;
	150	} else {
	151	clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
	152	mask = 0;
	153	}
	154
	155	/* waiting loop */
	156	return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
	157	val, (val & BSEC_MODE_PWR_MASK) == mask,
	158	BSEC_TIMEOUT_US);
	159	}
	160
	161	/**
	162	* bsec_shadow_register() - copy safmen otp to bsec data
	163	* @base: base address of bsec IP
	164	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
165	* Return: 0 if no error
166	*/
b66bfdf2	167	static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
19f58992 PD	168	{
	169	u32 val;
	170	int ret;
	171	bool power_up = false;
	172
	173	/* check if shadowing of otp is locked */
	174	if (bsec_read_SR_lock(base, otp))
b66bfdf2 PD	175	dev_dbg(dev, "OTP %d is locked and refreshed with 0\n",
b66bfdf2 PD	176	otp);
19f58992 PD	177
	178	/* check if safemem is power up */
	179	val = readl(base + BSEC_OTP_STATUS_OFF);
	180	if (!(val & BSEC_MODE_PWR_MASK)) {
	181	ret = bsec_power_safmem(base, true);
	182	if (ret)
	183	return ret;
815bc8bc	184	power_up = true;
19f58992 PD	185	}
	186	/* set BSEC_OTP_CTRL_OFF with the otp value*/
	187	writel(otp \| BSEC_READ, base + BSEC_OTP_CTRL_OFF);
	188
	189	/* check otp status*/
	190	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
	191	val, (val & BSEC_MODE_BUSY_MASK) == 0,
	192	BSEC_TIMEOUT_US);
	193	if (ret)
	194	return ret;
	195
	196	ret = bsec_check_error(base, otp);
	197
	198	if (power_up)
	199	bsec_power_safmem(base, false);
	200
	201	return ret;
	202	}
	203
	204	/**
	205	* bsec_read_shadow() - read an otp data value from shadow
	206	* @base: base address of bsec IP
	207	* @val: read value
	208	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	209	* Return: 0 if no error
	210	*/
b66bfdf2	211	static int bsec_read_shadow(struct udevice dev, u32 base, u32 val, u32 otp)
19f58992 PD	212	{
	213	val = readl(base + BSEC_OTP_DATA_OFF + otp sizeof(u32));
	214
	215	return bsec_check_error(base, otp);
	216	}
	217
	218	/**
	219	* bsec_write_shadow() - write value in BSEC data register in shadow
	220	* @base: base address of bsec IP
	221	* @val: value to write
	222	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	223	* Return: 0 if no error
	224	*/
b66bfdf2	225	static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
19f58992 PD	226	{
	227	/* check if programming of otp is locked */
	228	if (bsec_read_SW_lock(base, otp))
b66bfdf2	229	dev_dbg(dev, "OTP %d is lock, write will be ignore\n", otp);
19f58992 PD	230
	231	writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
	232
	233	return bsec_check_error(base, otp);
	234	}
	235
	236	/**
	237	* bsec_program_otp() - program a bit in SAFMEM
	238	* @base: base address of bsec IP
	239	* @val: value to program
	240	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	241	* after the function the otp data is not refreshed in shadow
	242	* Return: 0 if no error
	243	*/
b66bfdf2	244	static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
19f58992 PD	245	{
	246	u32 ret;
	247	bool power_up = false;
	248
	249	if (bsec_read_SP_lock(base, otp))
b66bfdf2	250	dev_dbg(dev, "OTP %d locked, prog will be ignore\n", otp);
19f58992 PD	251
19f58992 PD	252	if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
b66bfdf2	253	dev_dbg(dev, "Global lock, prog will be ignore\n");
19f58992 PD	254
	255	/* check if safemem is power up */
	256	if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
	257	ret = bsec_power_safmem(base, true);
	258	if (ret)
	259	return ret;
	260
	261	power_up = true;
	262	}
	263	/* set value in write register*/
	264	writel(val, base + BSEC_OTP_WRDATA_OFF);
	265
	266	/* set BSEC_OTP_CTRL_OFF with the otp value */
	267	writel(otp \| BSEC_WRITE, base + BSEC_OTP_CTRL_OFF);
	268
	269	/* check otp status*/
	270	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
	271	val, (val & BSEC_MODE_BUSY_MASK) == 0,
	272	BSEC_TIMEOUT_US);
	273	if (ret)
	274	return ret;
	275
	276	if (val & BSEC_MODE_PROGFAIL_MASK)
	277	ret = -EACCES;
	278	else
	279	ret = bsec_check_error(base, otp);
	280
	281	if (power_up)
	282	bsec_power_safmem(base, false);
	283
	284	return ret;
	285	}
	286
	287	/* BSEC MISC driver *******************************************************/
8a8d24bd	288	struct stm32mp_bsec_plat {
19f58992 PD	289	u32 base;
	290	};
	291
	292	static int stm32mp_bsec_read_otp(struct udevice dev, u32 val, u32 otp)
	293	{
8a8d24bd	294	struct stm32mp_bsec_plat *plat;
19f58992 PD	295	u32 tmp_data = 0;
	296	int ret;
	297
4e9e358f PD	298	if (IS_ENABLED(CONFIG_TFABOOT))
	299	return stm32_smc(STM32_SMC_BSEC,
	300	STM32_SMC_READ_OTP,
	301	otp, 0, val);
	302
c69cda25	303	plat = dev_get_plat(dev);
4e9e358f	304
19f58992	305	/* read current shadow value */
b66bfdf2	306	ret = bsec_read_shadow(dev, plat->base, &tmp_data, otp);
19f58992 PD	307	if (ret)
	308	return ret;
	309
	310	/* copy otp in shadow */
b66bfdf2	311	ret = bsec_shadow_register(dev, plat->base, otp);
19f58992 PD	312	if (ret)
	313	return ret;
	314
b66bfdf2	315	ret = bsec_read_shadow(dev, plat->base, val, otp);
19f58992 PD	316	if (ret)
	317	return ret;
	318
	319	/* restore shadow value */
b66bfdf2	320	ret = bsec_write_shadow(dev, plat->base, tmp_data, otp);
4e9e358f	321
19f58992 PD	322	return ret;
	323	}
	324
	325	static int stm32mp_bsec_read_shadow(struct udevice dev, u32 val, u32 otp)
	326	{
8a8d24bd	327	struct stm32mp_bsec_plat *plat;
4e9e358f PD	328
	329	if (IS_ENABLED(CONFIG_TFABOOT))
	330	return stm32_smc(STM32_SMC_BSEC,
	331	STM32_SMC_READ_SHADOW,
	332	otp, 0, val);
	333
c69cda25	334	plat = dev_get_plat(dev);
19f58992	335
b66bfdf2	336	return bsec_read_shadow(dev, plat->base, val, otp);
19f58992 PD	337	}
19f58992 PD	338
7ae22d72 PD	339	static int stm32mp_bsec_read_lock(struct udevice dev, u32 val, u32 otp)
7ae22d72 PD	340	{
8a8d24bd	341	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
7ae22d72 PD	342
	343	/* return OTP permanent write lock status */
	344	*val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
	345
	346	return 0;
	347	}
	348
19f58992 PD	349	static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
19f58992 PD	350	{
8a8d24bd	351	struct stm32mp_bsec_plat *plat;
4e9e358f PD	352
	353	if (IS_ENABLED(CONFIG_TFABOOT))
	354	return stm32_smc_exec(STM32_SMC_BSEC,
	355	STM32_SMC_PROG_OTP,
	356	otp, val);
	357
c69cda25	358	plat = dev_get_plat(dev);
19f58992	359
b66bfdf2	360	return bsec_program_otp(dev, plat->base, val, otp);
4e9e358f	361
19f58992 PD	362	}
	363
	364	static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
	365	{
8a8d24bd	366	struct stm32mp_bsec_plat *plat;
4e9e358f PD	367
	368	if (IS_ENABLED(CONFIG_TFABOOT))
	369	return stm32_smc_exec(STM32_SMC_BSEC,
	370	STM32_SMC_WRITE_SHADOW,
	371	otp, val);
	372
c69cda25	373	plat = dev_get_plat(dev);
19f58992	374
b66bfdf2	375	return bsec_write_shadow(dev, plat->base, val, otp);
19f58992 PD	376	}
19f58992 PD	377
7ae22d72 PD	378	static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
7ae22d72 PD	379	{
4e9e358f PD	380	if (!IS_ENABLED(CONFIG_TFABOOT))
	381	return -ENOTSUPP;
	382
7ae22d72 PD	383	if (val == 1)
	384	return stm32_smc_exec(STM32_SMC_BSEC,
	385	STM32_SMC_WRLOCK_OTP,
	386	otp, 0);
	387	if (val == 0)
	388	return 0; /* nothing to do */
	389
	390	return -EINVAL;
7ae22d72 PD	391	}
7ae22d72 PD	392
19f58992 PD	393	static int stm32mp_bsec_read(struct udevice *dev, int offset,
	394	void *buf, int size)
	395	{
	396	int ret;
	397	int i;
7ae22d72	398	bool shadow = true, lock = false;
19f58992 PD	399	int nb_otp = size / sizeof(u32);
19f58992 PD	400	int otp;
745b676d	401	unsigned int offs = offset;
19f58992	402
7ae22d72 PD	403	if (offs >= STM32_BSEC_LOCK_OFFSET) {
	404	offs -= STM32_BSEC_LOCK_OFFSET;
	405	lock = true;
	406	} else if (offs >= STM32_BSEC_OTP_OFFSET) {
745b676d	407	offs -= STM32_BSEC_OTP_OFFSET;
19f58992 PD	408	shadow = false;
19f58992 PD	409	}
19f58992	410
df2d1b8f	411	if ((offs % 4) \|\| (size % 4))
19f58992	412	return -EINVAL;
19f58992	413
0c8620d2 PD	414	otp = offs / sizeof(u32);
	415
	416	for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
19f58992 PD	417	u32 addr = &((u32 )buf)[i - otp];
19f58992 PD	418
7ae22d72 PD	419	if (lock)
	420	ret = stm32mp_bsec_read_lock(dev, addr, i);
	421	else if (shadow)
19f58992 PD	422	ret = stm32mp_bsec_read_shadow(dev, addr, i);
	423	else
	424	ret = stm32mp_bsec_read_otp(dev, addr, i);
	425
	426	if (ret)
	427	break;
	428	}
0c8620d2 PD	429	if (ret)
	430	return ret;
	431	else
	432	return (i - otp) * 4;
19f58992 PD	433	}
	434
	435	static int stm32mp_bsec_write(struct udevice *dev, int offset,
	436	const void *buf, int size)
	437	{
	438	int ret = 0;
	439	int i;
7ae22d72	440	bool shadow = true, lock = false;
19f58992 PD	441	int nb_otp = size / sizeof(u32);
19f58992 PD	442	int otp;
745b676d	443	unsigned int offs = offset;
19f58992	444
7ae22d72 PD	445	if (offs >= STM32_BSEC_LOCK_OFFSET) {
	446	offs -= STM32_BSEC_LOCK_OFFSET;
	447	lock = true;
	448	} else if (offs >= STM32_BSEC_OTP_OFFSET) {
745b676d	449	offs -= STM32_BSEC_OTP_OFFSET;
19f58992 PD	450	shadow = false;
19f58992 PD	451	}
19f58992	452
df2d1b8f	453	if ((offs % 4) \|\| (size % 4))
19f58992	454	return -EINVAL;
19f58992	455
0c8620d2 PD	456	otp = offs / sizeof(u32);
	457
	458	for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
19f58992 PD	459	u32 val = &((u32 )buf)[i - otp];
19f58992 PD	460
7ae22d72 PD	461	if (lock)
	462	ret = stm32mp_bsec_write_lock(dev, *val, i);
	463	else if (shadow)
19f58992 PD	464	ret = stm32mp_bsec_write_shadow(dev, *val, i);
	465	else
	466	ret = stm32mp_bsec_write_otp(dev, *val, i);
	467	if (ret)
	468	break;
	469	}
0c8620d2 PD	470	if (ret)
	471	return ret;
	472	else
	473	return (i - otp) * 4;
19f58992 PD	474	}
	475
	476	static const struct misc_ops stm32mp_bsec_ops = {
	477	.read = stm32mp_bsec_read,
	478	.write = stm32mp_bsec_write,
	479	};
	480
d1998a9f	481	static int stm32mp_bsec_of_to_plat(struct udevice *dev)
19f58992	482	{
8a8d24bd	483	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
19f58992 PD	484
	485	plat->base = (u32)dev_read_addr_ptr(dev);
	486
	487	return 0;
	488	}
	489
815bc8bc PD	490	static int stm32mp_bsec_probe(struct udevice *dev)
	491	{
	492	int otp;
8a8d24bd	493	struct stm32mp_bsec_plat *plat;
622c956c PD	494	struct clk_bulk clk_bulk;
	495	int ret;
	496
	497	ret = clk_get_bulk(dev, &clk_bulk);
	498	if (!ret) {
	499	ret = clk_enable_bulk(&clk_bulk);
	500	if (ret)
	501	return ret;
	502	}
815bc8bc	503
95bd49a5 PD	504	/*
	505	* update unlocked shadow for OTP cleared by the rom code
	506	* only executed in U-Boot proper when TF-A is not used
	507	*/
4e9e358f PD	508
4e9e358f PD	509	if (!IS_ENABLED(CONFIG_TFABOOT) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
c69cda25	510	plat = dev_get_plat(dev);
4e9e358f PD	511
	512	for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
	513	if (!bsec_read_SR_lock(plat->base, otp))
b66bfdf2	514	bsec_shadow_register(dev, plat->base, otp);
4e9e358f	515	}
815bc8bc PD	516
	517	return 0;
	518	}
815bc8bc	519
19f58992	520	static const struct udevice_id stm32mp_bsec_ids[] = {
bfe1f08f	521	{ .compatible = "st,stm32mp15-bsec" },
19f58992 PD	522	{}
	523	};
	524
	525	U_BOOT_DRIVER(stm32mp_bsec) = {
	526	.name = "stm32mp_bsec",
	527	.id = UCLASS_MISC,
	528	.of_match = stm32mp_bsec_ids,
d1998a9f	529	.of_to_plat = stm32mp_bsec_of_to_plat,
8a8d24bd	530	.plat_auto = sizeof(struct stm32mp_bsec_plat),
19f58992	531	.ops = &stm32mp_bsec_ops,
815bc8bc	532	.probe = stm32mp_bsec_probe,
19f58992	533	};
bd3f60d2 PD	534
	535	bool bsec_dbgswenable(void)
	536	{
	537	struct udevice *dev;
8a8d24bd	538	struct stm32mp_bsec_plat *plat;
bd3f60d2 PD	539	int ret;
	540
	541	ret = uclass_get_device_by_driver(UCLASS_MISC,
65e25bea	542	DM_DRIVER_GET(stm32mp_bsec), &dev);
bd3f60d2	543	if (ret \|\| !dev) {
b66bfdf2	544	log_debug("bsec driver not available\n");
bd3f60d2 PD	545	return false;
	546	}
	547
c69cda25	548	plat = dev_get_plat(dev);
bd3f60d2 PD	549	if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
	550	return true;
	551
	552	return false;
	553	}