[J-u-boot.git] / arch / arm / mach-stm32mp / bsec.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
 */

#define LOG_CATEGORY UCLASS_MISC

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <log.h>
#include <misc.h>
#include <asm/io.h>
#include <asm/arch/bsec.h>
#include <asm/arch/stm32mp1_smc.h>
#include <dm/device_compat.h>
#include <linux/arm-smccc.h>
#include <linux/iopoll.h>

#define BSEC_OTP_MAX_VALUE		95
#define BSEC_OTP_UPPER_START		32
#define BSEC_TIMEOUT_US			10000

/* BSEC REGISTER OFFSET (base relative) */
#define BSEC_OTP_CONF_OFF		0x000
#define BSEC_OTP_CTRL_OFF		0x004
#define BSEC_OTP_WRDATA_OFF		0x008
#define BSEC_OTP_STATUS_OFF		0x00C
#define BSEC_OTP_LOCK_OFF		0x010
#define BSEC_DENABLE_OFF		0x014
#define BSEC_DISTURBED_OFF		0x01C
#define BSEC_ERROR_OFF			0x034
#define BSEC_WRLOCK_OFF			0x04C /* OTP write permananet lock */
#define BSEC_SPLOCK_OFF			0x064 /* OTP write sticky lock */
#define BSEC_SWLOCK_OFF			0x07C /* shadow write sticky lock */
#define BSEC_SRLOCK_OFF			0x094 /* shadow read sticky lock */
#define BSEC_OTP_DATA_OFF		0x200

/* BSEC_CONFIGURATION Register MASK */
#define BSEC_CONF_POWER_UP		0x001

/* BSEC_CONTROL Register */
#define BSEC_READ			0x000
#define BSEC_WRITE			0x100
#define BSEC_LOCK			0x200

/* LOCK Register */
#define OTP_LOCK_MASK			0x1F
#define OTP_LOCK_BANK_SHIFT		0x05
#define OTP_LOCK_BIT_MASK		0x01

/* STATUS Register */
#define BSEC_MODE_BUSY_MASK		0x08
#define BSEC_MODE_PROGFAIL_MASK		0x10
#define BSEC_MODE_PWR_MASK		0x20

/* DENABLE Register */
#define BSEC_DENABLE_DBGSWENABLE	BIT(10)

/*
 * OTP Lock services definition
 * Value must corresponding to the bit number in the register
 */
#define BSEC_LOCK_PROGRAM		0x04

/*
 * OTP status: bit 0 permanent lock
 */
#define BSEC_LOCK_PERM			BIT(0)

/**
 * bsec_lock() - manage lock for each type SR/SP/SW
 * @address: address of bsec IP register
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: true if locked else false
 */
static bool bsec_read_lock(u32 address, u32 otp)
{
	u32 bit;
	u32 bank;

	bit = 1 << (otp & OTP_LOCK_MASK);
	bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);

	return !!(readl(address + bank) & bit);
}

/**
 * bsec_check_error() - Check status of one otp
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error, -EAGAIN or -ENOTSUPP
 */
static u32 bsec_check_error(u32 base, u32 otp)
{
	u32 bit;
	u32 bank;

	bit = 1 << (otp & OTP_LOCK_MASK);
	bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);

	if (readl(base + BSEC_DISTURBED_OFF + bank) & bit)
		return -EAGAIN;
	else if (readl(base + BSEC_ERROR_OFF + bank) & bit)
		return -ENOTSUPP;

	return 0;
}

/**
 * bsec_read_SR_lock() - read SR lock (Shadowing)
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: true if locked else false
 */
static bool bsec_read_SR_lock(u32 base, u32 otp)
{
	return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
}

/**
 * bsec_read_SP_lock() - read SP lock (program Lock)
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: true if locked else false
 */
static bool bsec_read_SP_lock(u32 base, u32 otp)
{
	return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
}

/**
 * bsec_SW_lock() - manage SW lock (Write in Shadow)
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: true if locked else false
 */
static bool bsec_read_SW_lock(u32 base, u32 otp)
{
	return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
}

/**
 * bsec_power_safmem() - Activate or deactivate safmem power
 * @base: base address of bsec IP
 * @power: true to power up , false to power down
 * Return: 0 if succeed
 */
static int bsec_power_safmem(u32 base, bool power)
{
	u32 val;
	u32 mask;

	if (power) {
		setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
		mask = BSEC_MODE_PWR_MASK;
	} else {
		clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
		mask = 0;
	}

	/* waiting loop */
	return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
				  val, (val & BSEC_MODE_PWR_MASK) == mask,
				  BSEC_TIMEOUT_US);
}

/**
 * bsec_shadow_register() - copy safmen otp to bsec data
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error
 */
static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
{
	u32 val;
	int ret;
	bool power_up = false;

	/* check if shadowing of otp is locked */
	if (bsec_read_SR_lock(base, otp))
		dev_dbg(dev, "OTP %d is locked and refreshed with 0\n",
			otp);

	/* check if safemem is power up */
	val = readl(base + BSEC_OTP_STATUS_OFF);
	if (!(val & BSEC_MODE_PWR_MASK)) {
		ret = bsec_power_safmem(base, true);
		if (ret)
			return ret;
		power_up = true;
	}
	/* set BSEC_OTP_CTRL_OFF with the otp value*/
	writel(otp | BSEC_READ, base + BSEC_OTP_CTRL_OFF);

	/* check otp status*/
	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
				 val, (val & BSEC_MODE_BUSY_MASK) == 0,
				 BSEC_TIMEOUT_US);
	if (ret)
		return ret;

	ret = bsec_check_error(base, otp);

	if (power_up)
		bsec_power_safmem(base, false);

	return ret;
}

/**
 * bsec_read_shadow() - read an otp data value from shadow
 * @base: base address of bsec IP
 * @val: read value
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error
 */
static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp)
{
	*val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));

	return bsec_check_error(base, otp);
}

/**
 * bsec_write_shadow() - write value in BSEC data register in shadow
 * @base: base address of bsec IP
 * @val: value to write
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error
 */
static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
{
	/* check if programming of otp is locked */
	if (bsec_read_SW_lock(base, otp))
		dev_dbg(dev, "OTP %d is lock, write will be ignore\n", otp);

	writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));

	return bsec_check_error(base, otp);
}

/**
 * bsec_program_otp() - program a bit in SAFMEM
 * @base: base address of bsec IP
 * @val: value to program
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * after the function the otp data is not refreshed in shadow
 * Return: 0 if no error
 */
static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
{
	u32 ret;
	bool power_up = false;

	if (bsec_read_SP_lock(base, otp))
		dev_dbg(dev, "OTP %d locked, prog will be ignore\n", otp);

	if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
		dev_dbg(dev, "Global lock, prog will be ignore\n");

	/* check if safemem is power up */
	if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
		ret = bsec_power_safmem(base, true);
		if (ret)
			return ret;

		power_up = true;
	}
	/* set value in write register*/
	writel(val, base + BSEC_OTP_WRDATA_OFF);

	/* set BSEC_OTP_CTRL_OFF with the otp value */
	writel(otp | BSEC_WRITE, base + BSEC_OTP_CTRL_OFF);

	/* check otp status*/
	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
				 val, (val & BSEC_MODE_BUSY_MASK) == 0,
				 BSEC_TIMEOUT_US);
	if (ret)
		return ret;

	if (val & BSEC_MODE_PROGFAIL_MASK)
		ret = -EACCES;
	else
		ret = bsec_check_error(base, otp);

	if (power_up)
		bsec_power_safmem(base, false);

	return ret;
}

/**
 * bsec_permanent_lock_otp() - permanent lock of OTP in SAFMEM
 * @dev: bsec IP device
 * @base: base address of bsec IP
 * @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
 * Return: 0 if no error
 */
static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp)
{
	int ret;
	bool power_up = false;
	u32 val, addr;

	/* check if safemem is power up */
	if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
		ret = bsec_power_safmem(base, true);
		if (ret)
			return ret;

		power_up = true;
	}

	/*
	 * low OTPs = 2 bits word for low OTPs, 1 bits per word for upper OTP
	 * and only 16 bits used in WRDATA
	 */
	if (otp < BSEC_OTP_UPPER_START) {
		addr = otp / 8;
		val = 0x03 << ((otp * 2) & 0xF);
	} else {
		addr = BSEC_OTP_UPPER_START / 8 +
		       ((otp - BSEC_OTP_UPPER_START) / 16);
		val = 0x01 << (otp & 0xF);
	}

	/* set value in write register*/
	writel(val, base + BSEC_OTP_WRDATA_OFF);

	/* set BSEC_OTP_CTRL_OFF with the otp addr and lock request*/
	writel(addr | BSEC_WRITE | BSEC_LOCK, base + BSEC_OTP_CTRL_OFF);

	/* check otp status*/
	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
				 val, (val & BSEC_MODE_BUSY_MASK) == 0,
				 BSEC_TIMEOUT_US);
	if (ret)
		return ret;

	if (val & BSEC_MODE_PROGFAIL_MASK)
		ret = -EACCES;
	else
		ret = bsec_check_error(base, otp);

	if (power_up)
		bsec_power_safmem(base, false);

	return ret;
}

/* BSEC MISC driver *******************************************************/
struct stm32mp_bsec_plat {
	u32 base;
};

static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;
	u32 tmp_data = 0;
	int ret;

	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
		return stm32_smc(STM32_SMC_BSEC,
				 STM32_SMC_READ_OTP,
				 otp, 0, val);

	plat = dev_get_plat(dev);

	/* read current shadow value */
	ret = bsec_read_shadow(dev, plat->base, &tmp_data, otp);
	if (ret)
		return ret;

	/* copy otp in shadow */
	ret = bsec_shadow_register(dev, plat->base, otp);
	if (ret)
		return ret;

	ret = bsec_read_shadow(dev, plat->base, val, otp);
	if (ret)
		return ret;

	/* restore shadow value */
	ret = bsec_write_shadow(dev, plat->base, tmp_data, otp);

	return ret;
}

static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;

	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
		return stm32_smc(STM32_SMC_BSEC,
				 STM32_SMC_READ_SHADOW,
				 otp, 0, val);

	plat = dev_get_plat(dev);

	return bsec_read_shadow(dev, plat->base, val, otp);
}

static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
{
	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
	u32 wrlock;

	/* return OTP permanent write lock status */
	wrlock = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);

	*val = 0;
	if (wrlock)
		*val = BSEC_LOCK_PERM;

	return 0;
}

static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;

	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
		return stm32_smc_exec(STM32_SMC_BSEC,
				      STM32_SMC_PROG_OTP,
				      otp, val);

	plat = dev_get_plat(dev);

	return bsec_program_otp(dev, plat->base, val, otp);

}

static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;

	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
		return stm32_smc_exec(STM32_SMC_BSEC,
				      STM32_SMC_WRITE_SHADOW,
				      otp, val);

	plat = dev_get_plat(dev);

	return bsec_write_shadow(dev, plat->base, val, otp);
}

static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
{
	struct stm32mp_bsec_plat *plat;

	/* only permanent write lock is supported in U-Boot */
	if (!(val & BSEC_LOCK_PERM)) {
		dev_dbg(dev, "lock option without BSEC_LOCK_PERM: %x\n", val);
		return 0; /* nothing to do */
	}

	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
		return stm32_smc_exec(STM32_SMC_BSEC,
				      STM32_SMC_WRLOCK_OTP,
				      otp, 0);

	plat = dev_get_plat(dev);

	return bsec_permanent_lock_otp(dev, plat->base, otp);

	return -EINVAL;
}

static int stm32mp_bsec_read(struct udevice *dev, int offset,
			     void *buf, int size)
{
	int ret;
	int i;
	bool shadow = true, lock = false;
	int nb_otp = size / sizeof(u32);
	int otp;
	unsigned int offs = offset;

	if (offs >= STM32_BSEC_LOCK_OFFSET) {
		offs -= STM32_BSEC_LOCK_OFFSET;
		lock = true;
	} else if (offs >= STM32_BSEC_OTP_OFFSET) {
		offs -= STM32_BSEC_OTP_OFFSET;
		shadow = false;
	}

	if ((offs % 4) || (size % 4))
		return -EINVAL;

	otp = offs / sizeof(u32);

	for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
		u32 *addr = &((u32 *)buf)[i - otp];

		if (lock)
			ret = stm32mp_bsec_read_lock(dev, addr, i);
		else if (shadow)
			ret = stm32mp_bsec_read_shadow(dev, addr, i);
		else
			ret = stm32mp_bsec_read_otp(dev, addr, i);

		if (ret)
			break;
	}
	if (ret)
		return ret;
	else
		return (i - otp) * 4;
}

static int stm32mp_bsec_write(struct udevice *dev, int offset,
			      const void *buf, int size)
{
	int ret = 0;
	int i;
	bool shadow = true, lock = false;
	int nb_otp = size / sizeof(u32);
	int otp;
	unsigned int offs = offset;

	if (offs >= STM32_BSEC_LOCK_OFFSET) {
		offs -= STM32_BSEC_LOCK_OFFSET;
		lock = true;
	} else if (offs >= STM32_BSEC_OTP_OFFSET) {
		offs -= STM32_BSEC_OTP_OFFSET;
		shadow = false;
	}

	if ((offs % 4) || (size % 4))
		return -EINVAL;

	otp = offs / sizeof(u32);

	for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
		u32 *val = &((u32 *)buf)[i - otp];

		if (lock)
			ret = stm32mp_bsec_write_lock(dev, *val, i);
		else if (shadow)
			ret = stm32mp_bsec_write_shadow(dev, *val, i);
		else
			ret = stm32mp_bsec_write_otp(dev, *val, i);
		if (ret)
			break;
	}
	if (ret)
		return ret;
	else
		return (i - otp) * 4;
}

static const struct misc_ops stm32mp_bsec_ops = {
	.read = stm32mp_bsec_read,
	.write = stm32mp_bsec_write,
};

static int stm32mp_bsec_of_to_plat(struct udevice *dev)
{
	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);

	plat->base = (u32)dev_read_addr_ptr(dev);

	return 0;
}

static int stm32mp_bsec_probe(struct udevice *dev)
{
	int otp;
	struct stm32mp_bsec_plat *plat;
	struct clk_bulk clk_bulk;
	int ret;

	ret = clk_get_bulk(dev, &clk_bulk);
	if (!ret) {
		ret = clk_enable_bulk(&clk_bulk);
		if (ret)
			return ret;
	}

	/*
	 * update unlocked shadow for OTP cleared by the rom code
	 * only executed in SPL, it is done in TF-A for TFABOOT
	 */
	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
		plat = dev_get_plat(dev);

		for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
			if (!bsec_read_SR_lock(plat->base, otp))
				bsec_shadow_register(dev, plat->base, otp);
	}

	return 0;
}

static const struct udevice_id stm32mp_bsec_ids[] = {
	{ .compatible = "st,stm32mp15-bsec" },
	{}
};

U_BOOT_DRIVER(stm32mp_bsec) = {
	.name = "stm32mp_bsec",
	.id = UCLASS_MISC,
	.of_match = stm32mp_bsec_ids,
	.of_to_plat = stm32mp_bsec_of_to_plat,
	.plat_auto	= sizeof(struct stm32mp_bsec_plat),
	.ops = &stm32mp_bsec_ops,
	.probe = stm32mp_bsec_probe,
};

bool bsec_dbgswenable(void)
{
	struct udevice *dev;
	struct stm32mp_bsec_plat *plat;
	int ret;

	ret = uclass_get_device_by_driver(UCLASS_MISC,
					  DM_DRIVER_GET(stm32mp_bsec), &dev);
	if (ret || !dev) {
		log_debug("bsec driver not available\n");
		return false;
	}

	plat = dev_get_plat(dev);
	if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
		return true;

	return false;
}
Commit	Line	Data
19f58992 PD	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
	4	*/
	5
b66bfdf2 PD	6	#define LOG_CATEGORY UCLASS_MISC
b66bfdf2 PD	7
19f58992	8	#include <common.h>
622c956c	9	#include <clk.h>
19f58992	10	#include <dm.h>
f7ae49fc	11	#include <log.h>
19f58992 PD	12	#include <misc.h>
19f58992 PD	13	#include <asm/io.h>
bd3f60d2	14	#include <asm/arch/bsec.h>
d859c611	15	#include <asm/arch/stm32mp1_smc.h>
b66bfdf2	16	#include <dm/device_compat.h>
d859c611	17	#include <linux/arm-smccc.h>
ee7d7723	18	#include <linux/iopoll.h>
19f58992 PD	19
19f58992 PD	20	#define BSEC_OTP_MAX_VALUE 95
0c20f53b	21	#define BSEC_OTP_UPPER_START 32
19f58992 PD	22	#define BSEC_TIMEOUT_US 10000
	23
	24	/* BSEC REGISTER OFFSET (base relative) */
	25	#define BSEC_OTP_CONF_OFF 0x000
	26	#define BSEC_OTP_CTRL_OFF 0x004
	27	#define BSEC_OTP_WRDATA_OFF 0x008
	28	#define BSEC_OTP_STATUS_OFF 0x00C
	29	#define BSEC_OTP_LOCK_OFF 0x010
bd3f60d2	30	#define BSEC_DENABLE_OFF 0x014
19f58992 PD	31	#define BSEC_DISTURBED_OFF 0x01C
19f58992 PD	32	#define BSEC_ERROR_OFF 0x034
7ae22d72 PD	33	#define BSEC_WRLOCK_OFF 0x04C /* OTP write permananet lock */
	34	#define BSEC_SPLOCK_OFF 0x064 /* OTP write sticky lock */
	35	#define BSEC_SWLOCK_OFF 0x07C /* shadow write sticky lock */
	36	#define BSEC_SRLOCK_OFF 0x094 /* shadow read sticky lock */
19f58992 PD	37	#define BSEC_OTP_DATA_OFF 0x200
	38
	39	/* BSEC_CONFIGURATION Register MASK */
	40	#define BSEC_CONF_POWER_UP 0x001
	41
	42	/* BSEC_CONTROL Register */
	43	#define BSEC_READ 0x000
	44	#define BSEC_WRITE 0x100
0c20f53b	45	#define BSEC_LOCK 0x200
19f58992 PD	46
	47	/* LOCK Register */
	48	#define OTP_LOCK_MASK 0x1F
	49	#define OTP_LOCK_BANK_SHIFT 0x05
	50	#define OTP_LOCK_BIT_MASK 0x01
	51
	52	/* STATUS Register */
	53	#define BSEC_MODE_BUSY_MASK 0x08
	54	#define BSEC_MODE_PROGFAIL_MASK 0x10
	55	#define BSEC_MODE_PWR_MASK 0x20
	56
bd3f60d2 PD	57	/* DENABLE Register */
	58	#define BSEC_DENABLE_DBGSWENABLE BIT(10)
	59
19f58992 PD	60	/*
	61	* OTP Lock services definition
	62	* Value must corresponding to the bit number in the register
	63	*/
	64	#define BSEC_LOCK_PROGRAM 0x04
	65
0c20f53b PD	66	/*
	67	* OTP status: bit 0 permanent lock
	68	*/
	69	#define BSEC_LOCK_PERM BIT(0)
	70
19f58992	71	/**
7ae22d72 PD	72	* bsec_lock() - manage lock for each type SR/SP/SW
7ae22d72 PD	73	* @address: address of bsec IP register
19f58992	74	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
7ae22d72	75	* Return: true if locked else false
19f58992	76	*/
7ae22d72	77	static bool bsec_read_lock(u32 address, u32 otp)
19f58992 PD	78	{
	79	u32 bit;
	80	u32 bank;
	81
	82	bit = 1 << (otp & OTP_LOCK_MASK);
	83	bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
	84
7ae22d72	85	return !!(readl(address + bank) & bit);
19f58992 PD	86	}
	87
	88	/**
7ae22d72 PD	89	* bsec_check_error() - Check status of one otp
7ae22d72 PD	90	* @base: base address of bsec IP
19f58992	91	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
7ae22d72	92	* Return: 0 if no error, -EAGAIN or -ENOTSUPP
19f58992	93	*/
7ae22d72	94	static u32 bsec_check_error(u32 base, u32 otp)
19f58992 PD	95	{
	96	u32 bit;
	97	u32 bank;
	98
	99	bit = 1 << (otp & OTP_LOCK_MASK);
	100	bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
	101
7ae22d72 PD	102	if (readl(base + BSEC_DISTURBED_OFF + bank) & bit)
	103	return -EAGAIN;
	104	else if (readl(base + BSEC_ERROR_OFF + bank) & bit)
	105	return -ENOTSUPP;
	106
	107	return 0;
19f58992 PD	108	}
	109
	110	/**
	111	* bsec_read_SR_lock() - read SR lock (Shadowing)
	112	* @base: base address of bsec IP
	113	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	114	* Return: true if locked else false
	115	*/
	116	static bool bsec_read_SR_lock(u32 base, u32 otp)
	117	{
	118	return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp);
	119	}
	120
	121	/**
	122	* bsec_read_SP_lock() - read SP lock (program Lock)
	123	* @base: base address of bsec IP
	124	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	125	* Return: true if locked else false
	126	*/
	127	static bool bsec_read_SP_lock(u32 base, u32 otp)
	128	{
	129	return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp);
	130	}
	131
	132	/**
	133	* bsec_SW_lock() - manage SW lock (Write in Shadow)
	134	* @base: base address of bsec IP
	135	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	136	* Return: true if locked else false
	137	*/
	138	static bool bsec_read_SW_lock(u32 base, u32 otp)
	139	{
	140	return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp);
	141	}
	142
	143	/**
	144	* bsec_power_safmem() - Activate or deactivate safmem power
	145	* @base: base address of bsec IP
	146	* @power: true to power up , false to power down
	147	* Return: 0 if succeed
	148	*/
	149	static int bsec_power_safmem(u32 base, bool power)
	150	{
	151	u32 val;
	152	u32 mask;
	153
	154	if (power) {
	155	setbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
	156	mask = BSEC_MODE_PWR_MASK;
	157	} else {
	158	clrbits_le32(base + BSEC_OTP_CONF_OFF, BSEC_CONF_POWER_UP);
	159	mask = 0;
	160	}
	161
	162	/* waiting loop */
	163	return readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
	164	val, (val & BSEC_MODE_PWR_MASK) == mask,
	165	BSEC_TIMEOUT_US);
	166	}
	167
	168	/**
	169	* bsec_shadow_register() - copy safmen otp to bsec data
	170	* @base: base address of bsec IP
	171	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
172	* Return: 0 if no error
173	*/
b66bfdf2	174	static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp)
19f58992 PD	175	{
	176	u32 val;
	177	int ret;
	178	bool power_up = false;
	179
	180	/* check if shadowing of otp is locked */
	181	if (bsec_read_SR_lock(base, otp))
b66bfdf2 PD	182	dev_dbg(dev, "OTP %d is locked and refreshed with 0\n",
b66bfdf2 PD	183	otp);
19f58992 PD	184
	185	/* check if safemem is power up */
	186	val = readl(base + BSEC_OTP_STATUS_OFF);
	187	if (!(val & BSEC_MODE_PWR_MASK)) {
	188	ret = bsec_power_safmem(base, true);
	189	if (ret)
	190	return ret;
815bc8bc	191	power_up = true;
19f58992 PD	192	}
	193	/* set BSEC_OTP_CTRL_OFF with the otp value*/
	194	writel(otp \| BSEC_READ, base + BSEC_OTP_CTRL_OFF);
	195
	196	/* check otp status*/
	197	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
	198	val, (val & BSEC_MODE_BUSY_MASK) == 0,
	199	BSEC_TIMEOUT_US);
	200	if (ret)
	201	return ret;
	202
	203	ret = bsec_check_error(base, otp);
	204
	205	if (power_up)
	206	bsec_power_safmem(base, false);
	207
	208	return ret;
	209	}
	210
	211	/**
	212	* bsec_read_shadow() - read an otp data value from shadow
	213	* @base: base address of bsec IP
	214	* @val: read value
	215	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	216	* Return: 0 if no error
	217	*/
b66bfdf2	218	static int bsec_read_shadow(struct udevice dev, u32 base, u32 val, u32 otp)
19f58992 PD	219	{
	220	val = readl(base + BSEC_OTP_DATA_OFF + otp sizeof(u32));
	221
	222	return bsec_check_error(base, otp);
	223	}
	224
	225	/**
	226	* bsec_write_shadow() - write value in BSEC data register in shadow
	227	* @base: base address of bsec IP
	228	* @val: value to write
	229	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	230	* Return: 0 if no error
	231	*/
b66bfdf2	232	static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp)
19f58992 PD	233	{
	234	/* check if programming of otp is locked */
	235	if (bsec_read_SW_lock(base, otp))
b66bfdf2	236	dev_dbg(dev, "OTP %d is lock, write will be ignore\n", otp);
19f58992 PD	237
	238	writel(val, base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
	239
	240	return bsec_check_error(base, otp);
	241	}
	242
	243	/**
	244	* bsec_program_otp() - program a bit in SAFMEM
	245	* @base: base address of bsec IP
	246	* @val: value to program
	247	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	248	* after the function the otp data is not refreshed in shadow
	249	* Return: 0 if no error
	250	*/
b66bfdf2	251	static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp)
19f58992 PD	252	{
	253	u32 ret;
	254	bool power_up = false;
	255
	256	if (bsec_read_SP_lock(base, otp))
b66bfdf2	257	dev_dbg(dev, "OTP %d locked, prog will be ignore\n", otp);
19f58992 PD	258
19f58992 PD	259	if (readl(base + BSEC_OTP_LOCK_OFF) & (1 << BSEC_LOCK_PROGRAM))
b66bfdf2	260	dev_dbg(dev, "Global lock, prog will be ignore\n");
19f58992 PD	261
	262	/* check if safemem is power up */
	263	if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
	264	ret = bsec_power_safmem(base, true);
	265	if (ret)
	266	return ret;
	267
	268	power_up = true;
	269	}
	270	/* set value in write register*/
	271	writel(val, base + BSEC_OTP_WRDATA_OFF);
	272
	273	/* set BSEC_OTP_CTRL_OFF with the otp value */
	274	writel(otp \| BSEC_WRITE, base + BSEC_OTP_CTRL_OFF);
	275
	276	/* check otp status*/
	277	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
	278	val, (val & BSEC_MODE_BUSY_MASK) == 0,
	279	BSEC_TIMEOUT_US);
	280	if (ret)
	281	return ret;
	282
	283	if (val & BSEC_MODE_PROGFAIL_MASK)
	284	ret = -EACCES;
	285	else
	286	ret = bsec_check_error(base, otp);
	287
	288	if (power_up)
	289	bsec_power_safmem(base, false);
	290
	291	return ret;
	292	}
	293
0c20f53b PD	294	/**
	295	* bsec_permanent_lock_otp() - permanent lock of OTP in SAFMEM
	296	* @dev: bsec IP device
	297	* @base: base address of bsec IP
	298	* @otp: otp number (0 - BSEC_OTP_MAX_VALUE)
	299	* Return: 0 if no error
	300	*/
	301	static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp)
	302	{
	303	int ret;
	304	bool power_up = false;
	305	u32 val, addr;
	306
	307	/* check if safemem is power up */
	308	if (!(readl(base + BSEC_OTP_STATUS_OFF) & BSEC_MODE_PWR_MASK)) {
	309	ret = bsec_power_safmem(base, true);
	310	if (ret)
	311	return ret;
	312
	313	power_up = true;
	314	}
	315
	316	/*
	317	* low OTPs = 2 bits word for low OTPs, 1 bits per word for upper OTP
	318	* and only 16 bits used in WRDATA
	319	*/
	320	if (otp < BSEC_OTP_UPPER_START) {
	321	addr = otp / 8;
	322	val = 0x03 << ((otp * 2) & 0xF);
	323	} else {
	324	addr = BSEC_OTP_UPPER_START / 8 +
	325	((otp - BSEC_OTP_UPPER_START) / 16);
	326	val = 0x01 << (otp & 0xF);
	327	}
	328
	329	/* set value in write register*/
	330	writel(val, base + BSEC_OTP_WRDATA_OFF);
	331
	332	/* set BSEC_OTP_CTRL_OFF with the otp addr and lock request*/
	333	writel(addr \| BSEC_WRITE \| BSEC_LOCK, base + BSEC_OTP_CTRL_OFF);
	334
	335	/* check otp status*/
	336	ret = readl_poll_timeout(base + BSEC_OTP_STATUS_OFF,
	337	val, (val & BSEC_MODE_BUSY_MASK) == 0,
	338	BSEC_TIMEOUT_US);
	339	if (ret)
	340	return ret;
	341
	342	if (val & BSEC_MODE_PROGFAIL_MASK)
	343	ret = -EACCES;
	344	else
	345	ret = bsec_check_error(base, otp);
	346
	347	if (power_up)
	348	bsec_power_safmem(base, false);
	349
	350	return ret;
	351	}
	352
19f58992	353	/* BSEC MISC driver *******************************************************/
8a8d24bd	354	struct stm32mp_bsec_plat {
19f58992 PD	355	u32 base;
	356	};
	357
	358	static int stm32mp_bsec_read_otp(struct udevice dev, u32 val, u32 otp)
	359	{
8a8d24bd	360	struct stm32mp_bsec_plat *plat;
19f58992 PD	361	u32 tmp_data = 0;
	362	int ret;
	363
f42045b2	364	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
4e9e358f PD	365	return stm32_smc(STM32_SMC_BSEC,
	366	STM32_SMC_READ_OTP,
	367	otp, 0, val);
	368
c69cda25	369	plat = dev_get_plat(dev);
4e9e358f	370
19f58992	371	/* read current shadow value */
b66bfdf2	372	ret = bsec_read_shadow(dev, plat->base, &tmp_data, otp);
19f58992 PD	373	if (ret)
	374	return ret;
	375
	376	/* copy otp in shadow */
b66bfdf2	377	ret = bsec_shadow_register(dev, plat->base, otp);
19f58992 PD	378	if (ret)
	379	return ret;
	380
b66bfdf2	381	ret = bsec_read_shadow(dev, plat->base, val, otp);
19f58992 PD	382	if (ret)
	383	return ret;
	384
	385	/* restore shadow value */
b66bfdf2	386	ret = bsec_write_shadow(dev, plat->base, tmp_data, otp);
4e9e358f	387
19f58992 PD	388	return ret;
	389	}
	390
	391	static int stm32mp_bsec_read_shadow(struct udevice dev, u32 val, u32 otp)
	392	{
8a8d24bd	393	struct stm32mp_bsec_plat *plat;
4e9e358f	394
f42045b2	395	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
4e9e358f PD	396	return stm32_smc(STM32_SMC_BSEC,
	397	STM32_SMC_READ_SHADOW,
	398	otp, 0, val);
	399
c69cda25	400	plat = dev_get_plat(dev);
19f58992	401
b66bfdf2	402	return bsec_read_shadow(dev, plat->base, val, otp);
19f58992 PD	403	}
19f58992 PD	404
7ae22d72 PD	405	static int stm32mp_bsec_read_lock(struct udevice dev, u32 val, u32 otp)
7ae22d72 PD	406	{
8a8d24bd	407	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
0c20f53b	408	u32 wrlock;
7ae22d72 PD	409
7ae22d72 PD	410	/* return OTP permanent write lock status */
0c20f53b PD	411	wrlock = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
	412
	413	*val = 0;
	414	if (wrlock)
	415	*val = BSEC_LOCK_PERM;
7ae22d72 PD	416
	417	return 0;
	418	}
	419
19f58992 PD	420	static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
19f58992 PD	421	{
8a8d24bd	422	struct stm32mp_bsec_plat *plat;
4e9e358f	423
f42045b2	424	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
4e9e358f PD	425	return stm32_smc_exec(STM32_SMC_BSEC,
	426	STM32_SMC_PROG_OTP,
	427	otp, val);
	428
c69cda25	429	plat = dev_get_plat(dev);
19f58992	430
b66bfdf2	431	return bsec_program_otp(dev, plat->base, val, otp);
4e9e358f	432
19f58992 PD	433	}
	434
	435	static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
	436	{
8a8d24bd	437	struct stm32mp_bsec_plat *plat;
4e9e358f	438
f42045b2	439	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
4e9e358f PD	440	return stm32_smc_exec(STM32_SMC_BSEC,
	441	STM32_SMC_WRITE_SHADOW,
	442	otp, val);
	443
c69cda25	444	plat = dev_get_plat(dev);
19f58992	445
b66bfdf2	446	return bsec_write_shadow(dev, plat->base, val, otp);
19f58992 PD	447	}
19f58992 PD	448
7ae22d72 PD	449	static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
7ae22d72 PD	450	{
0c20f53b PD	451	struct stm32mp_bsec_plat *plat;
	452
	453	/* only permanent write lock is supported in U-Boot */
	454	if (!(val & BSEC_LOCK_PERM)) {
	455	dev_dbg(dev, "lock option without BSEC_LOCK_PERM: %x\n", val);
	456	return 0; /* nothing to do */
	457	}
4e9e358f	458
0c20f53b	459	if (IS_ENABLED(CONFIG_ARM_SMCCC) && !IS_ENABLED(CONFIG_SPL_BUILD))
7ae22d72 PD	460	return stm32_smc_exec(STM32_SMC_BSEC,
	461	STM32_SMC_WRLOCK_OTP,
	462	otp, 0);
0c20f53b PD	463
	464	plat = dev_get_plat(dev);
	465
	466	return bsec_permanent_lock_otp(dev, plat->base, otp);
7ae22d72 PD	467
7ae22d72 PD	468	return -EINVAL;
7ae22d72 PD	469	}
7ae22d72 PD	470
19f58992 PD	471	static int stm32mp_bsec_read(struct udevice *dev, int offset,
	472	void *buf, int size)
	473	{
	474	int ret;
	475	int i;
7ae22d72	476	bool shadow = true, lock = false;
19f58992 PD	477	int nb_otp = size / sizeof(u32);
19f58992 PD	478	int otp;
745b676d	479	unsigned int offs = offset;
19f58992	480
7ae22d72 PD	481	if (offs >= STM32_BSEC_LOCK_OFFSET) {
	482	offs -= STM32_BSEC_LOCK_OFFSET;
	483	lock = true;
	484	} else if (offs >= STM32_BSEC_OTP_OFFSET) {
745b676d	485	offs -= STM32_BSEC_OTP_OFFSET;
19f58992 PD	486	shadow = false;
19f58992 PD	487	}
19f58992	488
df2d1b8f	489	if ((offs % 4) \|\| (size % 4))
19f58992	490	return -EINVAL;
19f58992	491
0c8620d2 PD	492	otp = offs / sizeof(u32);
	493
	494	for (i = otp; i < (otp + nb_otp) && i <= BSEC_OTP_MAX_VALUE; i++) {
19f58992 PD	495	u32 addr = &((u32 )buf)[i - otp];
19f58992 PD	496
7ae22d72 PD	497	if (lock)
	498	ret = stm32mp_bsec_read_lock(dev, addr, i);
	499	else if (shadow)
19f58992 PD	500	ret = stm32mp_bsec_read_shadow(dev, addr, i);
	501	else
	502	ret = stm32mp_bsec_read_otp(dev, addr, i);
	503
	504	if (ret)
	505	break;
	506	}
0c8620d2 PD	507	if (ret)
	508	return ret;
	509	else
	510	return (i - otp) * 4;
19f58992 PD	511	}
	512
	513	static int stm32mp_bsec_write(struct udevice *dev, int offset,
	514	const void *buf, int size)
	515	{
	516	int ret = 0;
	517	int i;
7ae22d72	518	bool shadow = true, lock = false;
19f58992 PD	519	int nb_otp = size / sizeof(u32);
19f58992 PD	520	int otp;
745b676d	521	unsigned int offs = offset;
19f58992	522
7ae22d72 PD	523	if (offs >= STM32_BSEC_LOCK_OFFSET) {
	524	offs -= STM32_BSEC_LOCK_OFFSET;
	525	lock = true;
	526	} else if (offs >= STM32_BSEC_OTP_OFFSET) {
745b676d	527	offs -= STM32_BSEC_OTP_OFFSET;
19f58992 PD	528	shadow = false;
19f58992 PD	529	}
19f58992	530
df2d1b8f	531	if ((offs % 4) \|\| (size % 4))
19f58992	532	return -EINVAL;
19f58992	533
0c8620d2 PD	534	otp = offs / sizeof(u32);
	535
	536	for (i = otp; i < otp + nb_otp && i <= BSEC_OTP_MAX_VALUE; i++) {
19f58992 PD	537	u32 val = &((u32 )buf)[i - otp];
19f58992 PD	538
7ae22d72 PD	539	if (lock)
	540	ret = stm32mp_bsec_write_lock(dev, *val, i);
	541	else if (shadow)
19f58992 PD	542	ret = stm32mp_bsec_write_shadow(dev, *val, i);
	543	else
	544	ret = stm32mp_bsec_write_otp(dev, *val, i);
	545	if (ret)
	546	break;
	547	}
0c8620d2 PD	548	if (ret)
	549	return ret;
	550	else
	551	return (i - otp) * 4;
19f58992 PD	552	}
	553
	554	static const struct misc_ops stm32mp_bsec_ops = {
	555	.read = stm32mp_bsec_read,
	556	.write = stm32mp_bsec_write,
	557	};
	558
d1998a9f	559	static int stm32mp_bsec_of_to_plat(struct udevice *dev)
19f58992	560	{
8a8d24bd	561	struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
19f58992 PD	562
	563	plat->base = (u32)dev_read_addr_ptr(dev);
	564
	565	return 0;
	566	}
	567
815bc8bc PD	568	static int stm32mp_bsec_probe(struct udevice *dev)
	569	{
	570	int otp;
8a8d24bd	571	struct stm32mp_bsec_plat *plat;
622c956c PD	572	struct clk_bulk clk_bulk;
	573	int ret;
	574
	575	ret = clk_get_bulk(dev, &clk_bulk);
	576	if (!ret) {
	577	ret = clk_enable_bulk(&clk_bulk);
	578	if (ret)
	579	return ret;
	580	}
815bc8bc	581
95bd49a5 PD	582	/*
95bd49a5 PD	583	* update unlocked shadow for OTP cleared by the rom code
9788708f	584	* only executed in SPL, it is done in TF-A for TFABOOT
95bd49a5	585	*/
9788708f	586	if (IS_ENABLED(CONFIG_SPL_BUILD)) {
c69cda25	587	plat = dev_get_plat(dev);
4e9e358f PD	588
	589	for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
	590	if (!bsec_read_SR_lock(plat->base, otp))
b66bfdf2	591	bsec_shadow_register(dev, plat->base, otp);
4e9e358f	592	}
815bc8bc PD	593
	594	return 0;
	595	}
815bc8bc	596
19f58992	597	static const struct udevice_id stm32mp_bsec_ids[] = {
bfe1f08f	598	{ .compatible = "st,stm32mp15-bsec" },
19f58992 PD	599	{}
	600	};
	601
	602	U_BOOT_DRIVER(stm32mp_bsec) = {
	603	.name = "stm32mp_bsec",
	604	.id = UCLASS_MISC,
	605	.of_match = stm32mp_bsec_ids,
d1998a9f	606	.of_to_plat = stm32mp_bsec_of_to_plat,
8a8d24bd	607	.plat_auto = sizeof(struct stm32mp_bsec_plat),
19f58992	608	.ops = &stm32mp_bsec_ops,
815bc8bc	609	.probe = stm32mp_bsec_probe,
19f58992	610	};
bd3f60d2 PD	611
	612	bool bsec_dbgswenable(void)
	613	{
	614	struct udevice *dev;
8a8d24bd	615	struct stm32mp_bsec_plat *plat;
bd3f60d2 PD	616	int ret;
	617
	618	ret = uclass_get_device_by_driver(UCLASS_MISC,
65e25bea	619	DM_DRIVER_GET(stm32mp_bsec), &dev);
bd3f60d2	620	if (ret \|\| !dev) {
b66bfdf2	621	log_debug("bsec driver not available\n");
bd3f60d2 PD	622	return false;
	623	}
	624
c69cda25	625	plat = dev_get_plat(dev);
bd3f60d2 PD	626	if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
	627	return true;
	628
	629	return false;
	630	}