[J-u-boot.git] / drivers / gpio / stm32_gpio.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Author(s): Vikas Manocha, <[email protected]> for STMicroelectronics.
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
#include <asm/arch/gpio.h>
#include <asm/arch/stm32.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/io.h>

#define STM32_GPIOS_PER_BANK		16

#define MODE_BITS(gpio_pin)		((gpio_pin) * 2)
#define MODE_BITS_MASK			3
#define BSRR_BIT(gpio_pin, value)	BIT((gpio_pin) + (value ? 0 : 16))

#define PUPD_BITS(gpio_pin)		((gpio_pin) * 2)
#define PUPD_MASK			3

#define OTYPE_BITS(gpio_pin)		(gpio_pin)
#define OTYPE_MSK			1

static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
				 int idx,
				 int mode)
{
	int bits_index;
	int mask;

	bits_index = MODE_BITS(idx);
	mask = MODE_BITS_MASK << bits_index;

	clrsetbits_le32(&regs->moder, mask, mode << bits_index);
}

static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
{
	return (readl(&regs->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
}

static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
				 int idx,
				 enum stm32_gpio_otype otype)
{
	int bits;

	bits = OTYPE_BITS(idx);
	clrsetbits_le32(&regs->otyper, OTYPE_MSK << bits, otype << bits);
}

static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
						  int idx)
{
	return (readl(&regs->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
}

static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
				int idx,
				enum stm32_gpio_pupd pupd)
{
	int bits;

	bits = PUPD_BITS(idx);
	clrsetbits_le32(&regs->pupdr, PUPD_MASK << bits, pupd << bits);
}

static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
						int idx)
{
	return (readl(&regs->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
}

/*
 * convert gpio offset to gpio index taking into account gpio holes
 * into gpio bank
 */
int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	unsigned int idx = 0;
	int i;

	for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
		if (priv->gpio_range & BIT(i)) {
			if (idx == offset)
				return idx;
			idx++;
		}
	}
	/* shouldn't happen */
	return -EINVAL;
}

static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);

	return 0;
}

static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
				       int value)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);

	writel(BSRR_BIT(idx, value), &regs->bsrr);

	return 0;
}

static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	return readl(&regs->idr) & BIT(idx) ? 1 : 0;
}

static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	writel(BSRR_BIT(idx, value), &regs->bsrr);

	return 0;
}

static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int bits_index;
	int mask;
	int idx;
	u32 mode;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	bits_index = MODE_BITS(idx);
	mask = MODE_BITS_MASK << bits_index;

	mode = (readl(&regs->moder) & mask) >> bits_index;
	if (mode == STM32_GPIO_MODE_OUT)
		return GPIOF_OUTPUT;
	if (mode == STM32_GPIO_MODE_IN)
		return GPIOF_INPUT;
	if (mode == STM32_GPIO_MODE_AN)
		return GPIOF_UNUSED;

	return GPIOF_FUNC;
}

static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
				    ulong flags)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	if (flags & GPIOD_IS_OUT) {
		int value = GPIOD_FLAGS_OUTPUT(flags);

		if (flags & GPIOD_OPEN_DRAIN)
			stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
		else
			stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
		stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
		writel(BSRR_BIT(idx, value), &regs->bsrr);

	} else if (flags & GPIOD_IS_IN) {
		stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
		if (flags & GPIOD_PULL_UP)
			stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
		else if (flags & GPIOD_PULL_DOWN)
			stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
	}

	return 0;
}

static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
				    ulong *flags)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;
	ulong dir_flags = 0;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	switch (stm32_gpio_get_moder(regs, idx)) {
	case STM32_GPIO_MODE_OUT:
		dir_flags |= GPIOD_IS_OUT;
		if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
			dir_flags |= GPIOD_OPEN_DRAIN;
		if (readl(&regs->idr) & BIT(idx))
			dir_flags |= GPIOD_IS_OUT_ACTIVE;
		break;
	case STM32_GPIO_MODE_IN:
		dir_flags |= GPIOD_IS_IN;
		switch (stm32_gpio_get_pupd(regs, idx)) {
		case STM32_GPIO_PUPD_UP:
			dir_flags |= GPIOD_PULL_UP;
			break;
		case STM32_GPIO_PUPD_DOWN:
			dir_flags |= GPIOD_PULL_DOWN;
			break;
		default:
			break;
		}
		break;
	default:
		break;
	}
	*flags = dir_flags;

	return 0;
}

static const struct dm_gpio_ops gpio_stm32_ops = {
	.direction_input	= stm32_gpio_direction_input,
	.direction_output	= stm32_gpio_direction_output,
	.get_value		= stm32_gpio_get_value,
	.set_value		= stm32_gpio_set_value,
	.get_function		= stm32_gpio_get_function,
	.set_dir_flags		= stm32_gpio_set_dir_flags,
	.get_dir_flags		= stm32_gpio_get_dir_flags,
};

static int gpio_stm32_probe(struct udevice *dev)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	struct ofnode_phandle_args args;
	const char *name;
	struct clk clk;
	fdt_addr_t addr;
	int ret, i;

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->regs = (struct stm32_gpio_regs *)addr;

	name = dev_read_string(dev, "st,bank-name");
	if (!name)
		return -EINVAL;
	uc_priv->bank_name = name;

	i = 0;
	ret = dev_read_phandle_with_args(dev, "gpio-ranges",
					 NULL, 3, i, &args);

	if (!ret && args.args_count < 3)
		return -EINVAL;

	if (ret == -ENOENT) {
		uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
		priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
	}

	while (ret != -ENOENT) {
		priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
				    args.args[0]);

		uc_priv->gpio_count += args.args[2];

		ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
						 ++i, &args);
		if (!ret && args.args_count < 3)
			return -EINVAL;
	}

	dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
		(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
		priv->gpio_range);

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0)
		return ret;

	ret = clk_enable(&clk);

	if (ret) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}
	debug("clock enabled for device %s\n", dev->name);

	return 0;
}

U_BOOT_DRIVER(gpio_stm32) = {
	.name	= "gpio_stm32",
	.id	= UCLASS_GPIO,
	.probe	= gpio_stm32_probe,
	.ops	= &gpio_stm32_ops,
	.flags	= DM_UC_FLAG_SEQ_ALIAS,
	.priv_auto_alloc_size	= sizeof(struct stm32_gpio_priv),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
77417102	2	/*
3bc599c9 PC	3	* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3bc599c9 PC	4	* Author(s): Vikas Manocha, <[email protected]> for STMicroelectronics.
77417102 VM	5	*/
	6
	7	#include <common.h>
	8	#include <clk.h>
	9	#include <dm.h>
	10	#include <fdtdec.h>
f7ae49fc	11	#include <log.h>
77417102 VM	12	#include <asm/arch/gpio.h>
	13	#include <asm/arch/stm32.h>
	14	#include <asm/gpio.h>
	15	#include <asm/io.h>
336d4615	16	#include <dm/device_compat.h>
cd93d625	17	#include <linux/bitops.h>
77417102 VM	18	#include <linux/errno.h>
	19	#include <linux/io.h>
	20
6af78d03 PD	21	#define STM32_GPIOS_PER_BANK 16
6af78d03 PD	22
f13ff88b	23	#define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
77417102	24	#define MODE_BITS_MASK 3
f13ff88b PD	25	#define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
	26
	27	#define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
	28	#define PUPD_MASK 3
	29
	30	#define OTYPE_BITS(gpio_pin) (gpio_pin)
	31	#define OTYPE_MSK 1
	32
	33	static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
	34	int idx,
	35	int mode)
	36	{
	37	int bits_index;
	38	int mask;
	39
	40	bits_index = MODE_BITS(idx);
	41	mask = MODE_BITS_MASK << bits_index;
	42
	43	clrsetbits_le32(&regs->moder, mask, mode << bits_index);
	44	}
	45
43efbb6a PD	46	static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
	47	{
	48	return (readl(&regs->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
	49	}
	50
f13ff88b PD	51	static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
	52	int idx,
	53	enum stm32_gpio_otype otype)
	54	{
	55	int bits;
	56
	57	bits = OTYPE_BITS(idx);
	58	clrsetbits_le32(&regs->otyper, OTYPE_MSK << bits, otype << bits);
	59	}
	60
43efbb6a PD	61	static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
	62	int idx)
	63	{
	64	return (readl(&regs->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
	65	}
	66
f13ff88b PD	67	static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
	68	int idx,
	69	enum stm32_gpio_pupd pupd)
	70	{
	71	int bits;
	72
	73	bits = PUPD_BITS(idx);
	74	clrsetbits_le32(&regs->pupdr, PUPD_MASK << bits, pupd << bits);
	75	}
77417102	76
43efbb6a PD	77	static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
	78	int idx)
	79	{
	80	return (readl(&regs->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
	81	}
	82
dbf928dd PC	83	/*
	84	* convert gpio offset to gpio index taking into account gpio holes
	85	* into gpio bank
	86	*/
	87	int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
	88	{
	89	struct stm32_gpio_priv *priv = dev_get_priv(dev);
99e14b27	90	unsigned int idx = 0;
dbf928dd PC	91	int i;
	92
	93	for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
	94	if (priv->gpio_range & BIT(i)) {
	95	if (idx == offset)
	96	return idx;
	97	idx++;
	98	}
	99	}
	100	/* shouldn't happen */
	101	return -EINVAL;
	102	}
	103
77417102 VM	104	static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
	105	{
	106	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	107	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	108	int idx;
	109
	110	idx = stm32_offset_to_index(dev, offset);
	111	if (idx < 0)
	112	return idx;
	113
f13ff88b	114	stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
77417102 VM	115
	116	return 0;
	117	}
	118
	119	static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
	120	int value)
	121	{
	122	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	123	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	124	int idx;
	125
	126	idx = stm32_offset_to_index(dev, offset);
	127	if (idx < 0)
	128	return idx;
	129
f13ff88b	130	stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
798cd708	131
dbf928dd	132	writel(BSRR_BIT(idx, value), &regs->bsrr);
77417102 VM	133
	134	return 0;
	135	}
	136
	137	static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
	138	{
	139	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	140	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	141	int idx;
	142
	143	idx = stm32_offset_to_index(dev, offset);
	144	if (idx < 0)
	145	return idx;
77417102	146
dbf928dd	147	return readl(&regs->idr) & BIT(idx) ? 1 : 0;
77417102 VM	148	}
	149
	150	static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
	151	{
	152	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	153	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd	154	int idx;
77417102	155
dbf928dd PC	156	idx = stm32_offset_to_index(dev, offset);
	157	if (idx < 0)
	158	return idx;
	159
	160	writel(BSRR_BIT(idx, value), &regs->bsrr);
77417102 VM	161
	162	return 0;
	163	}
	164
cad73249 PC	165	static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
	166	{
	167	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	168	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	169	int bits_index;
	170	int mask;
	171	int idx;
cad73249 PC	172	u32 mode;
cad73249 PC	173
dbf928dd PC	174	idx = stm32_offset_to_index(dev, offset);
	175	if (idx < 0)
	176	return idx;
	177
	178	bits_index = MODE_BITS(idx);
	179	mask = MODE_BITS_MASK << bits_index;
	180
cad73249 PC	181	mode = (readl(&regs->moder) & mask) >> bits_index;
	182	if (mode == STM32_GPIO_MODE_OUT)
	183	return GPIOF_OUTPUT;
	184	if (mode == STM32_GPIO_MODE_IN)
	185	return GPIOF_INPUT;
	186	if (mode == STM32_GPIO_MODE_AN)
	187	return GPIOF_UNUSED;
	188
	189	return GPIOF_FUNC;
	190	}
	191
f13ff88b PD	192	static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
	193	ulong flags)
	194	{
	195	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	196	struct stm32_gpio_regs *regs = priv->regs;
	197	int idx;
	198
	199	idx = stm32_offset_to_index(dev, offset);
	200	if (idx < 0)
	201	return idx;
	202
	203	if (flags & GPIOD_IS_OUT) {
	204	int value = GPIOD_FLAGS_OUTPUT(flags);
	205
	206	if (flags & GPIOD_OPEN_DRAIN)
	207	stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
	208	else
	209	stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
	210	stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
	211	writel(BSRR_BIT(idx, value), &regs->bsrr);
	212
	213	} else if (flags & GPIOD_IS_IN) {
	214	stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
	215	if (flags & GPIOD_PULL_UP)
	216	stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
	217	else if (flags & GPIOD_PULL_DOWN)
	218	stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
	219	}
	220
	221	return 0;
	222	}
	223
43efbb6a PD	224	static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
	225	ulong *flags)
	226	{
	227	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	228	struct stm32_gpio_regs *regs = priv->regs;
	229	int idx;
	230	ulong dir_flags = 0;
	231
	232	idx = stm32_offset_to_index(dev, offset);
	233	if (idx < 0)
	234	return idx;
	235
	236	switch (stm32_gpio_get_moder(regs, idx)) {
	237	case STM32_GPIO_MODE_OUT:
	238	dir_flags \|= GPIOD_IS_OUT;
	239	if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
	240	dir_flags \|= GPIOD_OPEN_DRAIN;
	241	if (readl(&regs->idr) & BIT(idx))
	242	dir_flags \|= GPIOD_IS_OUT_ACTIVE;
	243	break;
	244	case STM32_GPIO_MODE_IN:
	245	dir_flags \|= GPIOD_IS_IN;
	246	switch (stm32_gpio_get_pupd(regs, idx)) {
	247	case STM32_GPIO_PUPD_UP:
	248	dir_flags \|= GPIOD_PULL_UP;
	249	break;
	250	case STM32_GPIO_PUPD_DOWN:
	251	dir_flags \|= GPIOD_PULL_DOWN;
	252	break;
	253	default:
	254	break;
	255	}
	256	break;
	257	default:
	258	break;
	259	}
	260	*flags = dir_flags;
	261
	262	return 0;
	263	}
	264
77417102 VM	265	static const struct dm_gpio_ops gpio_stm32_ops = {
	266	.direction_input = stm32_gpio_direction_input,
	267	.direction_output = stm32_gpio_direction_output,
	268	.get_value = stm32_gpio_get_value,
	269	.set_value = stm32_gpio_set_value,
cad73249	270	.get_function = stm32_gpio_get_function,
f13ff88b	271	.set_dir_flags = stm32_gpio_set_dir_flags,
43efbb6a	272	.get_dir_flags = stm32_gpio_get_dir_flags,
77417102 VM	273	};
	274
	275	static int gpio_stm32_probe(struct udevice *dev)
	276	{
77417102	277	struct stm32_gpio_priv *priv = dev_get_priv(dev);
15c8cbfc PD	278	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	279	struct ofnode_phandle_args args;
	280	const char *name;
8b6d45ab	281	struct clk clk;
77417102	282	fdt_addr_t addr;
15c8cbfc	283	int ret, i;
77417102	284
d876eaf2	285	addr = dev_read_addr(dev);
77417102 VM	286	if (addr == FDT_ADDR_T_NONE)
	287	return -EINVAL;
	288
	289	priv->regs = (struct stm32_gpio_regs *)addr;
4fb22463	290
d876eaf2	291	name = dev_read_string(dev, "st,bank-name");
77417102 VM	292	if (!name)
	293	return -EINVAL;
	294	uc_priv->bank_name = name;
dbf928dd PC	295
	296	i = 0;
	297	ret = dev_read_phandle_with_args(dev, "gpio-ranges",
	298	NULL, 3, i, &args);
	299
cb08e84d PD	300	if (!ret && args.args_count < 3)
	301	return -EINVAL;
	302
39a8f0be PC	303	if (ret == -ENOENT) {
	304	uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
	305	priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
	306	}
	307
dbf928dd PC	308	while (ret != -ENOENT) {
	309	priv->gpio_range \|= GENMASK(args.args[2] + args.args[0] - 1,
	310	args.args[0]);
	311
	312	uc_priv->gpio_count += args.args[2];
	313
	314	ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
	315	++i, &args);
cb08e84d PD	316	if (!ret && args.args_count < 3)
cb08e84d PD	317	return -EINVAL;
dbf928dd PC	318	}
	319
	320	dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
	321	(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
	322	priv->gpio_range);
f17412ed	323
77417102 VM	324	ret = clk_get_by_index(dev, 0, &clk);
	325	if (ret < 0)
	326	return ret;
	327
	328	ret = clk_enable(&clk);
	329
	330	if (ret) {
	331	dev_err(dev, "failed to enable clock\n");
	332	return ret;
	333	}
	334	debug("clock enabled for device %s\n", dev->name);
77417102 VM	335
	336	return 0;
	337	}
	338
77417102 VM	339	U_BOOT_DRIVER(gpio_stm32) = {
	340	.name = "gpio_stm32",
	341	.id = UCLASS_GPIO,
77417102 VM	342	.probe = gpio_stm32_probe,
77417102 VM	343	.ops = &gpio_stm32_ops,
695c4994	344	.flags = DM_UC_FLAG_SEQ_ALIAS,
77417102 VM	345	.priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
77417102 VM	346	};