[J-u-boot.git] / drivers / gpio / stm32f7_gpio.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Author(s): Vikas Manocha, <[email protected]> for STMicroelectronics.
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <fdtdec.h>
#include <asm/arch/gpio.h>
#include <asm/arch/stm32.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <linux/io.h>

#define MODE_BITS(gpio_pin)		(gpio_pin * 2)
#define MODE_BITS_MASK			3
#define BSRR_BIT(gpio_pin, value)	BIT(gpio_pin + (value ? 0 : 16))

/*
 * convert gpio offset to gpio index taking into account gpio holes
 * into gpio bank
 */
int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	int idx = 0;
	int i;

	for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
		if (priv->gpio_range & BIT(i)) {
			if (idx == offset)
				return idx;
			idx++;
		}
	}
	/* shouldn't happen */
	return -EINVAL;
}

static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int bits_index;
	int mask;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	bits_index = MODE_BITS(idx);
	mask = MODE_BITS_MASK << bits_index;

	clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_IN << bits_index);

	return 0;
}

static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
				       int value)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int bits_index;
	int mask;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	bits_index = MODE_BITS(idx);
	mask = MODE_BITS_MASK << bits_index;

	clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_OUT << bits_index);

	writel(BSRR_BIT(idx, value), &regs->bsrr);

	return 0;
}

static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	return readl(&regs->idr) & BIT(idx) ? 1 : 0;
}

static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	writel(BSRR_BIT(idx, value), &regs->bsrr);

	return 0;
}

static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int bits_index;
	int mask;
	int idx;
	u32 mode;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	bits_index = MODE_BITS(idx);
	mask = MODE_BITS_MASK << bits_index;

	mode = (readl(&regs->moder) & mask) >> bits_index;
	if (mode == STM32_GPIO_MODE_OUT)
		return GPIOF_OUTPUT;
	if (mode == STM32_GPIO_MODE_IN)
		return GPIOF_INPUT;
	if (mode == STM32_GPIO_MODE_AN)
		return GPIOF_UNUSED;

	return GPIOF_FUNC;
}

static const struct dm_gpio_ops gpio_stm32_ops = {
	.direction_input	= stm32_gpio_direction_input,
	.direction_output	= stm32_gpio_direction_output,
	.get_value		= stm32_gpio_get_value,
	.set_value		= stm32_gpio_set_value,
	.get_function		= stm32_gpio_get_function,
};

static int gpio_stm32_probe(struct udevice *dev)
{
	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct ofnode_phandle_args args;
	fdt_addr_t addr;
	const char *name;
	int ret;
	int i;

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->regs = (struct stm32_gpio_regs *)addr;
	name = dev_read_string(dev, "st,bank-name");
	if (!name)
		return -EINVAL;
	uc_priv->bank_name = name;

	i = 0;
	ret = dev_read_phandle_with_args(dev, "gpio-ranges",
					 NULL, 3, i, &args);

	while (ret != -ENOENT) {
		priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
				    args.args[0]);

		uc_priv->gpio_count += args.args[2];

		ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
						 ++i, &args);
	}

	dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
		(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
		priv->gpio_range);

#ifdef CONFIG_CLK
	struct clk clk;
	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0)
		return ret;

	ret = clk_enable(&clk);

	if (ret) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}
	debug("clock enabled for device %s\n", dev->name);
#endif

	return 0;
}

static const struct udevice_id stm32_gpio_ids[] = {
	{ .compatible = "st,stm32-gpio" },
	{ }
};

U_BOOT_DRIVER(gpio_stm32) = {
	.name	= "gpio_stm32",
	.id	= UCLASS_GPIO,
	.of_match = stm32_gpio_ids,
	.probe	= gpio_stm32_probe,
	.ops	= &gpio_stm32_ops,
	.flags	= DM_UC_FLAG_SEQ_ALIAS,
	.priv_auto_alloc_size	= sizeof(struct stm32_gpio_priv),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
77417102	2	/*
3bc599c9 PC	3	* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3bc599c9 PC	4	* Author(s): Vikas Manocha, <[email protected]> for STMicroelectronics.
77417102 VM	5	*/
	6
	7	#include <common.h>
	8	#include <clk.h>
	9	#include <dm.h>
	10	#include <fdtdec.h>
	11	#include <asm/arch/gpio.h>
	12	#include <asm/arch/stm32.h>
	13	#include <asm/gpio.h>
	14	#include <asm/io.h>
	15	#include <linux/errno.h>
	16	#include <linux/io.h>
	17
77417102 VM	18	#define MODE_BITS(gpio_pin) (gpio_pin * 2)
77417102 VM	19	#define MODE_BITS_MASK 3
798cd708	20	#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
77417102	21
dbf928dd PC	22	/*
	23	* convert gpio offset to gpio index taking into account gpio holes
	24	* into gpio bank
	25	*/
	26	int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
	27	{
	28	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	29	int idx = 0;
	30	int i;
	31
	32	for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
	33	if (priv->gpio_range & BIT(i)) {
	34	if (idx == offset)
	35	return idx;
	36	idx++;
	37	}
	38	}
	39	/* shouldn't happen */
	40	return -EINVAL;
	41	}
	42
77417102 VM	43	static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
	44	{
	45	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	46	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	47	int bits_index;
	48	int mask;
	49	int idx;
	50
	51	idx = stm32_offset_to_index(dev, offset);
	52	if (idx < 0)
	53	return idx;
	54
	55	bits_index = MODE_BITS(idx);
	56	mask = MODE_BITS_MASK << bits_index;
77417102 VM	57
	58	clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_IN << bits_index);
	59
	60	return 0;
	61	}
	62
	63	static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
	64	int value)
	65	{
	66	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	67	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	68	int bits_index;
	69	int mask;
	70	int idx;
	71
	72	idx = stm32_offset_to_index(dev, offset);
	73	if (idx < 0)
	74	return idx;
	75
	76	bits_index = MODE_BITS(idx);
	77	mask = MODE_BITS_MASK << bits_index;
77417102 VM	78
77417102 VM	79	clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
798cd708	80
dbf928dd	81	writel(BSRR_BIT(idx, value), &regs->bsrr);
77417102 VM	82
	83	return 0;
	84	}
	85
	86	static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
	87	{
	88	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	89	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	90	int idx;
	91
	92	idx = stm32_offset_to_index(dev, offset);
	93	if (idx < 0)
	94	return idx;
77417102	95
dbf928dd	96	return readl(&regs->idr) & BIT(idx) ? 1 : 0;
77417102 VM	97	}
	98
	99	static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
	100	{
	101	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	102	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd	103	int idx;
77417102	104
dbf928dd PC	105	idx = stm32_offset_to_index(dev, offset);
	106	if (idx < 0)
	107	return idx;
	108
	109	writel(BSRR_BIT(idx, value), &regs->bsrr);
77417102 VM	110
	111	return 0;
	112	}
	113
cad73249 PC	114	static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
	115	{
	116	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	117	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	118	int bits_index;
	119	int mask;
	120	int idx;
cad73249 PC	121	u32 mode;
cad73249 PC	122
dbf928dd PC	123	idx = stm32_offset_to_index(dev, offset);
	124	if (idx < 0)
	125	return idx;
	126
	127	bits_index = MODE_BITS(idx);
	128	mask = MODE_BITS_MASK << bits_index;
	129
cad73249 PC	130	mode = (readl(&regs->moder) & mask) >> bits_index;
	131	if (mode == STM32_GPIO_MODE_OUT)
	132	return GPIOF_OUTPUT;
	133	if (mode == STM32_GPIO_MODE_IN)
	134	return GPIOF_INPUT;
	135	if (mode == STM32_GPIO_MODE_AN)
	136	return GPIOF_UNUSED;
	137
	138	return GPIOF_FUNC;
	139	}
	140
77417102 VM	141	static const struct dm_gpio_ops gpio_stm32_ops = {
	142	.direction_input = stm32_gpio_direction_input,
	143	.direction_output = stm32_gpio_direction_output,
	144	.get_value = stm32_gpio_get_value,
	145	.set_value = stm32_gpio_set_value,
cad73249	146	.get_function = stm32_gpio_get_function,
77417102 VM	147	};
	148
	149	static int gpio_stm32_probe(struct udevice *dev)
	150	{
	151	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	152	struct stm32_gpio_priv *priv = dev_get_priv(dev);
dbf928dd	153	struct ofnode_phandle_args args;
77417102	154	fdt_addr_t addr;
d876eaf2	155	const char *name;
dbf928dd PC	156	int ret;
dbf928dd PC	157	int i;
77417102	158
d876eaf2	159	addr = dev_read_addr(dev);
77417102 VM	160	if (addr == FDT_ADDR_T_NONE)
	161	return -EINVAL;
	162
	163	priv->regs = (struct stm32_gpio_regs *)addr;
d876eaf2	164	name = dev_read_string(dev, "st,bank-name");
77417102 VM	165	if (!name)
	166	return -EINVAL;
	167	uc_priv->bank_name = name;
dbf928dd PC	168
	169	i = 0;
	170	ret = dev_read_phandle_with_args(dev, "gpio-ranges",
	171	NULL, 3, i, &args);
	172
	173	while (ret != -ENOENT) {
	174	priv->gpio_range \|= GENMASK(args.args[2] + args.args[0] - 1,
	175	args.args[0]);
	176
	177	uc_priv->gpio_count += args.args[2];
	178
	179	ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
	180	++i, &args);
	181	}
	182
	183	dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
	184	(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
	185	priv->gpio_range);
77417102 VM	186
	187	#ifdef CONFIG_CLK
	188	struct clk clk;
77417102 VM	189	ret = clk_get_by_index(dev, 0, &clk);
	190	if (ret < 0)
	191	return ret;
	192
	193	ret = clk_enable(&clk);
	194
	195	if (ret) {
	196	dev_err(dev, "failed to enable clock\n");
	197	return ret;
	198	}
	199	debug("clock enabled for device %s\n", dev->name);
	200	#endif
	201
	202	return 0;
	203	}
	204
	205	static const struct udevice_id stm32_gpio_ids[] = {
	206	{ .compatible = "st,stm32-gpio" },
	207	{ }
	208	};
	209
	210	U_BOOT_DRIVER(gpio_stm32) = {
	211	.name = "gpio_stm32",
	212	.id = UCLASS_GPIO,
	213	.of_match = stm32_gpio_ids,
	214	.probe = gpio_stm32_probe,
	215	.ops = &gpio_stm32_ops,
695c4994	216	.flags = DM_UC_FLAG_SEQ_ALIAS,
77417102 VM	217	.priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
77417102 VM	218	};