[J-u-boot.git] / drivers / gpio / stm32_gpio.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Author(s): Vikas Manocha, <[email protected]> for STMicroelectronics.
 */

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <fdtdec.h>
#include <log.h>
#include <asm/arch/gpio.h>
#include <asm/arch/stm32.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/io.h>

#define MODE_BITS(gpio_pin)		((gpio_pin) * 2)
#define MODE_BITS_MASK			3
#define BSRR_BIT(gpio_pin, value)	BIT((gpio_pin) + (value ? 0 : 16))

#define PUPD_BITS(gpio_pin)		((gpio_pin) * 2)
#define PUPD_MASK			3

#define OTYPE_BITS(gpio_pin)		(gpio_pin)
#define OTYPE_MSK			1

static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
				 int idx,
				 int mode)
{
	int bits_index;
	int mask;

	bits_index = MODE_BITS(idx);
	mask = MODE_BITS_MASK << bits_index;

	clrsetbits_le32(&regs->moder, mask, mode << bits_index);
}

static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
{
	return (readl(&regs->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
}

static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
				 int idx,
				 enum stm32_gpio_otype otype)
{
	int bits;

	bits = OTYPE_BITS(idx);
	clrsetbits_le32(&regs->otyper, OTYPE_MSK << bits, otype << bits);
}

static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
						  int idx)
{
	return (readl(&regs->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
}

static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
				int idx,
				enum stm32_gpio_pupd pupd)
{
	int bits;

	bits = PUPD_BITS(idx);
	clrsetbits_le32(&regs->pupdr, PUPD_MASK << bits, pupd << bits);
}

static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
						int idx)
{
	return (readl(&regs->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
}

/*
 * convert gpio offset to gpio index taking into account gpio holes
 * into gpio bank
 */
int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	unsigned int idx = 0;
	int i;

	for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
		if (priv->gpio_range & BIT(i)) {
			if (idx == offset)
				return idx;
			idx++;
		}
	}
	/* shouldn't happen */
	return -EINVAL;
}

static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);

	return 0;
}

static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
				       int value)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);

	writel(BSRR_BIT(idx, value), &regs->bsrr);

	return 0;
}

static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	return readl(&regs->idr) & BIT(idx) ? 1 : 0;
}

static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	writel(BSRR_BIT(idx, value), &regs->bsrr);

	return 0;
}

static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int bits_index;
	int mask;
	int idx;
	u32 mode;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	bits_index = MODE_BITS(idx);
	mask = MODE_BITS_MASK << bits_index;

	mode = (readl(&regs->moder) & mask) >> bits_index;
	if (mode == STM32_GPIO_MODE_OUT)
		return GPIOF_OUTPUT;
	if (mode == STM32_GPIO_MODE_IN)
		return GPIOF_INPUT;
	if (mode == STM32_GPIO_MODE_AN)
		return GPIOF_UNUSED;

	return GPIOF_FUNC;
}

static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
				    ulong flags)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	if (flags & GPIOD_IS_OUT) {
		int value = GPIOD_FLAGS_OUTPUT(flags);

		if (flags & GPIOD_OPEN_DRAIN)
			stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
		else
			stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
		stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
		writel(BSRR_BIT(idx, value), &regs->bsrr);

	} else if (flags & GPIOD_IS_IN) {
		stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
		if (flags & GPIOD_PULL_UP)
			stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
		else if (flags & GPIOD_PULL_DOWN)
			stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
	}

	return 0;
}

static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
				    ulong *flags)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct stm32_gpio_regs *regs = priv->regs;
	int idx;
	ulong dir_flags = 0;

	idx = stm32_offset_to_index(dev, offset);
	if (idx < 0)
		return idx;

	switch (stm32_gpio_get_moder(regs, idx)) {
	case STM32_GPIO_MODE_OUT:
		dir_flags |= GPIOD_IS_OUT;
		if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
			dir_flags |= GPIOD_OPEN_DRAIN;
		if (readl(&regs->idr) & BIT(idx))
			dir_flags |= GPIOD_IS_OUT_ACTIVE;
		break;
	case STM32_GPIO_MODE_IN:
		dir_flags |= GPIOD_IS_IN;
		switch (stm32_gpio_get_pupd(regs, idx)) {
		case STM32_GPIO_PUPD_UP:
			dir_flags |= GPIOD_PULL_UP;
			break;
		case STM32_GPIO_PUPD_DOWN:
			dir_flags |= GPIOD_PULL_DOWN;
			break;
		default:
			break;
		}
		break;
	default:
		break;
	}
	*flags = dir_flags;

	return 0;
}

static const struct dm_gpio_ops gpio_stm32_ops = {
	.direction_input	= stm32_gpio_direction_input,
	.direction_output	= stm32_gpio_direction_output,
	.get_value		= stm32_gpio_get_value,
	.set_value		= stm32_gpio_set_value,
	.get_function		= stm32_gpio_get_function,
	.set_dir_flags		= stm32_gpio_set_dir_flags,
	.get_dir_flags		= stm32_gpio_get_dir_flags,
};

static int gpio_stm32_probe(struct udevice *dev)
{
	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	struct clk clk;
	fdt_addr_t addr;
	int ret;

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	priv->regs = (struct stm32_gpio_regs *)addr;

	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	struct ofnode_phandle_args args;
	const char *name;
	int i;

	name = dev_read_string(dev, "st,bank-name");
	if (!name)
		return -EINVAL;
	uc_priv->bank_name = name;

	i = 0;
	ret = dev_read_phandle_with_args(dev, "gpio-ranges",
					 NULL, 3, i, &args);

	if (ret == -ENOENT) {
		uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
		priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
	}

	while (ret != -ENOENT) {
		priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
				    args.args[0]);

		uc_priv->gpio_count += args.args[2];

		ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
						 ++i, &args);
	}

	dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
		(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
		priv->gpio_range);

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0)
		return ret;

	ret = clk_enable(&clk);

	if (ret) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}
	debug("clock enabled for device %s\n", dev->name);

	return 0;
}

U_BOOT_DRIVER(gpio_stm32) = {
	.name	= "gpio_stm32",
	.id	= UCLASS_GPIO,
	.probe	= gpio_stm32_probe,
	.ops	= &gpio_stm32_ops,
	.flags	= DM_UC_FLAG_SEQ_ALIAS,
	.priv_auto_alloc_size	= sizeof(struct stm32_gpio_priv),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
77417102	2	/*
3bc599c9 PC	3	* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3bc599c9 PC	4	* Author(s): Vikas Manocha, <[email protected]> for STMicroelectronics.
77417102 VM	5	*/
	6
	7	#include <common.h>
	8	#include <clk.h>
	9	#include <dm.h>
	10	#include <fdtdec.h>
f7ae49fc	11	#include <log.h>
77417102 VM	12	#include <asm/arch/gpio.h>
	13	#include <asm/arch/stm32.h>
	14	#include <asm/gpio.h>
	15	#include <asm/io.h>
336d4615	16	#include <dm/device_compat.h>
cd93d625	17	#include <linux/bitops.h>
77417102 VM	18	#include <linux/errno.h>
	19	#include <linux/io.h>
	20
f13ff88b	21	#define MODE_BITS(gpio_pin) ((gpio_pin) * 2)
77417102	22	#define MODE_BITS_MASK 3
f13ff88b PD	23	#define BSRR_BIT(gpio_pin, value) BIT((gpio_pin) + (value ? 0 : 16))
	24
	25	#define PUPD_BITS(gpio_pin) ((gpio_pin) * 2)
	26	#define PUPD_MASK 3
	27
	28	#define OTYPE_BITS(gpio_pin) (gpio_pin)
	29	#define OTYPE_MSK 1
	30
	31	static void stm32_gpio_set_moder(struct stm32_gpio_regs *regs,
	32	int idx,
	33	int mode)
	34	{
	35	int bits_index;
	36	int mask;
	37
	38	bits_index = MODE_BITS(idx);
	39	mask = MODE_BITS_MASK << bits_index;
	40
	41	clrsetbits_le32(&regs->moder, mask, mode << bits_index);
	42	}
	43
43efbb6a PD	44	static int stm32_gpio_get_moder(struct stm32_gpio_regs *regs, int idx)
	45	{
	46	return (readl(&regs->moder) >> MODE_BITS(idx)) & MODE_BITS_MASK;
	47	}
	48
f13ff88b PD	49	static void stm32_gpio_set_otype(struct stm32_gpio_regs *regs,
	50	int idx,
	51	enum stm32_gpio_otype otype)
	52	{
	53	int bits;
	54
	55	bits = OTYPE_BITS(idx);
	56	clrsetbits_le32(&regs->otyper, OTYPE_MSK << bits, otype << bits);
	57	}
	58
43efbb6a PD	59	static enum stm32_gpio_otype stm32_gpio_get_otype(struct stm32_gpio_regs *regs,
	60	int idx)
	61	{
	62	return (readl(&regs->otyper) >> OTYPE_BITS(idx)) & OTYPE_MSK;
	63	}
	64
f13ff88b PD	65	static void stm32_gpio_set_pupd(struct stm32_gpio_regs *regs,
	66	int idx,
	67	enum stm32_gpio_pupd pupd)
	68	{
	69	int bits;
	70
	71	bits = PUPD_BITS(idx);
	72	clrsetbits_le32(&regs->pupdr, PUPD_MASK << bits, pupd << bits);
	73	}
77417102	74
43efbb6a PD	75	static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
	76	int idx)
	77	{
	78	return (readl(&regs->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
	79	}
	80
dbf928dd PC	81	/*
	82	* convert gpio offset to gpio index taking into account gpio holes
	83	* into gpio bank
	84	*/
	85	int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
	86	{
	87	struct stm32_gpio_priv *priv = dev_get_priv(dev);
99e14b27	88	unsigned int idx = 0;
dbf928dd PC	89	int i;
	90
	91	for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
	92	if (priv->gpio_range & BIT(i)) {
	93	if (idx == offset)
	94	return idx;
	95	idx++;
	96	}
	97	}
	98	/* shouldn't happen */
	99	return -EINVAL;
	100	}
	101
77417102 VM	102	static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
	103	{
	104	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	105	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	106	int idx;
	107
	108	idx = stm32_offset_to_index(dev, offset);
	109	if (idx < 0)
	110	return idx;
	111
f13ff88b	112	stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
77417102 VM	113
	114	return 0;
	115	}
	116
	117	static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
	118	int value)
	119	{
	120	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	121	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	122	int idx;
	123
	124	idx = stm32_offset_to_index(dev, offset);
	125	if (idx < 0)
	126	return idx;
	127
f13ff88b	128	stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
798cd708	129
dbf928dd	130	writel(BSRR_BIT(idx, value), &regs->bsrr);
77417102 VM	131
	132	return 0;
	133	}
	134
	135	static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
	136	{
	137	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	138	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	139	int idx;
	140
	141	idx = stm32_offset_to_index(dev, offset);
	142	if (idx < 0)
	143	return idx;
77417102	144
dbf928dd	145	return readl(&regs->idr) & BIT(idx) ? 1 : 0;
77417102 VM	146	}
	147
	148	static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
	149	{
	150	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	151	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd	152	int idx;
77417102	153
dbf928dd PC	154	idx = stm32_offset_to_index(dev, offset);
	155	if (idx < 0)
	156	return idx;
	157
	158	writel(BSRR_BIT(idx, value), &regs->bsrr);
77417102 VM	159
	160	return 0;
	161	}
	162
cad73249 PC	163	static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
	164	{
	165	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	166	struct stm32_gpio_regs *regs = priv->regs;
dbf928dd PC	167	int bits_index;
	168	int mask;
	169	int idx;
cad73249 PC	170	u32 mode;
cad73249 PC	171
dbf928dd PC	172	idx = stm32_offset_to_index(dev, offset);
	173	if (idx < 0)
	174	return idx;
	175
	176	bits_index = MODE_BITS(idx);
	177	mask = MODE_BITS_MASK << bits_index;
	178
cad73249 PC	179	mode = (readl(&regs->moder) & mask) >> bits_index;
	180	if (mode == STM32_GPIO_MODE_OUT)
	181	return GPIOF_OUTPUT;
	182	if (mode == STM32_GPIO_MODE_IN)
	183	return GPIOF_INPUT;
	184	if (mode == STM32_GPIO_MODE_AN)
	185	return GPIOF_UNUSED;
	186
	187	return GPIOF_FUNC;
	188	}
	189
f13ff88b PD	190	static int stm32_gpio_set_dir_flags(struct udevice *dev, unsigned int offset,
	191	ulong flags)
	192	{
	193	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	194	struct stm32_gpio_regs *regs = priv->regs;
	195	int idx;
	196
	197	idx = stm32_offset_to_index(dev, offset);
	198	if (idx < 0)
	199	return idx;
	200
	201	if (flags & GPIOD_IS_OUT) {
	202	int value = GPIOD_FLAGS_OUTPUT(flags);
	203
	204	if (flags & GPIOD_OPEN_DRAIN)
	205	stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
	206	else
	207	stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
	208	stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
	209	writel(BSRR_BIT(idx, value), &regs->bsrr);
	210
	211	} else if (flags & GPIOD_IS_IN) {
	212	stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
	213	if (flags & GPIOD_PULL_UP)
	214	stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
	215	else if (flags & GPIOD_PULL_DOWN)
	216	stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
	217	}
	218
	219	return 0;
	220	}
	221
43efbb6a PD	222	static int stm32_gpio_get_dir_flags(struct udevice *dev, unsigned int offset,
	223	ulong *flags)
	224	{
	225	struct stm32_gpio_priv *priv = dev_get_priv(dev);
	226	struct stm32_gpio_regs *regs = priv->regs;
	227	int idx;
	228	ulong dir_flags = 0;
	229
	230	idx = stm32_offset_to_index(dev, offset);
	231	if (idx < 0)
	232	return idx;
	233
	234	switch (stm32_gpio_get_moder(regs, idx)) {
	235	case STM32_GPIO_MODE_OUT:
	236	dir_flags \|= GPIOD_IS_OUT;
	237	if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
	238	dir_flags \|= GPIOD_OPEN_DRAIN;
	239	if (readl(&regs->idr) & BIT(idx))
	240	dir_flags \|= GPIOD_IS_OUT_ACTIVE;
	241	break;
	242	case STM32_GPIO_MODE_IN:
	243	dir_flags \|= GPIOD_IS_IN;
	244	switch (stm32_gpio_get_pupd(regs, idx)) {
	245	case STM32_GPIO_PUPD_UP:
	246	dir_flags \|= GPIOD_PULL_UP;
	247	break;
	248	case STM32_GPIO_PUPD_DOWN:
	249	dir_flags \|= GPIOD_PULL_DOWN;
	250	break;
	251	default:
	252	break;
	253	}
	254	break;
	255	default:
	256	break;
	257	}
	258	*flags = dir_flags;
	259
	260	return 0;
	261	}
	262
77417102 VM	263	static const struct dm_gpio_ops gpio_stm32_ops = {
	264	.direction_input = stm32_gpio_direction_input,
	265	.direction_output = stm32_gpio_direction_output,
	266	.get_value = stm32_gpio_get_value,
	267	.set_value = stm32_gpio_set_value,
cad73249	268	.get_function = stm32_gpio_get_function,
f13ff88b	269	.set_dir_flags = stm32_gpio_set_dir_flags,
43efbb6a	270	.get_dir_flags = stm32_gpio_get_dir_flags,
77417102 VM	271	};
	272
	273	static int gpio_stm32_probe(struct udevice *dev)
	274	{
77417102	275	struct stm32_gpio_priv *priv = dev_get_priv(dev);
8b6d45ab	276	struct clk clk;
77417102	277	fdt_addr_t addr;
dbf928dd	278	int ret;
77417102	279
d876eaf2	280	addr = dev_read_addr(dev);
77417102 VM	281	if (addr == FDT_ADDR_T_NONE)
	282	return -EINVAL;
	283
	284	priv->regs = (struct stm32_gpio_regs *)addr;
4fb22463	285
4fb22463 PC	286	struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	287	struct ofnode_phandle_args args;
	288	const char *name;
	289	int i;
	290
d876eaf2	291	name = dev_read_string(dev, "st,bank-name");
77417102 VM	292	if (!name)
	293	return -EINVAL;
	294	uc_priv->bank_name = name;
dbf928dd PC	295
	296	i = 0;
	297	ret = dev_read_phandle_with_args(dev, "gpio-ranges",
	298	NULL, 3, i, &args);
	299
39a8f0be PC	300	if (ret == -ENOENT) {
	301	uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
	302	priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
	303	}
	304
dbf928dd PC	305	while (ret != -ENOENT) {
	306	priv->gpio_range \|= GENMASK(args.args[2] + args.args[0] - 1,
	307	args.args[0]);
	308
	309	uc_priv->gpio_count += args.args[2];
	310
	311	ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
	312	++i, &args);
	313	}
	314
	315	dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
	316	(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
	317	priv->gpio_range);
f17412ed	318
77417102 VM	319	ret = clk_get_by_index(dev, 0, &clk);
	320	if (ret < 0)
	321	return ret;
	322
	323	ret = clk_enable(&clk);
	324
	325	if (ret) {
	326	dev_err(dev, "failed to enable clock\n");
	327	return ret;
	328	}
	329	debug("clock enabled for device %s\n", dev->name);
77417102 VM	330
	331	return 0;
	332	}
	333
77417102 VM	334	U_BOOT_DRIVER(gpio_stm32) = {
	335	.name = "gpio_stm32",
	336	.id = UCLASS_GPIO,
77417102 VM	337	.probe = gpio_stm32_probe,
77417102 VM	338	.ops = &gpio_stm32_ops,
695c4994	339	.flags = DM_UC_FLAG_SEQ_ALIAS,
77417102 VM	340	.priv_auto_alloc_size = sizeof(struct stm32_gpio_priv),
77417102 VM	341	};