]> Git Repo - J-u-boot.git/blame - drivers/net/phy/phy.c
Fix some checkpatch warnings in calls to debug()
[J-u-boot.git] / drivers / net / phy / phy.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
5f184715
AF
2/*
3 * Generic PHY Management code
4 *
5f184715
AF
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 * author Andy Fleming
7 *
8 * Based loosely off of Linux's PHY Lib
9 */
5f184715 10#include <common.h>
24b852a7 11#include <console.h>
c74c8e66 12#include <dm.h>
5f184715
AF
13#include <malloc.h>
14#include <net.h>
15#include <command.h>
16#include <miiphy.h>
17#include <phy.h>
18#include <errno.h>
1adb406b 19#include <linux/err.h>
597fe041 20#include <linux/compiler.h>
5f184715 21
abbfcbe5
MS
22DECLARE_GLOBAL_DATA_PTR;
23
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AF
24/* Generic PHY support and helper functions */
25
26/**
8d631203 27 * genphy_config_advert - sanitize and advertise auto-negotiation parameters
5f184715
AF
28 * @phydev: target phy_device struct
29 *
30 * Description: Writes MII_ADVERTISE with the appropriate values,
31 * after sanitizing the values to make sure we only advertise
32 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
33 * hasn't changed, and > 0 if it has changed.
34 */
960d70c6 35static int genphy_config_advert(struct phy_device *phydev)
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AF
36{
37 u32 advertise;
bbdcaff1 38 int oldadv, adv, bmsr;
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AF
39 int err, changed = 0;
40
bbdcaff1 41 /* Only allow advertising what this PHY supports */
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AF
42 phydev->advertising &= phydev->supported;
43 advertise = phydev->advertising;
44
45 /* Setup standard advertisement */
bbdcaff1
FF
46 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
47 oldadv = adv;
5f184715
AF
48
49 if (adv < 0)
50 return adv;
51
52 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP |
53 ADVERTISE_PAUSE_ASYM);
54 if (advertise & ADVERTISED_10baseT_Half)
55 adv |= ADVERTISE_10HALF;
56 if (advertise & ADVERTISED_10baseT_Full)
57 adv |= ADVERTISE_10FULL;
58 if (advertise & ADVERTISED_100baseT_Half)
59 adv |= ADVERTISE_100HALF;
60 if (advertise & ADVERTISED_100baseT_Full)
61 adv |= ADVERTISE_100FULL;
62 if (advertise & ADVERTISED_Pause)
63 adv |= ADVERTISE_PAUSE_CAP;
64 if (advertise & ADVERTISED_Asym_Pause)
65 adv |= ADVERTISE_PAUSE_ASYM;
de1d786e
CC
66 if (advertise & ADVERTISED_1000baseX_Half)
67 adv |= ADVERTISE_1000XHALF;
68 if (advertise & ADVERTISED_1000baseX_Full)
69 adv |= ADVERTISE_1000XFULL;
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AF
70
71 if (adv != oldadv) {
72 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv);
73
74 if (err < 0)
75 return err;
76 changed = 1;
77 }
78
bbdcaff1
FF
79 bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
80 if (bmsr < 0)
81 return bmsr;
82
83 /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all
84 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a
85 * logical 1.
86 */
87 if (!(bmsr & BMSR_ESTATEN))
88 return changed;
89
5f184715 90 /* Configure gigabit if it's supported */
bbdcaff1
FF
91 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
92 oldadv = adv;
93
94 if (adv < 0)
95 return adv;
5f184715 96
bbdcaff1 97 adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
5f184715 98
bbdcaff1
FF
99 if (phydev->supported & (SUPPORTED_1000baseT_Half |
100 SUPPORTED_1000baseT_Full)) {
5f184715
AF
101 if (advertise & SUPPORTED_1000baseT_Half)
102 adv |= ADVERTISE_1000HALF;
103 if (advertise & SUPPORTED_1000baseT_Full)
104 adv |= ADVERTISE_1000FULL;
bbdcaff1 105 }
5f184715 106
bbdcaff1
FF
107 if (adv != oldadv)
108 changed = 1;
5f184715 109
bbdcaff1
FF
110 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv);
111 if (err < 0)
112 return err;
5f184715
AF
113
114 return changed;
115}
116
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AF
117/**
118 * genphy_setup_forced - configures/forces speed/duplex from @phydev
119 * @phydev: target phy_device struct
120 *
121 * Description: Configures MII_BMCR to force speed/duplex
122 * to the values in phydev. Assumes that the values are valid.
123 */
960d70c6 124static int genphy_setup_forced(struct phy_device *phydev)
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AF
125{
126 int err;
53b0c38c 127 int ctl = BMCR_ANRESTART;
5f184715 128
8d631203
MS
129 phydev->pause = 0;
130 phydev->asym_pause = 0;
5f184715 131
8d631203 132 if (phydev->speed == SPEED_1000)
5f184715 133 ctl |= BMCR_SPEED1000;
8d631203 134 else if (phydev->speed == SPEED_100)
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AF
135 ctl |= BMCR_SPEED100;
136
8d631203 137 if (phydev->duplex == DUPLEX_FULL)
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AF
138 ctl |= BMCR_FULLDPLX;
139
140 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
141
142 return err;
143}
144
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AF
145/**
146 * genphy_restart_aneg - Enable and Restart Autonegotiation
147 * @phydev: target phy_device struct
148 */
149int genphy_restart_aneg(struct phy_device *phydev)
150{
151 int ctl;
152
153 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
154
155 if (ctl < 0)
156 return ctl;
157
158 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
159
160 /* Don't isolate the PHY if we're negotiating */
161 ctl &= ~(BMCR_ISOLATE);
162
163 ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl);
164
165 return ctl;
166}
167
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AF
168/**
169 * genphy_config_aneg - restart auto-negotiation or write BMCR
170 * @phydev: target phy_device struct
171 *
172 * Description: If auto-negotiation is enabled, we configure the
173 * advertising, and then restart auto-negotiation. If it is not
174 * enabled, then we write the BMCR.
175 */
176int genphy_config_aneg(struct phy_device *phydev)
177{
178 int result;
179
8d631203 180 if (phydev->autoneg != AUTONEG_ENABLE)
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AF
181 return genphy_setup_forced(phydev);
182
183 result = genphy_config_advert(phydev);
184
185 if (result < 0) /* error */
186 return result;
187
188 if (result == 0) {
8d631203
MS
189 /*
190 * Advertisment hasn't changed, but maybe aneg was never on to
191 * begin with? Or maybe phy was isolated?
192 */
5f184715
AF
193 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
194
195 if (ctl < 0)
196 return ctl;
197
198 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
199 result = 1; /* do restart aneg */
200 }
201
8d631203
MS
202 /*
203 * Only restart aneg if we are advertising something different
204 * than we were before.
205 */
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AF
206 if (result > 0)
207 result = genphy_restart_aneg(phydev);
208
209 return result;
210}
211
212/**
213 * genphy_update_link - update link status in @phydev
214 * @phydev: target phy_device struct
215 *
216 * Description: Update the value in phydev->link to reflect the
217 * current link value. In order to do this, we need to read
218 * the status register twice, keeping the second value.
219 */
220int genphy_update_link(struct phy_device *phydev)
221{
222 unsigned int mii_reg;
223
224 /*
225 * Wait if the link is up, and autonegotiation is in progress
226 * (ie - we're capable and it's not done)
227 */
228 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
229
230 /*
231 * If we already saw the link up, and it hasn't gone down, then
232 * we don't need to wait for autoneg again
233 */
234 if (phydev->link && mii_reg & BMSR_LSTATUS)
235 return 0;
236
1f9e672c
AM
237 if ((phydev->autoneg == AUTONEG_ENABLE) &&
238 !(mii_reg & BMSR_ANEGCOMPLETE)) {
5f184715
AF
239 int i = 0;
240
241 printf("%s Waiting for PHY auto negotiation to complete",
8d631203 242 phydev->dev->name);
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AF
243 while (!(mii_reg & BMSR_ANEGCOMPLETE)) {
244 /*
245 * Timeout reached ?
246 */
a44ee246 247 if (i > (PHY_ANEG_TIMEOUT / 50)) {
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AF
248 printf(" TIMEOUT !\n");
249 phydev->link = 0;
ef5e821b 250 return -ETIMEDOUT;
5f184715
AF
251 }
252
253 if (ctrlc()) {
254 puts("user interrupt!\n");
255 phydev->link = 0;
256 return -EINTR;
257 }
258
27c3f70f 259 if ((i++ % 10) == 0)
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AF
260 printf(".");
261
5f184715 262 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
27c3f70f 263 mdelay(50); /* 50 ms */
5f184715
AF
264 }
265 printf(" done\n");
266 phydev->link = 1;
267 } else {
268 /* Read the link a second time to clear the latched state */
269 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
270
271 if (mii_reg & BMSR_LSTATUS)
272 phydev->link = 1;
273 else
274 phydev->link = 0;
275 }
276
277 return 0;
278}
279
280/*
281 * Generic function which updates the speed and duplex. If
282 * autonegotiation is enabled, it uses the AND of the link
283 * partner's advertised capabilities and our advertised
284 * capabilities. If autonegotiation is disabled, we use the
285 * appropriate bits in the control register.
286 *
287 * Stolen from Linux's mii.c and phy_device.c
288 */
e2043f5c 289int genphy_parse_link(struct phy_device *phydev)
5f184715
AF
290{
291 int mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
292
293 /* We're using autonegotiation */
1f9e672c 294 if (phydev->autoneg == AUTONEG_ENABLE) {
5f184715 295 u32 lpa = 0;
f6d1f6e4 296 int gblpa = 0;
de1d786e 297 u32 estatus = 0;
5f184715
AF
298
299 /* Check for gigabit capability */
3a530d1b
DD
300 if (phydev->supported & (SUPPORTED_1000baseT_Full |
301 SUPPORTED_1000baseT_Half)) {
5f184715
AF
302 /* We want a list of states supported by
303 * both PHYs in the link
304 */
305 gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
f6d1f6e4 306 if (gblpa < 0) {
8d631203
MS
307 debug("Could not read MII_STAT1000. ");
308 debug("Ignoring gigabit capability\n");
f6d1f6e4
HS
309 gblpa = 0;
310 }
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AF
311 gblpa &= phy_read(phydev,
312 MDIO_DEVAD_NONE, MII_CTRL1000) << 2;
313 }
314
315 /* Set the baseline so we only have to set them
316 * if they're different
317 */
318 phydev->speed = SPEED_10;
319 phydev->duplex = DUPLEX_HALF;
320
321 /* Check the gigabit fields */
322 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
323 phydev->speed = SPEED_1000;
324
325 if (gblpa & PHY_1000BTSR_1000FD)
326 phydev->duplex = DUPLEX_FULL;
327
328 /* We're done! */
329 return 0;
330 }
331
332 lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
333 lpa &= phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
334
0dcfb0fc 335 if (lpa & (LPA_100FULL | LPA_100HALF)) {
5f184715
AF
336 phydev->speed = SPEED_100;
337
0dcfb0fc
WD
338 if (lpa & LPA_100FULL)
339 phydev->duplex = DUPLEX_FULL;
340
8d631203 341 } else if (lpa & LPA_10FULL) {
5f184715 342 phydev->duplex = DUPLEX_FULL;
8d631203 343 }
de1d786e 344
9ba30f6b
SS
345 /*
346 * Extended status may indicate that the PHY supports
347 * 1000BASE-T/X even though the 1000BASE-T registers
348 * are missing. In this case we can't tell whether the
349 * peer also supports it, so we only check extended
350 * status if the 1000BASE-T registers are actually
351 * missing.
352 */
353 if ((mii_reg & BMSR_ESTATEN) && !(mii_reg & BMSR_ERCAP))
de1d786e
CC
354 estatus = phy_read(phydev, MDIO_DEVAD_NONE,
355 MII_ESTATUS);
356
357 if (estatus & (ESTATUS_1000_XFULL | ESTATUS_1000_XHALF |
358 ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
359 phydev->speed = SPEED_1000;
360 if (estatus & (ESTATUS_1000_XFULL | ESTATUS_1000_TFULL))
361 phydev->duplex = DUPLEX_FULL;
362 }
363
5f184715
AF
364 } else {
365 u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
366
367 phydev->speed = SPEED_10;
368 phydev->duplex = DUPLEX_HALF;
369
370 if (bmcr & BMCR_FULLDPLX)
371 phydev->duplex = DUPLEX_FULL;
372
373 if (bmcr & BMCR_SPEED1000)
374 phydev->speed = SPEED_1000;
375 else if (bmcr & BMCR_SPEED100)
376 phydev->speed = SPEED_100;
377 }
378
379 return 0;
380}
381
382int genphy_config(struct phy_device *phydev)
383{
384 int val;
385 u32 features;
386
5f184715
AF
387 features = (SUPPORTED_TP | SUPPORTED_MII
388 | SUPPORTED_AUI | SUPPORTED_FIBRE |
389 SUPPORTED_BNC);
390
391 /* Do we support autonegotiation? */
392 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
393
394 if (val < 0)
395 return val;
396
397 if (val & BMSR_ANEGCAPABLE)
398 features |= SUPPORTED_Autoneg;
399
400 if (val & BMSR_100FULL)
401 features |= SUPPORTED_100baseT_Full;
402 if (val & BMSR_100HALF)
403 features |= SUPPORTED_100baseT_Half;
404 if (val & BMSR_10FULL)
405 features |= SUPPORTED_10baseT_Full;
406 if (val & BMSR_10HALF)
407 features |= SUPPORTED_10baseT_Half;
408
409 if (val & BMSR_ESTATEN) {
410 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_ESTATUS);
411
412 if (val < 0)
413 return val;
414
415 if (val & ESTATUS_1000_TFULL)
416 features |= SUPPORTED_1000baseT_Full;
417 if (val & ESTATUS_1000_THALF)
418 features |= SUPPORTED_1000baseT_Half;
de1d786e
CC
419 if (val & ESTATUS_1000_XFULL)
420 features |= SUPPORTED_1000baseX_Full;
421 if (val & ESTATUS_1000_XHALF)
9a5dad23 422 features |= SUPPORTED_1000baseX_Half;
5f184715
AF
423 }
424
44bc3174
SH
425 phydev->supported &= features;
426 phydev->advertising &= features;
5f184715
AF
427
428 genphy_config_aneg(phydev);
429
430 return 0;
431}
432
433int genphy_startup(struct phy_device *phydev)
434{
b733c278 435 int ret;
5f184715 436
b733c278
MS
437 ret = genphy_update_link(phydev);
438 if (ret)
439 return ret;
440
441 return genphy_parse_link(phydev);
5f184715
AF
442}
443
444int genphy_shutdown(struct phy_device *phydev)
445{
446 return 0;
447}
448
449static struct phy_driver genphy_driver = {
450 .uid = 0xffffffff,
451 .mask = 0xffffffff,
452 .name = "Generic PHY",
44bc3174
SH
453 .features = PHY_GBIT_FEATURES | SUPPORTED_MII |
454 SUPPORTED_AUI | SUPPORTED_FIBRE |
455 SUPPORTED_BNC,
5f184715
AF
456 .config = genphy_config,
457 .startup = genphy_startup,
458 .shutdown = genphy_shutdown,
459};
460
be49508a
SDPP
461int genphy_init(void)
462{
463 return phy_register(&genphy_driver);
464}
465
5f184715
AF
466static LIST_HEAD(phy_drivers);
467
468int phy_init(void)
469{
c689c486
SDPP
470#ifdef CONFIG_NEEDS_MANUAL_RELOC
471 /*
472 * The pointers inside phy_drivers also needs to be updated incase of
473 * manual reloc, without which these points to some invalid
474 * pre reloc address and leads to invalid accesses, hangs.
475 */
476 struct list_head *head = &phy_drivers;
477
478 head->next = (void *)head->next + gd->reloc_off;
479 head->prev = (void *)head->prev + gd->reloc_off;
480#endif
481
137963d7
FF
482#ifdef CONFIG_B53_SWITCH
483 phy_b53_init();
484#endif
24ae3961
KS
485#ifdef CONFIG_MV88E61XX_SWITCH
486 phy_mv88e61xx_init();
487#endif
f7c38cf8
SX
488#ifdef CONFIG_PHY_AQUANTIA
489 phy_aquantia_init();
490#endif
9082eeac
AF
491#ifdef CONFIG_PHY_ATHEROS
492 phy_atheros_init();
493#endif
494#ifdef CONFIG_PHY_BROADCOM
495 phy_broadcom_init();
496#endif
9b18e519
SL
497#ifdef CONFIG_PHY_CORTINA
498 phy_cortina_init();
499#endif
9082eeac
AF
500#ifdef CONFIG_PHY_DAVICOM
501 phy_davicom_init();
502#endif
f485c8a3
MP
503#ifdef CONFIG_PHY_ET1011C
504 phy_et1011c_init();
505#endif
9082eeac
AF
506#ifdef CONFIG_PHY_LXT
507 phy_lxt_init();
508#endif
509#ifdef CONFIG_PHY_MARVELL
510 phy_marvell_init();
511#endif
d397f7c4
AG
512#ifdef CONFIG_PHY_MICREL_KSZ8XXX
513 phy_micrel_ksz8xxx_init();
514#endif
515#ifdef CONFIG_PHY_MICREL_KSZ90X1
516 phy_micrel_ksz90x1_init();
9082eeac 517#endif
8995a96d
NA
518#ifdef CONFIG_PHY_MESON_GXL
519 phy_meson_gxl_init();
520#endif
9082eeac
AF
521#ifdef CONFIG_PHY_NATSEMI
522 phy_natsemi_init();
523#endif
524#ifdef CONFIG_PHY_REALTEK
525 phy_realtek_init();
526#endif
5751aa2f
NI
527#ifdef CONFIG_PHY_SMSC
528 phy_smsc_init();
529#endif
9082eeac
AF
530#ifdef CONFIG_PHY_TERANETICS
531 phy_teranetics_init();
532#endif
721aed79
EI
533#ifdef CONFIG_PHY_TI
534 phy_ti_init();
535#endif
9082eeac
AF
536#ifdef CONFIG_PHY_VITESSE
537 phy_vitesse_init();
538#endif
ed6fad3e
SDPP
539#ifdef CONFIG_PHY_XILINX
540 phy_xilinx_init();
541#endif
a5fd13ad
JH
542#ifdef CONFIG_PHY_MSCC
543 phy_mscc_init();
544#endif
db40c1aa
HS
545#ifdef CONFIG_PHY_FIXED
546 phy_fixed_init();
f41e588c 547#endif
e2ffeaa1
SMJ
548#ifdef CONFIG_PHY_NCSI
549 phy_ncsi_init();
550#endif
f41e588c
SDPP
551#ifdef CONFIG_PHY_XILINX_GMII2RGMII
552 phy_xilinx_gmii2rgmii_init();
db40c1aa 553#endif
be49508a
SDPP
554 genphy_init();
555
5f184715
AF
556 return 0;
557}
558
559int phy_register(struct phy_driver *drv)
560{
561 INIT_LIST_HEAD(&drv->list);
562 list_add_tail(&drv->list, &phy_drivers);
563
abbfcbe5
MS
564#ifdef CONFIG_NEEDS_MANUAL_RELOC
565 if (drv->probe)
566 drv->probe += gd->reloc_off;
567 if (drv->config)
568 drv->config += gd->reloc_off;
569 if (drv->startup)
570 drv->startup += gd->reloc_off;
571 if (drv->shutdown)
572 drv->shutdown += gd->reloc_off;
573 if (drv->readext)
574 drv->readext += gd->reloc_off;
575 if (drv->writeext)
576 drv->writeext += gd->reloc_off;
4f6746dc
CC
577 if (drv->read_mmd)
578 drv->read_mmd += gd->reloc_off;
579 if (drv->write_mmd)
580 drv->write_mmd += gd->reloc_off;
abbfcbe5 581#endif
5f184715
AF
582 return 0;
583}
584
b18acb0a
AB
585int phy_set_supported(struct phy_device *phydev, u32 max_speed)
586{
587 /* The default values for phydev->supported are provided by the PHY
588 * driver "features" member, we want to reset to sane defaults first
589 * before supporting higher speeds.
590 */
591 phydev->supported &= PHY_DEFAULT_FEATURES;
592
593 switch (max_speed) {
594 default:
595 return -ENOTSUPP;
596 case SPEED_1000:
597 phydev->supported |= PHY_1000BT_FEATURES;
598 /* fall through */
599 case SPEED_100:
600 phydev->supported |= PHY_100BT_FEATURES;
601 /* fall through */
602 case SPEED_10:
603 phydev->supported |= PHY_10BT_FEATURES;
604 }
605
606 return 0;
607}
608
960d70c6 609static int phy_probe(struct phy_device *phydev)
5f184715
AF
610{
611 int err = 0;
612
8d631203
MS
613 phydev->advertising = phydev->drv->features;
614 phydev->supported = phydev->drv->features;
615
5f184715
AF
616 phydev->mmds = phydev->drv->mmds;
617
618 if (phydev->drv->probe)
619 err = phydev->drv->probe(phydev);
620
621 return err;
622}
623
624static struct phy_driver *generic_for_interface(phy_interface_t interface)
625{
626#ifdef CONFIG_PHYLIB_10G
627 if (is_10g_interface(interface))
628 return &gen10g_driver;
629#endif
630
631 return &genphy_driver;
632}
633
960d70c6 634static struct phy_driver *get_phy_driver(struct phy_device *phydev,
8d631203 635 phy_interface_t interface)
5f184715
AF
636{
637 struct list_head *entry;
638 int phy_id = phydev->phy_id;
639 struct phy_driver *drv = NULL;
640
641 list_for_each(entry, &phy_drivers) {
642 drv = list_entry(entry, struct phy_driver, list);
643 if ((drv->uid & drv->mask) == (phy_id & drv->mask))
644 return drv;
645 }
646
647 /* If we made it here, there's no driver for this PHY */
648 return generic_for_interface(interface);
649}
650
960d70c6 651static struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
b3eabd82 652 u32 phy_id, bool is_c45,
960d70c6 653 phy_interface_t interface)
5f184715
AF
654{
655 struct phy_device *dev;
656
8d631203
MS
657 /*
658 * We allocate the device, and initialize the
659 * default values
660 */
5f184715
AF
661 dev = malloc(sizeof(*dev));
662 if (!dev) {
663 printf("Failed to allocate PHY device for %s:%d\n",
8d631203 664 bus->name, addr);
5f184715
AF
665 return NULL;
666 }
667
668 memset(dev, 0, sizeof(*dev));
669
670 dev->duplex = -1;
26d3acda 671 dev->link = 0;
5f184715
AF
672 dev->interface = interface;
673
eef0b8a9
GS
674#ifdef CONFIG_DM_ETH
675 dev->node = ofnode_null();
676#endif
677
5f184715
AF
678 dev->autoneg = AUTONEG_ENABLE;
679
680 dev->addr = addr;
681 dev->phy_id = phy_id;
b3eabd82 682 dev->is_c45 = is_c45;
5f184715
AF
683 dev->bus = bus;
684
685 dev->drv = get_phy_driver(dev, interface);
686
05eb6a69
SDPP
687 if (phy_probe(dev)) {
688 printf("%s, PHY probe failed\n", __func__);
689 return NULL;
690 }
5f184715 691
7b4ea2d8
MS
692 if (addr >= 0 && addr < PHY_MAX_ADDR)
693 bus->phymap[addr] = dev;
5f184715
AF
694
695 return dev;
696}
697
698/**
699 * get_phy_id - reads the specified addr for its ID.
700 * @bus: the target MII bus
701 * @addr: PHY address on the MII bus
702 * @phy_id: where to store the ID retrieved.
703 *
704 * Description: Reads the ID registers of the PHY at @addr on the
705 * @bus, stores it in @phy_id and returns zero on success.
706 */
5707d5ff 707int __weak get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
5f184715
AF
708{
709 int phy_reg;
710
8d631203
MS
711 /*
712 * Grab the bits from PHYIR1, and put them
713 * in the upper half
714 */
5f184715
AF
715 phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
716
717 if (phy_reg < 0)
718 return -EIO;
719
720 *phy_id = (phy_reg & 0xffff) << 16;
721
722 /* Grab the bits from PHYIR2, and put them in the lower half */
723 phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
724
725 if (phy_reg < 0)
726 return -EIO;
727
728 *phy_id |= (phy_reg & 0xffff);
729
730 return 0;
731}
732
1adb406b 733static struct phy_device *create_phy_by_mask(struct mii_dev *bus,
8d631203
MS
734 uint phy_mask, int devad,
735 phy_interface_t interface)
1adb406b
TK
736{
737 u32 phy_id = 0xffffffff;
b3eabd82 738 bool is_c45;
8d631203 739
1adb406b
TK
740 while (phy_mask) {
741 int addr = ffs(phy_mask) - 1;
742 int r = get_phy_id(bus, addr, devad, &phy_id);
3bf135b6
AM
743
744 /*
745 * If the PHY ID is flat 0 we ignore it. There are C45 PHYs
746 * that return all 0s for C22 reads (like Aquantia AQR112) and
747 * there are C22 PHYs that return all 0s for C45 reads (like
748 * Atheros AR8035).
749 */
750 if (r == 0 && phy_id == 0)
751 goto next;
752
1adb406b 753 /* If the PHY ID is mostly f's, we didn't find anything */
b3eabd82
PB
754 if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff) {
755 is_c45 = (devad == MDIO_DEVAD_NONE) ? false : true;
756 return phy_device_create(bus, addr, phy_id, is_c45,
757 interface);
758 }
3bf135b6 759next:
1adb406b
TK
760 phy_mask &= ~(1 << addr);
761 }
762 return NULL;
763}
764
765static struct phy_device *search_for_existing_phy(struct mii_dev *bus,
8d631203
MS
766 uint phy_mask,
767 phy_interface_t interface)
1adb406b
TK
768{
769 /* If we have one, return the existing device, with new interface */
770 while (phy_mask) {
771 int addr = ffs(phy_mask) - 1;
8d631203 772
1adb406b
TK
773 if (bus->phymap[addr]) {
774 bus->phymap[addr]->interface = interface;
775 return bus->phymap[addr];
776 }
777 phy_mask &= ~(1 << addr);
778 }
779 return NULL;
780}
781
782static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus,
8d631203
MS
783 uint phy_mask,
784 phy_interface_t interface)
1adb406b
TK
785{
786 int i;
787 struct phy_device *phydev;
788
789 phydev = search_for_existing_phy(bus, phy_mask, interface);
790 if (phydev)
791 return phydev;
792 /* Try Standard (ie Clause 22) access */
793 /* Otherwise we have to try Clause 45 */
794 for (i = 0; i < 5; i++) {
795 phydev = create_phy_by_mask(bus, phy_mask,
8d631203 796 i ? i : MDIO_DEVAD_NONE, interface);
1adb406b
TK
797 if (IS_ERR(phydev))
798 return NULL;
799 if (phydev)
800 return phydev;
801 }
3e1949d7
BM
802
803 debug("\n%s PHY: ", bus->name);
804 while (phy_mask) {
805 int addr = ffs(phy_mask) - 1;
8d631203 806
3e1949d7
BM
807 debug("%d ", addr);
808 phy_mask &= ~(1 << addr);
809 }
810 debug("not found\n");
0132b9ab
BM
811
812 return NULL;
1adb406b
TK
813}
814
5f184715 815/**
8d631203
MS
816 * get_phy_device - reads the specified PHY device and returns its
817 * @phy_device struct
5f184715
AF
818 * @bus: the target MII bus
819 * @addr: PHY address on the MII bus
820 *
821 * Description: Reads the ID registers of the PHY at @addr on the
822 * @bus, then allocates and returns the phy_device to represent it.
823 */
960d70c6
KP
824static struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
825 phy_interface_t interface)
5f184715 826{
1adb406b 827 return get_phy_device_by_mask(bus, 1 << addr, interface);
5f184715
AF
828}
829
830int phy_reset(struct phy_device *phydev)
831{
832 int reg;
833 int timeout = 500;
834 int devad = MDIO_DEVAD_NONE;
835
ddcd1f30
SX
836 if (phydev->flags & PHY_FLAG_BROKEN_RESET)
837 return 0;
838
5f184715
AF
839#ifdef CONFIG_PHYLIB_10G
840 /* If it's 10G, we need to issue reset through one of the MMDs */
841 if (is_10g_interface(phydev->interface)) {
842 if (!phydev->mmds)
843 gen10g_discover_mmds(phydev);
844
845 devad = ffs(phydev->mmds) - 1;
846 }
847#endif
848
a058052c 849 if (phy_write(phydev, devad, MII_BMCR, BMCR_RESET) < 0) {
5f184715
AF
850 debug("PHY reset failed\n");
851 return -1;
852 }
853
854#ifdef CONFIG_PHY_RESET_DELAY
855 udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */
856#endif
857 /*
858 * Poll the control register for the reset bit to go to 0 (it is
859 * auto-clearing). This should happen within 0.5 seconds per the
860 * IEEE spec.
861 */
a058052c 862 reg = phy_read(phydev, devad, MII_BMCR);
5f184715
AF
863 while ((reg & BMCR_RESET) && timeout--) {
864 reg = phy_read(phydev, devad, MII_BMCR);
865
866 if (reg < 0) {
867 debug("PHY status read failed\n");
868 return -1;
869 }
870 udelay(1000);
871 }
872
873 if (reg & BMCR_RESET) {
874 puts("PHY reset timed out\n");
875 return -1;
876 }
877
878 return 0;
879}
880
881int miiphy_reset(const char *devname, unsigned char addr)
882{
883 struct mii_dev *bus = miiphy_get_dev_by_name(devname);
884 struct phy_device *phydev;
885
886 /*
887 * miiphy_reset was only used on standard PHYs, so we'll fake it here.
888 * If later code tries to connect with the right interface, this will
889 * be corrected by get_phy_device in phy_connect()
890 */
891 phydev = get_phy_device(bus, addr, PHY_INTERFACE_MODE_MII);
892
893 return phy_reset(phydev);
894}
895
8d631203
MS
896struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask,
897 phy_interface_t interface)
5f184715 898{
5f184715 899 /* Reset the bus */
59370f3f 900 if (bus->reset) {
e3a77218 901 bus->reset(bus);
5f184715 902
59370f3f 903 /* Wait 15ms to make sure the PHY has come out of hard reset */
8d631203 904 mdelay(15);
59370f3f
JK
905 }
906
1adb406b
TK
907 return get_phy_device_by_mask(bus, phy_mask, interface);
908}
5f184715 909
c74c8e66
SG
910#ifdef CONFIG_DM_ETH
911void phy_connect_dev(struct phy_device *phydev, struct udevice *dev)
912#else
1adb406b 913void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev)
c74c8e66 914#endif
1adb406b 915{
5f184715
AF
916 /* Soft Reset the PHY */
917 phy_reset(phydev);
17ecfa9b 918 if (phydev->dev && phydev->dev != dev) {
5f184715 919 printf("%s:%d is connected to %s. Reconnecting to %s\n",
8d631203
MS
920 phydev->bus->name, phydev->addr,
921 phydev->dev->name, dev->name);
1adb406b 922 }
5f184715 923 phydev->dev = dev;
b91a9d9d 924 debug("%s connected to %s\n", dev->name, phydev->drv->name);
1adb406b
TK
925}
926
f41e588c
SDPP
927#ifdef CONFIG_PHY_XILINX_GMII2RGMII
928#ifdef CONFIG_DM_ETH
929static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
930 struct udevice *dev,
931 phy_interface_t interface)
932#else
933static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus,
934 struct eth_device *dev,
935 phy_interface_t interface)
936#endif
937{
938 struct phy_device *phydev = NULL;
939 int sn = dev_of_offset(dev);
940 int off;
941
942 while (sn > 0) {
943 off = fdt_node_offset_by_compatible(gd->fdt_blob, sn,
944 "xlnx,gmii-to-rgmii-1.0");
945 if (off > 0) {
946 phydev = phy_device_create(bus, off,
947 PHY_GMII2RGMII_ID, false,
948 interface);
949 break;
950 }
951 if (off == -FDT_ERR_NOTFOUND)
952 sn = fdt_first_subnode(gd->fdt_blob, sn);
953 else
954 printf("%s: Error finding compat string:%d\n",
955 __func__, off);
956 }
957
958 return phydev;
959}
960#endif
961
c256d3f7 962#ifdef CONFIG_PHY_FIXED
c74c8e66 963#ifdef CONFIG_DM_ETH
c256d3f7
SDPP
964static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
965 struct udevice *dev,
966 phy_interface_t interface)
c74c8e66 967#else
c256d3f7
SDPP
968static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
969 struct eth_device *dev,
970 phy_interface_t interface)
c74c8e66 971#endif
1adb406b 972{
db40c1aa 973 struct phy_device *phydev = NULL;
db40c1aa
HS
974 int sn;
975 const char *name;
8d631203 976
da409ccc 977 sn = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev));
db40c1aa
HS
978 while (sn > 0) {
979 name = fdt_get_name(gd->fdt_blob, sn, NULL);
8d631203 980 if (name && strcmp(name, "fixed-link") == 0) {
b3eabd82
PB
981 phydev = phy_device_create(bus, sn, PHY_FIXED_ID, false,
982 interface);
db40c1aa
HS
983 break;
984 }
985 sn = fdt_next_subnode(gd->fdt_blob, sn);
986 }
c256d3f7
SDPP
987
988 return phydev;
989}
db40c1aa 990#endif
c256d3f7
SDPP
991
992#ifdef CONFIG_DM_ETH
993struct phy_device *phy_connect(struct mii_dev *bus, int addr,
994 struct udevice *dev,
995 phy_interface_t interface)
996#else
997struct phy_device *phy_connect(struct mii_dev *bus, int addr,
998 struct eth_device *dev,
999 phy_interface_t interface)
1000#endif
1001{
1002 struct phy_device *phydev = NULL;
1f607896 1003 uint mask = (addr >= 0) ? (1 << addr) : 0xffffffff;
c256d3f7
SDPP
1004
1005#ifdef CONFIG_PHY_FIXED
1006 phydev = phy_connect_fixed(bus, dev, interface);
1007#endif
e2ffeaa1
SMJ
1008
1009#ifdef CONFIG_PHY_NCSI
1010 if (!phydev)
1011 phydev = phy_device_create(bus, 0, PHY_NCSI_ID, false, interface);
1012#endif
1013
f41e588c
SDPP
1014#ifdef CONFIG_PHY_XILINX_GMII2RGMII
1015 if (!phydev)
1016 phydev = phy_connect_gmii2rgmii(bus, dev, interface);
1017#endif
c256d3f7 1018
8d631203 1019 if (!phydev)
afbc3194 1020 phydev = phy_find_by_mask(bus, mask, interface);
5f184715 1021
1adb406b
TK
1022 if (phydev)
1023 phy_connect_dev(phydev, dev);
1024 else
1025 printf("Could not get PHY for %s: addr %d\n", bus->name, addr);
5f184715
AF
1026 return phydev;
1027}
1028
6e5b9ac0
TT
1029/*
1030 * Start the PHY. Returns 0 on success, or a negative error code.
1031 */
5f184715
AF
1032int phy_startup(struct phy_device *phydev)
1033{
1034 if (phydev->drv->startup)
6e5b9ac0 1035 return phydev->drv->startup(phydev);
5f184715
AF
1036
1037 return 0;
1038}
1039
3c6928fd 1040__weak int board_phy_config(struct phy_device *phydev)
5f184715 1041{
9fafe7da
TK
1042 if (phydev->drv->config)
1043 return phydev->drv->config(phydev);
5f184715
AF
1044 return 0;
1045}
1046
5f184715
AF
1047int phy_config(struct phy_device *phydev)
1048{
5f184715 1049 /* Invoke an optional board-specific helper */
7a673f0b 1050 return board_phy_config(phydev);
5f184715
AF
1051}
1052
1053int phy_shutdown(struct phy_device *phydev)
1054{
1055 if (phydev->drv->shutdown)
1056 phydev->drv->shutdown(phydev);
1057
1058 return 0;
1059}
c74c8e66
SG
1060
1061int phy_get_interface_by_name(const char *str)
1062{
1063 int i;
1064
1065 for (i = 0; i < PHY_INTERFACE_MODE_COUNT; i++) {
1066 if (!strcmp(str, phy_interface_strings[i]))
1067 return i;
1068 }
1069
1070 return -1;
1071}
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