[J-u-boot.git] / drivers / ram / stm32_sdram.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
 * Author(s): Vikas Manocha, <[email protected]> for STMicroelectronics.
 */

#define LOG_CATEGORY UCLASS_RAM

#include <common.h>
#include <clk.h>
#include <dm.h>
#include <init.h>
#include <log.h>
#include <ram.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/printk.h>

#define MEM_MODE_MASK	GENMASK(2, 0)
#define SWP_FMC_OFFSET 10
#define SWP_FMC_MASK	GENMASK(SWP_FMC_OFFSET+1, SWP_FMC_OFFSET)
#define NOT_FOUND	0xff

struct stm32_fmc_regs {
	/* 0x0 */
	u32 bcr1;	/* NOR/PSRAM Chip select control register 1 */
	u32 btr1;	/* SRAM/NOR-Flash Chip select timing register 1 */
	u32 bcr2;	/* NOR/PSRAM Chip select Control register 2 */
	u32 btr2;	/* SRAM/NOR-Flash Chip select timing register 2 */
	u32 bcr3;	/* NOR/PSRAMChip select Control register 3 */
	u32 btr3;	/* SRAM/NOR-Flash Chip select timing register 3 */
	u32 bcr4;	/* NOR/PSRAM Chip select Control register 4 */
	u32 btr4;	/* SRAM/NOR-Flash Chip select timing register 4 */
	u32 reserved1[24];

	/* 0x80 */
	u32 pcr;	/* NAND Flash control register */
	u32 sr;		/* FIFO status and interrupt register */
	u32 pmem;	/* Common memory space timing register */
	u32 patt;	/* Attribute memory space timing registers  */
	u32 reserved2[1];
	u32 eccr;	/* ECC result registers */
	u32 reserved3[27];

	/* 0x104 */
	u32 bwtr1;	/* SRAM/NOR-Flash write timing register 1 */
	u32 reserved4[1];
	u32 bwtr2;	/* SRAM/NOR-Flash write timing register 2 */
	u32 reserved5[1];
	u32 bwtr3;	/* SRAM/NOR-Flash write timing register 3 */
	u32 reserved6[1];
	u32 bwtr4;	/* SRAM/NOR-Flash write timing register 4 */
	u32 reserved7[8];

	/* 0x140 */
	u32 sdcr1;	/* SDRAM Control register 1 */
	u32 sdcr2;	/* SDRAM Control register 2 */
	u32 sdtr1;	/* SDRAM Timing register 1 */
	u32 sdtr2;	/* SDRAM Timing register 2 */
	u32 sdcmr;	/* SDRAM Mode register */
	u32 sdrtr;	/* SDRAM Refresh timing register */
	u32 sdsr;	/* SDRAM Status register */
};

/*
 * NOR/PSRAM Control register BCR1
 * FMC controller Enable, only availabe for H7
 */
#define FMC_BCR1_FMCEN		BIT(31)

/* Control register SDCR */
#define FMC_SDCR_RPIPE_SHIFT	13	/* RPIPE bit shift */
#define FMC_SDCR_RBURST_SHIFT	12	/* RBURST bit shift */
#define FMC_SDCR_SDCLK_SHIFT	10	/* SDRAM clock divisor shift */
#define FMC_SDCR_WP_SHIFT	9	/* Write protection shift */
#define FMC_SDCR_CAS_SHIFT	7	/* CAS latency shift */
#define FMC_SDCR_NB_SHIFT	6	/* Number of banks shift */
#define FMC_SDCR_MWID_SHIFT	4	/* Memory width shift */
#define FMC_SDCR_NR_SHIFT	2	/* Number of row address bits shift */
#define FMC_SDCR_NC_SHIFT	0	/* Number of col address bits shift */

/* Timings register SDTR */
#define FMC_SDTR_TMRD_SHIFT	0	/* Load mode register to active */
#define FMC_SDTR_TXSR_SHIFT	4	/* Exit self-refresh time */
#define FMC_SDTR_TRAS_SHIFT	8	/* Self-refresh time */
#define FMC_SDTR_TRC_SHIFT	12	/* Row cycle delay */
#define FMC_SDTR_TWR_SHIFT	16	/* Recovery delay */
#define FMC_SDTR_TRP_SHIFT	20	/* Row precharge delay */
#define FMC_SDTR_TRCD_SHIFT	24	/* Row-to-column delay */

#define FMC_SDCMR_NRFS_SHIFT	5

#define FMC_SDCMR_MODE_NORMAL		0
#define FMC_SDCMR_MODE_START_CLOCK	1
#define FMC_SDCMR_MODE_PRECHARGE	2
#define FMC_SDCMR_MODE_AUTOREFRESH	3
#define FMC_SDCMR_MODE_WRITE_MODE	4
#define FMC_SDCMR_MODE_SELFREFRESH	5
#define FMC_SDCMR_MODE_POWERDOWN	6

#define FMC_SDCMR_BANK_1		BIT(4)
#define FMC_SDCMR_BANK_2		BIT(3)

#define FMC_SDCMR_MODE_REGISTER_SHIFT	9

#define FMC_SDSR_BUSY			BIT(5)

#define FMC_BUSY_WAIT(regs)	do { \
		__asm__ __volatile__ ("dsb" : : : "memory"); \
		while (regs->sdsr & FMC_SDSR_BUSY) \
			; \
	} while (0)

struct stm32_sdram_control {
	u8 no_columns;
	u8 no_rows;
	u8 memory_width;
	u8 no_banks;
	u8 cas_latency;
	u8 sdclk;
	u8 rd_burst;
	u8 rd_pipe_delay;
};

struct stm32_sdram_timing {
	u8 tmrd;
	u8 txsr;
	u8 tras;
	u8 trc;
	u8 trp;
	u8 twr;
	u8 trcd;
};
enum stm32_fmc_bank {
	SDRAM_BANK1,
	SDRAM_BANK2,
	MAX_SDRAM_BANK,
};

enum stm32_fmc_family {
	STM32F7_FMC,
	STM32H7_FMC,
};

struct bank_params {
	struct stm32_sdram_control *sdram_control;
	struct stm32_sdram_timing *sdram_timing;
	u32 sdram_ref_count;
	enum stm32_fmc_bank target_bank;
};

struct stm32_sdram_params {
	struct stm32_fmc_regs *base;
	u8 no_sdram_banks;
	struct bank_params bank_params[MAX_SDRAM_BANK];
	enum stm32_fmc_family family;
};

#define SDRAM_MODE_BL_SHIFT	0
#define SDRAM_MODE_CAS_SHIFT	4
#define SDRAM_MODE_BL		0

int stm32_sdram_init(struct udevice *dev)
{
	struct stm32_sdram_params *params = dev_get_plat(dev);
	struct stm32_sdram_control *control;
	struct stm32_sdram_timing *timing;
	struct stm32_fmc_regs *regs = params->base;
	enum stm32_fmc_bank target_bank;
	u32 ctb; /* SDCMR register: Command Target Bank */
	u32 ref_count;
	u8 i;

	/* disable the FMC controller */
	if (params->family == STM32H7_FMC)
		clrbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);

	for (i = 0; i < params->no_sdram_banks; i++) {
		control = params->bank_params[i].sdram_control;
		timing = params->bank_params[i].sdram_timing;
		target_bank = params->bank_params[i].target_bank;
		ref_count = params->bank_params[i].sdram_ref_count;

		writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
			| control->cas_latency << FMC_SDCR_CAS_SHIFT
			| control->no_banks << FMC_SDCR_NB_SHIFT
			| control->memory_width << FMC_SDCR_MWID_SHIFT
			| control->no_rows << FMC_SDCR_NR_SHIFT
			| control->no_columns << FMC_SDCR_NC_SHIFT
			| control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
			| control->rd_burst << FMC_SDCR_RBURST_SHIFT,
			&regs->sdcr1);

		if (target_bank == SDRAM_BANK2)
			writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
				| control->no_banks << FMC_SDCR_NB_SHIFT
				| control->memory_width << FMC_SDCR_MWID_SHIFT
				| control->no_rows << FMC_SDCR_NR_SHIFT
				| control->no_columns << FMC_SDCR_NC_SHIFT,
				&regs->sdcr2);

		writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
			| timing->trp << FMC_SDTR_TRP_SHIFT
			| timing->twr << FMC_SDTR_TWR_SHIFT
			| timing->trc << FMC_SDTR_TRC_SHIFT
			| timing->tras << FMC_SDTR_TRAS_SHIFT
			| timing->txsr << FMC_SDTR_TXSR_SHIFT
			| timing->tmrd << FMC_SDTR_TMRD_SHIFT,
			&regs->sdtr1);

		if (target_bank == SDRAM_BANK2)
			writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
				| timing->trp << FMC_SDTR_TRP_SHIFT
				| timing->twr << FMC_SDTR_TWR_SHIFT
				| timing->trc << FMC_SDTR_TRC_SHIFT
				| timing->tras << FMC_SDTR_TRAS_SHIFT
				| timing->txsr << FMC_SDTR_TXSR_SHIFT
				| timing->tmrd << FMC_SDTR_TMRD_SHIFT,
				&regs->sdtr2);

		if (target_bank == SDRAM_BANK1)
			ctb = FMC_SDCMR_BANK_1;
		else
			ctb = FMC_SDCMR_BANK_2;

		writel(ctb | FMC_SDCMR_MODE_START_CLOCK, &regs->sdcmr);
		udelay(200);	/* 200 us delay, page 10, "Power-Up" */
		FMC_BUSY_WAIT(regs);

		writel(ctb | FMC_SDCMR_MODE_PRECHARGE, &regs->sdcmr);
		udelay(100);
		FMC_BUSY_WAIT(regs);

		writel((ctb | FMC_SDCMR_MODE_AUTOREFRESH | 7 << FMC_SDCMR_NRFS_SHIFT),
		       &regs->sdcmr);
		udelay(100);
		FMC_BUSY_WAIT(regs);

		writel(ctb | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
		       | control->cas_latency << SDRAM_MODE_CAS_SHIFT)
		       << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
		       &regs->sdcmr);
		udelay(100);
		FMC_BUSY_WAIT(regs);

		writel(ctb | FMC_SDCMR_MODE_NORMAL, &regs->sdcmr);
		FMC_BUSY_WAIT(regs);

		/* Refresh timer */
		writel(ref_count << 1, &regs->sdrtr);
	}

	/* enable the FMC controller */
	if (params->family == STM32H7_FMC)
		setbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);

	return 0;
}

static int stm32_fmc_of_to_plat(struct udevice *dev)
{
	struct stm32_sdram_params *params = dev_get_plat(dev);
	struct bank_params *bank_params;
	struct ofnode_phandle_args args;
	u32 *syscfg_base;
	u32 mem_remap;
	u32 swp_fmc;
	ofnode bank_node;
	char *bank_name;
	char _bank_name[128] = {0};
	u8 bank = 0;
	int ret;

	ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
						 &args);
	if (ret) {
		dev_dbg(dev, "can't find syscon device (%d)\n", ret);
	} else {
		syscfg_base = (u32 *)ofnode_get_addr(args.node);

		mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
		if (mem_remap != NOT_FOUND) {
			/* set memory mapping selection */
			clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
		} else {
			dev_dbg(dev, "cannot find st,mem_remap property\n");
		}

		swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
		if (swp_fmc != NOT_FOUND) {
			/* set fmc swapping selection */
			clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
		} else {
			dev_dbg(dev, "cannot find st,swp_fmc property\n");
		}

		dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
	}

	dev_for_each_subnode(bank_node, dev) {
		/* extract the bank index from DT */
		bank_name = (char *)ofnode_get_name(bank_node);
		strlcpy(_bank_name, bank_name, sizeof(_bank_name));
		bank_name = (char *)_bank_name;
		strsep(&bank_name, "@");
		if (!bank_name) {
			pr_err("missing sdram bank index");
			return -EINVAL;
		}

		bank_params = &params->bank_params[bank];
		strict_strtoul(bank_name, 10,
			       (long unsigned int *)&bank_params->target_bank);

		if (bank_params->target_bank >= MAX_SDRAM_BANK) {
			pr_err("Found bank %d , but only bank 0 and 1 are supported",
			      bank_params->target_bank);
			return -EINVAL;
		}

		debug("Find bank %s %u\n", bank_name, bank_params->target_bank);

		params->bank_params[bank].sdram_control =
			(struct stm32_sdram_control *)
			 ofnode_read_u8_array_ptr(bank_node,
						  "st,sdram-control",
						  sizeof(struct stm32_sdram_control));

		if (!params->bank_params[bank].sdram_control) {
			pr_err("st,sdram-control not found for %s",
			      ofnode_get_name(bank_node));
			return -EINVAL;
		}


		params->bank_params[bank].sdram_timing =
			(struct stm32_sdram_timing *)
			 ofnode_read_u8_array_ptr(bank_node,
						  "st,sdram-timing",
						  sizeof(struct stm32_sdram_timing));

		if (!params->bank_params[bank].sdram_timing) {
			pr_err("st,sdram-timing not found for %s",
			      ofnode_get_name(bank_node));
			return -EINVAL;
		}


		bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
						"st,sdram-refcount", 8196);
		bank++;
	}

	params->no_sdram_banks = bank;
	dev_dbg(dev, "no of banks = %d\n", params->no_sdram_banks);

	return 0;
}

static int stm32_fmc_probe(struct udevice *dev)
{
	struct stm32_sdram_params *params = dev_get_plat(dev);
	int ret;
	fdt_addr_t addr;

	addr = dev_read_addr(dev);
	if (addr == FDT_ADDR_T_NONE)
		return -EINVAL;

	params->base = (struct stm32_fmc_regs *)addr;
	params->family = dev_get_driver_data(dev);

#ifdef CONFIG_CLK
	struct clk clk;

	ret = clk_get_by_index(dev, 0, &clk);
	if (ret < 0)
		return ret;

	ret = clk_enable(&clk);

	if (ret) {
		dev_err(dev, "failed to enable clock\n");
		return ret;
	}
#endif
	ret = stm32_sdram_init(dev);
	if (ret)
		return ret;

	return 0;
}

static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
{
	return 0;
}

static struct ram_ops stm32_fmc_ops = {
	.get_info = stm32_fmc_get_info,
};

static const struct udevice_id stm32_fmc_ids[] = {
	{ .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
	{ .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
	{ }
};

U_BOOT_DRIVER(stm32_fmc) = {
	.name = "stm32_fmc",
	.id = UCLASS_RAM,
	.of_match = stm32_fmc_ids,
	.ops = &stm32_fmc_ops,
	.of_to_plat = stm32_fmc_of_to_plat,
	.probe = stm32_fmc_probe,
	.plat_auto	= sizeof(struct stm32_sdram_params),
};
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
bf1ae442	2	/*
3bc599c9 PC	3	* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
3bc599c9 PC	4	* Author(s): Vikas Manocha, <[email protected]> for STMicroelectronics.
bf1ae442 VM	5	*/
bf1ae442 VM	6
997f7dab PD	7	#define LOG_CATEGORY UCLASS_RAM
997f7dab PD	8
bf1ae442	9	#include <common.h>
d0b24c1a	10	#include <clk.h>
910a52ed	11	#include <dm.h>
691d719d	12	#include <init.h>
f7ae49fc	13	#include <log.h>
910a52ed	14	#include <ram.h>
bf1ae442	15	#include <asm/io.h>
336d4615	16	#include <dm/device_compat.h>
cd93d625	17	#include <linux/bitops.h>
c05ed00a	18	#include <linux/delay.h>
1e94b46f	19	#include <linux/printk.h>
bf1ae442	20
0b3f789a	21	#define MEM_MODE_MASK GENMASK(2, 0)
246a5e5f RP	22	#define SWP_FMC_OFFSET 10
246a5e5f RP	23	#define SWP_FMC_MASK GENMASK(SWP_FMC_OFFSET+1, SWP_FMC_OFFSET)
0b3f789a PC	24	#define NOT_FOUND 0xff
0b3f789a PC	25
9242ece1	26	struct stm32_fmc_regs {
1421e0a3 PC	27	/* 0x0 */
	28	u32 bcr1; /* NOR/PSRAM Chip select control register 1 */
	29	u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
	30	u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */
	31	u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
	32	u32 bcr3; /* NOR/PSRAMChip select Control register 3 */
	33	u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
	34	u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */
	35	u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
	36	u32 reserved1[24];
	37
	38	/* 0x80 */
	39	u32 pcr; /* NAND Flash control register */
	40	u32 sr; /* FIFO status and interrupt register */
	41	u32 pmem; /* Common memory space timing register */
	42	u32 patt; /* Attribute memory space timing registers */
	43	u32 reserved2[1];
	44	u32 eccr; /* ECC result registers */
	45	u32 reserved3[27];
	46
	47	/* 0x104 */
	48	u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
	49	u32 reserved4[1];
	50	u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
	51	u32 reserved5[1];
	52	u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */
	53	u32 reserved6[1];
	54	u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */
	55	u32 reserved7[8];
	56
	57	/* 0x140 */
	58	u32 sdcr1; /* SDRAM Control register 1 */
	59	u32 sdcr2; /* SDRAM Control register 2 */
	60	u32 sdtr1; /* SDRAM Timing register 1 */
	61	u32 sdtr2; /* SDRAM Timing register 2 */
	62	u32 sdcmr; /* SDRAM Mode register */
	63	u32 sdrtr; /* SDRAM Refresh timing register */
	64	u32 sdsr; /* SDRAM Status register */
9242ece1 PC	65	};
9242ece1 PC	66
7016651e PC	67	/*
	68	* NOR/PSRAM Control register BCR1
	69	* FMC controller Enable, only availabe for H7
	70	*/
	71	#define FMC_BCR1_FMCEN BIT(31)
	72
9242ece1 PC	73	/* Control register SDCR */
	74	#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
	75	#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
	76	#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
	77	#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
	78	#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
	79	#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
	80	#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
	81	#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
	82	#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
	83
	84	/* Timings register SDTR */
	85	#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
	86	#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
	87	#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
	88	#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
	89	#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
	90	#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
	91	#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
	92
	93	#define FMC_SDCMR_NRFS_SHIFT 5
	94
	95	#define FMC_SDCMR_MODE_NORMAL 0
	96	#define FMC_SDCMR_MODE_START_CLOCK 1
	97	#define FMC_SDCMR_MODE_PRECHARGE 2
	98	#define FMC_SDCMR_MODE_AUTOREFRESH 3
	99	#define FMC_SDCMR_MODE_WRITE_MODE 4
	100	#define FMC_SDCMR_MODE_SELFREFRESH 5
	101	#define FMC_SDCMR_MODE_POWERDOWN 6
	102
	103	#define FMC_SDCMR_BANK_1 BIT(4)
	104	#define FMC_SDCMR_BANK_2 BIT(3)
	105
	106	#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
	107
	108	#define FMC_SDSR_BUSY BIT(5)
	109
1421e0a3	110	#define FMC_BUSY_WAIT(regs) do { \
9242ece1	111	__asm__ __volatile__ ("dsb" : : : "memory"); \
1421e0a3	112	while (regs->sdsr & FMC_SDSR_BUSY) \
9242ece1 PC	113	; \
	114	} while (0)
	115
6c9a1003 VM	116	struct stm32_sdram_control {
	117	u8 no_columns;
	118	u8 no_rows;
	119	u8 memory_width;
	120	u8 no_banks;
	121	u8 cas_latency;
bfea69ad	122	u8 sdclk;
6c9a1003 VM	123	u8 rd_burst;
	124	u8 rd_pipe_delay;
	125	};
	126
	127	struct stm32_sdram_timing {
	128	u8 tmrd;
	129	u8 txsr;
	130	u8 tras;
	131	u8 trc;
	132	u8 trp;
bfea69ad	133	u8 twr;
6c9a1003 VM	134	u8 trcd;
6c9a1003 VM	135	};
f303aaf2 PC	136	enum stm32_fmc_bank {
	137	SDRAM_BANK1,
	138	SDRAM_BANK2,
	139	MAX_SDRAM_BANK,
	140	};
	141
7016651e PC	142	enum stm32_fmc_family {
	143	STM32F7_FMC,
	144	STM32H7_FMC,
	145	};
	146
f303aaf2	147	struct bank_params {
f39b90dc PC	148	struct stm32_sdram_control *sdram_control;
f39b90dc PC	149	struct stm32_sdram_timing *sdram_timing;
bfea69ad	150	u32 sdram_ref_count;
f303aaf2 PC	151	enum stm32_fmc_bank target_bank;
	152	};
	153
	154	struct stm32_sdram_params {
	155	struct stm32_fmc_regs *base;
	156	u8 no_sdram_banks;
	157	struct bank_params bank_params[MAX_SDRAM_BANK];
7016651e	158	enum stm32_fmc_family family;
6c9a1003	159	};
bf1ae442 VM	160
	161	#define SDRAM_MODE_BL_SHIFT 0
	162	#define SDRAM_MODE_CAS_SHIFT 4
	163	#define SDRAM_MODE_BL 0
bf1ae442	164
6c9a1003	165	int stm32_sdram_init(struct udevice *dev)
bf1ae442	166	{
c69cda25	167	struct stm32_sdram_params *params = dev_get_plat(dev);
f303aaf2 PC	168	struct stm32_sdram_control *control;
f303aaf2 PC	169	struct stm32_sdram_timing *timing;
1421e0a3	170	struct stm32_fmc_regs *regs = params->base;
f303aaf2 PC	171	enum stm32_fmc_bank target_bank;
	172	u32 ctb; /* SDCMR register: Command Target Bank */
	173	u32 ref_count;
	174	u8 i;
	175
7016651e PC	176	/* disable the FMC controller */
	177	if (params->family == STM32H7_FMC)
	178	clrbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
	179
f303aaf2 PC	180	for (i = 0; i < params->no_sdram_banks; i++) {
	181	control = params->bank_params[i].sdram_control;
	182	timing = params->bank_params[i].sdram_timing;
	183	target_bank = params->bank_params[i].target_bank;
	184	ref_count = params->bank_params[i].sdram_ref_count;
	185
	186	writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT
	187	\| control->cas_latency << FMC_SDCR_CAS_SHIFT
	188	\| control->no_banks << FMC_SDCR_NB_SHIFT
	189	\| control->memory_width << FMC_SDCR_MWID_SHIFT
	190	\| control->no_rows << FMC_SDCR_NR_SHIFT
	191	\| control->no_columns << FMC_SDCR_NC_SHIFT
	192	\| control->rd_pipe_delay << FMC_SDCR_RPIPE_SHIFT
	193	\| control->rd_burst << FMC_SDCR_RBURST_SHIFT,
	194	&regs->sdcr1);
	195
	196	if (target_bank == SDRAM_BANK2)
	197	writel(control->cas_latency << FMC_SDCR_CAS_SHIFT
	198	\| control->no_banks << FMC_SDCR_NB_SHIFT
	199	\| control->memory_width << FMC_SDCR_MWID_SHIFT
	200	\| control->no_rows << FMC_SDCR_NR_SHIFT
	201	\| control->no_columns << FMC_SDCR_NC_SHIFT,
	202	&regs->sdcr2);
	203
	204	writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
	205	\| timing->trp << FMC_SDTR_TRP_SHIFT
	206	\| timing->twr << FMC_SDTR_TWR_SHIFT
	207	\| timing->trc << FMC_SDTR_TRC_SHIFT
	208	\| timing->tras << FMC_SDTR_TRAS_SHIFT
	209	\| timing->txsr << FMC_SDTR_TXSR_SHIFT
	210	\| timing->tmrd << FMC_SDTR_TMRD_SHIFT,
	211	&regs->sdtr1);
	212
	213	if (target_bank == SDRAM_BANK2)
	214	writel(timing->trcd << FMC_SDTR_TRCD_SHIFT
	215	\| timing->trp << FMC_SDTR_TRP_SHIFT
	216	\| timing->twr << FMC_SDTR_TWR_SHIFT
	217	\| timing->trc << FMC_SDTR_TRC_SHIFT
	218	\| timing->tras << FMC_SDTR_TRAS_SHIFT
	219	\| timing->txsr << FMC_SDTR_TXSR_SHIFT
	220	\| timing->tmrd << FMC_SDTR_TMRD_SHIFT,
	221	&regs->sdtr2);
7016651e	222
f303aaf2 PC	223	if (target_bank == SDRAM_BANK1)
	224	ctb = FMC_SDCMR_BANK_1;
	225	else
	226	ctb = FMC_SDCMR_BANK_2;
	227
	228	writel(ctb \| FMC_SDCMR_MODE_START_CLOCK, &regs->sdcmr);
	229	udelay(200); /* 200 us delay, page 10, "Power-Up" */
	230	FMC_BUSY_WAIT(regs);
	231
	232	writel(ctb \| FMC_SDCMR_MODE_PRECHARGE, &regs->sdcmr);
	233	udelay(100);
	234	FMC_BUSY_WAIT(regs);
	235
	236	writel((ctb \| FMC_SDCMR_MODE_AUTOREFRESH \| 7 << FMC_SDCMR_NRFS_SHIFT),
	237	&regs->sdcmr);
	238	udelay(100);
	239	FMC_BUSY_WAIT(regs);
	240
	241	writel(ctb \| (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
	242	\| control->cas_latency << SDRAM_MODE_CAS_SHIFT)
	243	<< FMC_SDCMR_MODE_REGISTER_SHIFT \| FMC_SDCMR_MODE_WRITE_MODE,
	244	&regs->sdcmr);
	245	udelay(100);
	246	FMC_BUSY_WAIT(regs);
	247
	248	writel(ctb \| FMC_SDCMR_MODE_NORMAL, &regs->sdcmr);
	249	FMC_BUSY_WAIT(regs);
	250
	251	/* Refresh timer */
	252	writel(ref_count << 1, &regs->sdrtr);
	253	}
bf1ae442	254
7016651e PC	255	/* enable the FMC controller */
	256	if (params->family == STM32H7_FMC)
	257	setbits_le32(&regs->bcr1, FMC_BCR1_FMCEN);
	258
bf1ae442 VM	259	return 0;
bf1ae442 VM	260	}
910a52ed	261
d1998a9f	262	static int stm32_fmc_of_to_plat(struct udevice *dev)
6c9a1003	263	{
c69cda25	264	struct stm32_sdram_params *params = dev_get_plat(dev);
f303aaf2	265	struct bank_params *bank_params;
0b3f789a PC	266	struct ofnode_phandle_args args;
	267	u32 *syscfg_base;
	268	u32 mem_remap;
246a5e5f	269	u32 swp_fmc;
f303aaf2 PC	270	ofnode bank_node;
f303aaf2 PC	271	char *bank_name;
1f0305e0	272	char _bank_name[128] = {0};
f303aaf2	273	u8 bank = 0;
0b3f789a PC	274	int ret;
0b3f789a PC	275
246a5e5f	276	ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
0b3f789a	277	&args);
246a5e5f	278	if (ret) {
997f7dab	279	dev_dbg(dev, "can't find syscon device (%d)\n", ret);
246a5e5f	280	} else {
0b3f789a PC	281	syscfg_base = (u32 *)ofnode_get_addr(args.node);
0b3f789a PC	282
246a5e5f RP	283	mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND);
	284	if (mem_remap != NOT_FOUND) {
	285	/* set memory mapping selection */
	286	clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap);
	287	} else {
997f7dab	288	dev_dbg(dev, "cannot find st,mem_remap property\n");
246a5e5f	289	}
0a50b3c9	290
246a5e5f RP	291	swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND);
	292	if (swp_fmc != NOT_FOUND) {
	293	/* set fmc swapping selection */
	294	clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET);
	295	} else {
997f7dab	296	dev_dbg(dev, "cannot find st,swp_fmc property\n");
246a5e5f RP	297	}
	298
	299	dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base);
0b3f789a	300	}
6c9a1003	301
f39b90dc	302	dev_for_each_subnode(bank_node, dev) {
f303aaf2 PC	303	/* extract the bank index from DT */
f303aaf2 PC	304	bank_name = (char *)ofnode_get_name(bank_node);
1f0305e0	305	strlcpy(_bank_name, bank_name, sizeof(_bank_name));
1f0305e0	306	bank_name = (char *)_bank_name;
f303aaf2 PC	307	strsep(&bank_name, "@");
f303aaf2 PC	308	if (!bank_name) {
9b643e31	309	pr_err("missing sdram bank index");
f303aaf2 PC	310	return -EINVAL;
	311	}
	312
	313	bank_params = &params->bank_params[bank];
	314	strict_strtoul(bank_name, 10,
	315	(long unsigned int *)&bank_params->target_bank);
	316
	317	if (bank_params->target_bank >= MAX_SDRAM_BANK) {
9b643e31	318	pr_err("Found bank %d , but only bank 0 and 1 are supported",
f303aaf2 PC	319	bank_params->target_bank);
	320	return -EINVAL;
	321	}
	322
	323	debug("Find bank %s %u\n", bank_name, bank_params->target_bank);
	324
	325	params->bank_params[bank].sdram_control =
	326	(struct stm32_sdram_control *)
	327	ofnode_read_u8_array_ptr(bank_node,
	328	"st,sdram-control",
	329	sizeof(struct stm32_sdram_control));
	330
	331	if (!params->bank_params[bank].sdram_control) {
9b643e31	332	pr_err("st,sdram-control not found for %s",
f303aaf2	333	ofnode_get_name(bank_node));
f39b90dc PC	334	return -EINVAL;
	335	}
	336
f39b90dc	337
f303aaf2 PC	338	params->bank_params[bank].sdram_timing =
	339	(struct stm32_sdram_timing *)
	340	ofnode_read_u8_array_ptr(bank_node,
	341	"st,sdram-timing",
	342	sizeof(struct stm32_sdram_timing));
	343
	344	if (!params->bank_params[bank].sdram_timing) {
9b643e31	345	pr_err("st,sdram-timing not found for %s",
f303aaf2	346	ofnode_get_name(bank_node));
f39b90dc PC	347	return -EINVAL;
	348	}
	349
f303aaf2 PC	350
f303aaf2 PC	351	bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node,
bfea69ad	352	"st,sdram-refcount", 8196);
f303aaf2	353	bank++;
6c9a1003 VM	354	}
6c9a1003 VM	355
f303aaf2	356	params->no_sdram_banks = bank;
997f7dab	357	dev_dbg(dev, "no of banks = %d\n", params->no_sdram_banks);
f303aaf2	358
6c9a1003 VM	359	return 0;
	360	}
	361
910a52ed VM	362	static int stm32_fmc_probe(struct udevice *dev)
910a52ed VM	363	{
c69cda25	364	struct stm32_sdram_params *params = dev_get_plat(dev);
d0b24c1a	365	int ret;
1421e0a3 PC	366	fdt_addr_t addr;
	367
	368	addr = dev_read_addr(dev);
	369	if (addr == FDT_ADDR_T_NONE)
	370	return -EINVAL;
	371
	372	params->base = (struct stm32_fmc_regs *)addr;
7016651e	373	params->family = dev_get_driver_data(dev);
1421e0a3	374
14a50e37	375	#ifdef CONFIG_CLK
d0b24c1a	376	struct clk clk;
6c9a1003	377
d0b24c1a VM	378	ret = clk_get_by_index(dev, 0, &clk);
	379	if (ret < 0)
	380	return ret;
	381
	382	ret = clk_enable(&clk);
	383
	384	if (ret) {
	385	dev_err(dev, "failed to enable clock\n");
	386	return ret;
	387	}
	388	#endif
6c9a1003 VM	389	ret = stm32_sdram_init(dev);
	390	if (ret)
	391	return ret;
	392
910a52ed VM	393	return 0;
	394	}
	395
	396	static int stm32_fmc_get_info(struct udevice dev, struct ram_info info)
	397	{
910a52ed VM	398	return 0;
	399	}
	400
	401	static struct ram_ops stm32_fmc_ops = {
	402	.get_info = stm32_fmc_get_info,
	403	};
	404
	405	static const struct udevice_id stm32_fmc_ids[] = {
7016651e PC	406	{ .compatible = "st,stm32-fmc", .data = STM32F7_FMC },
7016651e PC	407	{ .compatible = "st,stm32h7-fmc", .data = STM32H7_FMC },
910a52ed VM	408	{ }
	409	};
	410
	411	U_BOOT_DRIVER(stm32_fmc) = {
	412	.name = "stm32_fmc",
	413	.id = UCLASS_RAM,
	414	.of_match = stm32_fmc_ids,
	415	.ops = &stm32_fmc_ops,
d1998a9f	416	.of_to_plat = stm32_fmc_of_to_plat,
910a52ed	417	.probe = stm32_fmc_probe,
caa4daa2	418	.plat_auto = sizeof(struct stm32_sdram_params),
910a52ed	419	};