[J-u-boot.git] / drivers / ram / stm32_sdram.c

/*
 * (C) Copyright 2017
 * Vikas Manocha, <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <dm.h>
#include <ram.h>
#include <asm/io.h>
#include <asm/arch/fmc.h>
#include <asm/arch/stm32.h>

static inline u32 _ns2clk(u32 ns, u32 freq)
{
	u32 tmp = freq/1000000;
	return (tmp * ns) / 1000;
}

#define NS2CLK(ns) (_ns2clk(ns, freq))

/*
 * Following are timings for IS42S16400J, from corresponding datasheet
 */
#define SDRAM_CAS	3	/* 3 cycles */
#define SDRAM_NB	1	/* Number of banks */
#define SDRAM_MWID	1	/* 16 bit memory */

#define SDRAM_NR	0x1	/* 12-bit row */
#define SDRAM_NC	0x0	/* 8-bit col */
#define SDRAM_RBURST	0x1	/* Single read requests always as bursts */
#define SDRAM_RPIPE	0x0	/* No HCLK clock cycle delay */

#define SDRAM_TRRD	NS2CLK(12)
#define SDRAM_TRCD	NS2CLK(18)
#define SDRAM_TRP	NS2CLK(18)
#define SDRAM_TRAS	NS2CLK(42)
#define SDRAM_TRC	NS2CLK(60)
#define SDRAM_TRFC	NS2CLK(60)
#define SDRAM_TCDL	(1 - 1)
#define SDRAM_TRDL	NS2CLK(12)
#define SDRAM_TBDL	(1 - 1)
#define SDRAM_TREF	(NS2CLK(64000000 / 8192) - 20)
#define SDRAM_TCCD	(1 - 1)

#define SDRAM_TXSR	SDRAM_TRFC	/* Row cycle time after precharge */
#define SDRAM_TMRD	1		/* Page 10, Mode Register Set */


/* Last data in to row precharge, need also comply ineq on page 1648 */
#define SDRAM_TWR	max(\
		(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
		(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
		)


#define SDRAM_MODE_BL_SHIFT	0
#define SDRAM_MODE_CAS_SHIFT	4
#define SDRAM_MODE_BL		0
#define SDRAM_MODE_CAS		SDRAM_CAS

int stm32_sdram_init(void)
{
	u32 freq;

	/*
	 * Get frequency for NS2CLK calculation.
	 */
	freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;

	writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
			| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
			| SDRAM_NB << FMC_SDCR_NB_SHIFT
			| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
			| SDRAM_NR << FMC_SDCR_NR_SHIFT
			| SDRAM_NC << FMC_SDCR_NC_SHIFT
			| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
			| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
			&STM32_SDRAM_FMC->sdcr1);

	writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
			| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
			| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
			| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
			| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
			| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
			| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
			&STM32_SDRAM_FMC->sdtr1);

	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK,
	       &STM32_SDRAM_FMC->sdcmr);
	udelay(200);	/* 200 us delay, page 10, "Power-Up" */
	FMC_BUSY_WAIT();

	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE,
	       &STM32_SDRAM_FMC->sdcmr);
	udelay(100);
	FMC_BUSY_WAIT();

	writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH
		| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
	udelay(100);
	FMC_BUSY_WAIT();

	writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
	       | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
	       << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE,
	       &STM32_SDRAM_FMC->sdcmr);
	udelay(100);
	FMC_BUSY_WAIT();

	writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL,
	       &STM32_SDRAM_FMC->sdcmr);
	FMC_BUSY_WAIT();

	/* Refresh timer */
	writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);

	return 0;
}

static int stm32_fmc_probe(struct udevice *dev)
{
	stm32_sdram_init();
	return 0;
}

static int stm32_fmc_get_info(struct udevice *dev, struct ram_info *info)
{
	info->size = CONFIG_SYS_RAM_SIZE;
	return 0;
}

static struct ram_ops stm32_fmc_ops = {
	.get_info = stm32_fmc_get_info,
};

static const struct udevice_id stm32_fmc_ids[] = {
	{ .compatible = "st,stm32-fmc" },
	{ }
};

U_BOOT_DRIVER(stm32_fmc) = {
	.name = "stm32_fmc",
	.id = UCLASS_RAM,
	.of_match = stm32_fmc_ids,
	.ops = &stm32_fmc_ops,
	.probe = stm32_fmc_probe,
};
Commit	Line	Data
bf1ae442 VM	1	/*
	2	* (C) Copyright 2017
	3	* Vikas Manocha, <[email protected]>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
910a52ed VM	9	#include <dm.h>
910a52ed VM	10	#include <ram.h>
bf1ae442 VM	11	#include <asm/io.h>
	12	#include <asm/arch/fmc.h>
	13	#include <asm/arch/stm32.h>
	14
	15	static inline u32 _ns2clk(u32 ns, u32 freq)
	16	{
	17	u32 tmp = freq/1000000;
	18	return (tmp * ns) / 1000;
	19	}
	20
	21	#define NS2CLK(ns) (_ns2clk(ns, freq))
	22
	23	/*
	24	* Following are timings for IS42S16400J, from corresponding datasheet
	25	*/
	26	#define SDRAM_CAS 3 /* 3 cycles */
	27	#define SDRAM_NB 1 /* Number of banks */
	28	#define SDRAM_MWID 1 /* 16 bit memory */
	29
	30	#define SDRAM_NR 0x1 /* 12-bit row */
	31	#define SDRAM_NC 0x0 /* 8-bit col */
	32	#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */
	33	#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */
	34
	35	#define SDRAM_TRRD NS2CLK(12)
	36	#define SDRAM_TRCD NS2CLK(18)
	37	#define SDRAM_TRP NS2CLK(18)
	38	#define SDRAM_TRAS NS2CLK(42)
	39	#define SDRAM_TRC NS2CLK(60)
	40	#define SDRAM_TRFC NS2CLK(60)
	41	#define SDRAM_TCDL (1 - 1)
	42	#define SDRAM_TRDL NS2CLK(12)
	43	#define SDRAM_TBDL (1 - 1)
	44	#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20)
	45	#define SDRAM_TCCD (1 - 1)
	46
	47	#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */
	48	#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */
	49
	50
	51	/* Last data in to row precharge, need also comply ineq on page 1648 */
	52	#define SDRAM_TWR max(\
	53	(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
	54	(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
	55	)
	56
	57
	58	#define SDRAM_MODE_BL_SHIFT 0
	59	#define SDRAM_MODE_CAS_SHIFT 4
	60	#define SDRAM_MODE_BL 0
	61	#define SDRAM_MODE_CAS SDRAM_CAS
	62
	63	int stm32_sdram_init(void)
	64	{
	65	u32 freq;
	66
	67	/*
	68	* Get frequency for NS2CLK calculation.
	69	*/
	70	freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV;
	71
	72	writel(CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT
	73	\| SDRAM_CAS << FMC_SDCR_CAS_SHIFT
	74	\| SDRAM_NB << FMC_SDCR_NB_SHIFT
75	\| SDRAM_MWID << FMC_SDCR_MWID_SHIFT
76	\| SDRAM_NR << FMC_SDCR_NR_SHIFT
77	\| SDRAM_NC << FMC_SDCR_NC_SHIFT
78	\| SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT
79	\| SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT,
80	&STM32_SDRAM_FMC->sdcr1);
81
82	writel(SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT
83	\| SDRAM_TRP << FMC_SDTR_TRP_SHIFT
84	\| SDRAM_TWR << FMC_SDTR_TWR_SHIFT
85	\| SDRAM_TRC << FMC_SDTR_TRC_SHIFT
86	\| SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT
87	\| SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT
88	\| SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT,
89	&STM32_SDRAM_FMC->sdtr1);
90
91	writel(FMC_SDCMR_BANK_1 \| FMC_SDCMR_MODE_START_CLOCK,
92	&STM32_SDRAM_FMC->sdcmr);
93	udelay(200); /* 200 us delay, page 10, "Power-Up" */
94	FMC_BUSY_WAIT();
95
96	writel(FMC_SDCMR_BANK_1 \| FMC_SDCMR_MODE_PRECHARGE,
97	&STM32_SDRAM_FMC->sdcmr);
98	udelay(100);
99	FMC_BUSY_WAIT();
100
101	writel((FMC_SDCMR_BANK_1 \| FMC_SDCMR_MODE_AUTOREFRESH
102	\| 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr);
103	udelay(100);
104	FMC_BUSY_WAIT();
105
106	writel(FMC_SDCMR_BANK_1 \| (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT
107	\| SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT)
108	<< FMC_SDCMR_MODE_REGISTER_SHIFT \| FMC_SDCMR_MODE_WRITE_MODE,
109	&STM32_SDRAM_FMC->sdcmr);
110	udelay(100);
111	FMC_BUSY_WAIT();
112
113	writel(FMC_SDCMR_BANK_1 \| FMC_SDCMR_MODE_NORMAL,
114	&STM32_SDRAM_FMC->sdcmr);
115	FMC_BUSY_WAIT();
116
117	/* Refresh timer */
118	writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr);
119
120	return 0;
121	}
910a52ed VM	122
	123	static int stm32_fmc_probe(struct udevice *dev)
	124	{
	125	stm32_sdram_init();
	126	return 0;
	127	}
	128
	129	static int stm32_fmc_get_info(struct udevice dev, struct ram_info info)
	130	{
	131	info->size = CONFIG_SYS_RAM_SIZE;
	132	return 0;
	133	}
	134
	135	static struct ram_ops stm32_fmc_ops = {
	136	.get_info = stm32_fmc_get_info,
	137	};
	138
	139	static const struct udevice_id stm32_fmc_ids[] = {
	140	{ .compatible = "st,stm32-fmc" },
	141	{ }
	142	};
	143
	144	U_BOOT_DRIVER(stm32_fmc) = {
	145	.name = "stm32_fmc",
	146	.id = UCLASS_RAM,
	147	.of_match = stm32_fmc_ids,
	148	.ops = &stm32_fmc_ops,
	149	.probe = stm32_fmc_probe,
	150	};