dts/upstream/src/arm64/ti/k3-j721e-som-p0.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2 /*
   3  * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/
   4  *
   5  * Product Link: https://www.ti.com/tool/J721EXSOMXEVM
   6  */
   7
   8 /dts-v1/;
   9
  10 #include "k3-j721e.dtsi"
  11
  12 / {
  13         memory@80000000 {
  14                 device_type = "memory";
  15                 bootph-all;
  16                 /* 4G RAM */
  17                 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
  18                       <0x00000008 0x80000000 0x00000000 0x80000000>;
  19         };
  20
  21         reserved_memory: reserved-memory {
  22                 #address-cells = <2>;
  23                 #size-cells = <2>;
  24                 ranges;
  25
  26                 secure_ddr: optee@9e800000 {
  27                         reg = <0x00 0x9e800000 0x00 0x01800000>;
  28                         alignment = <0x1000>;
  29                         no-map;
  30                 };
  31
  32                 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
  33                         compatible = "shared-dma-pool";
  34                         reg = <0x00 0xa0000000 0x00 0x100000>;
  35                         no-map;
  36                 };
  37
  38                 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
  39                         compatible = "shared-dma-pool";
  40                         reg = <0x00 0xa0100000 0x00 0xf00000>;
  41                         no-map;
  42                 };
  43
  44                 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
  45                         compatible = "shared-dma-pool";
  46                         reg = <0x00 0xa1000000 0x00 0x100000>;
  47                         no-map;
  48                 };
  49
  50                 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
  51                         compatible = "shared-dma-pool";
  52                         reg = <0x00 0xa1100000 0x00 0xf00000>;
  53                         no-map;
  54                 };
  55
  56                 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
  57                         compatible = "shared-dma-pool";
  58                         reg = <0x00 0xa2000000 0x00 0x100000>;
  59                         no-map;
  60                 };
  61
  62                 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
  63                         compatible = "shared-dma-pool";
  64                         reg = <0x00 0xa2100000 0x00 0xf00000>;
  65                         no-map;
  66                 };
  67
  68                 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
  69                         compatible = "shared-dma-pool";
  70                         reg = <0x00 0xa3000000 0x00 0x100000>;
  71                         no-map;
  72                 };
  73
  74                 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
  75                         compatible = "shared-dma-pool";
  76                         reg = <0x00 0xa3100000 0x00 0xf00000>;
  77                         no-map;
  78                 };
  79
  80                 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
  81                         compatible = "shared-dma-pool";
  82                         reg = <0x00 0xa4000000 0x00 0x100000>;
  83                         no-map;
  84                 };
  85
  86                 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
  87                         compatible = "shared-dma-pool";
  88                         reg = <0x00 0xa4100000 0x00 0xf00000>;
  89                         no-map;
  90                 };
  91
  92                 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
  93                         compatible = "shared-dma-pool";
  94                         reg = <0x00 0xa5000000 0x00 0x100000>;
  95                         no-map;
  96                 };
  97
  98                 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
  99                         compatible = "shared-dma-pool";
 100                         reg = <0x00 0xa5100000 0x00 0xf00000>;
 101                         no-map;
 102                 };
 103
 104                 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
 105                         compatible = "shared-dma-pool";
 106                         reg = <0x00 0xa6000000 0x00 0x100000>;
 107                         no-map;
 108                 };
 109
 110                 c66_0_memory_region: c66-memory@a6100000 {
 111                         compatible = "shared-dma-pool";
 112                         reg = <0x00 0xa6100000 0x00 0xf00000>;
 113                         no-map;
 114                 };
 115
 116                 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
 117                         compatible = "shared-dma-pool";
 118                         reg = <0x00 0xa7000000 0x00 0x100000>;
 119                         no-map;
 120                 };
 121
 122                 c66_1_memory_region: c66-memory@a7100000 {
 123                         compatible = "shared-dma-pool";
 124                         reg = <0x00 0xa7100000 0x00 0xf00000>;
 125                         no-map;
 126                 };
 127
 128                 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
 129                         compatible = "shared-dma-pool";
 130                         reg = <0x00 0xa8000000 0x00 0x100000>;
 131                         no-map;
 132                 };
 133
 134                 c71_0_memory_region: c71-memory@a8100000 {
 135                         compatible = "shared-dma-pool";
 136                         reg = <0x00 0xa8100000 0x00 0xf00000>;
 137                         no-map;
 138                 };
 139
 140                 rtos_ipc_memory_region: ipc-memories@aa000000 {
 141                         reg = <0x00 0xaa000000 0x00 0x01c00000>;
 142                         alignment = <0x1000>;
 143                         no-map;
 144                 };
 145         };
 146 };
 147
 148 &wkup_pmx0 {
 149         wkup_i2c0_pins_default: wkup-i2c0-default-pins {
 150                 pinctrl-single,pins = <
 151                         J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
 152                         J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
 153                 >;
 154         };
 155
 156         pmic_irq_pins_default: pmic-irq-default-pins {
 157                 pinctrl-single,pins = <
 158                         J721E_WKUP_IOPAD(0x0d4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */
 159                 >;
 160         };
 161
 162         mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
 163                 pinctrl-single,pins = <
 164                         J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
 165                         J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
 166                         J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
 167                         J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
 168                         J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
 169                         J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
 170                         J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
 171                         J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
 172                         J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
 173                         J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
 174                         J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
 175                 >;
 176         };
 177
 178         mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
 179                 pinctrl-single,pins = <
 180                         J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1)  /* MCU_HYPERBUS0_CK */
 181                         J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1)  /* MCU_HYPERBUS0_CKn */
 182                         J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */
 183                         J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */
 184                         J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */
 185                         J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1)   /* MCU_HYPERBUS0_RWDS */
 186                         J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1)   /* MCU_HYPERBUS0_DQ0 */
 187                         J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ1 */
 188                         J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ2 */
 189                         J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ3 */
 190                         J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ4 */
 191                         J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ5 */
 192                         J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ6 */
 193                         J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ7 */
 194                 >;
 195         };
 196 };
 197
 198 &wkup_i2c0 {
 199         status = "okay";
 200         pinctrl-names = "default";
 201         pinctrl-0 = <&wkup_i2c0_pins_default>;
 202         clock-frequency = <400000>;
 203
 204         eeprom@50 {
 205                 /* CAV24C256WE-GT3 */
 206                 compatible = "atmel,24c256";
 207                 reg = <0x50>;
 208         };
 209
 210         tps659413: pmic@48 {
 211                 compatible = "ti,tps6594-q1";
 212                 reg = <0x48>;
 213                 system-power-controller;
 214                 pinctrl-names = "default";
 215                 pinctrl-0 = <&pmic_irq_pins_default>;
 216                 interrupt-parent = <&wkup_gpio0>;
 217                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
 218                 gpio-controller;
 219                 #gpio-cells = <2>;
 220                 ti,primary-pmic;
 221                 buck12-supply = <&vsys_3v3>;
 222                 buck3-supply = <&vsys_3v3>;
 223                 buck4-supply = <&vsys_3v3>;
 224                 buck5-supply = <&vsys_3v3>;
 225                 ldo1-supply = <&vsys_3v3>;
 226                 ldo2-supply = <&vsys_3v3>;
 227                 ldo3-supply = <&vsys_3v3>;
 228                 ldo4-supply = <&vsys_3v3>;
 229
 230                 regulators {
 231                         bucka12: buck12 {
 232                                 regulator-name = "vdd_cpu_avs";
 233                                 regulator-min-microvolt = <600000>;
 234                                 regulator-max-microvolt = <900000>;
 235                                 regulator-boot-on;
 236                                 regulator-always-on;
 237                                 bootph-pre-ram;
 238                         };
 239
 240                         bucka3: buck3 {
 241                                 regulator-name = "vdd_mcu_0v85";
 242                                 regulator-min-microvolt = <850000>;
 243                                 regulator-max-microvolt = <850000>;
 244                                 regulator-boot-on;
 245                                 regulator-always-on;
 246                         };
 247
 248                         bucka4: buck4 {
 249                                 regulator-name = "vdd_ddr_1v1";
 250                                 regulator-min-microvolt = <1100000>;
 251                                 regulator-max-microvolt = <1100000>;
 252                                 regulator-boot-on;
 253                                 regulator-always-on;
 254                         };
 255
 256                         bucka5: buck5 {
 257                                 regulator-name = "vdd_phyio_1v8";
 258                                 regulator-min-microvolt = <1800000>;
 259                                 regulator-max-microvolt = <1800000>;
 260                                 regulator-boot-on;
 261                                 regulator-always-on;
 262                         };
 263
 264                         ldoa1: ldo1 {
 265                                 regulator-name = "vdd1_lpddr4_1v8";
 266                                 regulator-min-microvolt = <1800000>;
 267                                 regulator-max-microvolt = <1800000>;
 268                                 regulator-boot-on;
 269                                 regulator-always-on;
 270                         };
 271
 272                         ldoa2: ldo2 {
 273                                 regulator-name = "vdd_mcuio_1v8";
 274                                 regulator-min-microvolt = <1800000>;
 275                                 regulator-max-microvolt = <1800000>;
 276                                 regulator-boot-on;
 277                                 regulator-always-on;
 278                         };
 279
 280                         ldoa3: ldo3 {
 281                                 regulator-name = "vdda_dll_0v8";
 282                                 regulator-min-microvolt = <800000>;
 283                                 regulator-max-microvolt = <800000>;
 284                                 regulator-boot-on;
 285                                 regulator-always-on;
 286                         };
 287
 288                         ldoa4: ldo4 {
 289                                 regulator-name = "vda_mcu_1v8";
 290                                 regulator-min-microvolt = <1800000>;
 291                                 regulator-max-microvolt = <1800000>;
 292                                 regulator-boot-on;
 293                                 regulator-always-on;
 294                         };
 295                 };
 296         };
 297
 298         tps659411: pmic@4c {
 299                 compatible = "ti,tps6594-q1";
 300                 reg = <0x4c>;
 301                 system-power-controller;
 302                 interrupt-parent = <&wkup_gpio0>;
 303                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
 304                 gpio-controller;
 305                 #gpio-cells = <2>;
 306                 buck1234-supply = <&vsys_3v3>;
 307                 buck5-supply = <&vsys_3v3>;
 308                 ldo1-supply = <&vsys_3v3>;
 309                 ldo2-supply = <&vsys_3v3>;
 310                 ldo3-supply = <&vsys_3v3>;
 311                 ldo4-supply = <&vsys_3v3>;
 312
 313                 regulators {
 314                         buckb1234: buck1234 {
 315                                 regulator-name = "vdd_core_0v8";
 316                                 regulator-min-microvolt = <800000>;
 317                                 regulator-max-microvolt = <800000>;
 318                                 regulator-boot-on;
 319                                 regulator-always-on;
 320                         };
 321
 322                         buckb5: buck5 {
 323                                 regulator-name = "vdd_ram_0v85";
 324                                 regulator-min-microvolt = <850000>;
 325                                 regulator-max-microvolt = <850000>;
 326                                 regulator-boot-on;
 327                                 regulator-always-on;
 328                         };
 329
 330                         ldob1: ldo1 {
 331                                 regulator-name = "vdd_sd_dv";
 332                                 regulator-min-microvolt = <1800000>;
 333                                 regulator-max-microvolt = <3300000>;
 334                                 regulator-boot-on;
 335                                 regulator-always-on;
 336                         };
 337
 338                         ldob2: ldo2 {
 339                                 regulator-name = "vdd_usb_3v3";
 340                                 regulator-min-microvolt = <3300000>;
 341                                 regulator-max-microvolt = <3300000>;
 342                                 regulator-boot-on;
 343                                 regulator-always-on;
 344                         };
 345
 346                         ldob3: ldo3 {
 347                                 regulator-name = "vdd_io_1v8";
 348                                 regulator-min-microvolt = <1800000>;
 349                                 regulator-max-microvolt = <1800000>;
 350                                 regulator-boot-on;
 351                                 regulator-always-on;
 352                         };
 353
 354                         ldob4: ldo4 {
 355                                 regulator-name = "vda_pll_1v8";
 356                                 regulator-min-microvolt = <1800000>;
 357                                 regulator-max-microvolt = <1800000>;
 358                                 regulator-boot-on;
 359                                 regulator-always-on;
 360                         };
 361                 };
 362         };
 363 };
 364
 365 &ospi0 {
 366         status = "okay";
 367         pinctrl-names = "default";
 368         pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
 369
 370         flash@0 {
 371                 compatible = "jedec,spi-nor";
 372                 reg = <0x0>;
 373                 spi-tx-bus-width = <8>;
 374                 spi-rx-bus-width = <8>;
 375                 spi-max-frequency = <25000000>;
 376                 cdns,tshsl-ns = <60>;
 377                 cdns,tsd2d-ns = <60>;
 378                 cdns,tchsh-ns = <60>;
 379                 cdns,tslch-ns = <60>;
 380                 cdns,read-delay = <0>;
 381
 382                 partitions {
 383                         compatible = "fixed-partitions";
 384                         #address-cells = <1>;
 385                         #size-cells = <1>;
 386
 387                         partition@0 {
 388                                 label = "ospi.tiboot3";
 389                                 reg = <0x0 0x80000>;
 390                         };
 391
 392                         partition@80000 {
 393                                 label = "ospi.tispl";
 394                                 reg = <0x80000 0x200000>;
 395                         };
 396
 397                         partition@280000 {
 398                                 label = "ospi.u-boot";
 399                                 reg = <0x280000 0x400000>;
 400                         };
 401
 402                         partition@680000 {
 403                                 label = "ospi.env";
 404                                 reg = <0x680000 0x20000>;
 405                         };
 406
 407                         partition@6a0000 {
 408                                 label = "ospi.env.backup";
 409                                 reg = <0x6a0000 0x20000>;
 410                         };
 411
 412                         partition@6c0000 {
 413                                 label = "ospi.sysfw";
 414                                 reg = <0x6c0000 0x100000>;
 415                         };
 416
 417                         partition@800000 {
 418                                 label = "ospi.rootfs";
 419                                 reg = <0x800000 0x37c0000>;
 420                         };
 421
 422                         partition@3fe0000 {
 423                                 label = "ospi.phypattern";
 424                                 reg = <0x3fe0000 0x20000>;
 425                         };
 426                 };
 427         };
 428 };
 429
 430 &hbmc {
 431         /* OSPI and HBMC are muxed inside FSS, Bootloader will enable
 432          * appropriate node based on board detection
 433          */
 434         status = "disabled";
 435         pinctrl-names = "default";
 436         pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
 437         ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
 438                  <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
 439
 440         flash@0,0 {
 441                 compatible = "cypress,hyperflash", "cfi-flash";
 442                 reg = <0x00 0x00 0x4000000>;
 443
 444                 partitions {
 445                         compatible = "fixed-partitions";
 446                         #address-cells = <1>;
 447                         #size-cells = <1>;
 448
 449                         partition@0 {
 450                                 label = "hbmc.tiboot3";
 451                                 reg = <0x0 0x80000>;
 452                         };
 453
 454                         partition@80000 {
 455                                 label = "hbmc.tispl";
 456                                 reg = <0x80000 0x200000>;
 457                         };
 458
 459                         partition@280000 {
 460                                 label = "hbmc.u-boot";
 461                                 reg = <0x280000 0x400000>;
 462                         };
 463
 464                         partition@680000 {
 465                                 label = "hbmc.env";
 466                                 reg = <0x680000 0x40000>;
 467                         };
 468
 469                         partition@6c0000 {
 470                                 label = "hbmc.sysfw";
 471                                 reg = <0x6c0000 0x100000>;
 472                         };
 473
 474                         partition@800000 {
 475                                 label = "hbmc.rootfs";
 476                                 reg = <0x800000 0x3800000>;
 477                         };
 478                 };
 479         };
 480 };
 481
 482 &mailbox0_cluster0 {
 483         status = "okay";
 484         interrupts = <436>;
 485
 486         mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
 487                 ti,mbox-rx = <0 0 0>;
 488                 ti,mbox-tx = <1 0 0>;
 489         };
 490
 491         mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 492                 ti,mbox-rx = <2 0 0>;
 493                 ti,mbox-tx = <3 0 0>;
 494         };
 495 };
 496
 497 &mailbox0_cluster1 {
 498         status = "okay";
 499         interrupts = <432>;
 500
 501         mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
 502                 ti,mbox-rx = <0 0 0>;
 503                 ti,mbox-tx = <1 0 0>;
 504         };
 505
 506         mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
 507                 ti,mbox-rx = <2 0 0>;
 508                 ti,mbox-tx = <3 0 0>;
 509         };
 510 };
 511
 512 &mailbox0_cluster2 {
 513         status = "okay";
 514         interrupts = <428>;
 515
 516         mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
 517                 ti,mbox-rx = <0 0 0>;
 518                 ti,mbox-tx = <1 0 0>;
 519         };
 520
 521         mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
 522                 ti,mbox-rx = <2 0 0>;
 523                 ti,mbox-tx = <3 0 0>;
 524         };
 525 };
 526
 527 &mailbox0_cluster3 {
 528         status = "okay";
 529         interrupts = <424>;
 530
 531         mbox_c66_0: mbox-c66-0 {
 532                 ti,mbox-rx = <0 0 0>;
 533                 ti,mbox-tx = <1 0 0>;
 534         };
 535
 536         mbox_c66_1: mbox-c66-1 {
 537                 ti,mbox-rx = <2 0 0>;
 538                 ti,mbox-tx = <3 0 0>;
 539         };
 540 };
 541
 542 &mailbox0_cluster4 {
 543         status = "okay";
 544         interrupts = <420>;
 545
 546         mbox_c71_0: mbox-c71-0 {
 547                 ti,mbox-rx = <0 0 0>;
 548                 ti,mbox-tx = <1 0 0>;
 549         };
 550 };
 551
 552 &mcu_r5fss0_core0 {
 553         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
 554         memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 555                         <&mcu_r5fss0_core0_memory_region>;
 556 };
 557
 558 &mcu_r5fss0_core1 {
 559         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
 560         memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 561                         <&mcu_r5fss0_core1_memory_region>;
 562 };
 563
 564 &main_r5fss0 {
 565         ti,cluster-mode = <0>;
 566 };
 567
 568 &main_r5fss1 {
 569         ti,cluster-mode = <0>;
 570 };
 571
 572 /* Timers are used by Remoteproc firmware */
 573 &main_timer0 {
 574         status = "reserved";
 575 };
 576
 577 &main_timer1 {
 578         status = "reserved";
 579 };
 580
 581 &main_timer2 {
 582         status = "reserved";
 583 };
 584
 585 &main_timer12 {
 586         status = "reserved";
 587 };
 588
 589 &main_timer13 {
 590         status = "reserved";
 591 };
 592
 593 &main_timer14 {
 594         status = "reserved";
 595 };
 596
 597 &main_timer15 {
 598         status = "reserved";
 599 };
 600
 601 &main_r5fss0_core0 {
 602         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
 603         memory-region = <&main_r5fss0_core0_dma_memory_region>,
 604                         <&main_r5fss0_core0_memory_region>;
 605 };
 606
 607 &main_r5fss0_core1 {
 608         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
 609         memory-region = <&main_r5fss0_core1_dma_memory_region>,
 610                         <&main_r5fss0_core1_memory_region>;
 611 };
 612
 613 &main_r5fss1_core0 {
 614         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
 615         memory-region = <&main_r5fss1_core0_dma_memory_region>,
 616                         <&main_r5fss1_core0_memory_region>;
 617 };
 618
 619 &main_r5fss1_core1 {
 620         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
 621         memory-region = <&main_r5fss1_core1_dma_memory_region>,
 622                         <&main_r5fss1_core1_memory_region>;
 623 };
 624
 625 &c66_0 {
 626         status = "okay";
 627         mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
 628         memory-region = <&c66_0_dma_memory_region>,
 629                         <&c66_0_memory_region>;
 630 };
 631
 632 &c66_1 {
 633         status = "okay";
 634         mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
 635         memory-region = <&c66_1_dma_memory_region>,
 636                         <&c66_1_memory_region>;
 637 };
 638
 639 &c71_0 {
 640         status = "okay";
 641         mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
 642         memory-region = <&c71_0_dma_memory_region>,
 643                         <&c71_0_memory_region>;
 644 };