dts/upstream/src/arm64/ti/k3-j721e-som-p0.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2 /*
   3  * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/
   4  *
   5  * Product Link: https://www.ti.com/tool/J721EXSOMXEVM
   6  */
   7
   8 /dts-v1/;
   9
  10 #include "k3-j721e.dtsi"
  11
  12 / {
  13         memory@80000000 {
  14                 device_type = "memory";
  15                 bootph-all;
  16                 /* 4G RAM */
  17                 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
  18                       <0x00000008 0x80000000 0x00000000 0x80000000>;
  19         };
  20
  21         reserved_memory: reserved-memory {
  22                 #address-cells = <2>;
  23                 #size-cells = <2>;
  24                 ranges;
  25
  26                 secure_ddr: optee@9e800000 {
  27                         reg = <0x00 0x9e800000 0x00 0x01800000>;
  28                         alignment = <0x1000>;
  29                         no-map;
  30                 };
  31
  32                 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
  33                         compatible = "shared-dma-pool";
  34                         reg = <0x00 0xa0000000 0x00 0x100000>;
  35                         no-map;
  36                 };
  37
  38                 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
  39                         compatible = "shared-dma-pool";
  40                         reg = <0x00 0xa0100000 0x00 0xf00000>;
  41                         no-map;
  42                 };
  43
  44                 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
  45                         compatible = "shared-dma-pool";
  46                         reg = <0x00 0xa1000000 0x00 0x100000>;
  47                         no-map;
  48                 };
  49
  50                 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
  51                         compatible = "shared-dma-pool";
  52                         reg = <0x00 0xa1100000 0x00 0xf00000>;
  53                         no-map;
  54                 };
  55
  56                 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
  57                         compatible = "shared-dma-pool";
  58                         reg = <0x00 0xa2000000 0x00 0x100000>;
  59                         no-map;
  60                 };
  61
  62                 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
  63                         compatible = "shared-dma-pool";
  64                         reg = <0x00 0xa2100000 0x00 0xf00000>;
  65                         no-map;
  66                 };
  67
  68                 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
  69                         compatible = "shared-dma-pool";
  70                         reg = <0x00 0xa3000000 0x00 0x100000>;
  71                         no-map;
  72                 };
  73
  74                 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
  75                         compatible = "shared-dma-pool";
  76                         reg = <0x00 0xa3100000 0x00 0xf00000>;
  77                         no-map;
  78                 };
  79
  80                 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
  81                         compatible = "shared-dma-pool";
  82                         reg = <0x00 0xa4000000 0x00 0x100000>;
  83                         no-map;
  84                 };
  85
  86                 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
  87                         compatible = "shared-dma-pool";
  88                         reg = <0x00 0xa4100000 0x00 0xf00000>;
  89                         no-map;
  90                 };
  91
  92                 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
  93                         compatible = "shared-dma-pool";
  94                         reg = <0x00 0xa5000000 0x00 0x100000>;
  95                         no-map;
  96                 };
  97
  98                 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
  99                         compatible = "shared-dma-pool";
 100                         reg = <0x00 0xa5100000 0x00 0xf00000>;
 101                         no-map;
 102                 };
 103
 104                 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
 105                         compatible = "shared-dma-pool";
 106                         reg = <0x00 0xa6000000 0x00 0x100000>;
 107                         no-map;
 108                 };
 109
 110                 c66_0_memory_region: c66-memory@a6100000 {
 111                         compatible = "shared-dma-pool";
 112                         reg = <0x00 0xa6100000 0x00 0xf00000>;
 113                         no-map;
 114                 };
 115
 116                 c66_0_dma_memory_region: c66-dma-memory@a7000000 {
 117                         compatible = "shared-dma-pool";
 118                         reg = <0x00 0xa7000000 0x00 0x100000>;
 119                         no-map;
 120                 };
 121
 122                 c66_1_memory_region: c66-memory@a7100000 {
 123                         compatible = "shared-dma-pool";
 124                         reg = <0x00 0xa7100000 0x00 0xf00000>;
 125                         no-map;
 126                 };
 127
 128                 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
 129                         compatible = "shared-dma-pool";
 130                         reg = <0x00 0xa8000000 0x00 0x100000>;
 131                         no-map;
 132                 };
 133
 134                 c71_0_memory_region: c71-memory@a8100000 {
 135                         compatible = "shared-dma-pool";
 136                         reg = <0x00 0xa8100000 0x00 0xf00000>;
 137                         no-map;
 138                 };
 139
 140                 rtos_ipc_memory_region: ipc-memories@aa000000 {
 141                         reg = <0x00 0xaa000000 0x00 0x01c00000>;
 142                         alignment = <0x1000>;
 143                         no-map;
 144                 };
 145         };
 146 };
 147
 148 &wkup_pmx0 {
 149         wkup_i2c0_pins_default: wkup-i2c0-default-pins {
 150                 pinctrl-single,pins = <
 151                         J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
 152                         J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
 153                 >;
 154                 bootph-all;
 155         };
 156
 157         pmic_irq_pins_default: pmic-irq-default-pins {
 158                 pinctrl-single,pins = <
 159                         J721E_WKUP_IOPAD(0x0d4, PIN_INPUT, 7) /* (G26) WKUP_GPIO0_9 */
 160                 >;
 161         };
 162
 163         mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
 164                 pinctrl-single,pins = <
 165                         J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */
 166                         J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */
 167                         J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */
 168                         J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */
 169                         J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */
 170                         J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */
 171                         J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */
 172                         J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */
 173                         J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */
 174                         J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */
 175                         J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */
 176                 >;
 177                 bootph-all;
 178         };
 179
 180         mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-default-pins {
 181                 pinctrl-single,pins = <
 182                         J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1)  /* MCU_HYPERBUS0_CK */
 183                         J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1)  /* MCU_HYPERBUS0_CKn */
 184                         J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_CSn0 */
 185                         J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* MCU_HYPERBUS0_CSn1 */
 186                         J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* MCU_HYPERBUS0_RESETn */
 187                         J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1)   /* MCU_HYPERBUS0_RWDS */
 188                         J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1)   /* MCU_HYPERBUS0_DQ0 */
 189                         J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ1 */
 190                         J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ2 */
 191                         J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ3 */
 192                         J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ4 */
 193                         J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ5 */
 194                         J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ6 */
 195                         J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1)  /* MCU_HYPERBUS0_DQ7 */
 196                 >;
 197                 bootph-all;
 198         };
 199 };
 200
 201 &wkup_i2c0 {
 202         status = "okay";
 203         pinctrl-names = "default";
 204         pinctrl-0 = <&wkup_i2c0_pins_default>;
 205         clock-frequency = <400000>;
 206
 207         eeprom@50 {
 208                 /* CAV24C256WE-GT3 */
 209                 compatible = "atmel,24c256";
 210                 reg = <0x50>;
 211         };
 212
 213         tps659413: pmic@48 {
 214                 compatible = "ti,tps6594-q1";
 215                 reg = <0x48>;
 216                 system-power-controller;
 217                 pinctrl-names = "default";
 218                 pinctrl-0 = <&pmic_irq_pins_default>;
 219                 interrupt-parent = <&wkup_gpio0>;
 220                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
 221                 gpio-controller;
 222                 #gpio-cells = <2>;
 223                 ti,primary-pmic;
 224                 buck12-supply = <&vsys_3v3>;
 225                 buck3-supply = <&vsys_3v3>;
 226                 buck4-supply = <&vsys_3v3>;
 227                 buck5-supply = <&vsys_3v3>;
 228                 ldo1-supply = <&vsys_3v3>;
 229                 ldo2-supply = <&vsys_3v3>;
 230                 ldo3-supply = <&vsys_3v3>;
 231                 ldo4-supply = <&vsys_3v3>;
 232
 233                 regulators {
 234                         bucka12: buck12 {
 235                                 regulator-name = "vdd_cpu_avs";
 236                                 regulator-min-microvolt = <600000>;
 237                                 regulator-max-microvolt = <900000>;
 238                                 regulator-boot-on;
 239                                 regulator-always-on;
 240                                 bootph-pre-ram;
 241                         };
 242
 243                         bucka3: buck3 {
 244                                 regulator-name = "vdd_mcu_0v85";
 245                                 regulator-min-microvolt = <850000>;
 246                                 regulator-max-microvolt = <850000>;
 247                                 regulator-boot-on;
 248                                 regulator-always-on;
 249                         };
 250
 251                         bucka4: buck4 {
 252                                 regulator-name = "vdd_ddr_1v1";
 253                                 regulator-min-microvolt = <1100000>;
 254                                 regulator-max-microvolt = <1100000>;
 255                                 regulator-boot-on;
 256                                 regulator-always-on;
 257                         };
 258
 259                         bucka5: buck5 {
 260                                 regulator-name = "vdd_phyio_1v8";
 261                                 regulator-min-microvolt = <1800000>;
 262                                 regulator-max-microvolt = <1800000>;
 263                                 regulator-boot-on;
 264                                 regulator-always-on;
 265                         };
 266
 267                         ldoa1: ldo1 {
 268                                 regulator-name = "vdd1_lpddr4_1v8";
 269                                 regulator-min-microvolt = <1800000>;
 270                                 regulator-max-microvolt = <1800000>;
 271                                 regulator-boot-on;
 272                                 regulator-always-on;
 273                         };
 274
 275                         ldoa2: ldo2 {
 276                                 regulator-name = "vdd_mcuio_1v8";
 277                                 regulator-min-microvolt = <1800000>;
 278                                 regulator-max-microvolt = <1800000>;
 279                                 regulator-boot-on;
 280                                 regulator-always-on;
 281                         };
 282
 283                         ldoa3: ldo3 {
 284                                 regulator-name = "vdda_dll_0v8";
 285                                 regulator-min-microvolt = <800000>;
 286                                 regulator-max-microvolt = <800000>;
 287                                 regulator-boot-on;
 288                                 regulator-always-on;
 289                         };
 290
 291                         ldoa4: ldo4 {
 292                                 regulator-name = "vda_mcu_1v8";
 293                                 regulator-min-microvolt = <1800000>;
 294                                 regulator-max-microvolt = <1800000>;
 295                                 regulator-boot-on;
 296                                 regulator-always-on;
 297                         };
 298                 };
 299         };
 300
 301         tps659411: pmic@4c {
 302                 compatible = "ti,tps6594-q1";
 303                 reg = <0x4c>;
 304                 system-power-controller;
 305                 interrupt-parent = <&wkup_gpio0>;
 306                 interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
 307                 gpio-controller;
 308                 #gpio-cells = <2>;
 309                 buck1234-supply = <&vsys_3v3>;
 310                 buck5-supply = <&vsys_3v3>;
 311                 ldo1-supply = <&vsys_3v3>;
 312                 ldo2-supply = <&vsys_3v3>;
 313                 ldo3-supply = <&vsys_3v3>;
 314                 ldo4-supply = <&vsys_3v3>;
 315
 316                 regulators {
 317                         buckb1234: buck1234 {
 318                                 regulator-name = "vdd_core_0v8";
 319                                 regulator-min-microvolt = <800000>;
 320                                 regulator-max-microvolt = <800000>;
 321                                 regulator-boot-on;
 322                                 regulator-always-on;
 323                         };
 324
 325                         buckb5: buck5 {
 326                                 regulator-name = "vdd_ram_0v85";
 327                                 regulator-min-microvolt = <850000>;
 328                                 regulator-max-microvolt = <850000>;
 329                                 regulator-boot-on;
 330                                 regulator-always-on;
 331                         };
 332
 333                         ldob1: ldo1 {
 334                                 regulator-name = "vdd_sd_dv";
 335                                 regulator-min-microvolt = <1800000>;
 336                                 regulator-max-microvolt = <3300000>;
 337                                 regulator-boot-on;
 338                                 regulator-always-on;
 339                         };
 340
 341                         ldob2: ldo2 {
 342                                 regulator-name = "vdd_usb_3v3";
 343                                 regulator-min-microvolt = <3300000>;
 344                                 regulator-max-microvolt = <3300000>;
 345                                 regulator-boot-on;
 346                                 regulator-always-on;
 347                         };
 348
 349                         ldob3: ldo3 {
 350                                 regulator-name = "vdd_io_1v8";
 351                                 regulator-min-microvolt = <1800000>;
 352                                 regulator-max-microvolt = <1800000>;
 353                                 regulator-boot-on;
 354                                 regulator-always-on;
 355                         };
 356
 357                         ldob4: ldo4 {
 358                                 regulator-name = "vda_pll_1v8";
 359                                 regulator-min-microvolt = <1800000>;
 360                                 regulator-max-microvolt = <1800000>;
 361                                 regulator-boot-on;
 362                                 regulator-always-on;
 363                         };
 364                 };
 365         };
 366 };
 367
 368 &ospi0 {
 369         status = "okay";
 370         pinctrl-names = "default";
 371         pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
 372
 373         flash@0 {
 374                 compatible = "jedec,spi-nor";
 375                 reg = <0x0>;
 376                 spi-tx-bus-width = <8>;
 377                 spi-rx-bus-width = <8>;
 378                 spi-max-frequency = <25000000>;
 379                 cdns,tshsl-ns = <60>;
 380                 cdns,tsd2d-ns = <60>;
 381                 cdns,tchsh-ns = <60>;
 382                 cdns,tslch-ns = <60>;
 383                 cdns,read-delay = <0>;
 384
 385                 partitions {
 386                         compatible = "fixed-partitions";
 387                         #address-cells = <1>;
 388                         #size-cells = <1>;
 389
 390                         partition@0 {
 391                                 label = "ospi.tiboot3";
 392                                 reg = <0x0 0x80000>;
 393                         };
 394
 395                         partition@80000 {
 396                                 label = "ospi.tispl";
 397                                 reg = <0x80000 0x200000>;
 398                         };
 399
 400                         partition@280000 {
 401                                 label = "ospi.u-boot";
 402                                 reg = <0x280000 0x400000>;
 403                         };
 404
 405                         partition@680000 {
 406                                 label = "ospi.env";
 407                                 reg = <0x680000 0x20000>;
 408                         };
 409
 410                         partition@6a0000 {
 411                                 label = "ospi.env.backup";
 412                                 reg = <0x6a0000 0x20000>;
 413                         };
 414
 415                         partition@6c0000 {
 416                                 label = "ospi.sysfw";
 417                                 reg = <0x6c0000 0x100000>;
 418                         };
 419
 420                         partition@800000 {
 421                                 label = "ospi.rootfs";
 422                                 reg = <0x800000 0x37c0000>;
 423                         };
 424
 425                         partition@3fe0000 {
 426                                 label = "ospi.phypattern";
 427                                 reg = <0x3fe0000 0x20000>;
 428                                 bootph-all;
 429                         };
 430                 };
 431         };
 432 };
 433
 434 &hbmc {
 435         /* OSPI and HBMC are muxed inside FSS, Bootloader will enable
 436          * appropriate node based on board detection
 437          */
 438         status = "disabled";
 439         pinctrl-names = "default";
 440         pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
 441         ranges = <0x00 0x00 0x05 0x00000000 0x4000000>, /* 64MB Flash on CS0 */
 442                  <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
 443
 444         flash@0,0 {
 445                 compatible = "cypress,hyperflash", "cfi-flash";
 446                 reg = <0x00 0x00 0x4000000>;
 447                 bootph-all;
 448
 449                 partitions {
 450                         compatible = "fixed-partitions";
 451                         #address-cells = <1>;
 452                         #size-cells = <1>;
 453
 454                         partition@0 {
 455                                 label = "hbmc.tiboot3";
 456                                 reg = <0x0 0x80000>;
 457                         };
 458
 459                         partition@80000 {
 460                                 label = "hbmc.tispl";
 461                                 reg = <0x80000 0x200000>;
 462                         };
 463
 464                         partition@280000 {
 465                                 label = "hbmc.u-boot";
 466                                 reg = <0x280000 0x400000>;
 467                         };
 468
 469                         partition@680000 {
 470                                 label = "hbmc.env";
 471                                 reg = <0x680000 0x40000>;
 472                         };
 473
 474                         partition@6c0000 {
 475                                 label = "hbmc.sysfw";
 476                                 reg = <0x6c0000 0x100000>;
 477                         };
 478
 479                         partition@800000 {
 480                                 label = "hbmc.rootfs";
 481                                 reg = <0x800000 0x3800000>;
 482                         };
 483                 };
 484         };
 485 };
 486
 487 &mailbox0_cluster0 {
 488         status = "okay";
 489         interrupts = <436>;
 490
 491         mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
 492                 ti,mbox-rx = <0 0 0>;
 493                 ti,mbox-tx = <1 0 0>;
 494         };
 495
 496         mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
 497                 ti,mbox-rx = <2 0 0>;
 498                 ti,mbox-tx = <3 0 0>;
 499         };
 500 };
 501
 502 &mailbox0_cluster1 {
 503         status = "okay";
 504         interrupts = <432>;
 505
 506         mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
 507                 ti,mbox-rx = <0 0 0>;
 508                 ti,mbox-tx = <1 0 0>;
 509         };
 510
 511         mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
 512                 ti,mbox-rx = <2 0 0>;
 513                 ti,mbox-tx = <3 0 0>;
 514         };
 515 };
 516
 517 &mailbox0_cluster2 {
 518         status = "okay";
 519         interrupts = <428>;
 520
 521         mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
 522                 ti,mbox-rx = <0 0 0>;
 523                 ti,mbox-tx = <1 0 0>;
 524         };
 525
 526         mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
 527                 ti,mbox-rx = <2 0 0>;
 528                 ti,mbox-tx = <3 0 0>;
 529         };
 530 };
 531
 532 &mailbox0_cluster3 {
 533         status = "okay";
 534         interrupts = <424>;
 535
 536         mbox_c66_0: mbox-c66-0 {
 537                 ti,mbox-rx = <0 0 0>;
 538                 ti,mbox-tx = <1 0 0>;
 539         };
 540
 541         mbox_c66_1: mbox-c66-1 {
 542                 ti,mbox-rx = <2 0 0>;
 543                 ti,mbox-tx = <3 0 0>;
 544         };
 545 };
 546
 547 &mailbox0_cluster4 {
 548         status = "okay";
 549         interrupts = <420>;
 550
 551         mbox_c71_0: mbox-c71-0 {
 552                 ti,mbox-rx = <0 0 0>;
 553                 ti,mbox-tx = <1 0 0>;
 554         };
 555 };
 556
 557 &mcu_r5fss0_core0 {
 558         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
 559         memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
 560                         <&mcu_r5fss0_core0_memory_region>;
 561 };
 562
 563 &mcu_r5fss0_core1 {
 564         mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
 565         memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
 566                         <&mcu_r5fss0_core1_memory_region>;
 567 };
 568
 569 &main_r5fss0 {
 570         ti,cluster-mode = <0>;
 571 };
 572
 573 &main_r5fss1 {
 574         ti,cluster-mode = <0>;
 575 };
 576
 577 /* Timers are used by Remoteproc firmware */
 578 &main_timer0 {
 579         status = "reserved";
 580 };
 581
 582 &main_timer1 {
 583         status = "reserved";
 584 };
 585
 586 &main_timer2 {
 587         status = "reserved";
 588 };
 589
 590 &main_timer12 {
 591         status = "reserved";
 592 };
 593
 594 &main_timer13 {
 595         status = "reserved";
 596 };
 597
 598 &main_timer14 {
 599         status = "reserved";
 600 };
 601
 602 &main_timer15 {
 603         status = "reserved";
 604 };
 605
 606 &main_r5fss0_core0 {
 607         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
 608         memory-region = <&main_r5fss0_core0_dma_memory_region>,
 609                         <&main_r5fss0_core0_memory_region>;
 610 };
 611
 612 &main_r5fss0_core1 {
 613         mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
 614         memory-region = <&main_r5fss0_core1_dma_memory_region>,
 615                         <&main_r5fss0_core1_memory_region>;
 616 };
 617
 618 &main_r5fss1_core0 {
 619         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>;
 620         memory-region = <&main_r5fss1_core0_dma_memory_region>,
 621                         <&main_r5fss1_core0_memory_region>;
 622 };
 623
 624 &main_r5fss1_core1 {
 625         mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>;
 626         memory-region = <&main_r5fss1_core1_dma_memory_region>,
 627                         <&main_r5fss1_core1_memory_region>;
 628 };
 629
 630 &c66_0 {
 631         status = "okay";
 632         mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
 633         memory-region = <&c66_0_dma_memory_region>,
 634                         <&c66_0_memory_region>;
 635 };
 636
 637 &c66_1 {
 638         status = "okay";
 639         mboxes = <&mailbox0_cluster3 &mbox_c66_1>;
 640         memory-region = <&c66_1_dma_memory_region>,
 641                         <&c66_1_memory_region>;
 642 };
 643
 644 &c71_0 {
 645         status = "okay";
 646         mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
 647         memory-region = <&c71_0_dma_memory_region>,
 648                         <&c71_0_memory_region>;
 649 };