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CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
1938f4a5
SG
2/*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * (C) Copyright 2002-2006
5 * Wolfgang Denk, DENX Software Engineering, [email protected].
6 *
7 * (C) Copyright 2002
8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9 * Marius Groeger <[email protected]>
1938f4a5
SG
10 */
11
03de305e 12#include <config.h>
f0293d33 13#include <bloblist.h>
52f24238 14#include <bootstage.h>
d96c2604 15#include <clock_legacy.h>
24b852a7 16#include <console.h>
5d6c61ac 17#include <cpu.h>
30c7c434 18#include <cpu_func.h>
70545642 19#include <cyclic.h>
4e4bf944 20#include <display_options.h>
ab7cd627 21#include <dm.h>
4bfd1f5d 22#include <env.h>
f3998fdc 23#include <env_internal.h>
5a421904 24#include <event.h>
1938f4a5 25#include <fdtdec.h>
f828bf25 26#include <fs.h>
db41d65a 27#include <hang.h>
e4fef6cf 28#include <i2c.h>
67c4e9f8 29#include <init.h>
1938f4a5 30#include <initcall.h>
f7ae49fc 31#include <log.h>
fb5cf7f1 32#include <malloc.h>
0eb25b61 33#include <mapmem.h>
a733b06b 34#include <os.h>
1938f4a5 35#include <post.h>
e47b2d67 36#include <relocate.h>
b03e0510 37#include <serial.h>
b0edea3c 38#include <spl.h>
c5d4001a 39#include <status_led.h>
23471aed 40#include <sysreset.h>
1057e6cf 41#include <timer.h>
71c52dba 42#include <trace.h>
0fc406ab 43#include <upl.h>
5a541945 44#include <video.h>
e4fef6cf 45#include <watchdog.h>
90526e9f 46#include <asm/cache.h>
401d1c4f 47#include <asm/global_data.h>
1938f4a5
SG
48#include <asm/io.h>
49#include <asm/sections.h>
ab7cd627 50#include <dm/root.h>
056285fd 51#include <linux/errno.h>
236f7396 52#include <linux/log2.h>
1938f4a5 53
1938f4a5 54DECLARE_GLOBAL_DATA_PTR;
1938f4a5
SG
55
56/*
4c509343 57 * TODO([email protected]): IMO this code should be
1938f4a5
SG
58 * refactored to a single function, something like:
59 *
60 * void led_set_state(enum led_colour_t colour, int on);
61 */
62/************************************************************************
63 * Coloured LED functionality
64 ************************************************************************
65 * May be supplied by boards if desired
66 */
c5d4001a
JH
67__weak void coloured_LED_init(void) {}
68__weak void red_led_on(void) {}
69__weak void red_led_off(void) {}
70__weak void green_led_on(void) {}
71__weak void green_led_off(void) {}
72__weak void yellow_led_on(void) {}
73__weak void yellow_led_off(void) {}
74__weak void blue_led_on(void) {}
75__weak void blue_led_off(void) {}
1938f4a5
SG
76
77/*
78 * Why is gd allocated a register? Prior to reloc it might be better to
79 * just pass it around to each function in this file?
80 *
81 * After reloc one could argue that it is hardly used and doesn't need
82 * to be in a register. Or if it is it should perhaps hold pointers to all
83 * global data for all modules, so that post-reloc we can avoid the massive
84 * literal pool we get on ARM. Or perhaps just encourage each module to use
85 * a structure...
86 */
87
d54d7eb9 88#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
e4fef6cf
SG
89static int init_func_watchdog_init(void)
90{
ea3310e8
TR
91# if defined(CONFIG_HW_WATCHDOG) && \
92 (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
1473f6ac 93 defined(CONFIG_SH) || \
46d7a3b3 94 defined(CONFIG_DESIGNWARE_WATCHDOG) || \
14a380a8 95 defined(CONFIG_IMX_WATCHDOG))
d54d7eb9 96 hw_watchdog_init();
e4fef6cf 97 puts(" Watchdog enabled\n");
ba169d98 98# endif
29caf930 99 schedule();
e4fef6cf
SG
100
101 return 0;
102}
103
104int init_func_watchdog_reset(void)
105{
29caf930 106 schedule();
e4fef6cf
SG
107
108 return 0;
109}
110#endif /* CONFIG_WATCHDOG */
111
dd2a6cd0 112__weak void board_add_ram_info(int use_default)
e4fef6cf
SG
113{
114 /* please define platform specific board_add_ram_info() */
115}
116
1938f4a5
SG
117static int init_baud_rate(void)
118{
bfebc8c9 119 gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
1938f4a5
SG
120 return 0;
121}
122
123static int display_text_info(void)
124{
9b217498 125#if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
9fdee7d7 126 ulong bss_start, bss_end, text_base;
1938f4a5 127
ccea96f4
SY
128 bss_start = (ulong)__bss_start;
129 bss_end = (ulong)__bss_end;
b60eff31 130
98463903
SG
131#ifdef CONFIG_TEXT_BASE
132 text_base = CONFIG_TEXT_BASE;
d54d7eb9 133#else
9fdee7d7 134 text_base = CONFIG_SYS_MONITOR_BASE;
d54d7eb9 135#endif
9fdee7d7
DS
136
137 debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
16ef1474 138 text_base, bss_start, bss_end);
a733b06b 139#endif
1938f4a5 140
1938f4a5
SG
141 return 0;
142}
143
23471aed
MS
144#ifdef CONFIG_SYSRESET
145static int print_resetinfo(void)
146{
147 struct udevice *dev;
148 char status[256];
9259bd17 149 bool status_printed = false;
23471aed
MS
150 int ret;
151
d8cb1dc9
BM
152 /*
153 * Not all boards have sysreset drivers available during early
9259bd17
MS
154 * boot, so don't fail if one can't be found.
155 */
156 for (ret = uclass_first_device_check(UCLASS_SYSRESET, &dev); dev;
d8cb1dc9 157 ret = uclass_next_device_check(&dev)) {
9259bd17
MS
158 if (ret) {
159 debug("%s: %s sysreset device (error: %d)\n",
160 __func__, dev->name, ret);
161 continue;
162 }
163
164 if (!sysreset_get_status(dev, status, sizeof(status))) {
165 printf("%s%s", status_printed ? " " : "", status);
166 status_printed = true;
167 }
23471aed 168 }
9259bd17
MS
169 if (status_printed)
170 printf("\n");
23471aed
MS
171
172 return 0;
173}
174#endif
175
5d6c61ac
MS
176#if defined(CONFIG_DISPLAY_CPUINFO) && CONFIG_IS_ENABLED(CPU)
177static int print_cpuinfo(void)
178{
179 struct udevice *dev;
180 char desc[512];
181 int ret;
182
f5b66af2
YL
183 dev = cpu_get_current_dev();
184 if (!dev) {
185 debug("%s: Could not get CPU device\n",
186 __func__);
187 return -ENODEV;
5d6c61ac
MS
188 }
189
190 ret = cpu_get_desc(dev, desc, sizeof(desc));
191 if (ret) {
192 debug("%s: Could not get CPU description (err = %d)\n",
193 dev->name, ret);
194 return ret;
195 }
196
ecfe6633 197 printf("CPU: %s\n", desc);
5d6c61ac
MS
198
199 return 0;
200}
201#endif
202
1938f4a5
SG
203static int announce_dram_init(void)
204{
205 puts("DRAM: ");
206 return 0;
207}
208
236f7396
T
209/*
210 * From input size calculate its nearest rounded unit scale (multiply of 2^10)
211 * and value in calculated unit scale multiplied by 10 (as fractional fixed
212 * point number with one decimal digit), which is human natural format,
213 * same what uses print_size() function for displaying. Mathematically it is:
214 * round_nearest(val * 2^scale) = size * 10; where: 10 <= val < 10240.
215 *
216 * For example for size=87654321 we calculate scale=20 and val=836 which means
217 * that input has natural human format 83.6 M (mega = 2^20).
218 */
219#define compute_size_scale_val(size, scale, val) do { \
220 scale = ilog2(size) / 10 * 10; \
221 val = (10 * size + ((1ULL << scale) >> 1)) >> scale; \
222 if (val == 10240) { val = 10; scale += 10; } \
223} while (0)
224
225/*
226 * Check if the sizes in their natural units written in decimal format with
227 * one fraction number are same.
228 */
229static int sizes_near(unsigned long long size1, unsigned long long size2)
230{
231 unsigned int size1_scale, size1_val, size2_scale, size2_val;
232
233 compute_size_scale_val(size1, size1_scale, size1_val);
234 compute_size_scale_val(size2, size2_scale, size2_val);
235
236 return size1_scale == size2_scale && size1_val == size2_val;
237}
238
1938f4a5
SG
239static int show_dram_config(void)
240{
fa39ffe5 241 unsigned long long size;
1938f4a5
SG
242 int i;
243
244 debug("\nRAM Configuration:\n");
245 for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
246 size += gd->bd->bi_dram[i].size;
715f599f
BM
247 debug("Bank #%d: %llx ", i,
248 (unsigned long long)(gd->bd->bi_dram[i].start));
1938f4a5
SG
249#ifdef DEBUG
250 print_size(gd->bd->bi_dram[i].size, "\n");
251#endif
252 }
253 debug("\nDRAM: ");
1938f4a5 254
236f7396
T
255 print_size(gd->ram_size, "");
256 if (!sizes_near(gd->ram_size, size)) {
257 printf(" (effective ");
258 print_size(size, ")");
259 }
e4fef6cf
SG
260 board_add_ram_info(0);
261 putc('\n');
1938f4a5
SG
262
263 return 0;
264}
265
76b00aca 266__weak int dram_init_banksize(void)
1938f4a5 267{
f120aa75 268 gd->bd->bi_dram[0].start = gd->ram_base;
1938f4a5 269 gd->bd->bi_dram[0].size = get_effective_memsize();
76b00aca
SG
270
271 return 0;
1938f4a5
SG
272}
273
55dabcc8 274#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
e4fef6cf
SG
275static int init_func_i2c(void)
276{
277 puts("I2C: ");
815a76f2 278 i2c_init_all();
e4fef6cf
SG
279 puts("ready\n");
280 return 0;
281}
282#endif
283
1938f4a5
SG
284static int setup_mon_len(void)
285{
d819250c
SB
286#if defined(CONFIG_ARCH_NEXELL)
287 gd->mon_len = (ulong)__bss_end - (ulong)__image_copy_start;
288#elif defined(__ARM__) || defined(__MICROBLAZE__)
ccea96f4 289 gd->mon_len = (ulong)__bss_end - (ulong)_start;
2c88d5e1 290#elif defined(CONFIG_SANDBOX) && !defined(__riscv)
ccea96f4 291 gd->mon_len = (ulong)_end - (ulong)_init;
3c9fc23c 292#elif defined(CONFIG_SANDBOX)
2c88d5e1 293 /* gcc does not provide _init in crti.o on RISC-V */
3c9fc23c
HS
294 gd->mon_len = 0;
295#elif defined(CONFIG_EFI_APP)
ccea96f4 296 gd->mon_len = (ulong)_end - (ulong)_init;
ea3310e8 297#elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
d54d7eb9 298 gd->mon_len = CONFIG_SYS_MONITOR_LEN;
11232139 299#elif defined(CONFIG_SH) || defined(CONFIG_RISCV)
ccea96f4 300 gd->mon_len = (ulong)(__bss_end) - (ulong)(_start);
b0b35953 301#elif defined(CONFIG_SYS_MONITOR_BASE)
ccea96f4
SY
302 /* TODO: use (ulong)__bss_end - (ulong)__text_start; ? */
303 gd->mon_len = (ulong)__bss_end - CONFIG_SYS_MONITOR_BASE;
632efa74 304#endif
1938f4a5
SG
305 return 0;
306}
307
924a5e4e
SG
308static int setup_spl_handoff(void)
309{
310#if CONFIG_IS_ENABLED(HANDOFF)
311 gd->spl_handoff = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF,
312 sizeof(struct spl_handoff));
313 debug("Found SPL hand-off info %p\n", gd->spl_handoff);
314#endif
315
316 return 0;
317}
318
1938f4a5
SG
319__weak int arch_cpu_init(void)
320{
321 return 0;
322}
323
8ebf5069
PB
324__weak int mach_cpu_init(void)
325{
326 return 0;
327}
328
1938f4a5 329/* Get the top of usable RAM */
d768dd88 330__weak phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
1938f4a5 331{
aa6e94de 332#if defined(CFG_SYS_SDRAM_BASE) && CFG_SYS_SDRAM_BASE > 0
1e4d11a5 333 /*
4c509343 334 * Detect whether we have so much RAM that it goes past the end of our
1e4d11a5
SW
335 * 32-bit address space. If so, clip the usable RAM so it doesn't.
336 */
aa6e94de 337 if (gd->ram_top < CFG_SYS_SDRAM_BASE)
1e4d11a5
SW
338 /*
339 * Will wrap back to top of 32-bit space when reservations
340 * are made.
341 */
342 return 0;
343#endif
1938f4a5
SG
344 return gd->ram_top;
345}
346
d63fc994
OP
347__weak int arch_setup_dest_addr(void)
348{
349 return 0;
350}
351
1938f4a5
SG
352static int setup_dest_addr(void)
353{
5aa828e3 354 debug("Monitor len: %08x\n", gd->mon_len);
1938f4a5
SG
355 /*
356 * Ram is setup, size stored in gd !!
357 */
d92aee57 358 debug("Ram size: %08llX\n", (unsigned long long)gd->ram_size);
24c904f3 359#if CONFIG_VAL(SYS_MEM_TOP_HIDE)
1938f4a5
SG
360 /*
361 * Subtract specified amount of memory to hide so that it won't
362 * get "touched" at all by U-Boot. By fixing up gd->ram_size
363 * the Linux kernel should now get passed the now "corrected"
36cc0de0
YS
364 * memory size and won't touch it either. This should work
365 * for arch/ppc and arch/powerpc. Only Linux board ports in
366 * arch/powerpc with bootwrapper support, that recalculate the
367 * memory size from the SDRAM controller setup will have to
368 * get fixed.
1938f4a5 369 */
36cc0de0
YS
370 gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
371#endif
aa6e94de
TR
372#ifdef CFG_SYS_SDRAM_BASE
373 gd->ram_base = CFG_SYS_SDRAM_BASE;
1938f4a5 374#endif
1473b12a 375 gd->ram_top = gd->ram_base + get_effective_memsize();
1938f4a5 376 gd->ram_top = board_get_usable_ram_top(gd->mon_len);
a0ba279a 377 gd->relocaddr = gd->ram_top;
d92aee57 378 debug("Ram top: %08llX\n", (unsigned long long)gd->ram_top);
d63fc994
OP
379
380 return arch_setup_dest_addr();
1938f4a5
SG
381}
382
7c5c137c 383#ifdef CFG_PRAM
1938f4a5
SG
384/* reserve protected RAM */
385static int reserve_pram(void)
386{
387 ulong reg;
388
7c5c137c 389 reg = env_get_ulong("pram", 10, CFG_PRAM);
a0ba279a 390 gd->relocaddr -= (reg << 10); /* size is in kB */
1938f4a5 391 debug("Reserving %ldk for protected RAM at %08lx\n", reg,
a0ba279a 392 gd->relocaddr);
1938f4a5
SG
393 return 0;
394}
7c5c137c 395#endif /* CFG_PRAM */
1938f4a5
SG
396
397/* Round memory pointer down to next 4 kB limit */
398static int reserve_round_4k(void)
399{
a0ba279a 400 gd->relocaddr &= ~(4096 - 1);
1938f4a5
SG
401 return 0;
402}
403
79926e4f
OP
404__weak int arch_reserve_mmu(void)
405{
406 return 0;
407}
408
4ef9c772 409static int reserve_video_from_videoblob(void)
5a541945 410{
456bdb70 411 if (IS_ENABLED(CONFIG_SPL_VIDEO_HANDOFF) && xpl_phase() > PHASE_SPL) {
5bc610a7 412 struct video_handoff *ho;
eefe23c1 413 int ret = 0;
5bc610a7
NJ
414
415 ho = bloblist_find(BLOBLISTT_U_BOOT_VIDEO, sizeof(*ho));
416 if (!ho)
eefe23c1
DT
417 return log_msg_ret("Missing video bloblist", -ENOENT);
418
419 ret = video_reserve_from_bloblist(ho);
420 if (ret)
421 return log_msg_ret("Invalid Video handoff info", ret);
4ef9c772
DT
422
423 /* Sanity check fb from blob is before current relocaddr */
424 if (likely(gd->relocaddr > (unsigned long)ho->fb))
425 gd->relocaddr = ho->fb;
426 }
427
428 return 0;
429}
430
431/*
432 * Check if any bloblist received specifying reserved areas from previous stage and adjust
433 * gd->relocaddr accordingly, so that we start reserving after pre-reserved areas
434 * from previous stage.
435 *
436 * NOTE:
437 * IT is recommended that all bloblists from previous stage are reserved from ram_top
438 * as next stage will simply start reserving further regions after them.
439 */
440static int setup_relocaddr_from_bloblist(void)
441{
442 reserve_video_from_videoblob();
443
444 return 0;
445}
446
447static int reserve_video(void)
448{
449 if (CONFIG_IS_ENABLED(VIDEO)) {
f9b7bd7e
SG
450 ulong addr;
451 int ret;
452
453 addr = gd->relocaddr;
454 ret = video_reserve(&addr);
455 if (ret)
456 return ret;
457 debug("Reserving %luk for video at: %08lx\n",
458 ((unsigned long)gd->relocaddr - addr) >> 10, addr);
459 gd->relocaddr = addr;
460 }
e4fef6cf
SG
461
462 return 0;
463}
e4fef6cf 464
8703ef3f
SG
465static int reserve_trace(void)
466{
467#ifdef CONFIG_TRACE
468 gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
469 gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
7ea33579
HS
470 debug("Reserving %luk for trace data at: %08lx\n",
471 (unsigned long)CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
8703ef3f
SG
472#endif
473
474 return 0;
475}
476
1938f4a5
SG
477static int reserve_uboot(void)
478{
ff2b2ba8
AB
479 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
480 /*
481 * reserve memory for U-Boot code, data & bss
482 * round down to next 4 kB limit
483 */
484 gd->relocaddr -= gd->mon_len;
485 gd->relocaddr &= ~(4096 - 1);
486 #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
487 /* round down to next 64 kB limit so that IVPR stays aligned */
488 gd->relocaddr &= ~(65536 - 1);
489 #endif
490
5aa828e3 491 debug("Reserving %dk for U-Boot at: %08lx\n",
ff2b2ba8
AB
492 gd->mon_len >> 10, gd->relocaddr);
493 }
a0ba279a
MY
494
495 gd->start_addr_sp = gd->relocaddr;
496
1938f4a5
SG
497 return 0;
498}
499
65c141eb
PD
500/*
501 * reserve after start_addr_sp the requested size and make the stack pointer
502 * 16-byte aligned, this alignment is needed for cast on the reserved memory
503 * ref = x86_64 ABI: https://reviews.llvm.org/D30049: 16 bytes
504 * = ARMv8 Instruction Set Overview: quad word, 16 bytes
505 */
506static unsigned long reserve_stack_aligned(size_t size)
507{
508 return ALIGN_DOWN(gd->start_addr_sp - size, 16);
509}
510
5f7adb5b
VM
511#ifdef CONFIG_SYS_NONCACHED_MEMORY
512static int reserve_noncached(void)
513{
5e0404ff 514 /*
09f5be61
SG
515 * The value of gd->start_addr_sp must match the value of
516 * mem_malloc_start calculated in board_r.c:initr_malloc(), which is
517 * passed to dlmalloc.c:mem_malloc_init() and then used by
5e0404ff
SW
518 * cache.c:noncached_init()
519 *
520 * These calculations must match the code in cache.c:noncached_init()
521 */
522 gd->start_addr_sp = ALIGN(gd->start_addr_sp, MMU_SECTION_SIZE) -
523 MMU_SECTION_SIZE;
524 gd->start_addr_sp -= ALIGN(CONFIG_SYS_NONCACHED_MEMORY,
525 MMU_SECTION_SIZE);
5f7adb5b
VM
526 debug("Reserving %dM for noncached_alloc() at: %08lx\n",
527 CONFIG_SYS_NONCACHED_MEMORY >> 20, gd->start_addr_sp);
528
529 return 0;
530}
531#endif
532
1938f4a5
SG
533/* reserve memory for malloc() area */
534static int reserve_malloc(void)
535{
65c141eb 536 gd->start_addr_sp = reserve_stack_aligned(TOTAL_MALLOC_LEN);
1938f4a5 537 debug("Reserving %dk for malloc() at: %08lx\n",
16ef1474 538 TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
5f7adb5b
VM
539#ifdef CONFIG_SYS_NONCACHED_MEMORY
540 reserve_noncached();
541#endif
542
1938f4a5
SG
543 return 0;
544}
545
546/* (permanently) allocate a Board Info struct */
547static int reserve_board(void)
548{
d54d7eb9 549 if (!gd->bd) {
b75d8dc5
MY
550 gd->start_addr_sp = reserve_stack_aligned(sizeof(struct bd_info));
551 gd->bd = (struct bd_info *)map_sysmem(gd->start_addr_sp,
552 sizeof(struct bd_info));
553 memset(gd->bd, '\0', sizeof(struct bd_info));
d54d7eb9 554 debug("Reserving %zu Bytes for Board Info at: %08lx\n",
b75d8dc5 555 sizeof(struct bd_info), gd->start_addr_sp);
d54d7eb9 556 }
1938f4a5
SG
557 return 0;
558}
559
1938f4a5
SG
560static int reserve_global_data(void)
561{
65c141eb 562 gd->start_addr_sp = reserve_stack_aligned(sizeof(gd_t));
a0ba279a 563 gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
1938f4a5 564 debug("Reserving %zu Bytes for Global Data at: %08lx\n",
16ef1474 565 sizeof(gd_t), gd->start_addr_sp);
1938f4a5
SG
566 return 0;
567}
568
569static int reserve_fdt(void)
570{
19b18daa
OP
571 if (!IS_ENABLED(CONFIG_OF_EMBED)) {
572 /*
573 * If the device tree is sitting immediately above our image
574 * then we must relocate it. If it is embedded in the data
575 * section, then it will be relocated with other data.
576 */
577 if (gd->fdt_blob) {
5019d328
SG
578 gd->boardf->fdt_size =
579 ALIGN(fdt_totalsize(gd->fdt_blob), 32);
19b18daa 580
5019d328
SG
581 gd->start_addr_sp = reserve_stack_aligned(
582 gd->boardf->fdt_size);
583 gd->boardf->new_fdt = map_sysmem(gd->start_addr_sp,
584 gd->boardf->fdt_size);
19b18daa 585 debug("Reserving %lu Bytes for FDT at: %08lx\n",
5019d328 586 gd->boardf->fdt_size, gd->start_addr_sp);
19b18daa 587 }
1938f4a5
SG
588 }
589
590 return 0;
591}
592
25e7dc6a
SG
593static int reserve_bootstage(void)
594{
595#ifdef CONFIG_BOOTSTAGE
48008ec7 596 int size = bootstage_get_size(true);
25e7dc6a 597
65c141eb 598 gd->start_addr_sp = reserve_stack_aligned(size);
89419728 599 gd->boardf->new_bootstage = map_sysmem(gd->start_addr_sp, size);
25e7dc6a
SG
600 debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
601 gd->start_addr_sp);
602#endif
603
604 return 0;
605}
606
d6f87712 607__weak int arch_reserve_stacks(void)
1938f4a5 608{
68145d4c
AB
609 return 0;
610}
8cae8a68 611
68145d4c
AB
612static int reserve_stacks(void)
613{
614 /* make stack pointer 16-byte aligned */
65c141eb 615 gd->start_addr_sp = reserve_stack_aligned(16);
1938f4a5
SG
616
617 /*
4c509343 618 * let the architecture-specific code tailor gd->start_addr_sp and
68145d4c 619 * gd->irq_sp
1938f4a5 620 */
68145d4c 621 return arch_reserve_stacks();
1938f4a5
SG
622}
623
f0293d33
SG
624static int reserve_bloblist(void)
625{
626#ifdef CONFIG_BLOBLIST
4a08fae1 627 /* Align to a 4KB boundary for easier reading of addresses */
9fe06464
SG
628 gd->start_addr_sp = ALIGN_DOWN(gd->start_addr_sp -
629 CONFIG_BLOBLIST_SIZE_RELOC, 0x1000);
e8218976
SG
630 gd->boardf->new_bloblist = map_sysmem(gd->start_addr_sp,
631 CONFIG_BLOBLIST_SIZE_RELOC);
f0293d33
SG
632#endif
633
634 return 0;
635}
636
1938f4a5
SG
637static int display_new_sp(void)
638{
a0ba279a 639 debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
1938f4a5
SG
640
641 return 0;
642}
643
81e7cb1e 644__weak int arch_setup_bdinfo(void)
ba743103
OP
645{
646 return 0;
647}
648
81e7cb1e
OP
649int setup_bdinfo(void)
650{
651 return arch_setup_bdinfo();
652}
653
1938f4a5
SG
654#ifdef CONFIG_POST
655static int init_post(void)
656{
657 post_bootmode_init();
658 post_run(NULL, POST_ROM | post_bootmode_get(0));
659
660 return 0;
661}
662#endif
663
1938f4a5
SG
664static int reloc_fdt(void)
665{
19b18daa 666 if (!IS_ENABLED(CONFIG_OF_EMBED)) {
6abd992a
SG
667 if (gd->boardf->new_fdt) {
668 memcpy(gd->boardf->new_fdt, gd->fdt_blob,
19b18daa 669 fdt_totalsize(gd->fdt_blob));
6abd992a 670 gd->fdt_blob = gd->boardf->new_fdt;
19b18daa 671 }
1938f4a5
SG
672 }
673
674 return 0;
675}
676
25e7dc6a
SG
677static int reloc_bootstage(void)
678{
679#ifdef CONFIG_BOOTSTAGE
680 if (gd->flags & GD_FLG_SKIP_RELOC)
681 return 0;
89419728
SG
682 if (gd->boardf->new_bootstage)
683 bootstage_relocate(gd->boardf->new_bootstage);
25e7dc6a
SG
684#endif
685
686 return 0;
687}
688
f0293d33
SG
689static int reloc_bloblist(void)
690{
691#ifdef CONFIG_BLOBLIST
d5b6e91b
SG
692 /*
693 * Relocate only if we are supposed to send it
694 */
695 if ((gd->flags & GD_FLG_SKIP_RELOC) &&
696 CONFIG_BLOBLIST_SIZE == CONFIG_BLOBLIST_SIZE_RELOC) {
697 debug("Not relocating bloblist\n");
f0293d33 698 return 0;
d5b6e91b 699 }
e8218976 700 if (gd->boardf->new_bloblist) {
f0293d33 701 debug("Copying bloblist from %p to %p, size %x\n",
e8218976
SG
702 gd->bloblist, gd->boardf->new_bloblist,
703 gd->bloblist->total_size);
704 return bloblist_reloc(gd->boardf->new_bloblist,
1ef43f3b 705 CONFIG_BLOBLIST_SIZE_RELOC);
f0293d33
SG
706 }
707#endif
708
709 return 0;
710}
711
7bceb161 712void mcheck_on_ramrelocation(size_t offset);
1938f4a5
SG
713static int setup_reloc(void)
714{
47d7d036 715 if (!(gd->flags & GD_FLG_SKIP_RELOC)) {
98463903 716#ifdef CONFIG_TEXT_BASE
53207bfd 717#ifdef ARM
47d7d036 718 gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
d58c0074
MS
719#elif defined(CONFIG_MICROBLAZE)
720 gd->reloc_off = gd->relocaddr - (u32)_start;
53207bfd 721#elif defined(CONFIG_M68K)
47d7d036
MV
722 /*
723 * On all ColdFire arch cpu, monitor code starts always
724 * just after the default vector table location, so at 0x400
725 */
98463903 726 gd->reloc_off = gd->relocaddr - (CONFIG_TEXT_BASE + 0x400);
001d1885 727#elif !defined(CONFIG_SANDBOX)
98463903 728 gd->reloc_off = gd->relocaddr - CONFIG_TEXT_BASE;
e310b93e 729#endif
d54d7eb9 730#endif
47d7d036
MV
731 }
732
1938f4a5
SG
733 memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
734
47d7d036
MV
735 if (gd->flags & GD_FLG_SKIP_RELOC) {
736 debug("Skipping relocation due to flag\n");
737 } else {
7bceb161
EU
738#ifdef MCHECK_HEAP_PROTECTION
739 mcheck_on_ramrelocation(gd->reloc_off);
740#endif
47d7d036
MV
741 debug("Relocation Offset is: %08lx\n", gd->reloc_off);
742 debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
743 gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
744 gd->start_addr_sp);
745 }
1938f4a5
SG
746
747 return 0;
748}
749
2a792753 750#ifdef CONFIG_OF_BOARD_FIXUP
751static int fix_fdt(void)
752{
753 return board_fix_fdt((void *)gd->fdt_blob);
754}
755#endif
756
1938f4a5 757/* ARM calls relocate_code from its crt0.S */
8f015d37 758#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
1938f4a5
SG
759
760static int jump_to_copy(void)
761{
f05ad9ba
SG
762 if (gd->flags & GD_FLG_SKIP_RELOC)
763 return 0;
48a33806
SG
764 /*
765 * x86 is special, but in a nice way. It uses a trampoline which
766 * enables the dcache if possible.
767 *
768 * For now, other archs use relocate_code(), which is implemented
769 * similarly for all archs. When we do generic relocation, hopefully
770 * we can make all archs enable the dcache prior to relocation.
771 */
3fb80163 772#if defined(CONFIG_X86) || defined(CONFIG_ARC)
48a33806
SG
773 /*
774 * SDRAM and console are now initialised. The final stack can now
775 * be setup in SDRAM. Code execution will continue in Flash, but
776 * with the stack in SDRAM and Global Data in temporary memory
777 * (CPU cache)
778 */
f0c7d9c7 779 arch_setup_gd(gd->new_gd);
8f015d37
SG
780# if CONFIG_IS_ENABLED(X86_64)
781 board_init_f_r_trampoline64(gd->new_gd, gd->start_addr_sp);
782# else
783 board_init_f_r_trampoline(gd->start_addr_sp);
784# endif
48a33806 785#else
a0ba279a 786 relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
48a33806 787#endif
1938f4a5
SG
788
789 return 0;
790}
791#endif
792
793/* Record the board_init_f() bootstage (after arch_cpu_init()) */
b383d6c0 794static int initf_bootstage(void)
1938f4a5 795{
baa7d345
SG
796 bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
797 IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
b383d6c0
SG
798 int ret;
799
824bb1b4 800 ret = bootstage_init(!from_spl);
b383d6c0
SG
801 if (ret)
802 return ret;
824bb1b4 803 if (from_spl) {
e83ced1a 804 ret = bootstage_unstash_default();
824bb1b4
SG
805 if (ret && ret != -ENOENT) {
806 debug("Failed to unstash bootstage: err=%d\n", ret);
807 return ret;
808 }
809 }
b383d6c0 810
1938f4a5
SG
811 bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
812
813 return 0;
814}
815
ab7cd627
SG
816static int initf_dm(void)
817{
ab7cd627
SG
818 int ret;
819
70c79dc8
SG
820 if (!CONFIG_IS_ENABLED(SYS_MALLOC_F))
821 return 0;
822
b67eefdb 823 bootstage_start(BOOTSTAGE_ID_ACCUM_DM_F, "dm_f");
ab7cd627 824 ret = dm_init_and_scan(true);
b67eefdb 825 bootstage_accum(BOOTSTAGE_ID_ACCUM_DM_F);
ab7cd627
SG
826 if (ret)
827 return ret;
4b9a121f 828
6995f2c8
SG
829 ret = dm_autoprobe();
830 if (ret)
831 return ret;
832
4b9a121f
OP
833 if (IS_ENABLED(CONFIG_TIMER_EARLY)) {
834 ret = dm_timer_init();
835 if (ret)
836 return ret;
837 }
ab7cd627
SG
838
839 return 0;
840}
841
146251f8
SG
842/* Architecture-specific memory reservation */
843__weak int reserve_arch(void)
844{
845 return 0;
846}
847
016e4ae7
OP
848__weak int checkcpu(void)
849{
850 return 0;
851}
852
fbf9c154
OP
853__weak int clear_bss(void)
854{
855 return 0;
856}
857
0fc406ab
SG
858static int initf_upl(void)
859{
860 struct upl *upl;
861 int ret;
862
863 if (!IS_ENABLED(CONFIG_UPL_IN) || !(gd->flags & GD_FLG_UPL))
864 return 0;
865
866 upl = malloc(sizeof(struct upl));
867 if (upl)
868 ret = upl_read_handoff(upl, oftree_default());
869 if (ret) {
870 printf("UPL handoff: read failure (err=%dE)\n", ret);
871 return ret;
872 }
873 gd_set_upl(upl);
874
875 return 0;
876}
877
4acff452 878static const init_fnc_t init_sequence_f[] = {
1938f4a5 879 setup_mon_len,
b45122fd 880#ifdef CONFIG_OF_CONTROL
0879361f 881 fdtdec_setup,
b45122fd 882#endif
7ef8e9b0 883#ifdef CONFIG_TRACE_EARLY
71c52dba 884 trace_early_init,
d210718d 885#endif
768e0f52 886 initf_malloc,
0fc406ab 887 initf_upl,
af1bc0cf 888 log_init,
5ac44a55 889 initf_bootstage, /* uses its own timer, so does not need DM */
5a421904 890 event_init,
3d653180 891 bloblist_maybe_init,
924a5e4e 892 setup_spl_handoff,
8e8d45ee
OP
893#if defined(CONFIG_CONSOLE_RECORD_INIT_F)
894 console_record_init,
895#endif
13a7db9a 896 INITCALL_EVENT(EVT_FSP_INIT_F),
1938f4a5 897 arch_cpu_init, /* basic arch cpu dependent setup */
8ebf5069 898 mach_cpu_init, /* SoC/machine dependent CPU setup */
3ea0953d 899 initf_dm,
1938f4a5
SG
900#if defined(CONFIG_BOARD_EARLY_INIT_F)
901 board_early_init_f,
902#endif
727e94a4 903#if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
c252c068 904 /* get CPU and bus clocks according to the environment variable */
e4fef6cf 905 get_clocks, /* get CPU and bus clocks (etc.) */
1793e782 906#endif
56c3aa9a 907#if !defined(CONFIG_M68K) || (defined(CONFIG_M68K) && !defined(CONFIG_MCFTMR))
1938f4a5 908 timer_init, /* initialize timer */
0ce45287 909#endif
e4fef6cf
SG
910#if defined(CONFIG_BOARD_POSTCLK_INIT)
911 board_postclk_init,
1938f4a5
SG
912#endif
913 env_init, /* initialize environment */
914 init_baud_rate, /* initialze baudrate settings */
915 serial_init, /* serial communications setup */
916 console_init_f, /* stage 1 init of console */
917 display_options, /* say that we are here */
918 display_text_info, /* show debugging info if required */
e4fef6cf 919 checkcpu,
23471aed
MS
920#if defined(CONFIG_SYSRESET)
921 print_resetinfo,
922#endif
cc664000 923#if defined(CONFIG_DISPLAY_CPUINFO)
1938f4a5 924 print_cpuinfo, /* display cpu info (and speed) */
cc664000 925#endif
af9e6ad4
CJF
926#if defined(CONFIG_DTB_RESELECT)
927 embedded_dtb_select,
928#endif
1938f4a5 929#if defined(CONFIG_DISPLAY_BOARDINFO)
0365ffcc 930 show_board_info,
e4fef6cf
SG
931#endif
932 INIT_FUNC_WATCHDOG_INIT
c9eff0a6 933 INITCALL_EVENT(EVT_MISC_INIT_F),
e4fef6cf 934 INIT_FUNC_WATCHDOG_RESET
55dabcc8 935#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY)
e4fef6cf 936 init_func_i2c,
1938f4a5
SG
937#endif
938 announce_dram_init,
1938f4a5 939 dram_init, /* configure available RAM banks */
e4fef6cf
SG
940#ifdef CONFIG_POST
941 post_init_f,
942#endif
943 INIT_FUNC_WATCHDOG_RESET
65cc0e2a 944#if defined(CFG_SYS_DRAM_TEST)
e4fef6cf 945 testdram,
65cc0e2a 946#endif /* CFG_SYS_DRAM_TEST */
e4fef6cf
SG
947 INIT_FUNC_WATCHDOG_RESET
948
1938f4a5
SG
949#ifdef CONFIG_POST
950 init_post,
951#endif
e4fef6cf 952 INIT_FUNC_WATCHDOG_RESET
1938f4a5
SG
953 /*
954 * Now that we have DRAM mapped and working, we can
955 * relocate the code and continue running from DRAM.
956 *
957 * Reserve memory at end of RAM for (top down in that order):
958 * - area that won't get touched by U-Boot and Linux (optional)
959 * - kernel log buffer
960 * - protected RAM
961 * - LCD framebuffer
962 * - monitor code
963 * - board info struct
964 */
965 setup_dest_addr,
0858e03b 966#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_OF_INITIAL_DTB_READONLY)
313981c2
PP
967 fix_fdt,
968#endif
7c5c137c 969#ifdef CFG_PRAM
1938f4a5
SG
970 reserve_pram,
971#endif
972 reserve_round_4k,
4ef9c772 973 setup_relocaddr_from_bloblist,
79926e4f 974 arch_reserve_mmu,
5a541945 975 reserve_video,
8703ef3f 976 reserve_trace,
1938f4a5
SG
977 reserve_uboot,
978 reserve_malloc,
979 reserve_board,
1938f4a5
SG
980 reserve_global_data,
981 reserve_fdt,
0858e03b
T
982#if defined(CONFIG_OF_BOARD_FIXUP) && defined(CONFIG_OF_INITIAL_DTB_READONLY)
983 reloc_fdt,
984 fix_fdt,
985#endif
25e7dc6a 986 reserve_bootstage,
f0293d33 987 reserve_bloblist,
146251f8 988 reserve_arch,
1938f4a5 989 reserve_stacks,
76b00aca 990 dram_init_banksize,
1938f4a5 991 show_dram_config,
e4fef6cf 992 INIT_FUNC_WATCHDOG_RESET
1532885c 993 setup_bdinfo,
1938f4a5 994 display_new_sp,
e4fef6cf 995 INIT_FUNC_WATCHDOG_RESET
0858e03b 996#if !defined(CONFIG_OF_BOARD_FIXUP) || !defined(CONFIG_OF_INITIAL_DTB_READONLY)
1938f4a5 997 reloc_fdt,
0858e03b 998#endif
25e7dc6a 999 reloc_bootstage,
f0293d33 1000 reloc_bloblist,
1938f4a5 1001 setup_reloc,
3fb80163 1002#if defined(CONFIG_X86) || defined(CONFIG_ARC)
313aef37 1003 copy_uboot_to_ram,
313aef37
SG
1004 do_elf_reloc_fixups,
1005#endif
de5e5cea 1006 clear_bss,
50128aeb
RV
1007 /*
1008 * Deregister all cyclic functions before relocation, so that
1009 * gd->cyclic_list does not contain any references to pre-relocation
1010 * devices. Drivers will register their cyclic functions anew when the
1011 * devices are probed again.
1012 *
1013 * This should happen as late as possible so that the window where a
1014 * watchdog device is not serviced is as small as possible.
1015 */
1016 cyclic_unregister_all,
8f015d37 1017#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX)
1938f4a5
SG
1018 jump_to_copy,
1019#endif
1020 NULL,
1021};
1022
1023void board_init_f(ulong boot_flags)
1024{
6abd992a
SG
1025 struct board_f boardf;
1026
1938f4a5 1027 gd->flags = boot_flags;
f44fded2 1028 gd->flags &= ~GD_FLG_HAVE_CONSOLE;
6abd992a 1029 gd->boardf = &boardf;
1938f4a5
SG
1030
1031 if (initcall_run_list(init_sequence_f))
1032 hang();
1033
9b217498 1034#if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
264d298f
AB
1035 !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
1036 !defined(CONFIG_ARC)
1938f4a5
SG
1037 /* NOTREACHED - jump_to_copy() does not return */
1038 hang();
1039#endif
1040}
1041
3fb80163 1042#if defined(CONFIG_X86) || defined(CONFIG_ARC)
48a33806
SG
1043/*
1044 * For now this code is only used on x86.
1045 *
1046 * init_sequence_f_r is the list of init functions which are run when
1047 * U-Boot is executing from Flash with a semi-limited 'C' environment.
1048 * The following limitations must be considered when implementing an
1049 * '_f_r' function:
1050 * - 'static' variables are read-only
1051 * - Global Data (gd->xxx) is read/write
1052 *
1053 * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
1054 * supported). It _should_, if possible, copy global data to RAM and
1055 * initialise the CPU caches (to speed up the relocation process)
1056 *
1057 * NOTE: At present only x86 uses this route, but it is intended that
1058 * all archs will move to this when generic relocation is implemented.
1059 */
4acff452 1060static const init_fnc_t init_sequence_f_r[] = {
530f27ea 1061#if !CONFIG_IS_ENABLED(X86_64)
48a33806 1062 init_cache_f_r,
530f27ea 1063#endif
48a33806
SG
1064
1065 NULL,
1066};
1067
1068void board_init_f_r(void)
1069{
1070 if (initcall_run_list(init_sequence_f_r))
1071 hang();
1072
e4d6ab0c
SG
1073 /*
1074 * The pre-relocation drivers may be using memory that has now gone
1075 * away. Mark serial as unavailable - this will fall back to the debug
1076 * UART if available.
af1bc0cf
SG
1077 *
1078 * Do the same with log drivers since the memory may not be available.
e4d6ab0c 1079 */
af1bc0cf 1080 gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
5ee94b4f
SG
1081#ifdef CONFIG_TIMER
1082 gd->timer = NULL;
1083#endif
e4d6ab0c 1084
48a33806
SG
1085 /*
1086 * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
1087 * Transfer execution from Flash to RAM by calculating the address
1088 * of the in-RAM copy of board_init_r() and calling it
1089 */
7bf9f20d 1090 (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
48a33806
SG
1091
1092 /* NOTREACHED - board_init_r() does not return */
1093 hang();
1094}
5bcd19aa 1095#endif /* CONFIG_X86 */
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