Juan Quintela [Tue, 17 Dec 2013 11:12:24 +0000 (12:12 +0100)]
bitmap: use long as index
Move index and size fields from int to long. We need that for
migration. long is 64 bits on sane architectures, and 32bits should
be enough on all the 32bits architectures.
Eduardo Habkost [Thu, 28 Nov 2013 14:01:10 +0000 (12:01 -0200)]
qemu-file: Make a few functions non-static
The QEMUFile code will be moved to qemu-file.c. This will require making
the following functions non-static because they are used by the savevm.c
code:
Matthew Garrett [Mon, 25 Nov 2013 19:42:43 +0000 (14:42 -0500)]
migration: Fix rate limit
The migration thread appears to want to allow writeout to occur at full
speed rather than being rate limited during completion of state saving,
but sets the limit to INT_MAX when xfer_limit is INT64_MAX. This causes
problems if there's more than 2GB of state left to save at this point. It
probably ought to just be INT64_MAX instead.
Zhanghaoyu (A) [Thu, 7 Nov 2013 08:21:23 +0000 (08:21 +0000)]
avoid a bogus COMPLETED->CANCELLED transition
Avoid a bogus COMPLETED->CANCELLED transition.
There is a period of time from the timing of setting COMPLETED state to that of migration thread exits, so during which it's problematic in COMPLETED->CANCELLED transition.
Anthony Liguori [Mon, 13 Jan 2014 01:50:52 +0000 (17:50 -0800)]
Merge remote-tracking branch 'pmaydell/tags/pull-cocoa-20140112' into staging
cocoa queue:
* pass command key to guest when VM has mousegrab
* add .qcow2 to extension list for image load dialog
* fix bugs in code for starting QEMU via image load dialog
* fix resize/redraw interaction
* draw window black if guest hasn't sent anything to screen
* minor style/typo fixes
* add myself as cocoa co-maintainer
# gpg: Signature made Sun 12 Jan 2014 02:45:52 PM PST using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found
* pmaydell/tags/pull-cocoa-20140112:
MAINTAINERS: add myself as cocoa UI co-maintainer
ui/cocoa: Remove stray tabs
ui/cocoa: Draw black rectangle if we have no data yet
ui/cocoa: Redraw at correct size when switching surface
ui/cocoa: Fix code for starting QEMU via image file load dialog
ui/cocoa: Add ".qcow2" to extension list for image load dialog
ui/cocoa: Send warning message to stderr, not stdout
ui/cocoa: Correct typos in comments and variable names
ui/cocoa: Pass command key through to guest when VM has mousegrab
Peter Maydell [Tue, 24 Dec 2013 02:51:47 +0000 (02:51 +0000)]
ui/cocoa: Draw black rectangle if we have no data yet
If our redraw method is called before we have any data from the guest,
then draw a black rectangle rather than leaving the window empty.
This mostly only matters when the guest machine has no framebuffer
device, but it is more in line with the behaviour of other QEMU UIs.
Peter Maydell [Tue, 24 Dec 2013 02:51:46 +0000 (02:51 +0000)]
ui/cocoa: Redraw at correct size when switching surface
If the surface switch involved a resize, we were doing the redraw
at the old size rather than the new, because the update of
screen.width and screen.height was being done after the setFrame
method calls which triggered a redraw. Normally this isn't very
noticeable because typically after the guest triggers the window
resize it also draws something to it, which will in turn cause
us to redraw. However, the combination of a guest which never
draws to the display and a command line setting of a screen size
larger than the default can reveal odd effects.
Move most of the handling of resizes to the top of the method,
and guard it with a check that the surface size actually changed,
to avoid unnecessary operations (including some user visible ones
like "recenter the window on the screen") if the surface is the
same size as the old one.
Peter Maydell [Sun, 8 Dec 2013 22:59:06 +0000 (22:59 +0000)]
ui/cocoa: Fix code for starting QEMU via image file load dialog
Fix a number of bugs in the code for starting QEMU via the image
file load dialog:
* use the actual argv[0] rather than "qemu": this avoids failures to
find BIOS image files caused by not looking in the correct directory
relative to the executable path
* allocate a large enough argv array to NULL terminate it
* use g_strdup(X) rather than g_strdup_printf("%s", X) or
g_strdup_printf(X)
* disable the printing of the simulated command line argument
(which is presumably intended for debug only)
Peter Maydell [Sun, 8 Dec 2013 22:59:05 +0000 (22:59 +0000)]
ui/cocoa: Add ".qcow2" to extension list for image load dialog
Add ".qcow2" to the list of file extensions which are accepted
by the initial disk image load dialog which is displayed if the
user runs QEMU without any command line arguments.
Peter Maydell [Sun, 8 Dec 2013 22:59:02 +0000 (22:59 +0000)]
ui/cocoa: Pass command key through to guest when VM has mousegrab
The guest might want to be able to use the command key for its won
purposes (as command if it is MacOS X, or for the Windows key if
it is a PC guest, for instance). In line with other UI frontends,
pass it through if the guest has mousegrab, and only use it for UI
menu accelerators if not grabbed.
Thanks to John Arbuckle for reporting this problem, helping
us work through what the best solution would be and providing
a patch which was the initial inspiration for this one.
Anthony Liguori [Fri, 10 Jan 2014 19:05:05 +0000 (11:05 -0800)]
Merge remote-tracking branch 'stefanha/block' into staging
* stefanha/block:
commit: Remove unused check
qemu-iotests: Update test cases for commit active
commit: Support commit active layer
block: Add commit_active_start()
mirror: Move base to MirrorBlockJob
mirror: Don't close target
qemu-iotests: drop duplicate virtio-blk initialization failure
vmdk: Allow vmdk_create to work with protocol
vmdk: Check VMFS extent line field number
docs: updated qemu-img man page and qemu-doc to reflect VHDX support.
block: vhdx - improve error message, and .bdrv_check implementation
block/iscsi: Fix compilation for libiscsi 1.4.0 (API change)
qapi-schema: fix QEMU 1.8 references
dataplane: replace hostmem with memory_region_find
dataplane: change vring API to use VirtQueueElement
vring: factor common code for error exits
vring: create a common function to parse descriptors
sheepdog: fix dynamic grow for running qcow2 format
Anthony Liguori [Fri, 10 Jan 2014 19:04:48 +0000 (11:04 -0800)]
Merge remote-tracking branch 'mst/tags/for_anthony' into staging
acpi,pci,pc,fedora,virtio fixes and enhancements
This includes some Preparatory patches for cpu hotplug for q25 and memory
hotplug by Igor, tests and memory mapping change
by Laszlo and pci reset cleanup by Paolo.
There are also some fixes for fedora and virtio:
included here since they are test blockers for me.
Signed-off-by: Michael S. Tsirkin <[email protected]>
# gpg: Signature made Mon 23 Dec 2013 08:07:18 AM PST using RSA key ID D28D5469
# gpg: Can't check signature: public key not found
* mst/tags/for_anthony:
target-arm: fix build with gcc 4.8.2
virtio: add back call to virtio_bus_device_unplugged
piix: fix 32bit pci hole
qdev: switch reset to post-order
qdev: allow both pre- and post-order vists in qdev walking functions
pci: clean up resetting of IRQs
pci: do not export pci_bus_reset
ACPI/DSDT-CPU: cleanup bogus comment
ACPI: Q35 DSDT: fix CPU hotplug GPE0.2 handler
acpi: ich9: allow guest to clear SCI rised by GPE
acpi: factor out common pm_update_sci() into acpi core
acpi: piix4: remove not needed GPE0 mask
i440fx-test: verify firmware under 4G and 1M, both -bios and -pflash
i440fx-test: generate temporary firmware blob
i440fx-test: give each GTest case its own qtest
i440fx-test: qtest_start() should be paired with qtest_end()
hw/i386/pc_sysfw: support two flash drives
pc_piix: document gigabyte_align
piix: gigabyte alignment for ram
# gpg: Signature made Tue 24 Dec 2013 04:51:52 AM PST using RSA key ID 3E7E013F
# gpg: Good signature from "Andreas Färber <[email protected]>"
# gpg: aka "Andreas Färber <[email protected]>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 174F 0347 1BCC 221A 6175 6F96 FA2E D12D 3E7E 013F
* afaerber/tags/qom-cpu-for-anthony:
target-i386: Cleanup 'foo=val' feature handling
target-i386: Cleanup 'foo' feature handling
target-i386: Convert 'check' and 'enforce' to static properties
target-i386: Convert 'hv_spinlocks' to static property
target-i386: Convert 'hv_vapic' to static property
target-i386: Convert 'hv_relaxed' to static property
cpu-exec: Optimize X86CPU usage in cpu_exec()
target-i386: Move apic_state field from CPUX86State to X86CPU
cputlb: Tidy memset() of arrays
cputlb: Use memset() when flushing entries
Anthony Liguori [Fri, 10 Jan 2014 18:48:46 +0000 (10:48 -0800)]
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140107' into staging
target-arm queue:
* further A64 decoder patches, including enabling the aarch64-linux-user
target; this includes full floating point support. Neon is not yet
supported.
* cadence UART model fixes.
* some minor bug fixes and cleanups.
* all the softfloat fixes required by the new A64 instructions;
several of these will also be used by PPC.
* pmaydell/tags/pull-target-arm-20140107: (61 commits)
target-arm: A64: Add support for FCVT between half, single and double
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
target-arm: A64: Add floating-point<->integer conversion instructions
target-arm: A64: Add floating-point<->fixed-point instructions
target-arm: A64: Add extra VFP fixed point conversion helpers
target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion
target-arm: Rename A32 VFP conversion helpers
target-arm: Prepare VFP_CONV_FIX helpers for A64 uses
softfloat: Add support for ties-away rounding
softfloat: Refactor code handling various rounding modes
softfloat: Add float16 <=> float64 conversion functions
softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal
softfloat: Provide complete set of accessors for fp state
softfloat: Fix float64_to_uint32_round_to_zero
softfloat: Fix float64_to_uint32
softfloat: Fix float64_to_uint64_round_to_zero
softfloat: Add float32_to_uint64()
softfloat: Fix factor 2 error for scalbn on denormal inputs
softfloat: Only raise Invalid when conversions to int are out of range
softfloat: Fix float64_to_uint64
...
Anthony Liguori [Thu, 9 Jan 2014 19:24:48 +0000 (11:24 -0800)]
Merge remote-tracking branch 'afaerber/tags/qom-devices-for-anthony' into staging
QOM infrastructure fixes and device conversions
* QOM interface fixes and unit test
* Device no_user sanitization and documentation
* Device error reporting improvement
* Conversion of APIC, ICC, IOAPIC to QOM realization model
# gpg: Signature made Tue 24 Dec 2013 09:04:05 AM PST using RSA key ID 3E7E013F
# gpg: Good signature from "Andreas Färber <[email protected]>"
# gpg: aka "Andreas Färber <[email protected]>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 174F 0347 1BCC 221A 6175 6F96 FA2E D12D 3E7E 013F
* afaerber/tags/qom-devices-for-anthony: (24 commits)
qdev-monitor: Improve error message for -device nonexistant
ioapic: QOM'ify ioapic
ioapic: Cleanup for QOM'ification
icc_bus: QOM'ify ICC
apic: QOM'ify APIC
apic: Cleanup for QOM'ification
qdev: Drop misleading qbus_free() function
qom: Detect bad reentrance during object_class_foreach()
tests: Test QOM interface casting
qom: Do not register interface "types" in the type table and fix names
qom: Split out object and class caches
qdev: Document that pointer properties kill device_add
hw: cannot_instantiate_with_device_add_yet due to pointer props
qdev-monitor: Avoid device_add crashing on non-device driver name
qdev: Do not let the user try to device_add when it cannot work
isa: Clean up use of cannot_instantiate_with_device_add_yet
vt82c686: Clean up use of cannot_instantiate_with_device_add_yet
piix3 piix4: Clean up use of cannot_instantiate_with_device_add_yet
ich9: Document why cannot_instantiate_with_device_add_yet
pci-host: Consistently set cannot_instantiate_with_device_add_yet
...
Anthony Liguori [Thu, 9 Jan 2014 19:24:12 +0000 (11:24 -0800)]
Merge remote-tracking branch 'mjt/trivial-patches' into staging
* mjt/trivial-patches:
acpi unit-test: Remove temporary disk after test
mainstone: Fix duplicate array values for key 'space'
pxa27x: Add 'const' attribute to keyboard maps
pxa27x: Reduce size of keyboard matrix mapping
doc: Mention chardev:id in available devices for -serial
configure: Python tests must be done before help message
configure: Rewrite code for help message
fix -boot strict regressed in commit 6ef4716
vl: make boot_strict variable static (not used outside vl.c)
x86: only allow real mode to access 32bit without LMA
linux-user: Use macro TARGET_NSIG_WORDS where possible
exynos4210: Use macro ARRAY_SIZE where possible
ui/cocoa: Use macro ARRAY_SIZE where possible
misc: Use macro ARRAY_SIZE where possible
openrisc: Fix spelling in comment (transaltion -> translation)
hw/arm/highbank: Simplify code (memory region in device state)
Anthony Liguori [Thu, 9 Jan 2014 19:23:49 +0000 (11:23 -0800)]
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140108' into staging
target-arm queue:
* further A64 decoder patches, including enabling the aarch64-linux-user
target; this includes full floating point support. Neon is not yet
supported.
* cadence UART model fixes.
* some minor bug fixes and cleanups.
* all the softfloat fixes required by the new A64 instructions;
several of these will also be used by PPC.
# gpg: Signature made Wed 08 Jan 2014 11:25:12 AM PST using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found
* pmaydell/tags/pull-target-arm-20140108: (76 commits)
target-arm: A64: Add support for FCVT between half, single and double
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
target-arm: A64: Add floating-point<->integer conversion instructions
target-arm: A64: Add floating-point<->fixed-point instructions
target-arm: A64: Add extra VFP fixed point conversion helpers
target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion
target-arm: Rename A32 VFP conversion helpers
target-arm: Prepare VFP_CONV_FIX helpers for A64 uses
softfloat: Add support for ties-away rounding
softfloat: Refactor code handling various rounding modes
softfloat: Add float16 <=> float64 conversion functions
softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal
softfloat: Provide complete set of accessors for fp state
softfloat: Fix float64_to_uint32_round_to_zero
softfloat: Fix float64_to_uint32
softfloat: Fix float64_to_uint64_round_to_zero
softfloat: Add float32_to_uint64()
softfloat: Fix factor 2 error for scalbn on denormal inputs
softfloat: Only raise Invalid when conversions to int are out of range
softfloat: Fix float64_to_uint64
...
Peter Maydell [Tue, 7 Jan 2014 17:19:14 +0000 (17:19 +0000)]
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
This patch adds support for those instructions in the "Floating-point
data-processing (1 source)" group which are simple 32-bit-to-32-bit
or 64-bit-to-64-bit operations (ie everything except FCVT between
single/double/half precision).
We put the new round-to-int helpers in helper.c because they will
also be used by the new ARMv8 A32/T32 rounding instructions.
Signed-off-by: Alexander Graf <[email protected]>
[WN: Commit message tweak, merged single and double precision patches,
updated to new infrastructure.] Signed-off-by: Will Newton <[email protected]>
[PMM: reworked decode, split FCVT out into their own patch] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Add support for the AArch64 floating-point <-> integer conversion
instructions to disas_fpintconv. In the process we can rearrange
and simplify the detection of unallocated encodings a little.
We also correct a typo in the instruction encoding diagram for this
instruction group: bit 21 is 1, not 0.
This patch adds emulation for the instruction group labeled
"Floating-point <-> fixed-point conversions" in the ARM ARM.
Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU
(scalar, fixed-point).
Signed-off-by: Alexander Graf <[email protected]>
[WN: Commit message tweak, rebased, updated to new infrastructure.
Applied bug fixes from Michael Matz and Janne Grunau.] Signed-off-by: Will Newton <[email protected]>
[PMM: significant cleanup] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Peter Maydell [Tue, 7 Jan 2014 17:19:13 +0000 (17:19 +0000)]
target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion
The VFP fixed point conversion helpers first call float_scalbn and
then convert the result to an integer. This scalbn operation may
set floating point exception flags for:
* overflow & inexact (if it overflows to infinity)
* input denormal squashed to zero
* output denormal squashed to zero
Of these, we only care about the input-denormal flag, since
the output of the whole scale-and-convert operation will be
an integer (so squashed-output-denormal and overflow don't
apply). Suppress the others by saving the pre-scalb exception
flags and only copying across a potential input-denormal flag.
Will Newton [Tue, 7 Jan 2014 17:19:13 +0000 (17:19 +0000)]
target-arm: Rename A32 VFP conversion helpers
The VFP conversion helpers for A32 round to zero as this is the only
rounding mode supported. Rename these helpers to make it clear that
they round to zero and are not suitable for use in the AArch64 code.
Will Newton [Tue, 7 Jan 2014 17:19:13 +0000 (17:19 +0000)]
target-arm: Prepare VFP_CONV_FIX helpers for A64 uses
Make the VFP_CONV_FIX helpers a little more flexible in
preparation for the A64 uses. This requires two changes:
* use the correct softfloat conversion function based on itype
rather than always the int32 one; this is possible now that
softfloat provides int16 versions and necessary for the
future conversion-to-int64 A64 variants. This also allows
us to drop the awkward 'sign' macro argument.
* split the 'fsz' argument which currently controls both
width of the input float type and width of the output
integer type into two; this will allow us to specify the
A64 64-bit-int-to-single conversion function, where the
two widths are different.
We can also drop the (itype##_t) cast now that softfloat
guarantees that all the itype##_to_float* functions take
an integer argument of exactly the correct type.
Peter Maydell [Tue, 7 Jan 2014 17:19:12 +0000 (17:19 +0000)]
softfloat: Add support for ties-away rounding
IEEE754-2008 specifies a new rounding mode:
"roundTiesToAway: the floating-point number nearest to the infinitely
precise result shall be delivered; if the two nearest floating-point
numbers bracketing an unrepresentable infinitely precise result are
equally near, the one with larger magnitude shall be delivered."
Implement this new mode (it is needed for ARM). The general principle
is that the required code is exactly like the ties-to-even code,
except that we do not need to do the "in case of exact tie clear LSB
to round-to-even", because the rounding operation naturally causes
the exact tie to round up in magnitude.
Peter Maydell [Tue, 7 Jan 2014 17:19:12 +0000 (17:19 +0000)]
softfloat: Refactor code handling various rounding modes
Refactor the code in various functions which calculates rounding
increments given the current rounding mode, so that instead of a
set of nested if statements we have a simple switch statement.
This will give us a clean place to add the case for the new
tiesAway rounding mode.
Peter Maydell [Tue, 7 Jan 2014 17:19:11 +0000 (17:19 +0000)]
softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal
In preparation for adding conversions between float16 and float64,
factor out code currently done inline in the float16<=>float32
conversion functions into functions RoundAndPackFloat16 and
NormalizeFloat16Subnormal along the lines of the existing versions
for the other float types.
Note that we change the handling of zExp from the inline code
to match the API of the other RoundAndPackFloat functions; however
we leave the positioning of the binary point between bits 22 and 23
rather than shifting it up to the high end of the word.
This patch re-implements the routine to use the float64_to_uint64_round_to_zero
routine. If saturation occurs we ignore any flags set by the
conversion function and raise only Invalid.
This contribution can be licensed under either the softfloat-2a or -2b
license.
This patch re-implements float64_to_uint32 to re-use the
float64_to_uint64 routine (instead of float64_to_int64). For the
saturation case, we ignore any flags which the conversion routine
has set and raise only the invalid flag.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Peter Maydell [Tue, 7 Jan 2014 17:17:50 +0000 (17:17 +0000)]
softfloat: Fix factor 2 error for scalbn on denormal inputs
If the input to float*_scalbn() is denormal then it represents
a number 0.[mantissabits] * 2^(1-exponentbias) (and the actual
exponent field is all zeroes). This means that when we convert
it to our unpacked encoding the unpacked exponent must be one
greater than for a normal number, which represents
1.[mantissabits] * 2^(e-exponentbias) for an exponent field e.
This meant we were giving answers too small by a factor of 2 for
all denormal inputs.
Note that the float-to-int routines also have this behaviour
of not adjusting the exponent for denormals; however there it is
harmless because denormals will all convert to integer zero anyway.
Peter Maydell [Tue, 7 Jan 2014 17:17:49 +0000 (17:17 +0000)]
softfloat: Only raise Invalid when conversions to int are out of range
We implement a number of float-to-integer conversions using conversion
to an integer type with a wider range and then a check against the
narrower range we are actually converting to. If we find the result to
be out of range we correctly raise the Invalid exception, but we must
also suppress other exceptions which might have been raised by the
conversion function we called.
This won't throw away exceptions we should have preserved, because for
the 'core' exception flags the IEEE spec mandates that the only valid
combinations of exception that can be raised by a single operation are
Inexact + Overflow and Inexact + Underflow. For the non-IEEE softfloat
flag for input denormals, we can guarantee that that flag won't have
been set for out of range float-to-int conversions because a squashed
denormal by definition goes to plus or minus zero, which is always in
range after conversion to integer zero.
This bug has been fixed for some of the float-to-int conversion routines
by previous patches; fix it for the remaining functions as well, so
that they all restore the pre-conversion status flags prior to raising
Invalid.
Peter Maydell [Tue, 7 Jan 2014 17:17:49 +0000 (17:17 +0000)]
softfloat: Make the int-to-float functions take exact-width types
Currently the int-to-float functions take types which are specified
as "at least X bits wide", rather than "exactly X bits wide". This is
confusing and unhelpful since it means that the callers have to include
an explicit cast to [u]intXX_t to ensure the correct behaviour. Fix
them all to take the exactly-X-bits-wide types instead.
Note that this doesn't change behaviour at all since at the moment
we happen to define the 'int32' and 'uint32' types as exactly 32 bits
wide, and the 'int64' and 'uint64' types as exactly 64 bits wide.
Peter Maydell [Tue, 7 Jan 2014 17:17:49 +0000 (17:17 +0000)]
softfloat: Add 16 bit integer to float conversions
Add the float to 16 bit integer conversion routines. These can be
trivially implemented in terms of the int32_to_float* routines, but
providing them makes our API more symmetrical and can simplify callers.
Will Newton [Tue, 7 Jan 2014 17:17:48 +0000 (17:17 +0000)]
softfloat: Add float to 16bit integer conversions.
ARMv8 requires support for converting 32 and 64bit floating point
values to signed and unsigned 16bit integers.
Signed-off-by: Will Newton <[email protected]>
[PMM: updated not to incorrectly set Inexact for Invalid inputs] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Peter Maydell [Mon, 6 Jan 2014 11:47:21 +0000 (11:47 +0000)]
softfloat: Fix exception flag handling for float32_to_float16()
Our float32 to float16 conversion routine was generating the correct
numerical answers, but not always setting the right set of exception
flags. Fix this, mostly by rearranging the code to more closely
resemble RoundAndPackFloat*, and in particular:
* non-IEEE halfprec always raises Invalid for input NaNs
* we need to check for the overflow case before underflow
* we weren't getting the tininess-detected-after-rounding
case correct (somewhat academic since only ARM uses halfprec
and it is always tininess-detected-before-rounding)
* non-IEEE halfprec overflow raises only Invalid, not
Invalid + Inexact
* we weren't setting Inexact when we should
Also add some clarifying comments about what the code is doing.
Christoffer Dall [Sat, 21 Dec 2013 06:09:33 +0000 (22:09 -0800)]
hw: arm_gic: Introduce gic_set_priority function
To make the code slightly cleaner to look at and make the save/restore
code easier to understand, introduce this function to set the priority of
interrupts.
Christoffer Dall [Sat, 21 Dec 2013 06:09:32 +0000 (22:09 -0800)]
arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER
TRIGGER can really mean mean anything (e.g. was it triggered, is it
level-triggered, is it edge-triggered, etc.). Rename to EDGE_TRIGGER to
make the code comprehensible without looking up the data structure.
introduces an array aarch64_cpus which is zero
size if this code is built without CONFIG_USER_ONLY.
In particular an attempt to iterate over this array produces a warning
under gcc 4.8.2:
CC aarch64-softmmu/target-arm/cpu64.o
/scm/qemu/target-arm/cpu64.c: In function ‘aarch64_cpu_register_types’:
/scm/qemu/target-arm/cpu64.c:124:5: error: comparison of unsigned
expression < 0 is always false [-Werror=type-limits]
for (i = 0; i < ARRAY_SIZE(aarch64_cpus); i++) {
^
cc1: all warnings being treated as errors
This is the result of ARRAY_SIZE being an unsigned type,
causing "i" to be promoted to unsigned int as well.
As zero size arrays are a gcc extension, it seems
cleanest to add a dummy element with NULL name,
and test for it during registration.
Don't conditionalise GEM instantiation on networking attachments. The
device should always be present even if not attached to a network.
This allows for probing of the device by expectant guests (such as
OS's). This is needed because sysbus (or AXI in Xilinx's real hw case)
is not self identifying so the guest has no dynamic way of detecting
device absence.
Also allows for testing of the GEM in loopback mode with -net none.
If the UART back-end blocks, buffer in the Tx FIFO to try again later.
This stops the IO-thread busy waiting on char back-ends (which causes
all sorts of performance problems).
The can_receive logic was only taking into account the RxFIFO
occupancy. RxFIFO population is only used for the echo and normal modes
however. Improve the logic to correctly return the true number of
receivable characters based on the current mode:
Normal mode: RxFIFO vacancy.
Remote loopback: TxFIFO vacancy.
Echo mode: The min of the TxFIFO and RxFIFO vacancies.
Local Loopback: Return non-zero (to implement droppage)
char/cadence_uart: Remove TX timer & add TX FIFO state
This tx timer implementation is flawed. Despite the controller
attempting to time the guest visable assertion of the TX-empty status
bit (and corresponding interrupt) the controller is still transmitting
characters instantaneously. There is also no sense of multiple character
delay.
The only side effect of this timer is assertion of tx-empty status. So
just remove the timer completely and hold tx-empty as permanently
asserted (its reset status). This matches the actual behaviour of
instantaneous transmission.
While we are VMSD version bumping, add the tx_fifo as device state to
prepare for upcomming TxFIFO flow control. Implement the interrupt
generation logic for the TxFIFO occupancy.
Some (interrupt) status register bits relating to the TxFIFO path were
not defined. Define them. This prepares support for proper Tx data path
flow control.
The status register bits are always pure functions of other device
state. Move the generation of these bits to the update_status()
function to simplify. Makes developing much easier as theres now no need
to recheck status bits on all the changes to rx/tx fifo state.
This should be rechecked on bus write accesses as such accesses may
change the underlying state that generates the interrupt. Particular
relevant for when the guest touches the interrupt status or mask.
Alexander Graf [Sat, 4 Jan 2014 22:15:51 +0000 (22:15 +0000)]
target-arm: Give the FPSCR rounding modes names
When setting rounding modes we currently just hardcode the numeric values
for rounding modes in a big switch statement.
With AArch64 support coming, we will need to refer to these rounding modes
at different places throughout the code though, so let's better give them
names so we don't get confused by accident.
This patch adds emulation for the "Floating-point data-processing (3 source)"
group of instructions.
Signed-off-by: Alexander Graf <[email protected]>
[WN: Commit message tweak, merged single and double precision patches.
Implement using muladd as suggested by Richard Henderson.] Signed-off-by: Will Newton <[email protected]>
[PMM: pull field decode up a level, use register accessors] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
This patch adds emulation for the "Floating-point data-processing (2 source)"
group of instructions.
Signed-off-by: Alexander Graf <[email protected]>
[WN: Commit message tweak, merge single and double precision patches. Rebase
and update to new infrastructure. Incorporate FMIN/FMAX support patch by
Michael Matz.] Signed-off-by: Will Newton <[email protected]>
[PMM:
* added convenience accessors for FP s and d regs
* pulled the field decode and opcode validity check up a level] Signed-off-by: Peter Maydell <[email protected]> Reviewed-by: Richard Henderson <[email protected]>
Peter Maydell [Sat, 4 Jan 2014 22:15:49 +0000 (22:15 +0000)]
target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum
Use the VFP_BINOP macro to provide helpers for min, max, minnum
and maxnum, rather than hand-rolling them. (The float64 max
version is not used by A32 but will be needed for A64.)
Peter Maydell [Sat, 4 Jan 2014 22:15:49 +0000 (22:15 +0000)]
target-arm: A64: Fix vector register access on bigendian hosts
The A64 128 bit vector registers are stored as a pair of
uint64_t values in the register array. This means that if
we're directly loading or storing a value of size less than
64 bits we must adjust the offset appropriately to account
for whether the host is bigendian or not. Provide utility
functions to abstract away the offsetof() calculations for
the FP registers.
For do_fp_st() we can sidestep most of the issues for 64 bit
and smaller reg-to-mem transfers by always doing a 64 bit
load from the register and writing just the piece we need
to memory.
The AArch64 linux-user support was written before but merged after
commit 4ce6243dc621 which cleaned up the handling of the clone()
syscall argument order, so we failed to notice that AArch64 also needs
TARGET_CLONE_BACKWARDS to be defined. Add this define so that clone
and fork syscalls work correctly.
Michael Matz [Sat, 4 Jan 2014 22:15:47 +0000 (22:15 +0000)]
target-arm: A64: support for ld/st/cl exclusive
This implement exclusive loads/stores for aarch64 along the lines of
arm32 and ppc implementations. The exclusive load remembers the address
and loaded value. The exclusive store throws an an exception which uses
those values to check for equality in a proper exclusive region.
This is not actually the architecture mandated semantics (for either
AArch32 or AArch64) but it is close enough for typical guest code
sequences to work correctly, and saves us from having to monitor all
guest stores. It's fairly easy to come up with test cases where we
don't behave like hardware - we don't for example model cache line
behaviour. However in the common patterns this works, and the existing
32 bit ARM exclusive access implementation has the same limitations.
AArch64 also implements new acquire/release loads/stores (which may be
either exclusive or non-exclusive). These imposes extra ordering
constraints on memory operations (ie they act as if they have an implicit
barrier built into them). As TCG is single-threaded all our barriers
are no-ops, so these just behave like normal loads and stores.
Peter Maydell [Sat, 4 Jan 2014 22:15:47 +0000 (22:15 +0000)]
target-arm: Widen exclusive-access support struct fields to 64 bits
In preparation for adding support for A64 load/store exclusive instructions,
widen the fields in the CPU state struct that deal with address and data values
for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32
exclusive accesses will be generally separate there are some odd theoretical
corner cases (eg you should be able to do the exclusive load in AArch32, take
an exception to AArch64 and successfully do the store exclusive there), and it's
also easier to reason about.
The changes in semantics for the variables are:
exclusive_addr -> extended to 64 bits; -1ULL for "monitor lost",
otherwise always < 2^32 for AArch32
exclusive_val -> extended to 64 bits. 64 bit exclusives in AArch32 now
use the high half of exclusive_val instead of a separate exclusive_high
exclusive_high -> is no longer used in AArch32; extended to 64 bits as
it will be needed for AArch64's pair-of-64-bit-values exclusives.
exclusive_test -> extended to 64 bits, as it is an address. Since this is
a linux-user-only field, in arm-linux-user it will always have the top
32 bits zero.
exclusive_info -> stays 32 bits, as it is neither data nor address, but
simply holds register indexes etc. AArch64 will be able to fit all its
information into 32 bits as well.
Note that the refactoring of gen_store_exclusive() coincidentally fixes
a minor bug where ldrexd would incorrectly update the first CPU register
even if the load for the second register faulted.
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