spapr: Implement processor compatibility in ibm, client-architecture-support
Modern Linux kernels support last POWERPC CPUs so when a kernel boots,
in most cases it can find a matching cpu_spec in the kernel's cpu_specs
list. However if the kernel is quite old, it may be missing a definition
of the actual CPU. To provide an ability for old kernels to work on modern
hardware, a Processor Compatibility Mode has been introduced
by the PowerISA specification.
>From the hardware prospective, it is supported by the Processor
Compatibility Register (PCR) which is defined in PowerISA. The register
enables one of the compatibility modes (2.05/2.06/2.07).
Since PCR is a hypervisor privileged register and cannot be
directly accessed from the guest, the mode selection is done via
ibm,client-architecture-support (CAS) RTAS call using which the guest
specifies what "raw" and "architected" CPU versions it supports.
QEMU works out the best match, changes a "cpu-version" property of
every CPU and notifies the guest about the change by setting these
properties in the buffer passed as a response on a custom H_CAS hypercall.
This implements ibm,client-architecture-support parameters parsing
(now only for PVRs) and cooks the device tree diff with new values for
"cpu-version", "ibm,ppc-interrupt-server#s" and
"ibm,ppc-interrupt-server#s" properties.
spapr: Limit threads per core according to current compatibility mode
This puts a limit to the number of threads per core based on the current
compatibility mode. Although PowerISA specs do not specify the maximum
threads per core number, the linux guest still expects that
PowerISA2.05-compatible CPU supports only 2 threads per core as this
is what POWER6 (2.05 compliant CPU) implements, the same is for
POWER7 (2.06, 4 threads) and POWER8 (2.07, 8 threads).
This calls spapr_fixup_cpu_smt_dt() with the maximum allowed number of
threads which affects ibm,ppc-interrupt-server#s and
ibm,ppc-interrupt-gserver#s properties.
In PPC code we usually use the "cs" name for a CPUState* variables
and "cpu" for PowerPCCPU. So let's change spapr_fixup_cpu_dt() to
use same rules as spapr_create_fdt_skel() does.
This adds missing nodes creation if they do not already exist in
the current device tree, this is going to be used from
the client-architecture-support handler.
The PAPR+ specification defines a ibm,client-architecture-support (CAS)
RTAS call which purpose is to provide a negotiation mechanism for
the guest and the hypervisor to work out the best compatibility parameters.
During the negotiation process, the guest provides an array of various
options and capabilities which it supports, the hypervisor adjusts
the device tree and (optionally) reboots the guest.
At the moment the Linux guest calls CAS method at early boot so SLOF
gets called. SLOF allocates a memory buffer for the device tree changes
and calls a custom KVMPPC_H_CAS hypercall. QEMU parses the options,
composes a diff for the device tree, copies it to the buffer provided
by SLOF and returns to SLOF. SLOF updates the device tree and returns
control to the guest kernel. Only then the Linux guest parses the device
tree so it is possible to avoid unnecessary reboot in most cases.
The device tree diff is a header with an update format version
(defined as 1 in this patch) followed by a device tree with the properties
which require update.
If QEMU detects that it has to reboot the guest, it silently does so
as the guest expects reboot to happen because this is usual pHyp firmware
behavior.
This defines custom KVMPPC_H_CAS hypercall. The current SLOF already
has support for it.
This implements stub which returns very basic tree (root node,
no properties) to the guest.
As the return buffer does not contain any change, no change in behavior is
expected.
This adds basic support for the "compat" CPU option. By specifying
the compat property, the user can manually switch guest CPU mode from
"raw" to "architected".
This defines feature disable bits which are not used yet as, for example,
PowerISA 2.07 says if 2.06 mode is selected, the TM bit does not matter -
transactional memory (TM) will be disabled because 2.06 does not define
it at all. The same is true for VSX and 2.05 mode. So just setting a mode
must be ok.
This does not change the existing behavior as the actual compatibility
mode support is coming in next patches.
Signed-off-by: Alexey Kardashevskiy <[email protected]>
[agraf: fix compilation on 32bit hosts] Signed-off-by: Alexander Graf <[email protected]>
spapr: Move SMT-related properties out of skeleton fdt
The upcoming support of the "ibm,client-architecture-support"
reconfiguration call will be able to change dynamically the number
of threads per core (SMT mode). From the device tree prospective
this does not change the number of CPU nodes (as it is one node per
a CPU core) but affects content and size of the ibm,ppc-interrupt-server#s
and ibm,ppc-interrupt-gserver#s properties.
This moves ibm,ppc-interrupt-server#s and ibm,ppc-interrupt-gserver#s
out of the device tree skeleton.
PowerISA defines a compatibility mode for server POWERPC CPUs which
is supported by the PCR special register which is hypervisor privileged.
To support this mode for guests, SPAPR defines a set of virtual PVRs,
one per PowerISA spec version. When a hypervisor needs a guest to work in
a compatibility mode, it puts a virtual PVR value into @cpu-version
property of a CPU node.
This introduces a "compat" CPU option which defines maximal compatibility
mode enabled. The supported modes are power6/power7/power8.
This does not change the existing behaviour, new property will be used
by next patches.
Alexander Graf [Thu, 22 May 2014 15:12:23 +0000 (17:12 +0200)]
PPC: openpic_kvm: Implement reset
When we trigger a system reset, the in-kernel openpic controller should also
get reset. This happens through a write to the GCR.RESET register which is
the same mechanism a guest would use to manually reset the device.
Paul Janzen [Thu, 22 May 2014 06:09:45 +0000 (23:09 -0700)]
openpic: Reset IRQ source private members
The openpic emulation code maintains an allowable-CPU's bitmap
("destmask") for each IRQ source which is calculated from the IDR
register value whenever the guest OS writes to it. However, if the
guest OS relies on the system to set the IDR register to a default
value at reset, and does not write IDR, then destmask does not get
updated, and interrupts do not get propagated to the guest.
Additionally, if an IRQ source is marked as critical, the source's
internal "output" and "nomask" fields are not correctly reset when the
PIC is reset.
Fix both these issues by calling write_IRQreg_idr from within
openpic_reset, instead of simply setting the IDR register to the
specified idr_reset value.
Paul Janzen [Thu, 22 May 2014 04:46:52 +0000 (21:46 -0700)]
openpic: Move definition of openpic_reset
This patch moves the definition of openpic_reset after the various
register read/write functions. No functional change. It is in
preparation for using the register read/write functions in
openpic_reset.
Greg Kurz [Mon, 19 May 2014 17:59:05 +0000 (19:59 +0200)]
target-ppc: Introduce callback for interrupt endianness
POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR
special purpose register to decide the endianness to use when
entering interrupt handlers. When running a Linux guest, this
provides a hint on the endianness used by the kernel. And when
it comes to dumping a guest, the information is needed to write
ELF headers using the kernel endianness.
Bharata B Rao [Mon, 19 May 2014 17:58:35 +0000 (19:58 +0200)]
target-ppc: Support dump for little endian ppc64
Fix ppc64 arch specific dump code to support all combinations of little/big
endian hosts/guests. FWIW the current code is broken for altivec registers
when guest and host have a different endianness: these 128-bit registers
are written to guest memory as a two 64-bit entities and we should also swap
them.
Unit testing was done with the following program provided by Tom Musta:
We introduce a NoteFuncArg type to avoid adding extra arguments to all note
functions.
Signed-off-by: Bharata B Rao <[email protected]>
[ rebased on top of current master branch,
introduced NoteFuncArg,
use new cpu_to_dump{16,32,64} endian helpers,
fix altivec support,
Greg Kurz <[email protected]> ] Reviewed-by: Alexander Graf <[email protected]> Signed-off-by: Greg Kurz <[email protected]> Signed-off-by: Alexander Graf <[email protected]>
Bharata B Rao [Mon, 19 May 2014 17:57:44 +0000 (19:57 +0200)]
dump: Make DumpState and endian conversion routines available for arch-specific dump code
Make DumpState and endian conversion routines available for arch-specific dump
code by moving into dump.h. DumpState will be needed by arch-specific dump
code to access target endian information from DumpState->ArchDumpInfo. Also
break the dependency of dump.h from stubs/dump.c by creating a separate
dump-arch.h.
This patch doesn't change any functionality.
Signed-off-by: Bharata B Rao <[email protected]>
[ rebased on top of current master branch,
renamed endian helpers to cpu_to_dump{16,32,64},
pass a DumpState * argument to endian helpers,
Greg Kurz <[email protected]> ] Signed-off-by: Greg Kurz <[email protected]>
[agraf: fix to apply] Signed-off-by: Alexander Graf <[email protected]>
Mark Cave-Ayland [Sun, 18 May 2014 12:20:55 +0000 (13:20 +0100)]
macio: handle non-block ATAPI DMA transfers
Currently the macio DMA routines assume that all DMA requests are for read/write
block transfers. This is not always the case for ATAPI, for example when
requesting a TOC where the response is generated directly in the IDE buffer.
Detect these non-block ATAPI DMA transfers (where no lba is specified in the
command) and copy the results directly into RAM as indicated by the DBDMA
descriptor. This fixes CDROM access under MorphOS.
This adds a "ibm,chip-id" property for CPU nodes which should be the same
for all cores in the same CPU socket. The recent guest kernels use this
information to associate threads with sockets.
This allows guests to have a different timebase origin from the host.
This is needed for migration, where a guest can migrate from one host
to another and the two hosts might have a different timebase origin.
However, the timebase seen by the guest must not go backwards, and
should go forwards only by a small amount corresponding to the time
taken for the migration.
This is only supported for recent POWER hardware which has the TBU40
(timebase upper 40 bits) register. That includes POWER6, 7, 8 but not
970.
This adds kvm_access_one_reg() to access a special register which is not
in env->spr. This requires kvm_set_one_reg/kvm_get_one_reg patch.
The feature must be present in the host kernel.
This bumps vmstate_spapr::version_id and enables new vmstate_ppc_timebase
only for it. Since the vmstate_spapr::minimum_version_id remains
unchanged, migration from older QEMU is supported but without
vmstate_ppc_timebase.
Alexander Graf [Sun, 19 Jan 2014 23:27:25 +0000 (00:27 +0100)]
PPC: e500: Move to u-boot as firmware
Almost all platforms QEMU emulates have some sort of firmware they can load
to expose a guest environment that closely resembles the way it would look
like on real hardware.
This patch introduces such a firmware on our e500 platforms. U-boot is the
default firmware for most of these systems and as such our preferred choice.
For backwards compatibility reasons (and speed and simplicity) we skip u-boot
when you use -kernel and don't pass in -bios. For all other combinations like
-kernel and -bios or no -kernel you get u-boot as firmware.
This allows you to modify the boot environment, execute a networked boot through
the e1000 emulation and execute u-boot payloads.
Alexander Graf [Sun, 19 Jan 2014 23:25:40 +0000 (00:25 +0100)]
PPC: Add u-boot firmware for e500
This adds a special build of u-boot tailored for the e500 platforms we
emulate. It is based on the current version of upstream u-boot which
contains all the code necessary to drive our QEMU provided machines.
Alexander Graf [Sun, 19 Jan 2014 16:28:33 +0000 (17:28 +0100)]
PPC: Fail on leaking temporaries
When QEMU gets compiled with --enable-debug-tcg we can check for temporary
leakage. Implement the necessary target code for this and fail emulation
when we hit a leakage.
This hopefully ensures that we don't get new leaks.
Alexander Graf [Sun, 19 Jan 2014 16:26:33 +0000 (17:26 +0100)]
PPC: Fix TCG chunks that don't free their temps
We want to make sure that every instruction cleans up after itself and
clears every temporary it allocated.
While checking whether this is already the case, I came across a few
cases where it isn't. This patch fixes every translation I found that
doesn't free their allocated temporaries.
Bharat Bhushan [Mon, 12 May 2014 09:45:40 +0000 (15:15 +0530)]
PPC: e500: implement PCI INTx routing
This patch adds pci pin to irq_num routing callback.
This callback is called from pci_device_route_intx_to_irq to
find which pci device maps to which irq.
This fix is required for pci-device passthrough using vfio.
Alexander Graf [Sun, 11 May 2014 16:37:00 +0000 (18:37 +0200)]
KVM: PPC: Don't secretly add 1T segment feature to CPU
When we select a CPU type that does not support 1TB segments, we should
not expose 1TB just because KVM supports 1TB segments. User configuration
always wins over feature availability.
Tom Musta [Thu, 13 Mar 2014 14:13:30 +0000 (09:13 -0500)]
target-ppc: Refactor AES Instructions
This patch refactors the PowerPC Advanced Encryption Standard (AES) instructions
to use the common AES tables (include/qemu/aes.h).
Specifically:
- vsbox is recoded to use the AES_sbox table.
- vcipher, vcipherlast and vncipherlast are all recoded to use the optimized
AES_t[ed][0-4] tables.
- vncipher is recoded to use a combination of InvS-Box, InvShiftRows and
InvMixColumns tables. It was not possible to use AES_Td[0-4] due to a
slight difference in how PowerPC implements vncipher.
Tom Musta [Thu, 13 Mar 2014 14:13:28 +0000 (09:13 -0500)]
target-i386: Use Common ShiftRows and InvShiftRows Tables
This patch eliminates the (now) redundant copy of the Advanced Encryption Standard (AES)
ShiftRows and InvShiftRows tables; the code is updated to use the common tables declared in
include/qemu/aes.h.
Tom Musta [Thu, 13 Mar 2014 14:13:26 +0000 (09:13 -0500)]
util: Add AES ShiftRows and InvShiftRows Tables
This patch adds tables that implement the Advanced Encryption Standard (AES) ShiftRows
and InvShiftRows transformations. These are commonly used in instruction models.
At the moment XICS does not support interrupts reuse so sPAPR PHB
implements this. sPAPRPHBState holds array of 32 spapr_pci_msi to
describe PCI config address, first MSI and number of MSIs. Once
allocated for a device, QEMU tries reusing this config until the number
of MSIs changes.
Existing SPAPR guests call ibm,change-msi in a loop until the handler
returns the requested number of vectors.
Recently introduced check for the maximum number of MSI/MSIX vectors
supported by a device only works for a device which is new for PHB's
MSI cache. If it is already there, the check is not performed which
leads to new IRQ block allocation. This happens during PCI hotplug
even when the user hot plug the same device which he just hot unplugged.
Tom Musta [Mon, 21 Apr 2014 20:55:21 +0000 (15:55 -0500)]
target-ppc: Introduce DFP Shift Significand
Add emulation of the PowerPC Decimal Floating Point Shift Significand
Left Immediate (dscli[q][.]) and DFP Shift Significant Right Immediate
(dscri[q][.]) instructions.
Tom Musta [Mon, 21 Apr 2014 20:55:12 +0000 (15:55 -0500)]
target-ppc: Introduce DFP Round to Integer
Add emulation of the PowerPC Decimal Floating Point (DFP) Round
to FP Integer With Inexact (drintx[q][.]) and DFP Round to FP
Integer Without Inexact (drintn[q][.]) instructions.
Tom Musta [Mon, 21 Apr 2014 20:55:00 +0000 (15:55 -0500)]
target-ppc: Introduce DFP Post Processor Utilities
Add post-processing utilities to the PowerPC Decimal Floating Point
(DFP) helper code. Post-processors are small routines that execute
after a preliminary DFP result is computed. They are used, among other
things, to compute status bits.
This change defines a function type for post processors as well as a
generic routine to run a list (array) of post-processors.
Actual post-processor implementations will be added as needed by specific
DFP helpers in subsequent changes.
Some routines are annotated with the GCC unused attribute in order to
preserve build bisection. The annotation will be removed in subsequent
patches.
Tom Musta [Mon, 21 Apr 2014 20:54:59 +0000 (15:54 -0500)]
target-ppc: Introduce DFP Helper Utilities
Add a new file (dfp_helper.c) to the PowerPC implementation for Decimal Floating
Point (DFP) emulation. This first version of the file declares a structure that
will be used by DFP helpers. It also implements utilities that will initialize
such a structure for either a long (64 bit) DFP instruction or an extended (128
bit, aka "quad") instruction.
Some utility functions are annotated with the unused attribute in order to preserve
build bisection.
Signed-off-by: Tom Musta <[email protected]>
[agraf: Add never reached assert on dfp_prepare_rounding_mode()] Signed-off-by: Alexander Graf <[email protected]>
Tom Musta [Mon, 21 Apr 2014 20:54:58 +0000 (15:54 -0500)]
target-ppc: Introduce Decoder Macros for DFP
Add decoder macros for the various Decimal Floating Point
instruction forms. Illegal instruction masks are used to not only
guard against reserved instruction field use, but also to catch
illegal quad word forms that use odd-numbered floating point registers.
Tom Musta [Mon, 21 Apr 2014 20:54:56 +0000 (15:54 -0500)]
target-ppc: Define FPR Pointer Type for Helpers
Define a floating pointer register pointer type in the PowerPC
helper header. The type will be used to pass FPR register operands
to Decimal Floating Point (DFP) helpers. A pointer is used because
the quad word forms of PowerPC DFP instructions operate on adjacent
pairs of floating point registers and thus can be thought of as
arrays of length 2.
Tom Musta [Mon, 21 Apr 2014 20:54:55 +0000 (15:54 -0500)]
libdecnumber: Fix decNumberSetBCD
Fix a simple bug in the decNumberSetBCD() function. This function
encodes a decNumber with "n" BCD digits. The original code erroneously
computed the number of declets from the dn argument, which is the output
decNumber value, and hence may contain garbage. Instead, the input "n"
value is used.
Tom Musta [Mon, 21 Apr 2014 20:54:54 +0000 (15:54 -0500)]
libdecnumber: Introduce decNumberIntegralToInt64
Introduce a new conversion function to the libdecnumber library.
This function converts a decNumber to a signed 64-bit integer.
In order to support 64-bit integers (which may have up to 19
decimal digits), the existing "powers of 10" array is expanded
from 10 to 19 entries.
Tom Musta [Mon, 21 Apr 2014 20:54:53 +0000 (15:54 -0500)]
libdecnumber: Introduce decNumberFrom[U]Int64
Introduce two conversion functions to the libdecnumber library.
These conversions transform 64 bit integers to the internal decNumber
representation. Both a signed and unsigned version is added.
Tom Musta [Mon, 21 Apr 2014 20:54:52 +0000 (15:54 -0500)]
target-ppc: Enable Building of libdecnumber
Enable compilation of the newly added libdecnumber library code.
Object file targets are added to Makefile.target using a newly
introduced flag CONFIG_LIBDECNUMBER. The flag is added
to the PowerPC targets (ppc[64]-linux-user, ppc[64]-softmmu).
Signed-off-by: Tom Musta <[email protected]>
[agraf: add ppcemb and ppc64abi32 config] Signed-off-by: Alexander Graf <[email protected]>
Tom Musta [Mon, 21 Apr 2014 20:54:51 +0000 (15:54 -0500)]
libdecnumber: Eliminate Unused Variable in decSetSubnormal
Eliminate an unused variable in the decSetSubnormal routine. The
variable dnexp is declared and eventually set but never used, and
thus may trigger an unused-but-set-variable warning.
Tom Musta [Mon, 21 Apr 2014 20:54:50 +0000 (15:54 -0500)]
libdecnumber: Eliminate redundant declarations
Eliminate redundant declarations of symbols DPD2BIN and BIN2DPD in
various .c source files. These symbols are already declared in decDPD.h and
thus will trigger 'redundant redeclaration of ?XXX?' warnings, which, of
course, may fail QEMU compilation.
Tom Musta [Mon, 21 Apr 2014 20:54:48 +0000 (15:54 -0500)]
libdecnumber: Modify dconfig.h to Integrate with QEMU
Modify the dconfig.h header file so that libdecnumber code integrates QEMU
configuration. Specifically:
- the WORDS_BIGENDIAN preprocessor macro is used in libdecnumber code to
determines endianness. It is derived from the existing QEMU macro
HOST_WORDS_BIGENDIAN which is defined in config-host.h.
- the DECPUN macro determines the number of decimal digits (aka declets) per
unit (byte). This is 3 for PowerPC DFP.
Tom Musta [Mon, 21 Apr 2014 20:54:47 +0000 (15:54 -0500)]
libdecnumber: Prepare libdecnumber for QEMU include structure
Consistent with other libraries in QEMU, the libdecnumber header files were
placed in include/libdecnumber, separate from the C code. This is different
from the original libdecnumber source, where they were co-located.
Change the libdecnumber source code so that it reflects this split. Specifically,
modify directives of the form:
Tom Musta [Mon, 21 Apr 2014 20:54:46 +0000 (15:54 -0500)]
libdecnumber: Eliminate #include *Symbols.h
The various *Symbols.h files were not copied from the original GCC libdecnumber
library; they are not necessary for use in QEMU. Remove all instances of
Tom Musta [Mon, 21 Apr 2014 20:54:45 +0000 (15:54 -0500)]
libdecnumber: Introduce libdecnumber Code
Add files from the libdecnumber decimal floating point library to QEMU. The libdecnumber
library was originally part of GCC and contains code that is useful in emulating the PowerPC
decimal floating point (DFP) instructions. This particular copy of the source comes from
GCC 4.3 and is licensed at GPLv2+.
Currently migration fails if CPU version (PVR register) is different
even a bit. This check is performed at the very end of migration when
device states are sent. This is too late for management software and
we need to provide a way for the user to make sure that migration
will succeed if QEMU is started with appropritate command line parameters.
This removes the PVR check.
This resets PVR to the default value as the existing VMSTATE record
for SPR array sends all 1024 registers unconditionally and overwrites
the destination PVR.
If the user wants some guarantees for migration to succeed, then
a CPU name or "host" CPU with a "compat" option (on its way to upsteam)
should be used and KVM or TCG is expected to fail on unsupported values
at the moment of QEMU start.
spapr_pci: Fix number of returned vectors in ibm, change-msi
Current guest kernels try allocating as many vectors as the quota is.
For example, in the case of virtio-net (which has just 3 vectors)
the guest requests 4 vectors (that is the quota in the test) and
the existing ibm,change-msi handler returns 4. But before it returns,
it calls msix_set_message() in a loop and corrupts memory behind
the end of msix_table.
This limits the number of vectors returned by ibm,change-msi to
the maximum supported by the actual device.
Greg Kurz [Fri, 7 Feb 2014 13:44:17 +0000 (14:44 +0100)]
spapr-pci: remove io ports workaround
In the past, IO space could not be mapped into the memory address space
so we introduced a workaround for that. Nowadays it does not look
necessary so we can remove the workaround and make sPAPR PCI
configuration simplier.
At the moment there are 3 versions of POWER7 CPUs defined. However
we do not emulate these CPUs diffent and it does not make much
sense to keep them all.
This removes POWER7_v2.0 and POWER7_v2.1 and leaves just one versioned
CPU per family which is POWER7_v2.3 with POWER7 alias.
This moves aliases lookup after CPU class lookup. This is to let new generic
CPU to be found first if it is present and only if it is not (TCG case), use
aliases.
target-ppc: Create versionless CPU class per family if KVM
At the moment generic version-less CPUs are supported via hardcoded aliases.
For example, POWER7 is an alias for POWER7_v2.1. So when QEMU is started
with -cpu POWER7, the POWER7_v2.1 class instance is created.
This approach works for TCG and KVMs other than HV KVM. HV KVM cannot emulate
PVR value so the guest always sees the real PVR. HV KVM will not allow setting
PVR other that the host PVR because of that (the kernel patch for it is on
its way). So in most cases it is impossible to run QEMU with -cpu POWER7
unless the host PVR is exactly the same as the one from the alias (which
is now POWER7_v2.3). It was decided that under HV KVM QEMU should use
-cpu host.
Using "host" CPU type creates a problem for management tools such as libvirt
because they want to know in advance if the destination guest can possibly
run on the destination. Since the "host" type is really not a type and will
always work with any KVM, there is no way for libvirt to know if the migration
will success.
This registers additional CPU class derived from the host CPU family.
The name for it is taken from @desc field of the CPU family class.
Tom Musta [Wed, 9 Apr 2014 19:53:24 +0000 (14:53 -0500)]
monitor: QEMU Monitor Instruction Disassembly Incorrect for PowerPC LE Mode
The monitor support for disassembling instructions does not honor the MSR[LE]
bit for PowerPC processors.
This change enhances the monitor_disas() routine by supporting a flag bit
for Little Endian mode. Bit 16 is used since that bit was used in the
analagous guest disassembly routine target_disas().
Also, to be consistent with target_disas(), the disassembler bfd_mach field
can be passed in the flags argument.
Tom Musta [Wed, 9 Apr 2014 19:53:23 +0000 (14:53 -0500)]
target-ppc: Fix target_disas
Inspect only bit 16 for the Little Endian test. Correct comment preceding
the target_disas() function. Correct grammar in comment for flags processing.
# gpg: Signature made Mon 16 Jun 2014 04:10:18 BST using RSA key ID 5872D723
# gpg: Can't check signature: public key not found
* remotes/juanquintela/tags/migration/20140616:
migration: catch unknown flags in ram_load
rdma: Fix block during rdma migration
migration: Increase default max_downtime from 30ms to 300ms
vmstate: Refactor opening of files
savevm: Remove all the unneeded version_minimum_id_old (x86)
savevm: Remove all the unneeded version_minimum_id_old (ppc)
Gonglei [Tue, 13 May 2014 12:25:38 +0000 (20:25 +0800)]
rdma: Fix block during rdma migration
If the networking break or there's something wrong with rdma
device(ib0 with no IP) during rdma migration, the main_loop of
qemu will be blocked in rdma_destroy_id. I add rdma_ack_cm_event
to fix this bug.
migration: Increase default max_downtime from 30ms to 300ms
The existing timeout is 30ms which on 100MB/s (1Gbit) gives us
3MB/s rate maximum. If we put some load on the guest, it is easy to
get page dirtying rate too big so live migration will never complete.
In the case of libvirt that means that the guest will be stopped
anyway after a timeout specified in the "virsh migrate" command and
this normally generates even bigger delay.
This changes max_downtime to 300ms which seems to be more
reasonable value.
Juan Quintela [Wed, 16 Apr 2014 13:32:32 +0000 (15:32 +0200)]
savevm: Remove all the unneeded version_minimum_id_old (x86)
After previous Peter patch, they are redundant. This way we don't
assign them except when needed. Once there, there were lots of case
where the ".fields" indentation was wrong:
Juan Quintela [Wed, 16 Apr 2014 13:24:04 +0000 (15:24 +0200)]
savevm: Remove all the unneeded version_minimum_id_old (ppc)
After previous Peter patch, they are redundant. This way we don't
assign them except when needed. Once there, there were lots of case
where the ".fields" indentation was wrong:
projects / qemu.git / log