Git Repo - qemu.git/commit

]> Git Repo - qemu.git/commit

author	Alexander Graf <[email protected]>
	Sun, 19 Jan 2014 16:49:11 +0000 (17:49 +0100)
committer	Alexander Graf <[email protected]>
	Mon, 16 Jun 2014 11:24:35 +0000 (13:24 +0200)
commit	ea71258da4b8141d8a808d94518a0964c0f92810
tree	253b6f10663b08f0846bd40a08821501a15495dd	tree \| snapshot
parent	d2ea2bf740c515de41f45e4d6f36683db3458881	commit \| diff

PPC: Properly emulate L1CSR0 and L1CSR1

There are 2 L1 cache control registers - one for data (L1CSR0) and
one for instructions (L1CSR1).

Emulate both of them well enough to give the guest the illusion that
it could actually do anything about its caches.

Signed-off-by: Alexander Graf <[email protected]>

target-ppc/cpu.h		diff \| blob \| blame \| history
target-ppc/translate_init.c		diff \| blob \| blame \| history

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