PPC: Add L1CFG1 SPR emulation

In addition to the L1 data cache configuration register L1CFG0 there is
also another one for the L1 instruction cache called L1CFG1.

Emulate that one with the same values as the data one.

Signed-off-by: Alexander Graf <[email protected]>

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 178fc55689d418b2fd8f343ad3e3ca41bb8e8ac2..f36c90b47b825397b27301829cc40cd35ab8006d 100644 (file)
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1375,6 +1375,7 @@ static inline int cpu_mmu_index (CPUPPCState *env)
 #define SPR_Exxx_BBEAR        (0x201)
 #define SPR_Exxx_BBTAR        (0x202)
 #define SPR_Exxx_L1CFG0       (0x203)
+#define SPR_Exxx_L1CFG1       (0x204)
 #define SPR_Exxx_NPIDR        (0x205)
 #define SPR_ATBL              (0x20E)
 #define SPR_ATBU              (0x20F)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 07f723da065e157f6eb33853af89e07b2981e72a..fc9d9322689203f76448309ac5675f2408ab187c 100644 (file)
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -4651,6 +4651,8 @@ static void init_proc_e500 (CPUPPCState *env, int version)
     uint64_t ivpr_mask = 0xFFFF0000ULL;
     uint32_t l1cfg0 = 0x3800  /* 8 ways */
                     | 0x0020; /* 32 kb */
+    uint32_t l1cfg1 = 0x3800  /* 8 ways */
+                    | 0x0020; /* 32 kb */
 #if !defined(CONFIG_USER_ONLY)
     int i;
 #endif
@@ -4719,6 +4721,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
         env->dcache_line_size = 64;
         env->icache_line_size = 64;
         l1cfg0 |= 0x1000000; /* 64 byte cache block size */
+        l1cfg1 |= 0x1000000; /* 64 byte cache block size */
         break;
     default:
         cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
@@ -4769,7 +4772,10 @@ static void init_proc_e500 (CPUPPCState *env, int version)
                  &spr_read_generic, SPR_NOACCESS,
                  &spr_read_generic, SPR_NOACCESS,
                  l1cfg0);
-    /* XXX : not implemented */
+    spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
+                 &spr_read_generic, SPR_NOACCESS,
+                 &spr_read_generic, SPR_NOACCESS,
+                 l1cfg1);
     spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
                  SPR_NOACCESS, SPR_NOACCESS,
                  &spr_read_generic, &spr_write_e500_l1csr0,