target-arm: Move MVFR* setup to per cpu init fns

Move the MVFR* VFP feature register values to ARMCPU,
so they are set up by the implementation-specific instance
init functions rather than in cpu_reset_model_id().

Signed-off-by: Peter Maydell <[email protected]>
Acked-by: Andreas Färber <[email protected]>

diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 7cc4cd51ba2e5af180ac298bd4068ed624eb09ec..c51eb84817554665485695ffb9157747116ab37d 100644 (file)
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -71,6 +71,8 @@ typedef struct ARMCPU {
      */
     uint32_t midr;
     uint32_t reset_fpsid;
+    uint32_t mvfr0;
+    uint32_t mvfr1;
 } ARMCPU;
 
 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 5fb78030a3bbdbfe01e713564752e24e16f925e7..80ca7aa2a83006f5977bc8d4acddb14cca1dec57 100644 (file)
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -128,6 +128,8 @@ static void arm1136_r2_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_VFP);
     cpu->midr = ARM_CPUID_ARM1136_R2;
     cpu->reset_fpsid = 0x410120b4;
+    cpu->mvfr0 = 0x11111111;
+    cpu->mvfr1 = 0x00000000;
 }
 
 static void arm1136_initfn(Object *obj)
@@ -138,6 +140,8 @@ static void arm1136_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_VFP);
     cpu->midr = ARM_CPUID_ARM1136;
     cpu->reset_fpsid = 0x410120b4;
+    cpu->mvfr0 = 0x11111111;
+    cpu->mvfr1 = 0x00000000;
 }
 
 static void arm1176_initfn(Object *obj)
@@ -148,6 +152,8 @@ static void arm1176_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_VAPA);
     cpu->midr = ARM_CPUID_ARM1176;
     cpu->reset_fpsid = 0x410120b5;
+    cpu->mvfr0 = 0x11111111;
+    cpu->mvfr1 = 0x00000000;
 }
 
 static void arm11mpcore_initfn(Object *obj)
@@ -158,6 +164,8 @@ static void arm11mpcore_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_VAPA);
     cpu->midr = ARM_CPUID_ARM11MPCORE;
     cpu->reset_fpsid = 0x410120b4;
+    cpu->mvfr0 = 0x11111111;
+    cpu->mvfr1 = 0x00000000;
 }
 
 static void cortex_m3_initfn(Object *obj)
@@ -177,6 +185,8 @@ static void cortex_a8_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
     cpu->midr = ARM_CPUID_CORTEXA8;
     cpu->reset_fpsid = 0x410330c0;
+    cpu->mvfr0 = 0x11110222;
+    cpu->mvfr1 = 0x00011100;
 }
 
 static void cortex_a9_initfn(Object *obj)
@@ -194,6 +204,8 @@ static void cortex_a9_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_V7MP);
     cpu->midr = ARM_CPUID_CORTEXA9;
     cpu->reset_fpsid = 0x41033090;
+    cpu->mvfr0 = 0x11110222;
+    cpu->mvfr1 = 0x01111111;
 }
 
 static void cortex_a15_initfn(Object *obj)
@@ -209,6 +221,8 @@ static void cortex_a15_initfn(Object *obj)
     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
     cpu->midr = ARM_CPUID_CORTEXA15;
     cpu->reset_fpsid = 0x410430f0;
+    cpu->mvfr0 = 0x10110222;
+    cpu->mvfr1 = 0x11111111;
 }
 
 static void ti925t_initfn(Object *obj)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3247dd31d7de7f7758d9f160716e911b5d7713b5..777bb036e4d72f4d54d7839ca614cee02df76d1e 100644 (file)
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -72,31 +72,23 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
          * for 1136_r2 (in particular r0p2 does not actually implement most
          * of the ID registers).
          */
-        env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
-        env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
         memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
         memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
         env->cp15.c0_cachetype = 0x1dd20d2;
         env->cp15.c1_sys = 0x00050078;
         break;
     case ARM_CPUID_ARM1176:
-        env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
-        env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
         memcpy(env->cp15.c0_c1, arm1176_cp15_c0_c1, 8 * sizeof(uint32_t));
         memcpy(env->cp15.c0_c2, arm1176_cp15_c0_c2, 8 * sizeof(uint32_t));
         env->cp15.c0_cachetype = 0x1dd20d2;
         env->cp15.c1_sys = 0x00050078;
         break;
     case ARM_CPUID_ARM11MPCORE:
-        env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
-        env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
         memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
         memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
         env->cp15.c0_cachetype = 0x1dd20d2;
         break;
     case ARM_CPUID_CORTEXA8:
-        env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
-        env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
         memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
         memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
         env->cp15.c0_cachetype = 0x82048004;
@@ -107,8 +99,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         env->cp15.c1_sys = 0x00c50078;
         break;
     case ARM_CPUID_CORTEXA9:
-        env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
-        env->vfp.xregs[ARM_VFP_MVFR1] = 0x01111111;
         memcpy(env->cp15.c0_c1, cortexa9_cp15_c0_c1, 8 * sizeof(uint32_t));
         memcpy(env->cp15.c0_c2, cortexa9_cp15_c0_c2, 8 * sizeof(uint32_t));
         env->cp15.c0_cachetype = 0x80038003;
@@ -118,8 +108,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         env->cp15.c1_sys = 0x00c50078;
         break;
     case ARM_CPUID_CORTEXA15:
-        env->vfp.xregs[ARM_VFP_MVFR0] = 0x10110222;
-        env->vfp.xregs[ARM_VFP_MVFR1] = 0x11111111;
         memcpy(env->cp15.c0_c1, cortexa15_cp15_c0_c1, 8 * sizeof(uint32_t));
         memcpy(env->cp15.c0_c2, cortexa15_cp15_c0_c2, 8 * sizeof(uint32_t));
         env->cp15.c0_cachetype = 0x8444c004;
@@ -194,6 +182,8 @@ void cpu_state_reset(CPUARMState *env)
     env->cp15.c15_config_base_address = tmp;
     env->cp15.c0_cpuid = cpu->midr;
     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
+    env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
+    env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
 
 #if defined (CONFIG_USER_ONLY)
     env->uncached_cpsr = ARM_CPU_MODE_USR;