/* new file */
schedule_new_file(s, qemu_strdup(path), cluster_num);
else {
- assert(0);
+ abort();
return 0;
}
}
if (offset != mapping->info.file.offset + s->cluster_size
* (cluster_num - mapping->begin)) {
/* offset of this cluster in file chain has changed */
- assert(0);
+ abort();
copy_it = 1;
} else if (offset == 0) {
const char* basename = get_basename(mapping->path);
if (mapping->first_mapping_index != first_mapping_index
&& mapping->info.file.offset > 0) {
- assert(0);
+ abort();
copy_it = 1;
}
goto fail;
}
} else
- assert(0); /* cluster_count = 0; */
+ abort(); /* cluster_count = 0; */
ret += cluster_count;
}
commit_t* commit = array_get(&(s->commits), i);
switch(commit->action) {
case ACTION_RENAME: case ACTION_MKDIR:
- assert(0);
+ abort();
fail = -2;
break;
case ACTION_WRITEOUT: {
break;
}
default:
- assert(0);
+ abort();
}
}
if (i > 0 && array_remove_slice(&(s->commits), 0, i))
ret = handle_renames_and_mkdirs(s);
if (ret) {
fprintf(stderr, "Error handling renames (%d)\n", ret);
- assert(0);
+ abort();
return ret;
}
ret = commit_direntries(s, 0, -1);
if (ret) {
fprintf(stderr, "Fatal: error while committing (%d)\n", ret);
- assert(0);
+ abort();
return ret;
}
ret = handle_commits(s);
if (ret) {
fprintf(stderr, "Error handling commits (%d)\n", ret);
- assert(0);
+ abort();
return ret;
}
ret = handle_deletes(s);
if (ret) {
fprintf(stderr, "Error deleting\n");
- assert(0);
+ abort();
return ret;
}
switch (addr) {
default:
error_access("byte read", addr);
- assert(0);
+ abort();
}
}
return 0;
default:
error_access("word read", addr);
- assert(0);
+ abort();
}
}
return s->cpu->prr;
default:
error_access("long read", addr);
- assert(0);
+ abort();
}
}
}
error_access("byte write", addr);
- assert(0);
+ abort();
}
static void sh7750_mem_writew(void *opaque, target_phys_addr_t addr,
s->gpioic = mem_value;
if (mem_value != 0) {
fprintf(stderr, "I/O interrupts not implemented\n");
- assert(0);
+ abort();
}
return;
default:
error_access("word write", addr);
- assert(0);
+ abort();
}
}
return;
default:
error_access("long write", addr);
- assert(0);
+ abort();
}
}
static uint32_t invalid_read(void *opaque, target_phys_addr_t addr)
{
- assert(0);
+ abort();
return 0;
}
case MM_ITLB_ADDR:
case MM_ITLB_DATA:
/* XXXXX */
- assert(0);
+ abort();
break;
case MM_OCACHE_ADDR:
case MM_OCACHE_DATA:
case MM_UTLB_ADDR:
case MM_UTLB_DATA:
/* XXXXX */
- assert(0);
+ abort();
break;
default:
- assert(0);
+ abort();
}
return ret;
static void invalid_write(void *opaque, target_phys_addr_t addr,
uint32_t mem_value)
{
- assert(0);
+ abort();
}
static void sh7750_mmct_writel(void *opaque, target_phys_addr_t addr,
case MM_ITLB_ADDR:
case MM_ITLB_DATA:
/* XXXXX */
- assert(0);
+ abort();
break;
case MM_OCACHE_ADDR:
case MM_OCACHE_DATA:
break;
case MM_UTLB_DATA:
/* XXXXX */
- assert(0);
+ abort();
break;
default:
- assert(0);
+ abort();
break;
}
}
}
}
- assert(0);
+ abort();
}
#define INTC_MODE_NONE 0
}
}
- assert(0);
+ abort();
}
static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
case INTC_MODE_DUAL_SET: value |= *valuep; break;
case INTC_MODE_DUAL_CLR: value = *valuep & ~value; break;
- default: assert(0);
+ default: abort();
}
for (k = 0; k <= first; k++) {
}
fprintf(stderr, "sh_serial: unsupported write to 0x%02x\n", offs);
- assert(0);
+ abort();
}
static uint32_t sh_serial_ioport_read(void *opaque, uint32_t offs)
if (ret & ~((1 << 16) - 1)) {
fprintf(stderr, "sh_serial: unsupported read from 0x%02x\n", offs);
- assert(0);
+ abort();
}
return ret;
break;
default:
printf("invalid hw cursor color.\n");
- assert(0);
+ abort();
}
switch (index) {
default:
printf("sm501 system config : not implemented register read."
" addr=%x\n", (int)addr);
- assert(0);
+ abort();
}
return ret;
default:
printf("sm501 system config : not implemented register write."
" addr=%x, val=%x\n", (int)addr, value);
- assert(0);
+ abort();
}
}
default:
printf("sm501 disp ctrl : not implemented register read."
" addr=%x\n", (int)addr);
- assert(0);
+ abort();
}
return ret;
default:
printf("sm501 disp ctrl : not implemented register write."
" addr=%x, val=%x\n", (int)addr, value);
- assert(0);
+ abort();
}
}
default:
printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
s->dc_crt_control);
- assert(0);
+ abort();
break;
}
break;
default:
fprintf(stderr, "unknown flash command 0x%02x\n", command);
- assert(0);
+ abort();
}
}
break;
default:
/* Invalid data */
- assert(0);
+ abort();
}
dev->address_cycle++;
break;
default:
- assert(0);
+ abort();
}
}
*periph_pdtra &= 0xff00;
*periph_pdtra |= handle_read(&tc58128_devs[dev]);
} else {
- assert(0);
+ abort();
}
return 1;
}
sigsuspend(&act.sa_mask);
/* unreachable */
- assert(0);
abort();
}
case QTYPE_QINT:
return qint_get_int(qobject_to_qint(obj));
default:
- assert(0);
- return 0.0;
+ abort();
}
}
break;
case EXCP_BUSFAULT:
- assert(0);
+ cpu_abort(env, "Unhandled busfault");
break;
default:
default:
LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
- assert(0);
+ cpu_abort(dc->env, "Unhandled quickimm\n");
break;
}
return 2;
case 4: tmp = 2; break;
case 2: tmp = 1; break;
case 1: tmp = 0; break;
- default: assert(0); break;
+ default:
+ cpu_abort(dc->env, "Unhandled BIAP");
+ break;
}
t = tcg_temp_new();
default:
LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
dc->opcode, dc->src, dc->dst);
- assert(0);
+ cpu_abort(dc->env, "Unhandled opcode");
break;
}
} else {
default:
LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
dc->opcode, dc->src, dc->dst);
- assert(0);
+ cpu_abort(dc->env, "Unhandled opcode");
break;
}
}
if (!dc->postinc && (dc->ir & (1 << 11))) {
int simm = dc->ir & 0xff;
- // assert(0);
+ /* cpu_abort(dc->env, "Unhandled opcode"); */
/* sign extended. */
simm = (int8_t)simm;
default:
LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
dc->pc, size, dc->opcode, dc->src, dc->dst);
- assert(0);
+ cpu_abort(dc->env, "Unhandled opcode");
break;
}
return insn_len;
break;
default:
LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
- assert(0);
+ cpu_abort(dc->env, "Unhandled opcode");
break;
}
file describes the current state of implementation.
Most places requiring attention and/or modification can be detected by
-looking for "XXXXX" or "assert (0)".
+looking for "XXXXX" or "abort()".
The sh4 core is located in target-sh4/*, while the 7750 peripheral
features (IO ports for example) are located in hw/sh7750.[ch]. The
return 2;
if ((env->mmucr & 0x2c000000) == 0x00000000)
return 3;
- assert(0);
+ cpu_abort(env, "Unhandled itlb_replacement");
}
/* Find the corresponding entry in the right TLB
env->exception_index = 0x100;
break;
default:
- assert(0);
+ cpu_abort(env, "Unhandled MMU fault");
}
return 1;
}
entry->size = 1024 * 1024; /* 1M */
break;
default:
- assert(0);
+ cpu_abort(env, "Unhandled load_tlb");
break;
}
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
{
#ifdef CONFIG_USER_ONLY
/* XXXXX */
- assert(0);
+ cpu_abort(env, "Unhandled ldtlb");
#else
cpu_load_tlb(env);
#endif