target/arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "target/arm/idau.h"
  23 #include "qemu/error-report.h"
  24 #include "qapi/error.h"
  25 #include "cpu.h"
  26 #include "internals.h"
  27 #include "qemu-common.h"
  28 #include "exec/exec-all.h"
  29 #include "hw/qdev-properties.h"
  30 #if !defined(CONFIG_USER_ONLY)
  31 #include "hw/loader.h"
  32 #endif
  33 #include "hw/arm/arm.h"
  34 #include "sysemu/sysemu.h"
  35 #include "sysemu/hw_accel.h"
  36 #include "kvm_arm.h"
  37 #include "disas/capstone.h"
  38 #include "fpu/softfloat.h"
  39
  40 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  41 {
  42     ARMCPU *cpu = ARM_CPU(cs);
  43
  44     cpu->env.regs[15] = value;
  45 }
  46
  47 static bool arm_cpu_has_work(CPUState *cs)
  48 {
  49     ARMCPU *cpu = ARM_CPU(cs);
  50
  51     return (cpu->power_state != PSCI_OFF)
  52         && cs->interrupt_request &
  53         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  54          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  55          | CPU_INTERRUPT_EXITTB);
  56 }
  57
  58 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
  59                                  void *opaque)
  60 {
  61     ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
  62
  63     entry->hook = hook;
  64     entry->opaque = opaque;
  65
  66     QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
  67 }
  68
  69 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
  70                                  void *opaque)
  71 {
  72     ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
  73
  74     entry->hook = hook;
  75     entry->opaque = opaque;
  76
  77     QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
  78 }
  79
  80 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  81 {
  82     /* Reset a single ARMCPRegInfo register */
  83     ARMCPRegInfo *ri = value;
  84     ARMCPU *cpu = opaque;
  85
  86     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
  87         return;
  88     }
  89
  90     if (ri->resetfn) {
  91         ri->resetfn(&cpu->env, ri);
  92         return;
  93     }
  94
  95     /* A zero offset is never possible as it would be regs[0]
  96      * so we use it to indicate that reset is being handled elsewhere.
  97      * This is basically only used for fields in non-core coprocessors
  98      * (like the pxa2xx ones).
  99      */
 100     if (!ri->fieldoffset) {
 101         return;
 102     }
 103
 104     if (cpreg_field_is_64bit(ri)) {
 105         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
 106     } else {
 107         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
 108     }
 109 }
 110
 111 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
 112 {
 113     /* Purely an assertion check: we've already done reset once,
 114      * so now check that running the reset for the cpreg doesn't
 115      * change its value. This traps bugs where two different cpregs
 116      * both try to reset the same state field but to different values.
 117      */
 118     ARMCPRegInfo *ri = value;
 119     ARMCPU *cpu = opaque;
 120     uint64_t oldvalue, newvalue;
 121
 122     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
 123         return;
 124     }
 125
 126     oldvalue = read_raw_cp_reg(&cpu->env, ri);
 127     cp_reg_reset(key, value, opaque);
 128     newvalue = read_raw_cp_reg(&cpu->env, ri);
 129     assert(oldvalue == newvalue);
 130 }
 131
 132 /* CPUClass::reset() */
 133 static void arm_cpu_reset(CPUState *s)
 134 {
 135     ARMCPU *cpu = ARM_CPU(s);
 136     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 137     CPUARMState *env = &cpu->env;
 138
 139     acc->parent_reset(s);
 140
 141     memset(env, 0, offsetof(CPUARMState, end_reset_fields));
 142
 143     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
 144     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 145
 146     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
 147     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
 148     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
 149     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
 150
 151     cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
 152     s->halted = cpu->start_powered_off;
 153
 154     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 155         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 156     }
 157
 158     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 159         /* 64 bit CPUs always start in 64 bit mode */
 160         env->aarch64 = 1;
 161 #if defined(CONFIG_USER_ONLY)
 162         env->pstate = PSTATE_MODE_EL0t;
 163         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 164         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 165         /* and to the FP/Neon instructions */
 166         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 167         /* and to the SVE instructions */
 168         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
 169         env->cp15.cptr_el[3] |= CPTR_EZ;
 170         /* with maximum vector length */
 171         env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
 172         env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
 173         env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
 174 #else
 175         /* Reset into the highest available EL */
 176         if (arm_feature(env, ARM_FEATURE_EL3)) {
 177             env->pstate = PSTATE_MODE_EL3h;
 178         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 179             env->pstate = PSTATE_MODE_EL2h;
 180         } else {
 181             env->pstate = PSTATE_MODE_EL1h;
 182         }
 183         env->pc = cpu->rvbar;
 184 #endif
 185     } else {
 186 #if defined(CONFIG_USER_ONLY)
 187         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 188         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 189 #endif
 190     }
 191
 192 #if defined(CONFIG_USER_ONLY)
 193     env->uncached_cpsr = ARM_CPU_MODE_USR;
 194     /* For user mode we must enable access to coprocessors */
 195     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 196     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 197         env->cp15.c15_cpar = 3;
 198     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 199         env->cp15.c15_cpar = 1;
 200     }
 201 #else
 202
 203     /*
 204      * If the highest available EL is EL2, AArch32 will start in Hyp
 205      * mode; otherwise it starts in SVC. Note that if we start in
 206      * AArch64 then these values in the uncached_cpsr will be ignored.
 207      */
 208     if (arm_feature(env, ARM_FEATURE_EL2) &&
 209         !arm_feature(env, ARM_FEATURE_EL3)) {
 210         env->uncached_cpsr = ARM_CPU_MODE_HYP;
 211     } else {
 212         env->uncached_cpsr = ARM_CPU_MODE_SVC;
 213     }
 214     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 215
 216     if (arm_feature(env, ARM_FEATURE_M)) {
 217         uint32_t initial_msp; /* Loaded from 0x0 */
 218         uint32_t initial_pc; /* Loaded from 0x4 */
 219         uint8_t *rom;
 220         uint32_t vecbase;
 221
 222         if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 223             env->v7m.secure = true;
 224         } else {
 225             /* This bit resets to 0 if security is supported, but 1 if
 226              * it is not. The bit is not present in v7M, but we set it
 227              * here so we can avoid having to make checks on it conditional
 228              * on ARM_FEATURE_V8 (we don't let the guest see the bit).
 229              */
 230             env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
 231         }
 232
 233         /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
 234          * that it resets to 1, so QEMU always does that rather than making
 235          * it dependent on CPU model. In v8M it is RES1.
 236          */
 237         env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
 238         env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
 239         if (arm_feature(env, ARM_FEATURE_V8)) {
 240             /* in v8M the NONBASETHRDENA bit [0] is RES1 */
 241             env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
 242             env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
 243         }
 244         if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
 245             env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
 246             env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
 247         }
 248
 249         /* Unlike A/R profile, M profile defines the reset LR value */
 250         env->regs[14] = 0xffffffff;
 251
 252         env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
 253
 254         /* Load the initial SP and PC from offset 0 and 4 in the vector table */
 255         vecbase = env->v7m.vecbase[env->v7m.secure];
 256         rom = rom_ptr(vecbase, 8);
 257         if (rom) {
 258             /* Address zero is covered by ROM which hasn't yet been
 259              * copied into physical memory.
 260              */
 261             initial_msp = ldl_p(rom);
 262             initial_pc = ldl_p(rom + 4);
 263         } else {
 264             /* Address zero not covered by a ROM blob, or the ROM blob
 265              * is in non-modifiable memory and this is a second reset after
 266              * it got copied into memory. In the latter case, rom_ptr
 267              * will return a NULL pointer and we should use ldl_phys instead.
 268              */
 269             initial_msp = ldl_phys(s->as, vecbase);
 270             initial_pc = ldl_phys(s->as, vecbase + 4);
 271         }
 272
 273         env->regs[13] = initial_msp & 0xFFFFFFFC;
 274         env->regs[15] = initial_pc & ~1;
 275         env->thumb = initial_pc & 1;
 276     }
 277
 278     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 279      * executing as AArch32 then check if highvecs are enabled and
 280      * adjust the PC accordingly.
 281      */
 282     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 283         env->regs[15] = 0xFFFF0000;
 284     }
 285
 286     /* M profile requires that reset clears the exclusive monitor;
 287      * A profile does not, but clearing it makes more sense than having it
 288      * set with an exclusive access on address zero.
 289      */
 290     arm_clear_exclusive(env);
 291
 292     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 293 #endif
 294
 295     if (arm_feature(env, ARM_FEATURE_PMSA)) {
 296         if (cpu->pmsav7_dregion > 0) {
 297             if (arm_feature(env, ARM_FEATURE_V8)) {
 298                 memset(env->pmsav8.rbar[M_REG_NS], 0,
 299                        sizeof(*env->pmsav8.rbar[M_REG_NS])
 300                        * cpu->pmsav7_dregion);
 301                 memset(env->pmsav8.rlar[M_REG_NS], 0,
 302                        sizeof(*env->pmsav8.rlar[M_REG_NS])
 303                        * cpu->pmsav7_dregion);
 304                 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 305                     memset(env->pmsav8.rbar[M_REG_S], 0,
 306                            sizeof(*env->pmsav8.rbar[M_REG_S])
 307                            * cpu->pmsav7_dregion);
 308                     memset(env->pmsav8.rlar[M_REG_S], 0,
 309                            sizeof(*env->pmsav8.rlar[M_REG_S])
 310                            * cpu->pmsav7_dregion);
 311                 }
 312             } else if (arm_feature(env, ARM_FEATURE_V7)) {
 313                 memset(env->pmsav7.drbar, 0,
 314                        sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
 315                 memset(env->pmsav7.drsr, 0,
 316                        sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
 317                 memset(env->pmsav7.dracr, 0,
 318                        sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
 319             }
 320         }
 321         env->pmsav7.rnr[M_REG_NS] = 0;
 322         env->pmsav7.rnr[M_REG_S] = 0;
 323         env->pmsav8.mair0[M_REG_NS] = 0;
 324         env->pmsav8.mair0[M_REG_S] = 0;
 325         env->pmsav8.mair1[M_REG_NS] = 0;
 326         env->pmsav8.mair1[M_REG_S] = 0;
 327     }
 328
 329     if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 330         if (cpu->sau_sregion > 0) {
 331             memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
 332             memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
 333         }
 334         env->sau.rnr = 0;
 335         /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
 336          * the Cortex-M33 does.
 337          */
 338         env->sau.ctrl = 0;
 339     }
 340
 341     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 342     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 343     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 344     set_float_detect_tininess(float_tininess_before_rounding,
 345                               &env->vfp.fp_status);
 346     set_float_detect_tininess(float_tininess_before_rounding,
 347                               &env->vfp.standard_fp_status);
 348     set_float_detect_tininess(float_tininess_before_rounding,
 349                               &env->vfp.fp_status_f16);
 350 #ifndef CONFIG_USER_ONLY
 351     if (kvm_enabled()) {
 352         kvm_arm_reset_vcpu(cpu);
 353     }
 354 #endif
 355
 356     hw_breakpoint_update_all(cpu);
 357     hw_watchpoint_update_all(cpu);
 358 }
 359
 360 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 361 {
 362     CPUClass *cc = CPU_GET_CLASS(cs);
 363     CPUARMState *env = cs->env_ptr;
 364     uint32_t cur_el = arm_current_el(env);
 365     bool secure = arm_is_secure(env);
 366     uint32_t target_el;
 367     uint32_t excp_idx;
 368     bool ret = false;
 369
 370     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 371         excp_idx = EXCP_FIQ;
 372         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 373         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 374             cs->exception_index = excp_idx;
 375             env->exception.target_el = target_el;
 376             cc->do_interrupt(cs);
 377             ret = true;
 378         }
 379     }
 380     if (interrupt_request & CPU_INTERRUPT_HARD) {
 381         excp_idx = EXCP_IRQ;
 382         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 383         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 384             cs->exception_index = excp_idx;
 385             env->exception.target_el = target_el;
 386             cc->do_interrupt(cs);
 387             ret = true;
 388         }
 389     }
 390     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 391         excp_idx = EXCP_VIRQ;
 392         target_el = 1;
 393         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 394             cs->exception_index = excp_idx;
 395             env->exception.target_el = target_el;
 396             cc->do_interrupt(cs);
 397             ret = true;
 398         }
 399     }
 400     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 401         excp_idx = EXCP_VFIQ;
 402         target_el = 1;
 403         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 404             cs->exception_index = excp_idx;
 405             env->exception.target_el = target_el;
 406             cc->do_interrupt(cs);
 407             ret = true;
 408         }
 409     }
 410
 411     return ret;
 412 }
 413
 414 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 415 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 416 {
 417     CPUClass *cc = CPU_GET_CLASS(cs);
 418     ARMCPU *cpu = ARM_CPU(cs);
 419     CPUARMState *env = &cpu->env;
 420     bool ret = false;
 421
 422     /* ARMv7-M interrupt masking works differently than -A or -R.
 423      * There is no FIQ/IRQ distinction. Instead of I and F bits
 424      * masking FIQ and IRQ interrupts, an exception is taken only
 425      * if it is higher priority than the current execution priority
 426      * (which depends on state like BASEPRI, FAULTMASK and the
 427      * currently active exception).
 428      */
 429     if (interrupt_request & CPU_INTERRUPT_HARD
 430         && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
 431         cs->exception_index = EXCP_IRQ;
 432         cc->do_interrupt(cs);
 433         ret = true;
 434     }
 435     return ret;
 436 }
 437 #endif
 438
 439 #ifndef CONFIG_USER_ONLY
 440 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 441 {
 442     ARMCPU *cpu = opaque;
 443     CPUARMState *env = &cpu->env;
 444     CPUState *cs = CPU(cpu);
 445     static const int mask[] = {
 446         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 447         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 448         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 449         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 450     };
 451
 452     if (level) {
 453         env->irq_line_state |= mask[irq];
 454     } else {
 455         env->irq_line_state &= ~mask[irq];
 456     }
 457
 458     switch (irq) {
 459     case ARM_CPU_VIRQ:
 460     case ARM_CPU_VFIQ:
 461         assert(arm_feature(env, ARM_FEATURE_EL2));
 462         /* fall through */
 463     case ARM_CPU_IRQ:
 464     case ARM_CPU_FIQ:
 465         if (level) {
 466             cpu_interrupt(cs, mask[irq]);
 467         } else {
 468             cpu_reset_interrupt(cs, mask[irq]);
 469         }
 470         break;
 471     default:
 472         g_assert_not_reached();
 473     }
 474 }
 475
 476 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 477 {
 478 #ifdef CONFIG_KVM
 479     ARMCPU *cpu = opaque;
 480     CPUARMState *env = &cpu->env;
 481     CPUState *cs = CPU(cpu);
 482     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 483     uint32_t linestate_bit;
 484
 485     switch (irq) {
 486     case ARM_CPU_IRQ:
 487         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 488         linestate_bit = CPU_INTERRUPT_HARD;
 489         break;
 490     case ARM_CPU_FIQ:
 491         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 492         linestate_bit = CPU_INTERRUPT_FIQ;
 493         break;
 494     default:
 495         g_assert_not_reached();
 496     }
 497
 498     if (level) {
 499         env->irq_line_state |= linestate_bit;
 500     } else {
 501         env->irq_line_state &= ~linestate_bit;
 502     }
 503
 504     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 505     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 506 #endif
 507 }
 508
 509 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
 510 {
 511     ARMCPU *cpu = ARM_CPU(cs);
 512     CPUARMState *env = &cpu->env;
 513
 514     cpu_synchronize_state(cs);
 515     return arm_cpu_data_is_big_endian(env);
 516 }
 517
 518 #endif
 519
 520 static inline void set_feature(CPUARMState *env, int feature)
 521 {
 522     env->features |= 1ULL << feature;
 523 }
 524
 525 static inline void unset_feature(CPUARMState *env, int feature)
 526 {
 527     env->features &= ~(1ULL << feature);
 528 }
 529
 530 static int
 531 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 532 {
 533   return print_insn_arm(pc | 1, info);
 534 }
 535
 536 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 537 {
 538     ARMCPU *ac = ARM_CPU(cpu);
 539     CPUARMState *env = &ac->env;
 540     bool sctlr_b;
 541
 542     if (is_a64(env)) {
 543         /* We might not be compiled with the A64 disassembler
 544          * because it needs a C++ compiler. Leave print_insn
 545          * unset in this case to use the caller default behaviour.
 546          */
 547 #if defined(CONFIG_ARM_A64_DIS)
 548         info->print_insn = print_insn_arm_a64;
 549 #endif
 550         info->cap_arch = CS_ARCH_ARM64;
 551         info->cap_insn_unit = 4;
 552         info->cap_insn_split = 4;
 553     } else {
 554         int cap_mode;
 555         if (env->thumb) {
 556             info->print_insn = print_insn_thumb1;
 557             info->cap_insn_unit = 2;
 558             info->cap_insn_split = 4;
 559             cap_mode = CS_MODE_THUMB;
 560         } else {
 561             info->print_insn = print_insn_arm;
 562             info->cap_insn_unit = 4;
 563             info->cap_insn_split = 4;
 564             cap_mode = CS_MODE_ARM;
 565         }
 566         if (arm_feature(env, ARM_FEATURE_V8)) {
 567             cap_mode |= CS_MODE_V8;
 568         }
 569         if (arm_feature(env, ARM_FEATURE_M)) {
 570             cap_mode |= CS_MODE_MCLASS;
 571         }
 572         info->cap_arch = CS_ARCH_ARM;
 573         info->cap_mode = cap_mode;
 574     }
 575
 576     sctlr_b = arm_sctlr_b(env);
 577     if (bswap_code(sctlr_b)) {
 578 #ifdef TARGET_WORDS_BIGENDIAN
 579         info->endian = BFD_ENDIAN_LITTLE;
 580 #else
 581         info->endian = BFD_ENDIAN_BIG;
 582 #endif
 583     }
 584     info->flags &= ~INSN_ARM_BE32;
 585 #ifndef CONFIG_USER_ONLY
 586     if (sctlr_b) {
 587         info->flags |= INSN_ARM_BE32;
 588     }
 589 #endif
 590 }
 591
 592 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
 593 {
 594     uint32_t Aff1 = idx / clustersz;
 595     uint32_t Aff0 = idx % clustersz;
 596     return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 597 }
 598
 599 static void arm_cpu_initfn(Object *obj)
 600 {
 601     CPUState *cs = CPU(obj);
 602     ARMCPU *cpu = ARM_CPU(obj);
 603
 604     cs->env_ptr = &cpu->env;
 605     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 606                                          g_free, g_free);
 607
 608     QLIST_INIT(&cpu->pre_el_change_hooks);
 609     QLIST_INIT(&cpu->el_change_hooks);
 610
 611 #ifndef CONFIG_USER_ONLY
 612     /* Our inbound IRQ and FIQ lines */
 613     if (kvm_enabled()) {
 614         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 615          * the same interface as non-KVM CPUs.
 616          */
 617         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 618     } else {
 619         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 620     }
 621
 622     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 623                                                 arm_gt_ptimer_cb, cpu);
 624     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 625                                                 arm_gt_vtimer_cb, cpu);
 626     cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 627                                                 arm_gt_htimer_cb, cpu);
 628     cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 629                                                 arm_gt_stimer_cb, cpu);
 630     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 631                        ARRAY_SIZE(cpu->gt_timer_outputs));
 632
 633     qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
 634                              "gicv3-maintenance-interrupt", 1);
 635     qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
 636                              "pmu-interrupt", 1);
 637 #endif
 638
 639     /* DTB consumers generally don't in fact care what the 'compatible'
 640      * string is, so always provide some string and trust that a hypothetical
 641      * picky DTB consumer will also provide a helpful error message.
 642      */
 643     cpu->dtb_compatible = "qemu,unknown";
 644     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 645     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 646
 647     if (tcg_enabled()) {
 648         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 649     }
 650 }
 651
 652 static Property arm_cpu_reset_cbar_property =
 653             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 654
 655 static Property arm_cpu_reset_hivecs_property =
 656             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 657
 658 static Property arm_cpu_rvbar_property =
 659             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 660
 661 static Property arm_cpu_has_el2_property =
 662             DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
 663
 664 static Property arm_cpu_has_el3_property =
 665             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 666
 667 static Property arm_cpu_cfgend_property =
 668             DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
 669
 670 /* use property name "pmu" to match other archs and virt tools */
 671 static Property arm_cpu_has_pmu_property =
 672             DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
 673
 674 static Property arm_cpu_has_mpu_property =
 675             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 676
 677 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
 678  * because the CPU initfn will have already set cpu->pmsav7_dregion to
 679  * the right value for that particular CPU type, and we don't want
 680  * to override that with an incorrect constant value.
 681  */
 682 static Property arm_cpu_pmsav7_dregion_property =
 683             DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
 684                                            pmsav7_dregion,
 685                                            qdev_prop_uint32, uint32_t);
 686
 687 /* M profile: initial value of the Secure VTOR */
 688 static Property arm_cpu_initsvtor_property =
 689             DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
 690
 691 static void arm_cpu_post_init(Object *obj)
 692 {
 693     ARMCPU *cpu = ARM_CPU(obj);
 694
 695     /* M profile implies PMSA. We have to do this here rather than
 696      * in realize with the other feature-implication checks because
 697      * we look at the PMSA bit to see if we should add some properties.
 698      */
 699     if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
 700         set_feature(&cpu->env, ARM_FEATURE_PMSA);
 701     }
 702
 703     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 704         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 705         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 706                                  &error_abort);
 707     }
 708
 709     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 710         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 711                                  &error_abort);
 712     }
 713
 714     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 715         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 716                                  &error_abort);
 717     }
 718
 719     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 720         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 721          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 722          */
 723         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 724                                  &error_abort);
 725
 726 #ifndef CONFIG_USER_ONLY
 727         object_property_add_link(obj, "secure-memory",
 728                                  TYPE_MEMORY_REGION,
 729                                  (Object **)&cpu->secure_memory,
 730                                  qdev_prop_allow_set_link_before_realize,
 731                                  OBJ_PROP_LINK_STRONG,
 732                                  &error_abort);
 733 #endif
 734     }
 735
 736     if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
 737         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
 738                                  &error_abort);
 739     }
 740
 741     if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
 742         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
 743                                  &error_abort);
 744     }
 745
 746     if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
 747         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 748                                  &error_abort);
 749         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 750             qdev_property_add_static(DEVICE(obj),
 751                                      &arm_cpu_pmsav7_dregion_property,
 752                                      &error_abort);
 753         }
 754     }
 755
 756     if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
 757         object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
 758                                  qdev_prop_allow_set_link_before_realize,
 759                                  OBJ_PROP_LINK_STRONG,
 760                                  &error_abort);
 761         qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property,
 762                                  &error_abort);
 763     }
 764
 765     qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
 766                              &error_abort);
 767 }
 768
 769 static void arm_cpu_finalizefn(Object *obj)
 770 {
 771     ARMCPU *cpu = ARM_CPU(obj);
 772     ARMELChangeHook *hook, *next;
 773
 774     g_hash_table_destroy(cpu->cp_regs);
 775
 776     QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
 777         QLIST_REMOVE(hook, node);
 778         g_free(hook);
 779     }
 780     QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
 781         QLIST_REMOVE(hook, node);
 782         g_free(hook);
 783     }
 784 }
 785
 786 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 787 {
 788     CPUState *cs = CPU(dev);
 789     ARMCPU *cpu = ARM_CPU(dev);
 790     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 791     CPUARMState *env = &cpu->env;
 792     int pagebits;
 793     Error *local_err = NULL;
 794     bool no_aa32 = false;
 795
 796     /* If we needed to query the host kernel for the CPU features
 797      * then it's possible that might have failed in the initfn, but
 798      * this is the first point where we can report it.
 799      */
 800     if (cpu->host_cpu_probe_failed) {
 801         if (!kvm_enabled()) {
 802             error_setg(errp, "The 'host' CPU type can only be used with KVM");
 803         } else {
 804             error_setg(errp, "Failed to retrieve host CPU features");
 805         }
 806         return;
 807     }
 808
 809 #ifndef CONFIG_USER_ONLY
 810     /* The NVIC and M-profile CPU are two halves of a single piece of
 811      * hardware; trying to use one without the other is a command line
 812      * error and will result in segfaults if not caught here.
 813      */
 814     if (arm_feature(env, ARM_FEATURE_M)) {
 815         if (!env->nvic) {
 816             error_setg(errp, "This board cannot be used with Cortex-M CPUs");
 817             return;
 818         }
 819     } else {
 820         if (env->nvic) {
 821             error_setg(errp, "This board can only be used with Cortex-M CPUs");
 822             return;
 823         }
 824     }
 825 #endif
 826
 827     cpu_exec_realizefn(cs, &local_err);
 828     if (local_err != NULL) {
 829         error_propagate(errp, local_err);
 830         return;
 831     }
 832
 833     /* Some features automatically imply others: */
 834     if (arm_feature(env, ARM_FEATURE_V8)) {
 835         if (arm_feature(env, ARM_FEATURE_M)) {
 836             set_feature(env, ARM_FEATURE_V7);
 837         } else {
 838             set_feature(env, ARM_FEATURE_V7VE);
 839         }
 840     }
 841
 842     /*
 843      * There exist AArch64 cpus without AArch32 support.  When KVM
 844      * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
 845      * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
 846      */
 847     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 848         no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
 849     }
 850
 851     if (arm_feature(env, ARM_FEATURE_V7VE)) {
 852         /* v7 Virtualization Extensions. In real hardware this implies
 853          * EL2 and also the presence of the Security Extensions.
 854          * For QEMU, for backwards-compatibility we implement some
 855          * CPUs or CPU configs which have no actual EL2 or EL3 but do
 856          * include the various other features that V7VE implies.
 857          * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
 858          * Security Extensions is ARM_FEATURE_EL3.
 859          */
 860         assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
 861         set_feature(env, ARM_FEATURE_LPAE);
 862         set_feature(env, ARM_FEATURE_V7);
 863     }
 864     if (arm_feature(env, ARM_FEATURE_V7)) {
 865         set_feature(env, ARM_FEATURE_VAPA);
 866         set_feature(env, ARM_FEATURE_THUMB2);
 867         set_feature(env, ARM_FEATURE_MPIDR);
 868         if (!arm_feature(env, ARM_FEATURE_M)) {
 869             set_feature(env, ARM_FEATURE_V6K);
 870         } else {
 871             set_feature(env, ARM_FEATURE_V6);
 872         }
 873
 874         /* Always define VBAR for V7 CPUs even if it doesn't exist in
 875          * non-EL3 configs. This is needed by some legacy boards.
 876          */
 877         set_feature(env, ARM_FEATURE_VBAR);
 878     }
 879     if (arm_feature(env, ARM_FEATURE_V6K)) {
 880         set_feature(env, ARM_FEATURE_V6);
 881         set_feature(env, ARM_FEATURE_MVFR);
 882     }
 883     if (arm_feature(env, ARM_FEATURE_V6)) {
 884         set_feature(env, ARM_FEATURE_V5);
 885         if (!arm_feature(env, ARM_FEATURE_M)) {
 886             assert(no_aa32 || cpu_isar_feature(jazelle, cpu));
 887             set_feature(env, ARM_FEATURE_AUXCR);
 888         }
 889     }
 890     if (arm_feature(env, ARM_FEATURE_V5)) {
 891         set_feature(env, ARM_FEATURE_V4T);
 892     }
 893     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 894         set_feature(env, ARM_FEATURE_VFP3);
 895         set_feature(env, ARM_FEATURE_VFP_FP16);
 896     }
 897     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 898         set_feature(env, ARM_FEATURE_VFP);
 899     }
 900     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 901         set_feature(env, ARM_FEATURE_V7MP);
 902         set_feature(env, ARM_FEATURE_PXN);
 903     }
 904     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 905         set_feature(env, ARM_FEATURE_CBAR);
 906     }
 907     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 908         !arm_feature(env, ARM_FEATURE_M)) {
 909         set_feature(env, ARM_FEATURE_THUMB_DSP);
 910     }
 911
 912     if (arm_feature(env, ARM_FEATURE_V7) &&
 913         !arm_feature(env, ARM_FEATURE_M) &&
 914         !arm_feature(env, ARM_FEATURE_PMSA)) {
 915         /* v7VMSA drops support for the old ARMv5 tiny pages, so we
 916          * can use 4K pages.
 917          */
 918         pagebits = 12;
 919     } else {
 920         /* For CPUs which might have tiny 1K pages, or which have an
 921          * MPU and might have small region sizes, stick with 1K pages.
 922          */
 923         pagebits = 10;
 924     }
 925     if (!set_preferred_target_page_bits(pagebits)) {
 926         /* This can only ever happen for hotplugging a CPU, or if
 927          * the board code incorrectly creates a CPU which it has
 928          * promised via minimum_page_size that it will not.
 929          */
 930         error_setg(errp, "This CPU requires a smaller page size than the "
 931                    "system is using");
 932         return;
 933     }
 934
 935     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
 936      * We don't support setting cluster ID ([16..23]) (known as Aff2
 937      * in later ARM ARM versions), or any of the higher affinity level fields,
 938      * so these bits always RAZ.
 939      */
 940     if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
 941         cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
 942                                                ARM_DEFAULT_CPUS_PER_CLUSTER);
 943     }
 944
 945     if (cpu->reset_hivecs) {
 946             cpu->reset_sctlr |= (1 << 13);
 947     }
 948
 949     if (cpu->cfgend) {
 950         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 951             cpu->reset_sctlr |= SCTLR_EE;
 952         } else {
 953             cpu->reset_sctlr |= SCTLR_B;
 954         }
 955     }
 956
 957     if (!cpu->has_el3) {
 958         /* If the has_el3 CPU property is disabled then we need to disable the
 959          * feature.
 960          */
 961         unset_feature(env, ARM_FEATURE_EL3);
 962
 963         /* Disable the security extension feature bits in the processor feature
 964          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 965          */
 966         cpu->id_pfr1 &= ~0xf0;
 967         cpu->isar.id_aa64pfr0 &= ~0xf000;
 968     }
 969
 970     if (!cpu->has_el2) {
 971         unset_feature(env, ARM_FEATURE_EL2);
 972     }
 973
 974     if (!cpu->has_pmu) {
 975         unset_feature(env, ARM_FEATURE_PMU);
 976         cpu->id_aa64dfr0 &= ~0xf00;
 977     }
 978
 979     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 980         /* Disable the hypervisor feature bits in the processor feature
 981          * registers if we don't have EL2. These are id_pfr1[15:12] and
 982          * id_aa64pfr0_el1[11:8].
 983          */
 984         cpu->isar.id_aa64pfr0 &= ~0xf00;
 985         cpu->id_pfr1 &= ~0xf000;
 986     }
 987
 988     /* MPU can be configured out of a PMSA CPU either by setting has-mpu
 989      * to false or by setting pmsav7-dregion to 0.
 990      */
 991     if (!cpu->has_mpu) {
 992         cpu->pmsav7_dregion = 0;
 993     }
 994     if (cpu->pmsav7_dregion == 0) {
 995         cpu->has_mpu = false;
 996     }
 997
 998     if (arm_feature(env, ARM_FEATURE_PMSA) &&
 999         arm_feature(env, ARM_FEATURE_V7)) {
1000         uint32_t nr = cpu->pmsav7_dregion;
1001
1002         if (nr > 0xff) {
1003             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
1004             return;
1005         }
1006
1007         if (nr) {
1008             if (arm_feature(env, ARM_FEATURE_V8)) {
1009                 /* PMSAv8 */
1010                 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1011                 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1012                 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1013                     env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1014                     env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1015                 }
1016             } else {
1017                 env->pmsav7.drbar = g_new0(uint32_t, nr);
1018                 env->pmsav7.drsr = g_new0(uint32_t, nr);
1019                 env->pmsav7.dracr = g_new0(uint32_t, nr);
1020             }
1021         }
1022     }
1023
1024     if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1025         uint32_t nr = cpu->sau_sregion;
1026
1027         if (nr > 0xff) {
1028             error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1029             return;
1030         }
1031
1032         if (nr) {
1033             env->sau.rbar = g_new0(uint32_t, nr);
1034             env->sau.rlar = g_new0(uint32_t, nr);
1035         }
1036     }
1037
1038     if (arm_feature(env, ARM_FEATURE_EL3)) {
1039         set_feature(env, ARM_FEATURE_VBAR);
1040     }
1041
1042     register_cp_regs_for_features(cpu);
1043     arm_cpu_register_gdb_regs_for_features(cpu);
1044
1045     init_cpreg_list(cpu);
1046
1047 #ifndef CONFIG_USER_ONLY
1048     if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1049         cs->num_ases = 2;
1050
1051         if (!cpu->secure_memory) {
1052             cpu->secure_memory = cs->memory;
1053         }
1054         cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1055                                cpu->secure_memory);
1056     } else {
1057         cs->num_ases = 1;
1058     }
1059     cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
1060
1061     /* No core_count specified, default to smp_cpus. */
1062     if (cpu->core_count == -1) {
1063         cpu->core_count = smp_cpus;
1064     }
1065 #endif
1066
1067     qemu_init_vcpu(cs);
1068     cpu_reset(cs);
1069
1070     acc->parent_realize(dev, errp);
1071 }
1072
1073 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1074 {
1075     ObjectClass *oc;
1076     char *typename;
1077     char **cpuname;
1078     const char *cpunamestr;
1079
1080     cpuname = g_strsplit(cpu_model, ",", 1);
1081     cpunamestr = cpuname[0];
1082 #ifdef CONFIG_USER_ONLY
1083     /* For backwards compatibility usermode emulation allows "-cpu any",
1084      * which has the same semantics as "-cpu max".
1085      */
1086     if (!strcmp(cpunamestr, "any")) {
1087         cpunamestr = "max";
1088     }
1089 #endif
1090     typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
1091     oc = object_class_by_name(typename);
1092     g_strfreev(cpuname);
1093     g_free(typename);
1094     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1095         object_class_is_abstract(oc)) {
1096         return NULL;
1097     }
1098     return oc;
1099 }
1100
1101 /* CPU models. These are not needed for the AArch64 linux-user build. */
1102 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1103
1104 static void arm926_initfn(Object *obj)
1105 {
1106     ARMCPU *cpu = ARM_CPU(obj);
1107
1108     cpu->dtb_compatible = "arm,arm926";
1109     set_feature(&cpu->env, ARM_FEATURE_V5);
1110     set_feature(&cpu->env, ARM_FEATURE_VFP);
1111     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1112     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1113     cpu->midr = 0x41069265;
1114     cpu->reset_fpsid = 0x41011090;
1115     cpu->ctr = 0x1dd20d2;
1116     cpu->reset_sctlr = 0x00090078;
1117
1118     /*
1119      * ARMv5 does not have the ID_ISAR registers, but we can still
1120      * set the field to indicate Jazelle support within QEMU.
1121      */
1122     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1123 }
1124
1125 static void arm946_initfn(Object *obj)
1126 {
1127     ARMCPU *cpu = ARM_CPU(obj);
1128
1129     cpu->dtb_compatible = "arm,arm946";
1130     set_feature(&cpu->env, ARM_FEATURE_V5);
1131     set_feature(&cpu->env, ARM_FEATURE_PMSA);
1132     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1133     cpu->midr = 0x41059461;
1134     cpu->ctr = 0x0f004006;
1135     cpu->reset_sctlr = 0x00000078;
1136 }
1137
1138 static void arm1026_initfn(Object *obj)
1139 {
1140     ARMCPU *cpu = ARM_CPU(obj);
1141
1142     cpu->dtb_compatible = "arm,arm1026";
1143     set_feature(&cpu->env, ARM_FEATURE_V5);
1144     set_feature(&cpu->env, ARM_FEATURE_VFP);
1145     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
1146     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1147     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1148     cpu->midr = 0x4106a262;
1149     cpu->reset_fpsid = 0x410110a0;
1150     cpu->ctr = 0x1dd20d2;
1151     cpu->reset_sctlr = 0x00090078;
1152     cpu->reset_auxcr = 1;
1153
1154     /*
1155      * ARMv5 does not have the ID_ISAR registers, but we can still
1156      * set the field to indicate Jazelle support within QEMU.
1157      */
1158     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1159
1160     {
1161         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1162         ARMCPRegInfo ifar = {
1163             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1164             .access = PL1_RW,
1165             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
1166             .resetvalue = 0
1167         };
1168         define_one_arm_cp_reg(cpu, &ifar);
1169     }
1170 }
1171
1172 static void arm1136_r2_initfn(Object *obj)
1173 {
1174     ARMCPU *cpu = ARM_CPU(obj);
1175     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1176      * older core than plain "arm1136". In particular this does not
1177      * have the v6K features.
1178      * These ID register values are correct for 1136 but may be wrong
1179      * for 1136_r2 (in particular r0p2 does not actually implement most
1180      * of the ID registers).
1181      */
1182
1183     cpu->dtb_compatible = "arm,arm1136";
1184     set_feature(&cpu->env, ARM_FEATURE_V6);
1185     set_feature(&cpu->env, ARM_FEATURE_VFP);
1186     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1187     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1188     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1189     cpu->midr = 0x4107b362;
1190     cpu->reset_fpsid = 0x410120b4;
1191     cpu->isar.mvfr0 = 0x11111111;
1192     cpu->isar.mvfr1 = 0x00000000;
1193     cpu->ctr = 0x1dd20d2;
1194     cpu->reset_sctlr = 0x00050078;
1195     cpu->id_pfr0 = 0x111;
1196     cpu->id_pfr1 = 0x1;
1197     cpu->id_dfr0 = 0x2;
1198     cpu->id_afr0 = 0x3;
1199     cpu->id_mmfr0 = 0x01130003;
1200     cpu->id_mmfr1 = 0x10030302;
1201     cpu->id_mmfr2 = 0x01222110;
1202     cpu->isar.id_isar0 = 0x00140011;
1203     cpu->isar.id_isar1 = 0x12002111;
1204     cpu->isar.id_isar2 = 0x11231111;
1205     cpu->isar.id_isar3 = 0x01102131;
1206     cpu->isar.id_isar4 = 0x141;
1207     cpu->reset_auxcr = 7;
1208 }
1209
1210 static void arm1136_initfn(Object *obj)
1211 {
1212     ARMCPU *cpu = ARM_CPU(obj);
1213
1214     cpu->dtb_compatible = "arm,arm1136";
1215     set_feature(&cpu->env, ARM_FEATURE_V6K);
1216     set_feature(&cpu->env, ARM_FEATURE_V6);
1217     set_feature(&cpu->env, ARM_FEATURE_VFP);
1218     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1219     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1220     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1221     cpu->midr = 0x4117b363;
1222     cpu->reset_fpsid = 0x410120b4;
1223     cpu->isar.mvfr0 = 0x11111111;
1224     cpu->isar.mvfr1 = 0x00000000;
1225     cpu->ctr = 0x1dd20d2;
1226     cpu->reset_sctlr = 0x00050078;
1227     cpu->id_pfr0 = 0x111;
1228     cpu->id_pfr1 = 0x1;
1229     cpu->id_dfr0 = 0x2;
1230     cpu->id_afr0 = 0x3;
1231     cpu->id_mmfr0 = 0x01130003;
1232     cpu->id_mmfr1 = 0x10030302;
1233     cpu->id_mmfr2 = 0x01222110;
1234     cpu->isar.id_isar0 = 0x00140011;
1235     cpu->isar.id_isar1 = 0x12002111;
1236     cpu->isar.id_isar2 = 0x11231111;
1237     cpu->isar.id_isar3 = 0x01102131;
1238     cpu->isar.id_isar4 = 0x141;
1239     cpu->reset_auxcr = 7;
1240 }
1241
1242 static void arm1176_initfn(Object *obj)
1243 {
1244     ARMCPU *cpu = ARM_CPU(obj);
1245
1246     cpu->dtb_compatible = "arm,arm1176";
1247     set_feature(&cpu->env, ARM_FEATURE_V6K);
1248     set_feature(&cpu->env, ARM_FEATURE_VFP);
1249     set_feature(&cpu->env, ARM_FEATURE_VAPA);
1250     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1251     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1252     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1253     set_feature(&cpu->env, ARM_FEATURE_EL3);
1254     cpu->midr = 0x410fb767;
1255     cpu->reset_fpsid = 0x410120b5;
1256     cpu->isar.mvfr0 = 0x11111111;
1257     cpu->isar.mvfr1 = 0x00000000;
1258     cpu->ctr = 0x1dd20d2;
1259     cpu->reset_sctlr = 0x00050078;
1260     cpu->id_pfr0 = 0x111;
1261     cpu->id_pfr1 = 0x11;
1262     cpu->id_dfr0 = 0x33;
1263     cpu->id_afr0 = 0;
1264     cpu->id_mmfr0 = 0x01130003;
1265     cpu->id_mmfr1 = 0x10030302;
1266     cpu->id_mmfr2 = 0x01222100;
1267     cpu->isar.id_isar0 = 0x0140011;
1268     cpu->isar.id_isar1 = 0x12002111;
1269     cpu->isar.id_isar2 = 0x11231121;
1270     cpu->isar.id_isar3 = 0x01102131;
1271     cpu->isar.id_isar4 = 0x01141;
1272     cpu->reset_auxcr = 7;
1273 }
1274
1275 static void arm11mpcore_initfn(Object *obj)
1276 {
1277     ARMCPU *cpu = ARM_CPU(obj);
1278
1279     cpu->dtb_compatible = "arm,arm11mpcore";
1280     set_feature(&cpu->env, ARM_FEATURE_V6K);
1281     set_feature(&cpu->env, ARM_FEATURE_VFP);
1282     set_feature(&cpu->env, ARM_FEATURE_VAPA);
1283     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
1284     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1285     cpu->midr = 0x410fb022;
1286     cpu->reset_fpsid = 0x410120b4;
1287     cpu->isar.mvfr0 = 0x11111111;
1288     cpu->isar.mvfr1 = 0x00000000;
1289     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
1290     cpu->id_pfr0 = 0x111;
1291     cpu->id_pfr1 = 0x1;
1292     cpu->id_dfr0 = 0;
1293     cpu->id_afr0 = 0x2;
1294     cpu->id_mmfr0 = 0x01100103;
1295     cpu->id_mmfr1 = 0x10020302;
1296     cpu->id_mmfr2 = 0x01222000;
1297     cpu->isar.id_isar0 = 0x00100011;
1298     cpu->isar.id_isar1 = 0x12002111;
1299     cpu->isar.id_isar2 = 0x11221011;
1300     cpu->isar.id_isar3 = 0x01102131;
1301     cpu->isar.id_isar4 = 0x141;
1302     cpu->reset_auxcr = 1;
1303 }
1304
1305 static void cortex_m0_initfn(Object *obj)
1306 {
1307     ARMCPU *cpu = ARM_CPU(obj);
1308     set_feature(&cpu->env, ARM_FEATURE_V6);
1309     set_feature(&cpu->env, ARM_FEATURE_M);
1310
1311     cpu->midr = 0x410cc200;
1312 }
1313
1314 static void cortex_m3_initfn(Object *obj)
1315 {
1316     ARMCPU *cpu = ARM_CPU(obj);
1317     set_feature(&cpu->env, ARM_FEATURE_V7);
1318     set_feature(&cpu->env, ARM_FEATURE_M);
1319     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1320     cpu->midr = 0x410fc231;
1321     cpu->pmsav7_dregion = 8;
1322     cpu->id_pfr0 = 0x00000030;
1323     cpu->id_pfr1 = 0x00000200;
1324     cpu->id_dfr0 = 0x00100000;
1325     cpu->id_afr0 = 0x00000000;
1326     cpu->id_mmfr0 = 0x00000030;
1327     cpu->id_mmfr1 = 0x00000000;
1328     cpu->id_mmfr2 = 0x00000000;
1329     cpu->id_mmfr3 = 0x00000000;
1330     cpu->isar.id_isar0 = 0x01141110;
1331     cpu->isar.id_isar1 = 0x02111000;
1332     cpu->isar.id_isar2 = 0x21112231;
1333     cpu->isar.id_isar3 = 0x01111110;
1334     cpu->isar.id_isar4 = 0x01310102;
1335     cpu->isar.id_isar5 = 0x00000000;
1336     cpu->isar.id_isar6 = 0x00000000;
1337 }
1338
1339 static void cortex_m4_initfn(Object *obj)
1340 {
1341     ARMCPU *cpu = ARM_CPU(obj);
1342
1343     set_feature(&cpu->env, ARM_FEATURE_V7);
1344     set_feature(&cpu->env, ARM_FEATURE_M);
1345     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1346     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1347     cpu->midr = 0x410fc240; /* r0p0 */
1348     cpu->pmsav7_dregion = 8;
1349     cpu->id_pfr0 = 0x00000030;
1350     cpu->id_pfr1 = 0x00000200;
1351     cpu->id_dfr0 = 0x00100000;
1352     cpu->id_afr0 = 0x00000000;
1353     cpu->id_mmfr0 = 0x00000030;
1354     cpu->id_mmfr1 = 0x00000000;
1355     cpu->id_mmfr2 = 0x00000000;
1356     cpu->id_mmfr3 = 0x00000000;
1357     cpu->isar.id_isar0 = 0x01141110;
1358     cpu->isar.id_isar1 = 0x02111000;
1359     cpu->isar.id_isar2 = 0x21112231;
1360     cpu->isar.id_isar3 = 0x01111110;
1361     cpu->isar.id_isar4 = 0x01310102;
1362     cpu->isar.id_isar5 = 0x00000000;
1363     cpu->isar.id_isar6 = 0x00000000;
1364 }
1365
1366 static void cortex_m33_initfn(Object *obj)
1367 {
1368     ARMCPU *cpu = ARM_CPU(obj);
1369
1370     set_feature(&cpu->env, ARM_FEATURE_V8);
1371     set_feature(&cpu->env, ARM_FEATURE_M);
1372     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1373     set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1374     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1375     cpu->midr = 0x410fd213; /* r0p3 */
1376     cpu->pmsav7_dregion = 16;
1377     cpu->sau_sregion = 8;
1378     cpu->id_pfr0 = 0x00000030;
1379     cpu->id_pfr1 = 0x00000210;
1380     cpu->id_dfr0 = 0x00200000;
1381     cpu->id_afr0 = 0x00000000;
1382     cpu->id_mmfr0 = 0x00101F40;
1383     cpu->id_mmfr1 = 0x00000000;
1384     cpu->id_mmfr2 = 0x01000000;
1385     cpu->id_mmfr3 = 0x00000000;
1386     cpu->isar.id_isar0 = 0x01101110;
1387     cpu->isar.id_isar1 = 0x02212000;
1388     cpu->isar.id_isar2 = 0x20232232;
1389     cpu->isar.id_isar3 = 0x01111131;
1390     cpu->isar.id_isar4 = 0x01310132;
1391     cpu->isar.id_isar5 = 0x00000000;
1392     cpu->isar.id_isar6 = 0x00000000;
1393     cpu->clidr = 0x00000000;
1394     cpu->ctr = 0x8000c000;
1395 }
1396
1397 static void arm_v7m_class_init(ObjectClass *oc, void *data)
1398 {
1399     CPUClass *cc = CPU_CLASS(oc);
1400
1401 #ifndef CONFIG_USER_ONLY
1402     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1403 #endif
1404
1405     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1406 }
1407
1408 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1409     /* Dummy the TCM region regs for the moment */
1410     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1411       .access = PL1_RW, .type = ARM_CP_CONST },
1412     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1413       .access = PL1_RW, .type = ARM_CP_CONST },
1414     { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
1415       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
1416     REGINFO_SENTINEL
1417 };
1418
1419 static void cortex_r5_initfn(Object *obj)
1420 {
1421     ARMCPU *cpu = ARM_CPU(obj);
1422
1423     set_feature(&cpu->env, ARM_FEATURE_V7);
1424     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1425     set_feature(&cpu->env, ARM_FEATURE_PMSA);
1426     cpu->midr = 0x411fc153; /* r1p3 */
1427     cpu->id_pfr0 = 0x0131;
1428     cpu->id_pfr1 = 0x001;
1429     cpu->id_dfr0 = 0x010400;
1430     cpu->id_afr0 = 0x0;
1431     cpu->id_mmfr0 = 0x0210030;
1432     cpu->id_mmfr1 = 0x00000000;
1433     cpu->id_mmfr2 = 0x01200000;
1434     cpu->id_mmfr3 = 0x0211;
1435     cpu->isar.id_isar0 = 0x02101111;
1436     cpu->isar.id_isar1 = 0x13112111;
1437     cpu->isar.id_isar2 = 0x21232141;
1438     cpu->isar.id_isar3 = 0x01112131;
1439     cpu->isar.id_isar4 = 0x0010142;
1440     cpu->isar.id_isar5 = 0x0;
1441     cpu->isar.id_isar6 = 0x0;
1442     cpu->mp_is_up = true;
1443     cpu->pmsav7_dregion = 16;
1444     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1445 }
1446
1447 static void cortex_r5f_initfn(Object *obj)
1448 {
1449     ARMCPU *cpu = ARM_CPU(obj);
1450
1451     cortex_r5_initfn(obj);
1452     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1453 }
1454
1455 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1456     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1457       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1458     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1459       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1460     REGINFO_SENTINEL
1461 };
1462
1463 static void cortex_a8_initfn(Object *obj)
1464 {
1465     ARMCPU *cpu = ARM_CPU(obj);
1466
1467     cpu->dtb_compatible = "arm,cortex-a8";
1468     set_feature(&cpu->env, ARM_FEATURE_V7);
1469     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1470     set_feature(&cpu->env, ARM_FEATURE_NEON);
1471     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1472     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1473     set_feature(&cpu->env, ARM_FEATURE_EL3);
1474     cpu->midr = 0x410fc080;
1475     cpu->reset_fpsid = 0x410330c0;
1476     cpu->isar.mvfr0 = 0x11110222;
1477     cpu->isar.mvfr1 = 0x00011111;
1478     cpu->ctr = 0x82048004;
1479     cpu->reset_sctlr = 0x00c50078;
1480     cpu->id_pfr0 = 0x1031;
1481     cpu->id_pfr1 = 0x11;
1482     cpu->id_dfr0 = 0x400;
1483     cpu->id_afr0 = 0;
1484     cpu->id_mmfr0 = 0x31100003;
1485     cpu->id_mmfr1 = 0x20000000;
1486     cpu->id_mmfr2 = 0x01202000;
1487     cpu->id_mmfr3 = 0x11;
1488     cpu->isar.id_isar0 = 0x00101111;
1489     cpu->isar.id_isar1 = 0x12112111;
1490     cpu->isar.id_isar2 = 0x21232031;
1491     cpu->isar.id_isar3 = 0x11112131;
1492     cpu->isar.id_isar4 = 0x00111142;
1493     cpu->dbgdidr = 0x15141000;
1494     cpu->clidr = (1 << 27) | (2 << 24) | 3;
1495     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1496     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1497     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1498     cpu->reset_auxcr = 2;
1499     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1500 }
1501
1502 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1503     /* power_control should be set to maximum latency. Again,
1504      * default to 0 and set by private hook
1505      */
1506     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1507       .access = PL1_RW, .resetvalue = 0,
1508       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1509     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1510       .access = PL1_RW, .resetvalue = 0,
1511       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1512     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1513       .access = PL1_RW, .resetvalue = 0,
1514       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1515     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1516       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1517     /* TLB lockdown control */
1518     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1519       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1520     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1521       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1522     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1523       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1524     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1525       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1526     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1527       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1528     REGINFO_SENTINEL
1529 };
1530
1531 static void cortex_a9_initfn(Object *obj)
1532 {
1533     ARMCPU *cpu = ARM_CPU(obj);
1534
1535     cpu->dtb_compatible = "arm,cortex-a9";
1536     set_feature(&cpu->env, ARM_FEATURE_V7);
1537     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1538     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1539     set_feature(&cpu->env, ARM_FEATURE_NEON);
1540     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1541     set_feature(&cpu->env, ARM_FEATURE_EL3);
1542     /* Note that A9 supports the MP extensions even for
1543      * A9UP and single-core A9MP (which are both different
1544      * and valid configurations; we don't model A9UP).
1545      */
1546     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1547     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1548     cpu->midr = 0x410fc090;
1549     cpu->reset_fpsid = 0x41033090;
1550     cpu->isar.mvfr0 = 0x11110222;
1551     cpu->isar.mvfr1 = 0x01111111;
1552     cpu->ctr = 0x80038003;
1553     cpu->reset_sctlr = 0x00c50078;
1554     cpu->id_pfr0 = 0x1031;
1555     cpu->id_pfr1 = 0x11;
1556     cpu->id_dfr0 = 0x000;
1557     cpu->id_afr0 = 0;
1558     cpu->id_mmfr0 = 0x00100103;
1559     cpu->id_mmfr1 = 0x20000000;
1560     cpu->id_mmfr2 = 0x01230000;
1561     cpu->id_mmfr3 = 0x00002111;
1562     cpu->isar.id_isar0 = 0x00101111;
1563     cpu->isar.id_isar1 = 0x13112111;
1564     cpu->isar.id_isar2 = 0x21232041;
1565     cpu->isar.id_isar3 = 0x11112131;
1566     cpu->isar.id_isar4 = 0x00111142;
1567     cpu->dbgdidr = 0x35141000;
1568     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1569     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1570     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1571     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1572 }
1573
1574 #ifndef CONFIG_USER_ONLY
1575 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1576 {
1577     /* Linux wants the number of processors from here.
1578      * Might as well set the interrupt-controller bit too.
1579      */
1580     return ((smp_cpus - 1) << 24) | (1 << 23);
1581 }
1582 #endif
1583
1584 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1585 #ifndef CONFIG_USER_ONLY
1586     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1587       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1588       .writefn = arm_cp_write_ignore, },
1589 #endif
1590     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1591       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1592     REGINFO_SENTINEL
1593 };
1594
1595 static void cortex_a7_initfn(Object *obj)
1596 {
1597     ARMCPU *cpu = ARM_CPU(obj);
1598
1599     cpu->dtb_compatible = "arm,cortex-a7";
1600     set_feature(&cpu->env, ARM_FEATURE_V7VE);
1601     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1602     set_feature(&cpu->env, ARM_FEATURE_NEON);
1603     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1604     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1605     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1606     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1607     set_feature(&cpu->env, ARM_FEATURE_EL3);
1608     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1609     cpu->midr = 0x410fc075;
1610     cpu->reset_fpsid = 0x41023075;
1611     cpu->isar.mvfr0 = 0x10110222;
1612     cpu->isar.mvfr1 = 0x11111111;
1613     cpu->ctr = 0x84448003;
1614     cpu->reset_sctlr = 0x00c50078;
1615     cpu->id_pfr0 = 0x00001131;
1616     cpu->id_pfr1 = 0x00011011;
1617     cpu->id_dfr0 = 0x02010555;
1618     cpu->pmceid0 = 0x00000000;
1619     cpu->pmceid1 = 0x00000000;
1620     cpu->id_afr0 = 0x00000000;
1621     cpu->id_mmfr0 = 0x10101105;
1622     cpu->id_mmfr1 = 0x40000000;
1623     cpu->id_mmfr2 = 0x01240000;
1624     cpu->id_mmfr3 = 0x02102211;
1625     /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
1626      * table 4-41 gives 0x02101110, which includes the arm div insns.
1627      */
1628     cpu->isar.id_isar0 = 0x02101110;
1629     cpu->isar.id_isar1 = 0x13112111;
1630     cpu->isar.id_isar2 = 0x21232041;
1631     cpu->isar.id_isar3 = 0x11112131;
1632     cpu->isar.id_isar4 = 0x10011142;
1633     cpu->dbgdidr = 0x3515f005;
1634     cpu->clidr = 0x0a200023;
1635     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1636     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1637     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1638     define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
1639 }
1640
1641 static void cortex_a15_initfn(Object *obj)
1642 {
1643     ARMCPU *cpu = ARM_CPU(obj);
1644
1645     cpu->dtb_compatible = "arm,cortex-a15";
1646     set_feature(&cpu->env, ARM_FEATURE_V7VE);
1647     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1648     set_feature(&cpu->env, ARM_FEATURE_NEON);
1649     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1650     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1651     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1652     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1653     set_feature(&cpu->env, ARM_FEATURE_EL3);
1654     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1655     cpu->midr = 0x412fc0f1;
1656     cpu->reset_fpsid = 0x410430f0;
1657     cpu->isar.mvfr0 = 0x10110222;
1658     cpu->isar.mvfr1 = 0x11111111;
1659     cpu->ctr = 0x8444c004;
1660     cpu->reset_sctlr = 0x00c50078;
1661     cpu->id_pfr0 = 0x00001131;
1662     cpu->id_pfr1 = 0x00011011;
1663     cpu->id_dfr0 = 0x02010555;
1664     cpu->pmceid0 = 0x0000000;
1665     cpu->pmceid1 = 0x00000000;
1666     cpu->id_afr0 = 0x00000000;
1667     cpu->id_mmfr0 = 0x10201105;
1668     cpu->id_mmfr1 = 0x20000000;
1669     cpu->id_mmfr2 = 0x01240000;
1670     cpu->id_mmfr3 = 0x02102211;
1671     cpu->isar.id_isar0 = 0x02101110;
1672     cpu->isar.id_isar1 = 0x13112111;
1673     cpu->isar.id_isar2 = 0x21232041;
1674     cpu->isar.id_isar3 = 0x11112131;
1675     cpu->isar.id_isar4 = 0x10011142;
1676     cpu->dbgdidr = 0x3515f021;
1677     cpu->clidr = 0x0a200023;
1678     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1679     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1680     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1681     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1682 }
1683
1684 static void ti925t_initfn(Object *obj)
1685 {
1686     ARMCPU *cpu = ARM_CPU(obj);
1687     set_feature(&cpu->env, ARM_FEATURE_V4T);
1688     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1689     cpu->midr = ARM_CPUID_TI925T;
1690     cpu->ctr = 0x5109149;
1691     cpu->reset_sctlr = 0x00000070;
1692 }
1693
1694 static void sa1100_initfn(Object *obj)
1695 {
1696     ARMCPU *cpu = ARM_CPU(obj);
1697
1698     cpu->dtb_compatible = "intel,sa1100";
1699     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1700     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1701     cpu->midr = 0x4401A11B;
1702     cpu->reset_sctlr = 0x00000070;
1703 }
1704
1705 static void sa1110_initfn(Object *obj)
1706 {
1707     ARMCPU *cpu = ARM_CPU(obj);
1708     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1709     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1710     cpu->midr = 0x6901B119;
1711     cpu->reset_sctlr = 0x00000070;
1712 }
1713
1714 static void pxa250_initfn(Object *obj)
1715 {
1716     ARMCPU *cpu = ARM_CPU(obj);
1717
1718     cpu->dtb_compatible = "marvell,xscale";
1719     set_feature(&cpu->env, ARM_FEATURE_V5);
1720     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1721     cpu->midr = 0x69052100;
1722     cpu->ctr = 0xd172172;
1723     cpu->reset_sctlr = 0x00000078;
1724 }
1725
1726 static void pxa255_initfn(Object *obj)
1727 {
1728     ARMCPU *cpu = ARM_CPU(obj);
1729
1730     cpu->dtb_compatible = "marvell,xscale";
1731     set_feature(&cpu->env, ARM_FEATURE_V5);
1732     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1733     cpu->midr = 0x69052d00;
1734     cpu->ctr = 0xd172172;
1735     cpu->reset_sctlr = 0x00000078;
1736 }
1737
1738 static void pxa260_initfn(Object *obj)
1739 {
1740     ARMCPU *cpu = ARM_CPU(obj);
1741
1742     cpu->dtb_compatible = "marvell,xscale";
1743     set_feature(&cpu->env, ARM_FEATURE_V5);
1744     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1745     cpu->midr = 0x69052903;
1746     cpu->ctr = 0xd172172;
1747     cpu->reset_sctlr = 0x00000078;
1748 }
1749
1750 static void pxa261_initfn(Object *obj)
1751 {
1752     ARMCPU *cpu = ARM_CPU(obj);
1753
1754     cpu->dtb_compatible = "marvell,xscale";
1755     set_feature(&cpu->env, ARM_FEATURE_V5);
1756     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1757     cpu->midr = 0x69052d05;
1758     cpu->ctr = 0xd172172;
1759     cpu->reset_sctlr = 0x00000078;
1760 }
1761
1762 static void pxa262_initfn(Object *obj)
1763 {
1764     ARMCPU *cpu = ARM_CPU(obj);
1765
1766     cpu->dtb_compatible = "marvell,xscale";
1767     set_feature(&cpu->env, ARM_FEATURE_V5);
1768     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1769     cpu->midr = 0x69052d06;
1770     cpu->ctr = 0xd172172;
1771     cpu->reset_sctlr = 0x00000078;
1772 }
1773
1774 static void pxa270a0_initfn(Object *obj)
1775 {
1776     ARMCPU *cpu = ARM_CPU(obj);
1777
1778     cpu->dtb_compatible = "marvell,xscale";
1779     set_feature(&cpu->env, ARM_FEATURE_V5);
1780     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1781     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1782     cpu->midr = 0x69054110;
1783     cpu->ctr = 0xd172172;
1784     cpu->reset_sctlr = 0x00000078;
1785 }
1786
1787 static void pxa270a1_initfn(Object *obj)
1788 {
1789     ARMCPU *cpu = ARM_CPU(obj);
1790
1791     cpu->dtb_compatible = "marvell,xscale";
1792     set_feature(&cpu->env, ARM_FEATURE_V5);
1793     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1794     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1795     cpu->midr = 0x69054111;
1796     cpu->ctr = 0xd172172;
1797     cpu->reset_sctlr = 0x00000078;
1798 }
1799
1800 static void pxa270b0_initfn(Object *obj)
1801 {
1802     ARMCPU *cpu = ARM_CPU(obj);
1803
1804     cpu->dtb_compatible = "marvell,xscale";
1805     set_feature(&cpu->env, ARM_FEATURE_V5);
1806     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1807     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1808     cpu->midr = 0x69054112;
1809     cpu->ctr = 0xd172172;
1810     cpu->reset_sctlr = 0x00000078;
1811 }
1812
1813 static void pxa270b1_initfn(Object *obj)
1814 {
1815     ARMCPU *cpu = ARM_CPU(obj);
1816
1817     cpu->dtb_compatible = "marvell,xscale";
1818     set_feature(&cpu->env, ARM_FEATURE_V5);
1819     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1820     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1821     cpu->midr = 0x69054113;
1822     cpu->ctr = 0xd172172;
1823     cpu->reset_sctlr = 0x00000078;
1824 }
1825
1826 static void pxa270c0_initfn(Object *obj)
1827 {
1828     ARMCPU *cpu = ARM_CPU(obj);
1829
1830     cpu->dtb_compatible = "marvell,xscale";
1831     set_feature(&cpu->env, ARM_FEATURE_V5);
1832     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1833     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1834     cpu->midr = 0x69054114;
1835     cpu->ctr = 0xd172172;
1836     cpu->reset_sctlr = 0x00000078;
1837 }
1838
1839 static void pxa270c5_initfn(Object *obj)
1840 {
1841     ARMCPU *cpu = ARM_CPU(obj);
1842
1843     cpu->dtb_compatible = "marvell,xscale";
1844     set_feature(&cpu->env, ARM_FEATURE_V5);
1845     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1846     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1847     cpu->midr = 0x69054117;
1848     cpu->ctr = 0xd172172;
1849     cpu->reset_sctlr = 0x00000078;
1850 }
1851
1852 #ifndef TARGET_AARCH64
1853 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
1854  * otherwise, a CPU with as many features enabled as our emulation supports.
1855  * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1856  * this only needs to handle 32 bits.
1857  */
1858 static void arm_max_initfn(Object *obj)
1859 {
1860     ARMCPU *cpu = ARM_CPU(obj);
1861
1862     if (kvm_enabled()) {
1863         kvm_arm_set_cpu_features_from_host(cpu);
1864     } else {
1865         cortex_a15_initfn(obj);
1866 #ifdef CONFIG_USER_ONLY
1867         /* We don't set these in system emulation mode for the moment,
1868          * since we don't correctly set (all of) the ID registers to
1869          * advertise them.
1870          */
1871         set_feature(&cpu->env, ARM_FEATURE_V8);
1872         {
1873             uint32_t t;
1874
1875             t = cpu->isar.id_isar5;
1876             t = FIELD_DP32(t, ID_ISAR5, AES, 2);
1877             t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
1878             t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
1879             t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
1880             t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
1881             t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
1882             cpu->isar.id_isar5 = t;
1883
1884             t = cpu->isar.id_isar6;
1885             t = FIELD_DP32(t, ID_ISAR6, DP, 1);
1886             cpu->isar.id_isar6 = t;
1887         }
1888 #endif
1889     }
1890 }
1891 #endif
1892
1893 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1894
1895 typedef struct ARMCPUInfo {
1896     const char *name;
1897     void (*initfn)(Object *obj);
1898     void (*class_init)(ObjectClass *oc, void *data);
1899 } ARMCPUInfo;
1900
1901 static const ARMCPUInfo arm_cpus[] = {
1902 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1903     { .name = "arm926",      .initfn = arm926_initfn },
1904     { .name = "arm946",      .initfn = arm946_initfn },
1905     { .name = "arm1026",     .initfn = arm1026_initfn },
1906     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1907      * older core than plain "arm1136". In particular this does not
1908      * have the v6K features.
1909      */
1910     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1911     { .name = "arm1136",     .initfn = arm1136_initfn },
1912     { .name = "arm1176",     .initfn = arm1176_initfn },
1913     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1914     { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
1915                              .class_init = arm_v7m_class_init },
1916     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1917                              .class_init = arm_v7m_class_init },
1918     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1919                              .class_init = arm_v7m_class_init },
1920     { .name = "cortex-m33",  .initfn = cortex_m33_initfn,
1921                              .class_init = arm_v7m_class_init },
1922     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1923     { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
1924     { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
1925     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1926     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1927     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1928     { .name = "ti925t",      .initfn = ti925t_initfn },
1929     { .name = "sa1100",      .initfn = sa1100_initfn },
1930     { .name = "sa1110",      .initfn = sa1110_initfn },
1931     { .name = "pxa250",      .initfn = pxa250_initfn },
1932     { .name = "pxa255",      .initfn = pxa255_initfn },
1933     { .name = "pxa260",      .initfn = pxa260_initfn },
1934     { .name = "pxa261",      .initfn = pxa261_initfn },
1935     { .name = "pxa262",      .initfn = pxa262_initfn },
1936     /* "pxa270" is an alias for "pxa270-a0" */
1937     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1938     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1939     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1940     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1941     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1942     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1943     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1944 #ifndef TARGET_AARCH64
1945     { .name = "max",         .initfn = arm_max_initfn },
1946 #endif
1947 #ifdef CONFIG_USER_ONLY
1948     { .name = "any",         .initfn = arm_max_initfn },
1949 #endif
1950 #endif
1951     { .name = NULL }
1952 };
1953
1954 static Property arm_cpu_properties[] = {
1955     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1956     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1957     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1958     DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
1959                         mp_affinity, ARM64_AFFINITY_INVALID),
1960     DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
1961     DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
1962     DEFINE_PROP_END_OF_LIST()
1963 };
1964
1965 #ifdef CONFIG_USER_ONLY
1966 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
1967                                     int rw, int mmu_idx)
1968 {
1969     ARMCPU *cpu = ARM_CPU(cs);
1970     CPUARMState *env = &cpu->env;
1971
1972     env->exception.vaddress = address;
1973     if (rw == 2) {
1974         cs->exception_index = EXCP_PREFETCH_ABORT;
1975     } else {
1976         cs->exception_index = EXCP_DATA_ABORT;
1977     }
1978     return 1;
1979 }
1980 #endif
1981
1982 static gchar *arm_gdb_arch_name(CPUState *cs)
1983 {
1984     ARMCPU *cpu = ARM_CPU(cs);
1985     CPUARMState *env = &cpu->env;
1986
1987     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1988         return g_strdup("iwmmxt");
1989     }
1990     return g_strdup("arm");
1991 }
1992
1993 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1994 {
1995     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1996     CPUClass *cc = CPU_CLASS(acc);
1997     DeviceClass *dc = DEVICE_CLASS(oc);
1998
1999     device_class_set_parent_realize(dc, arm_cpu_realizefn,
2000                                     &acc->parent_realize);
2001     dc->props = arm_cpu_properties;
2002
2003     acc->parent_reset = cc->reset;
2004     cc->reset = arm_cpu_reset;
2005
2006     cc->class_by_name = arm_cpu_class_by_name;
2007     cc->has_work = arm_cpu_has_work;
2008     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
2009     cc->dump_state = arm_cpu_dump_state;
2010     cc->set_pc = arm_cpu_set_pc;
2011     cc->gdb_read_register = arm_cpu_gdb_read_register;
2012     cc->gdb_write_register = arm_cpu_gdb_write_register;
2013 #ifdef CONFIG_USER_ONLY
2014     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
2015 #else
2016     cc->do_interrupt = arm_cpu_do_interrupt;
2017     cc->do_unaligned_access = arm_cpu_do_unaligned_access;
2018     cc->do_transaction_failed = arm_cpu_do_transaction_failed;
2019     cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
2020     cc->asidx_from_attrs = arm_asidx_from_attrs;
2021     cc->vmsd = &vmstate_arm_cpu;
2022     cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
2023     cc->write_elf64_note = arm_cpu_write_elf64_note;
2024     cc->write_elf32_note = arm_cpu_write_elf32_note;
2025 #endif
2026     cc->gdb_num_core_regs = 26;
2027     cc->gdb_core_xml_file = "arm-core.xml";
2028     cc->gdb_arch_name = arm_gdb_arch_name;
2029     cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2030     cc->gdb_stop_before_watchpoint = true;
2031     cc->debug_excp_handler = arm_debug_excp_handler;
2032     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
2033 #if !defined(CONFIG_USER_ONLY)
2034     cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
2035 #endif
2036
2037     cc->disas_set_info = arm_disas_set_info;
2038 #ifdef CONFIG_TCG
2039     cc->tcg_initialize = arm_translate_init;
2040 #endif
2041 }
2042
2043 #ifdef CONFIG_KVM
2044 static void arm_host_initfn(Object *obj)
2045 {
2046     ARMCPU *cpu = ARM_CPU(obj);
2047
2048     kvm_arm_set_cpu_features_from_host(cpu);
2049 }
2050
2051 static const TypeInfo host_arm_cpu_type_info = {
2052     .name = TYPE_ARM_HOST_CPU,
2053 #ifdef TARGET_AARCH64
2054     .parent = TYPE_AARCH64_CPU,
2055 #else
2056     .parent = TYPE_ARM_CPU,
2057 #endif
2058     .instance_init = arm_host_initfn,
2059 };
2060
2061 #endif
2062
2063 static void cpu_register(const ARMCPUInfo *info)
2064 {
2065     TypeInfo type_info = {
2066         .parent = TYPE_ARM_CPU,
2067         .instance_size = sizeof(ARMCPU),
2068         .instance_init = info->initfn,
2069         .class_size = sizeof(ARMCPUClass),
2070         .class_init = info->class_init,
2071     };
2072
2073     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2074     type_register(&type_info);
2075     g_free((void *)type_info.name);
2076 }
2077
2078 static const TypeInfo arm_cpu_type_info = {
2079     .name = TYPE_ARM_CPU,
2080     .parent = TYPE_CPU,
2081     .instance_size = sizeof(ARMCPU),
2082     .instance_init = arm_cpu_initfn,
2083     .instance_post_init = arm_cpu_post_init,
2084     .instance_finalize = arm_cpu_finalizefn,
2085     .abstract = true,
2086     .class_size = sizeof(ARMCPUClass),
2087     .class_init = arm_cpu_class_init,
2088 };
2089
2090 static const TypeInfo idau_interface_type_info = {
2091     .name = TYPE_IDAU_INTERFACE,
2092     .parent = TYPE_INTERFACE,
2093     .class_size = sizeof(IDAUInterfaceClass),
2094 };
2095
2096 static void arm_cpu_register_types(void)
2097 {
2098     const ARMCPUInfo *info = arm_cpus;
2099
2100     type_register_static(&arm_cpu_type_info);
2101     type_register_static(&idau_interface_type_info);
2102
2103     while (info->name) {
2104         cpu_register(info);
2105         info++;
2106     }
2107
2108 #ifdef CONFIG_KVM
2109     type_register_static(&host_arm_cpu_type_info);
2110 #endif
2111 }
2112
2113 type_init(arm_cpu_register_types)