target/arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/error-report.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "internals.h"
  26 #include "qemu-common.h"
  27 #include "exec/exec-all.h"
  28 #include "hw/qdev-properties.h"
  29 #if !defined(CONFIG_USER_ONLY)
  30 #include "hw/loader.h"
  31 #endif
  32 #include "hw/arm/arm.h"
  33 #include "sysemu/sysemu.h"
  34 #include "sysemu/hw_accel.h"
  35 #include "kvm_arm.h"
  36
  37 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  38 {
  39     ARMCPU *cpu = ARM_CPU(cs);
  40
  41     cpu->env.regs[15] = value;
  42 }
  43
  44 static bool arm_cpu_has_work(CPUState *cs)
  45 {
  46     ARMCPU *cpu = ARM_CPU(cs);
  47
  48     return (cpu->power_state != PSCI_OFF)
  49         && cs->interrupt_request &
  50         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  51          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  52          | CPU_INTERRUPT_EXITTB);
  53 }
  54
  55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
  56                                  void *opaque)
  57 {
  58     /* We currently only support registering a single hook function */
  59     assert(!cpu->el_change_hook);
  60     cpu->el_change_hook = hook;
  61     cpu->el_change_hook_opaque = opaque;
  62 }
  63
  64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  65 {
  66     /* Reset a single ARMCPRegInfo register */
  67     ARMCPRegInfo *ri = value;
  68     ARMCPU *cpu = opaque;
  69
  70     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
  71         return;
  72     }
  73
  74     if (ri->resetfn) {
  75         ri->resetfn(&cpu->env, ri);
  76         return;
  77     }
  78
  79     /* A zero offset is never possible as it would be regs[0]
  80      * so we use it to indicate that reset is being handled elsewhere.
  81      * This is basically only used for fields in non-core coprocessors
  82      * (like the pxa2xx ones).
  83      */
  84     if (!ri->fieldoffset) {
  85         return;
  86     }
  87
  88     if (cpreg_field_is_64bit(ri)) {
  89         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  90     } else {
  91         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  92     }
  93 }
  94
  95 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
  96 {
  97     /* Purely an assertion check: we've already done reset once,
  98      * so now check that running the reset for the cpreg doesn't
  99      * change its value. This traps bugs where two different cpregs
 100      * both try to reset the same state field but to different values.
 101      */
 102     ARMCPRegInfo *ri = value;
 103     ARMCPU *cpu = opaque;
 104     uint64_t oldvalue, newvalue;
 105
 106     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
 107         return;
 108     }
 109
 110     oldvalue = read_raw_cp_reg(&cpu->env, ri);
 111     cp_reg_reset(key, value, opaque);
 112     newvalue = read_raw_cp_reg(&cpu->env, ri);
 113     assert(oldvalue == newvalue);
 114 }
 115
 116 /* CPUClass::reset() */
 117 static void arm_cpu_reset(CPUState *s)
 118 {
 119     ARMCPU *cpu = ARM_CPU(s);
 120     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 121     CPUARMState *env = &cpu->env;
 122
 123     acc->parent_reset(s);
 124
 125     memset(env, 0, offsetof(CPUARMState, end_reset_fields));
 126
 127     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
 128     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 129
 130     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
 131     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
 132     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
 133     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
 134
 135     cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
 136     s->halted = cpu->start_powered_off;
 137
 138     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 139         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 140     }
 141
 142     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 143         /* 64 bit CPUs always start in 64 bit mode */
 144         env->aarch64 = 1;
 145 #if defined(CONFIG_USER_ONLY)
 146         env->pstate = PSTATE_MODE_EL0t;
 147         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 148         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 149         /* and to the FP/Neon instructions */
 150         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 151 #else
 152         /* Reset into the highest available EL */
 153         if (arm_feature(env, ARM_FEATURE_EL3)) {
 154             env->pstate = PSTATE_MODE_EL3h;
 155         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 156             env->pstate = PSTATE_MODE_EL2h;
 157         } else {
 158             env->pstate = PSTATE_MODE_EL1h;
 159         }
 160         env->pc = cpu->rvbar;
 161 #endif
 162     } else {
 163 #if defined(CONFIG_USER_ONLY)
 164         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 165         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 166 #endif
 167     }
 168
 169 #if defined(CONFIG_USER_ONLY)
 170     env->uncached_cpsr = ARM_CPU_MODE_USR;
 171     /* For user mode we must enable access to coprocessors */
 172     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 173     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 174         env->cp15.c15_cpar = 3;
 175     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 176         env->cp15.c15_cpar = 1;
 177     }
 178 #else
 179     /* SVC mode with interrupts disabled.  */
 180     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 181     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 182
 183     if (arm_feature(env, ARM_FEATURE_M)) {
 184         uint32_t initial_msp; /* Loaded from 0x0 */
 185         uint32_t initial_pc; /* Loaded from 0x4 */
 186         uint8_t *rom;
 187
 188         /* For M profile we store FAULTMASK and PRIMASK in the
 189          * PSTATE F and I bits; these are both clear at reset.
 190          */
 191         env->daif &= ~(PSTATE_I | PSTATE_F);
 192
 193         /* The reset value of this bit is IMPDEF, but ARM recommends
 194          * that it resets to 1, so QEMU always does that rather than making
 195          * it dependent on CPU model.
 196          */
 197         env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;
 198
 199         /* Unlike A/R profile, M profile defines the reset LR value */
 200         env->regs[14] = 0xffffffff;
 201
 202         /* Load the initial SP and PC from the vector table at address 0 */
 203         rom = rom_ptr(0);
 204         if (rom) {
 205             /* Address zero is covered by ROM which hasn't yet been
 206              * copied into physical memory.
 207              */
 208             initial_msp = ldl_p(rom);
 209             initial_pc = ldl_p(rom + 4);
 210         } else {
 211             /* Address zero not covered by a ROM blob, or the ROM blob
 212              * is in non-modifiable memory and this is a second reset after
 213              * it got copied into memory. In the latter case, rom_ptr
 214              * will return a NULL pointer and we should use ldl_phys instead.
 215              */
 216             initial_msp = ldl_phys(s->as, 0);
 217             initial_pc = ldl_phys(s->as, 4);
 218         }
 219
 220         env->regs[13] = initial_msp & 0xFFFFFFFC;
 221         env->regs[15] = initial_pc & ~1;
 222         env->thumb = initial_pc & 1;
 223     }
 224
 225     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 226      * executing as AArch32 then check if highvecs are enabled and
 227      * adjust the PC accordingly.
 228      */
 229     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 230         env->regs[15] = 0xFFFF0000;
 231     }
 232
 233     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 234 #endif
 235     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 236     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 237     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 238     set_float_detect_tininess(float_tininess_before_rounding,
 239                               &env->vfp.fp_status);
 240     set_float_detect_tininess(float_tininess_before_rounding,
 241                               &env->vfp.standard_fp_status);
 242 #ifndef CONFIG_USER_ONLY
 243     if (kvm_enabled()) {
 244         kvm_arm_reset_vcpu(cpu);
 245     }
 246 #endif
 247
 248     hw_breakpoint_update_all(cpu);
 249     hw_watchpoint_update_all(cpu);
 250 }
 251
 252 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 253 {
 254     CPUClass *cc = CPU_GET_CLASS(cs);
 255     CPUARMState *env = cs->env_ptr;
 256     uint32_t cur_el = arm_current_el(env);
 257     bool secure = arm_is_secure(env);
 258     uint32_t target_el;
 259     uint32_t excp_idx;
 260     bool ret = false;
 261
 262     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 263         excp_idx = EXCP_FIQ;
 264         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 265         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 266             cs->exception_index = excp_idx;
 267             env->exception.target_el = target_el;
 268             cc->do_interrupt(cs);
 269             ret = true;
 270         }
 271     }
 272     if (interrupt_request & CPU_INTERRUPT_HARD) {
 273         excp_idx = EXCP_IRQ;
 274         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 275         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 276             cs->exception_index = excp_idx;
 277             env->exception.target_el = target_el;
 278             cc->do_interrupt(cs);
 279             ret = true;
 280         }
 281     }
 282     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 283         excp_idx = EXCP_VIRQ;
 284         target_el = 1;
 285         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 286             cs->exception_index = excp_idx;
 287             env->exception.target_el = target_el;
 288             cc->do_interrupt(cs);
 289             ret = true;
 290         }
 291     }
 292     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 293         excp_idx = EXCP_VFIQ;
 294         target_el = 1;
 295         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 296             cs->exception_index = excp_idx;
 297             env->exception.target_el = target_el;
 298             cc->do_interrupt(cs);
 299             ret = true;
 300         }
 301     }
 302
 303     return ret;
 304 }
 305
 306 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 307 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 308 {
 309     CPUClass *cc = CPU_GET_CLASS(cs);
 310     ARMCPU *cpu = ARM_CPU(cs);
 311     CPUARMState *env = &cpu->env;
 312     bool ret = false;
 313
 314     /* ARMv7-M interrupt masking works differently than -A or -R.
 315      * There is no FIQ/IRQ distinction. Instead of I and F bits
 316      * masking FIQ and IRQ interrupts, an exception is taken only
 317      * if it is higher priority than the current execution priority
 318      * (which depends on state like BASEPRI, FAULTMASK and the
 319      * currently active exception).
 320      */
 321     if (interrupt_request & CPU_INTERRUPT_HARD
 322         && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
 323         cs->exception_index = EXCP_IRQ;
 324         cc->do_interrupt(cs);
 325         ret = true;
 326     }
 327     return ret;
 328 }
 329 #endif
 330
 331 #ifndef CONFIG_USER_ONLY
 332 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 333 {
 334     ARMCPU *cpu = opaque;
 335     CPUARMState *env = &cpu->env;
 336     CPUState *cs = CPU(cpu);
 337     static const int mask[] = {
 338         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 339         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 340         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 341         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 342     };
 343
 344     switch (irq) {
 345     case ARM_CPU_VIRQ:
 346     case ARM_CPU_VFIQ:
 347         assert(arm_feature(env, ARM_FEATURE_EL2));
 348         /* fall through */
 349     case ARM_CPU_IRQ:
 350     case ARM_CPU_FIQ:
 351         if (level) {
 352             cpu_interrupt(cs, mask[irq]);
 353         } else {
 354             cpu_reset_interrupt(cs, mask[irq]);
 355         }
 356         break;
 357     default:
 358         g_assert_not_reached();
 359     }
 360 }
 361
 362 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 363 {
 364 #ifdef CONFIG_KVM
 365     ARMCPU *cpu = opaque;
 366     CPUState *cs = CPU(cpu);
 367     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 368
 369     switch (irq) {
 370     case ARM_CPU_IRQ:
 371         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 372         break;
 373     case ARM_CPU_FIQ:
 374         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 375         break;
 376     default:
 377         g_assert_not_reached();
 378     }
 379     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 380     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 381 #endif
 382 }
 383
 384 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
 385 {
 386     ARMCPU *cpu = ARM_CPU(cs);
 387     CPUARMState *env = &cpu->env;
 388
 389     cpu_synchronize_state(cs);
 390     return arm_cpu_data_is_big_endian(env);
 391 }
 392
 393 #endif
 394
 395 static inline void set_feature(CPUARMState *env, int feature)
 396 {
 397     env->features |= 1ULL << feature;
 398 }
 399
 400 static inline void unset_feature(CPUARMState *env, int feature)
 401 {
 402     env->features &= ~(1ULL << feature);
 403 }
 404
 405 static int
 406 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 407 {
 408   return print_insn_arm(pc | 1, info);
 409 }
 410
 411 static int arm_read_memory_func(bfd_vma memaddr, bfd_byte *b,
 412                                 int length, struct disassemble_info *info)
 413 {
 414     assert(info->read_memory_inner_func);
 415     assert((info->flags & INSN_ARM_BE32) == 0 || length == 2 || length == 4);
 416
 417     if ((info->flags & INSN_ARM_BE32) != 0 && length == 2) {
 418         assert(info->endian == BFD_ENDIAN_LITTLE);
 419         return info->read_memory_inner_func(memaddr ^ 2, (bfd_byte *)b, 2,
 420                                             info);
 421     } else {
 422         return info->read_memory_inner_func(memaddr, b, length, info);
 423     }
 424 }
 425
 426 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 427 {
 428     ARMCPU *ac = ARM_CPU(cpu);
 429     CPUARMState *env = &ac->env;
 430
 431     if (is_a64(env)) {
 432         /* We might not be compiled with the A64 disassembler
 433          * because it needs a C++ compiler. Leave print_insn
 434          * unset in this case to use the caller default behaviour.
 435          */
 436 #if defined(CONFIG_ARM_A64_DIS)
 437         info->print_insn = print_insn_arm_a64;
 438 #endif
 439     } else if (env->thumb) {
 440         info->print_insn = print_insn_thumb1;
 441     } else {
 442         info->print_insn = print_insn_arm;
 443     }
 444     if (bswap_code(arm_sctlr_b(env))) {
 445 #ifdef TARGET_WORDS_BIGENDIAN
 446         info->endian = BFD_ENDIAN_LITTLE;
 447 #else
 448         info->endian = BFD_ENDIAN_BIG;
 449 #endif
 450     }
 451     if (info->read_memory_inner_func == NULL) {
 452         info->read_memory_inner_func = info->read_memory_func;
 453         info->read_memory_func = arm_read_memory_func;
 454     }
 455     info->flags &= ~INSN_ARM_BE32;
 456     if (arm_sctlr_b(env)) {
 457         info->flags |= INSN_ARM_BE32;
 458     }
 459 }
 460
 461 static void arm_cpu_initfn(Object *obj)
 462 {
 463     CPUState *cs = CPU(obj);
 464     ARMCPU *cpu = ARM_CPU(obj);
 465     static bool inited;
 466
 467     cs->env_ptr = &cpu->env;
 468     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 469                                          g_free, g_free);
 470
 471 #ifndef CONFIG_USER_ONLY
 472     /* Our inbound IRQ and FIQ lines */
 473     if (kvm_enabled()) {
 474         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 475          * the same interface as non-KVM CPUs.
 476          */
 477         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 478     } else {
 479         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 480     }
 481
 482     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 483                                                 arm_gt_ptimer_cb, cpu);
 484     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 485                                                 arm_gt_vtimer_cb, cpu);
 486     cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 487                                                 arm_gt_htimer_cb, cpu);
 488     cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 489                                                 arm_gt_stimer_cb, cpu);
 490     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 491                        ARRAY_SIZE(cpu->gt_timer_outputs));
 492
 493     qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
 494                              "gicv3-maintenance-interrupt", 1);
 495 #endif
 496
 497     /* DTB consumers generally don't in fact care what the 'compatible'
 498      * string is, so always provide some string and trust that a hypothetical
 499      * picky DTB consumer will also provide a helpful error message.
 500      */
 501     cpu->dtb_compatible = "qemu,unknown";
 502     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 503     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 504
 505     if (tcg_enabled()) {
 506         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 507         if (!inited) {
 508             inited = true;
 509             arm_translate_init();
 510         }
 511     }
 512 }
 513
 514 static Property arm_cpu_reset_cbar_property =
 515             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 516
 517 static Property arm_cpu_reset_hivecs_property =
 518             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 519
 520 static Property arm_cpu_rvbar_property =
 521             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 522
 523 static Property arm_cpu_has_el2_property =
 524             DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
 525
 526 static Property arm_cpu_has_el3_property =
 527             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 528
 529 static Property arm_cpu_cfgend_property =
 530             DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
 531
 532 /* use property name "pmu" to match other archs and virt tools */
 533 static Property arm_cpu_has_pmu_property =
 534             DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
 535
 536 static Property arm_cpu_has_mpu_property =
 537             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 538
 539 static Property arm_cpu_pmsav7_dregion_property =
 540             DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
 541
 542 static void arm_cpu_post_init(Object *obj)
 543 {
 544     ARMCPU *cpu = ARM_CPU(obj);
 545
 546     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 547         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 548         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 549                                  &error_abort);
 550     }
 551
 552     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 553         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 554                                  &error_abort);
 555     }
 556
 557     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 558         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 559                                  &error_abort);
 560     }
 561
 562     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 563         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 564          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 565          */
 566         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 567                                  &error_abort);
 568
 569 #ifndef CONFIG_USER_ONLY
 570         object_property_add_link(obj, "secure-memory",
 571                                  TYPE_MEMORY_REGION,
 572                                  (Object **)&cpu->secure_memory,
 573                                  qdev_prop_allow_set_link_before_realize,
 574                                  OBJ_PROP_LINK_UNREF_ON_RELEASE,
 575                                  &error_abort);
 576 #endif
 577     }
 578
 579     if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
 580         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
 581                                  &error_abort);
 582     }
 583
 584     if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
 585         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
 586                                  &error_abort);
 587     }
 588
 589     if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
 590         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 591                                  &error_abort);
 592         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 593             qdev_property_add_static(DEVICE(obj),
 594                                      &arm_cpu_pmsav7_dregion_property,
 595                                      &error_abort);
 596         }
 597     }
 598
 599     qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
 600                              &error_abort);
 601 }
 602
 603 static void arm_cpu_finalizefn(Object *obj)
 604 {
 605     ARMCPU *cpu = ARM_CPU(obj);
 606     g_hash_table_destroy(cpu->cp_regs);
 607 }
 608
 609 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 610 {
 611     CPUState *cs = CPU(dev);
 612     ARMCPU *cpu = ARM_CPU(dev);
 613     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 614     CPUARMState *env = &cpu->env;
 615     int pagebits;
 616     Error *local_err = NULL;
 617
 618     cpu_exec_realizefn(cs, &local_err);
 619     if (local_err != NULL) {
 620         error_propagate(errp, local_err);
 621         return;
 622     }
 623
 624     /* Some features automatically imply others: */
 625     if (arm_feature(env, ARM_FEATURE_V8)) {
 626         set_feature(env, ARM_FEATURE_V7);
 627         set_feature(env, ARM_FEATURE_ARM_DIV);
 628         set_feature(env, ARM_FEATURE_LPAE);
 629     }
 630     if (arm_feature(env, ARM_FEATURE_V7)) {
 631         set_feature(env, ARM_FEATURE_VAPA);
 632         set_feature(env, ARM_FEATURE_THUMB2);
 633         set_feature(env, ARM_FEATURE_MPIDR);
 634         if (!arm_feature(env, ARM_FEATURE_M)) {
 635             set_feature(env, ARM_FEATURE_V6K);
 636         } else {
 637             set_feature(env, ARM_FEATURE_V6);
 638         }
 639
 640         /* Always define VBAR for V7 CPUs even if it doesn't exist in
 641          * non-EL3 configs. This is needed by some legacy boards.
 642          */
 643         set_feature(env, ARM_FEATURE_VBAR);
 644     }
 645     if (arm_feature(env, ARM_FEATURE_V6K)) {
 646         set_feature(env, ARM_FEATURE_V6);
 647         set_feature(env, ARM_FEATURE_MVFR);
 648     }
 649     if (arm_feature(env, ARM_FEATURE_V6)) {
 650         set_feature(env, ARM_FEATURE_V5);
 651         if (!arm_feature(env, ARM_FEATURE_M)) {
 652             set_feature(env, ARM_FEATURE_AUXCR);
 653         }
 654     }
 655     if (arm_feature(env, ARM_FEATURE_V5)) {
 656         set_feature(env, ARM_FEATURE_V4T);
 657     }
 658     if (arm_feature(env, ARM_FEATURE_M)) {
 659         set_feature(env, ARM_FEATURE_THUMB_DIV);
 660     }
 661     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 662         set_feature(env, ARM_FEATURE_THUMB_DIV);
 663     }
 664     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 665         set_feature(env, ARM_FEATURE_VFP3);
 666         set_feature(env, ARM_FEATURE_VFP_FP16);
 667     }
 668     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 669         set_feature(env, ARM_FEATURE_VFP);
 670     }
 671     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 672         set_feature(env, ARM_FEATURE_V7MP);
 673         set_feature(env, ARM_FEATURE_PXN);
 674     }
 675     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 676         set_feature(env, ARM_FEATURE_CBAR);
 677     }
 678     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 679         !arm_feature(env, ARM_FEATURE_M)) {
 680         set_feature(env, ARM_FEATURE_THUMB_DSP);
 681     }
 682
 683     if (arm_feature(env, ARM_FEATURE_V7) &&
 684         !arm_feature(env, ARM_FEATURE_M) &&
 685         !arm_feature(env, ARM_FEATURE_MPU)) {
 686         /* v7VMSA drops support for the old ARMv5 tiny pages, so we
 687          * can use 4K pages.
 688          */
 689         pagebits = 12;
 690     } else {
 691         /* For CPUs which might have tiny 1K pages, or which have an
 692          * MPU and might have small region sizes, stick with 1K pages.
 693          */
 694         pagebits = 10;
 695     }
 696     if (!set_preferred_target_page_bits(pagebits)) {
 697         /* This can only ever happen for hotplugging a CPU, or if
 698          * the board code incorrectly creates a CPU which it has
 699          * promised via minimum_page_size that it will not.
 700          */
 701         error_setg(errp, "This CPU requires a smaller page size than the "
 702                    "system is using");
 703         return;
 704     }
 705
 706     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
 707      * We don't support setting cluster ID ([16..23]) (known as Aff2
 708      * in later ARM ARM versions), or any of the higher affinity level fields,
 709      * so these bits always RAZ.
 710      */
 711     if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
 712         uint32_t Aff1 = cs->cpu_index / ARM_DEFAULT_CPUS_PER_CLUSTER;
 713         uint32_t Aff0 = cs->cpu_index % ARM_DEFAULT_CPUS_PER_CLUSTER;
 714         cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 715     }
 716
 717     if (cpu->reset_hivecs) {
 718             cpu->reset_sctlr |= (1 << 13);
 719     }
 720
 721     if (cpu->cfgend) {
 722         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 723             cpu->reset_sctlr |= SCTLR_EE;
 724         } else {
 725             cpu->reset_sctlr |= SCTLR_B;
 726         }
 727     }
 728
 729     if (!cpu->has_el3) {
 730         /* If the has_el3 CPU property is disabled then we need to disable the
 731          * feature.
 732          */
 733         unset_feature(env, ARM_FEATURE_EL3);
 734
 735         /* Disable the security extension feature bits in the processor feature
 736          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 737          */
 738         cpu->id_pfr1 &= ~0xf0;
 739         cpu->id_aa64pfr0 &= ~0xf000;
 740     }
 741
 742     if (!cpu->has_el2) {
 743         unset_feature(env, ARM_FEATURE_EL2);
 744     }
 745
 746     if (!cpu->has_pmu) {
 747         cpu->has_pmu = false;
 748         unset_feature(env, ARM_FEATURE_PMU);
 749     }
 750
 751     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 752         /* Disable the hypervisor feature bits in the processor feature
 753          * registers if we don't have EL2. These are id_pfr1[15:12] and
 754          * id_aa64pfr0_el1[11:8].
 755          */
 756         cpu->id_aa64pfr0 &= ~0xf00;
 757         cpu->id_pfr1 &= ~0xf000;
 758     }
 759
 760     if (!cpu->has_mpu) {
 761         unset_feature(env, ARM_FEATURE_MPU);
 762     }
 763
 764     if (arm_feature(env, ARM_FEATURE_MPU) &&
 765         arm_feature(env, ARM_FEATURE_V7)) {
 766         uint32_t nr = cpu->pmsav7_dregion;
 767
 768         if (nr > 0xff) {
 769             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
 770             return;
 771         }
 772
 773         if (nr) {
 774             env->pmsav7.drbar = g_new0(uint32_t, nr);
 775             env->pmsav7.drsr = g_new0(uint32_t, nr);
 776             env->pmsav7.dracr = g_new0(uint32_t, nr);
 777         }
 778     }
 779
 780     if (arm_feature(env, ARM_FEATURE_EL3)) {
 781         set_feature(env, ARM_FEATURE_VBAR);
 782     }
 783
 784     register_cp_regs_for_features(cpu);
 785     arm_cpu_register_gdb_regs_for_features(cpu);
 786
 787     init_cpreg_list(cpu);
 788
 789 #ifndef CONFIG_USER_ONLY
 790     if (cpu->has_el3) {
 791         cs->num_ases = 2;
 792     } else {
 793         cs->num_ases = 1;
 794     }
 795
 796     if (cpu->has_el3) {
 797         AddressSpace *as;
 798
 799         if (!cpu->secure_memory) {
 800             cpu->secure_memory = cs->memory;
 801         }
 802         as = address_space_init_shareable(cpu->secure_memory,
 803                                           "cpu-secure-memory");
 804         cpu_address_space_init(cs, as, ARMASIdx_S);
 805     }
 806     cpu_address_space_init(cs,
 807                            address_space_init_shareable(cs->memory,
 808                                                         "cpu-memory"),
 809                            ARMASIdx_NS);
 810 #endif
 811
 812     qemu_init_vcpu(cs);
 813     cpu_reset(cs);
 814
 815     acc->parent_realize(dev, errp);
 816 }
 817
 818 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 819 {
 820     ObjectClass *oc;
 821     char *typename;
 822     char **cpuname;
 823
 824     if (!cpu_model) {
 825         return NULL;
 826     }
 827
 828     cpuname = g_strsplit(cpu_model, ",", 1);
 829     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
 830     oc = object_class_by_name(typename);
 831     g_strfreev(cpuname);
 832     g_free(typename);
 833     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 834         object_class_is_abstract(oc)) {
 835         return NULL;
 836     }
 837     return oc;
 838 }
 839
 840 /* CPU models. These are not needed for the AArch64 linux-user build. */
 841 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 842
 843 static void arm926_initfn(Object *obj)
 844 {
 845     ARMCPU *cpu = ARM_CPU(obj);
 846
 847     cpu->dtb_compatible = "arm,arm926";
 848     set_feature(&cpu->env, ARM_FEATURE_V5);
 849     set_feature(&cpu->env, ARM_FEATURE_VFP);
 850     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 851     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 852     cpu->midr = 0x41069265;
 853     cpu->reset_fpsid = 0x41011090;
 854     cpu->ctr = 0x1dd20d2;
 855     cpu->reset_sctlr = 0x00090078;
 856 }
 857
 858 static void arm946_initfn(Object *obj)
 859 {
 860     ARMCPU *cpu = ARM_CPU(obj);
 861
 862     cpu->dtb_compatible = "arm,arm946";
 863     set_feature(&cpu->env, ARM_FEATURE_V5);
 864     set_feature(&cpu->env, ARM_FEATURE_MPU);
 865     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 866     cpu->midr = 0x41059461;
 867     cpu->ctr = 0x0f004006;
 868     cpu->reset_sctlr = 0x00000078;
 869 }
 870
 871 static void arm1026_initfn(Object *obj)
 872 {
 873     ARMCPU *cpu = ARM_CPU(obj);
 874
 875     cpu->dtb_compatible = "arm,arm1026";
 876     set_feature(&cpu->env, ARM_FEATURE_V5);
 877     set_feature(&cpu->env, ARM_FEATURE_VFP);
 878     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 879     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 880     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 881     cpu->midr = 0x4106a262;
 882     cpu->reset_fpsid = 0x410110a0;
 883     cpu->ctr = 0x1dd20d2;
 884     cpu->reset_sctlr = 0x00090078;
 885     cpu->reset_auxcr = 1;
 886     {
 887         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 888         ARMCPRegInfo ifar = {
 889             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 890             .access = PL1_RW,
 891             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 892             .resetvalue = 0
 893         };
 894         define_one_arm_cp_reg(cpu, &ifar);
 895     }
 896 }
 897
 898 static void arm1136_r2_initfn(Object *obj)
 899 {
 900     ARMCPU *cpu = ARM_CPU(obj);
 901     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 902      * older core than plain "arm1136". In particular this does not
 903      * have the v6K features.
 904      * These ID register values are correct for 1136 but may be wrong
 905      * for 1136_r2 (in particular r0p2 does not actually implement most
 906      * of the ID registers).
 907      */
 908
 909     cpu->dtb_compatible = "arm,arm1136";
 910     set_feature(&cpu->env, ARM_FEATURE_V6);
 911     set_feature(&cpu->env, ARM_FEATURE_VFP);
 912     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 913     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 914     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 915     cpu->midr = 0x4107b362;
 916     cpu->reset_fpsid = 0x410120b4;
 917     cpu->mvfr0 = 0x11111111;
 918     cpu->mvfr1 = 0x00000000;
 919     cpu->ctr = 0x1dd20d2;
 920     cpu->reset_sctlr = 0x00050078;
 921     cpu->id_pfr0 = 0x111;
 922     cpu->id_pfr1 = 0x1;
 923     cpu->id_dfr0 = 0x2;
 924     cpu->id_afr0 = 0x3;
 925     cpu->id_mmfr0 = 0x01130003;
 926     cpu->id_mmfr1 = 0x10030302;
 927     cpu->id_mmfr2 = 0x01222110;
 928     cpu->id_isar0 = 0x00140011;
 929     cpu->id_isar1 = 0x12002111;
 930     cpu->id_isar2 = 0x11231111;
 931     cpu->id_isar3 = 0x01102131;
 932     cpu->id_isar4 = 0x141;
 933     cpu->reset_auxcr = 7;
 934 }
 935
 936 static void arm1136_initfn(Object *obj)
 937 {
 938     ARMCPU *cpu = ARM_CPU(obj);
 939
 940     cpu->dtb_compatible = "arm,arm1136";
 941     set_feature(&cpu->env, ARM_FEATURE_V6K);
 942     set_feature(&cpu->env, ARM_FEATURE_V6);
 943     set_feature(&cpu->env, ARM_FEATURE_VFP);
 944     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 945     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 946     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 947     cpu->midr = 0x4117b363;
 948     cpu->reset_fpsid = 0x410120b4;
 949     cpu->mvfr0 = 0x11111111;
 950     cpu->mvfr1 = 0x00000000;
 951     cpu->ctr = 0x1dd20d2;
 952     cpu->reset_sctlr = 0x00050078;
 953     cpu->id_pfr0 = 0x111;
 954     cpu->id_pfr1 = 0x1;
 955     cpu->id_dfr0 = 0x2;
 956     cpu->id_afr0 = 0x3;
 957     cpu->id_mmfr0 = 0x01130003;
 958     cpu->id_mmfr1 = 0x10030302;
 959     cpu->id_mmfr2 = 0x01222110;
 960     cpu->id_isar0 = 0x00140011;
 961     cpu->id_isar1 = 0x12002111;
 962     cpu->id_isar2 = 0x11231111;
 963     cpu->id_isar3 = 0x01102131;
 964     cpu->id_isar4 = 0x141;
 965     cpu->reset_auxcr = 7;
 966 }
 967
 968 static void arm1176_initfn(Object *obj)
 969 {
 970     ARMCPU *cpu = ARM_CPU(obj);
 971
 972     cpu->dtb_compatible = "arm,arm1176";
 973     set_feature(&cpu->env, ARM_FEATURE_V6K);
 974     set_feature(&cpu->env, ARM_FEATURE_VFP);
 975     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 976     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 977     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 978     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 979     set_feature(&cpu->env, ARM_FEATURE_EL3);
 980     cpu->midr = 0x410fb767;
 981     cpu->reset_fpsid = 0x410120b5;
 982     cpu->mvfr0 = 0x11111111;
 983     cpu->mvfr1 = 0x00000000;
 984     cpu->ctr = 0x1dd20d2;
 985     cpu->reset_sctlr = 0x00050078;
 986     cpu->id_pfr0 = 0x111;
 987     cpu->id_pfr1 = 0x11;
 988     cpu->id_dfr0 = 0x33;
 989     cpu->id_afr0 = 0;
 990     cpu->id_mmfr0 = 0x01130003;
 991     cpu->id_mmfr1 = 0x10030302;
 992     cpu->id_mmfr2 = 0x01222100;
 993     cpu->id_isar0 = 0x0140011;
 994     cpu->id_isar1 = 0x12002111;
 995     cpu->id_isar2 = 0x11231121;
 996     cpu->id_isar3 = 0x01102131;
 997     cpu->id_isar4 = 0x01141;
 998     cpu->reset_auxcr = 7;
 999 }
1000
1001 static void arm11mpcore_initfn(Object *obj)
1002 {
1003     ARMCPU *cpu = ARM_CPU(obj);
1004
1005     cpu->dtb_compatible = "arm,arm11mpcore";
1006     set_feature(&cpu->env, ARM_FEATURE_V6K);
1007     set_feature(&cpu->env, ARM_FEATURE_VFP);
1008     set_feature(&cpu->env, ARM_FEATURE_VAPA);
1009     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
1010     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1011     cpu->midr = 0x410fb022;
1012     cpu->reset_fpsid = 0x410120b4;
1013     cpu->mvfr0 = 0x11111111;
1014     cpu->mvfr1 = 0x00000000;
1015     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
1016     cpu->id_pfr0 = 0x111;
1017     cpu->id_pfr1 = 0x1;
1018     cpu->id_dfr0 = 0;
1019     cpu->id_afr0 = 0x2;
1020     cpu->id_mmfr0 = 0x01100103;
1021     cpu->id_mmfr1 = 0x10020302;
1022     cpu->id_mmfr2 = 0x01222000;
1023     cpu->id_isar0 = 0x00100011;
1024     cpu->id_isar1 = 0x12002111;
1025     cpu->id_isar2 = 0x11221011;
1026     cpu->id_isar3 = 0x01102131;
1027     cpu->id_isar4 = 0x141;
1028     cpu->reset_auxcr = 1;
1029 }
1030
1031 static void cortex_m3_initfn(Object *obj)
1032 {
1033     ARMCPU *cpu = ARM_CPU(obj);
1034     set_feature(&cpu->env, ARM_FEATURE_V7);
1035     set_feature(&cpu->env, ARM_FEATURE_M);
1036     cpu->midr = 0x410fc231;
1037 }
1038
1039 static void cortex_m4_initfn(Object *obj)
1040 {
1041     ARMCPU *cpu = ARM_CPU(obj);
1042
1043     set_feature(&cpu->env, ARM_FEATURE_V7);
1044     set_feature(&cpu->env, ARM_FEATURE_M);
1045     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1046     cpu->midr = 0x410fc240; /* r0p0 */
1047 }
1048 static void arm_v7m_class_init(ObjectClass *oc, void *data)
1049 {
1050     CPUClass *cc = CPU_CLASS(oc);
1051
1052 #ifndef CONFIG_USER_ONLY
1053     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1054 #endif
1055
1056     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1057 }
1058
1059 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1060     /* Dummy the TCM region regs for the moment */
1061     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1062       .access = PL1_RW, .type = ARM_CP_CONST },
1063     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1064       .access = PL1_RW, .type = ARM_CP_CONST },
1065     REGINFO_SENTINEL
1066 };
1067
1068 static void cortex_r5_initfn(Object *obj)
1069 {
1070     ARMCPU *cpu = ARM_CPU(obj);
1071
1072     set_feature(&cpu->env, ARM_FEATURE_V7);
1073     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
1074     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1075     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1076     set_feature(&cpu->env, ARM_FEATURE_MPU);
1077     cpu->midr = 0x411fc153; /* r1p3 */
1078     cpu->id_pfr0 = 0x0131;
1079     cpu->id_pfr1 = 0x001;
1080     cpu->id_dfr0 = 0x010400;
1081     cpu->id_afr0 = 0x0;
1082     cpu->id_mmfr0 = 0x0210030;
1083     cpu->id_mmfr1 = 0x00000000;
1084     cpu->id_mmfr2 = 0x01200000;
1085     cpu->id_mmfr3 = 0x0211;
1086     cpu->id_isar0 = 0x2101111;
1087     cpu->id_isar1 = 0x13112111;
1088     cpu->id_isar2 = 0x21232141;
1089     cpu->id_isar3 = 0x01112131;
1090     cpu->id_isar4 = 0x0010142;
1091     cpu->id_isar5 = 0x0;
1092     cpu->mp_is_up = true;
1093     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1094 }
1095
1096 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1097     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1098       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1099     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1100       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1101     REGINFO_SENTINEL
1102 };
1103
1104 static void cortex_a8_initfn(Object *obj)
1105 {
1106     ARMCPU *cpu = ARM_CPU(obj);
1107
1108     cpu->dtb_compatible = "arm,cortex-a8";
1109     set_feature(&cpu->env, ARM_FEATURE_V7);
1110     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1111     set_feature(&cpu->env, ARM_FEATURE_NEON);
1112     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1113     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1114     set_feature(&cpu->env, ARM_FEATURE_EL3);
1115     cpu->midr = 0x410fc080;
1116     cpu->reset_fpsid = 0x410330c0;
1117     cpu->mvfr0 = 0x11110222;
1118     cpu->mvfr1 = 0x00011111;
1119     cpu->ctr = 0x82048004;
1120     cpu->reset_sctlr = 0x00c50078;
1121     cpu->id_pfr0 = 0x1031;
1122     cpu->id_pfr1 = 0x11;
1123     cpu->id_dfr0 = 0x400;
1124     cpu->id_afr0 = 0;
1125     cpu->id_mmfr0 = 0x31100003;
1126     cpu->id_mmfr1 = 0x20000000;
1127     cpu->id_mmfr2 = 0x01202000;
1128     cpu->id_mmfr3 = 0x11;
1129     cpu->id_isar0 = 0x00101111;
1130     cpu->id_isar1 = 0x12112111;
1131     cpu->id_isar2 = 0x21232031;
1132     cpu->id_isar3 = 0x11112131;
1133     cpu->id_isar4 = 0x00111142;
1134     cpu->dbgdidr = 0x15141000;
1135     cpu->clidr = (1 << 27) | (2 << 24) | 3;
1136     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1137     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1138     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1139     cpu->reset_auxcr = 2;
1140     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1141 }
1142
1143 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1144     /* power_control should be set to maximum latency. Again,
1145      * default to 0 and set by private hook
1146      */
1147     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1148       .access = PL1_RW, .resetvalue = 0,
1149       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1150     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1151       .access = PL1_RW, .resetvalue = 0,
1152       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1153     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1154       .access = PL1_RW, .resetvalue = 0,
1155       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1156     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1157       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1158     /* TLB lockdown control */
1159     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1160       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1161     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1162       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1163     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1164       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1165     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1166       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1167     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1168       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1169     REGINFO_SENTINEL
1170 };
1171
1172 static void cortex_a9_initfn(Object *obj)
1173 {
1174     ARMCPU *cpu = ARM_CPU(obj);
1175
1176     cpu->dtb_compatible = "arm,cortex-a9";
1177     set_feature(&cpu->env, ARM_FEATURE_V7);
1178     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1179     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1180     set_feature(&cpu->env, ARM_FEATURE_NEON);
1181     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1182     set_feature(&cpu->env, ARM_FEATURE_EL3);
1183     /* Note that A9 supports the MP extensions even for
1184      * A9UP and single-core A9MP (which are both different
1185      * and valid configurations; we don't model A9UP).
1186      */
1187     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1188     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1189     cpu->midr = 0x410fc090;
1190     cpu->reset_fpsid = 0x41033090;
1191     cpu->mvfr0 = 0x11110222;
1192     cpu->mvfr1 = 0x01111111;
1193     cpu->ctr = 0x80038003;
1194     cpu->reset_sctlr = 0x00c50078;
1195     cpu->id_pfr0 = 0x1031;
1196     cpu->id_pfr1 = 0x11;
1197     cpu->id_dfr0 = 0x000;
1198     cpu->id_afr0 = 0;
1199     cpu->id_mmfr0 = 0x00100103;
1200     cpu->id_mmfr1 = 0x20000000;
1201     cpu->id_mmfr2 = 0x01230000;
1202     cpu->id_mmfr3 = 0x00002111;
1203     cpu->id_isar0 = 0x00101111;
1204     cpu->id_isar1 = 0x13112111;
1205     cpu->id_isar2 = 0x21232041;
1206     cpu->id_isar3 = 0x11112131;
1207     cpu->id_isar4 = 0x00111142;
1208     cpu->dbgdidr = 0x35141000;
1209     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1210     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1211     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1212     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1213 }
1214
1215 #ifndef CONFIG_USER_ONLY
1216 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1217 {
1218     /* Linux wants the number of processors from here.
1219      * Might as well set the interrupt-controller bit too.
1220      */
1221     return ((smp_cpus - 1) << 24) | (1 << 23);
1222 }
1223 #endif
1224
1225 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1226 #ifndef CONFIG_USER_ONLY
1227     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1228       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1229       .writefn = arm_cp_write_ignore, },
1230 #endif
1231     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1232       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1233     REGINFO_SENTINEL
1234 };
1235
1236 static void cortex_a7_initfn(Object *obj)
1237 {
1238     ARMCPU *cpu = ARM_CPU(obj);
1239
1240     cpu->dtb_compatible = "arm,cortex-a7";
1241     set_feature(&cpu->env, ARM_FEATURE_V7);
1242     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1243     set_feature(&cpu->env, ARM_FEATURE_NEON);
1244     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1245     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1246     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1247     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1248     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1249     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1250     set_feature(&cpu->env, ARM_FEATURE_EL3);
1251     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1252     cpu->midr = 0x410fc075;
1253     cpu->reset_fpsid = 0x41023075;
1254     cpu->mvfr0 = 0x10110222;
1255     cpu->mvfr1 = 0x11111111;
1256     cpu->ctr = 0x84448003;
1257     cpu->reset_sctlr = 0x00c50078;
1258     cpu->id_pfr0 = 0x00001131;
1259     cpu->id_pfr1 = 0x00011011;
1260     cpu->id_dfr0 = 0x02010555;
1261     cpu->pmceid0 = 0x00000000;
1262     cpu->pmceid1 = 0x00000000;
1263     cpu->id_afr0 = 0x00000000;
1264     cpu->id_mmfr0 = 0x10101105;
1265     cpu->id_mmfr1 = 0x40000000;
1266     cpu->id_mmfr2 = 0x01240000;
1267     cpu->id_mmfr3 = 0x02102211;
1268     cpu->id_isar0 = 0x01101110;
1269     cpu->id_isar1 = 0x13112111;
1270     cpu->id_isar2 = 0x21232041;
1271     cpu->id_isar3 = 0x11112131;
1272     cpu->id_isar4 = 0x10011142;
1273     cpu->dbgdidr = 0x3515f005;
1274     cpu->clidr = 0x0a200023;
1275     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1276     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1277     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1278     define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
1279 }
1280
1281 static void cortex_a15_initfn(Object *obj)
1282 {
1283     ARMCPU *cpu = ARM_CPU(obj);
1284
1285     cpu->dtb_compatible = "arm,cortex-a15";
1286     set_feature(&cpu->env, ARM_FEATURE_V7);
1287     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1288     set_feature(&cpu->env, ARM_FEATURE_NEON);
1289     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1290     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1291     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1292     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1293     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1294     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1295     set_feature(&cpu->env, ARM_FEATURE_EL3);
1296     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1297     cpu->midr = 0x412fc0f1;
1298     cpu->reset_fpsid = 0x410430f0;
1299     cpu->mvfr0 = 0x10110222;
1300     cpu->mvfr1 = 0x11111111;
1301     cpu->ctr = 0x8444c004;
1302     cpu->reset_sctlr = 0x00c50078;
1303     cpu->id_pfr0 = 0x00001131;
1304     cpu->id_pfr1 = 0x00011011;
1305     cpu->id_dfr0 = 0x02010555;
1306     cpu->pmceid0 = 0x0000000;
1307     cpu->pmceid1 = 0x00000000;
1308     cpu->id_afr0 = 0x00000000;
1309     cpu->id_mmfr0 = 0x10201105;
1310     cpu->id_mmfr1 = 0x20000000;
1311     cpu->id_mmfr2 = 0x01240000;
1312     cpu->id_mmfr3 = 0x02102211;
1313     cpu->id_isar0 = 0x02101110;
1314     cpu->id_isar1 = 0x13112111;
1315     cpu->id_isar2 = 0x21232041;
1316     cpu->id_isar3 = 0x11112131;
1317     cpu->id_isar4 = 0x10011142;
1318     cpu->dbgdidr = 0x3515f021;
1319     cpu->clidr = 0x0a200023;
1320     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1321     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1322     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1323     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1324 }
1325
1326 static void ti925t_initfn(Object *obj)
1327 {
1328     ARMCPU *cpu = ARM_CPU(obj);
1329     set_feature(&cpu->env, ARM_FEATURE_V4T);
1330     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1331     cpu->midr = ARM_CPUID_TI925T;
1332     cpu->ctr = 0x5109149;
1333     cpu->reset_sctlr = 0x00000070;
1334 }
1335
1336 static void sa1100_initfn(Object *obj)
1337 {
1338     ARMCPU *cpu = ARM_CPU(obj);
1339
1340     cpu->dtb_compatible = "intel,sa1100";
1341     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1342     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1343     cpu->midr = 0x4401A11B;
1344     cpu->reset_sctlr = 0x00000070;
1345 }
1346
1347 static void sa1110_initfn(Object *obj)
1348 {
1349     ARMCPU *cpu = ARM_CPU(obj);
1350     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1351     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1352     cpu->midr = 0x6901B119;
1353     cpu->reset_sctlr = 0x00000070;
1354 }
1355
1356 static void pxa250_initfn(Object *obj)
1357 {
1358     ARMCPU *cpu = ARM_CPU(obj);
1359
1360     cpu->dtb_compatible = "marvell,xscale";
1361     set_feature(&cpu->env, ARM_FEATURE_V5);
1362     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1363     cpu->midr = 0x69052100;
1364     cpu->ctr = 0xd172172;
1365     cpu->reset_sctlr = 0x00000078;
1366 }
1367
1368 static void pxa255_initfn(Object *obj)
1369 {
1370     ARMCPU *cpu = ARM_CPU(obj);
1371
1372     cpu->dtb_compatible = "marvell,xscale";
1373     set_feature(&cpu->env, ARM_FEATURE_V5);
1374     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1375     cpu->midr = 0x69052d00;
1376     cpu->ctr = 0xd172172;
1377     cpu->reset_sctlr = 0x00000078;
1378 }
1379
1380 static void pxa260_initfn(Object *obj)
1381 {
1382     ARMCPU *cpu = ARM_CPU(obj);
1383
1384     cpu->dtb_compatible = "marvell,xscale";
1385     set_feature(&cpu->env, ARM_FEATURE_V5);
1386     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1387     cpu->midr = 0x69052903;
1388     cpu->ctr = 0xd172172;
1389     cpu->reset_sctlr = 0x00000078;
1390 }
1391
1392 static void pxa261_initfn(Object *obj)
1393 {
1394     ARMCPU *cpu = ARM_CPU(obj);
1395
1396     cpu->dtb_compatible = "marvell,xscale";
1397     set_feature(&cpu->env, ARM_FEATURE_V5);
1398     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1399     cpu->midr = 0x69052d05;
1400     cpu->ctr = 0xd172172;
1401     cpu->reset_sctlr = 0x00000078;
1402 }
1403
1404 static void pxa262_initfn(Object *obj)
1405 {
1406     ARMCPU *cpu = ARM_CPU(obj);
1407
1408     cpu->dtb_compatible = "marvell,xscale";
1409     set_feature(&cpu->env, ARM_FEATURE_V5);
1410     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1411     cpu->midr = 0x69052d06;
1412     cpu->ctr = 0xd172172;
1413     cpu->reset_sctlr = 0x00000078;
1414 }
1415
1416 static void pxa270a0_initfn(Object *obj)
1417 {
1418     ARMCPU *cpu = ARM_CPU(obj);
1419
1420     cpu->dtb_compatible = "marvell,xscale";
1421     set_feature(&cpu->env, ARM_FEATURE_V5);
1422     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1423     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1424     cpu->midr = 0x69054110;
1425     cpu->ctr = 0xd172172;
1426     cpu->reset_sctlr = 0x00000078;
1427 }
1428
1429 static void pxa270a1_initfn(Object *obj)
1430 {
1431     ARMCPU *cpu = ARM_CPU(obj);
1432
1433     cpu->dtb_compatible = "marvell,xscale";
1434     set_feature(&cpu->env, ARM_FEATURE_V5);
1435     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1436     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1437     cpu->midr = 0x69054111;
1438     cpu->ctr = 0xd172172;
1439     cpu->reset_sctlr = 0x00000078;
1440 }
1441
1442 static void pxa270b0_initfn(Object *obj)
1443 {
1444     ARMCPU *cpu = ARM_CPU(obj);
1445
1446     cpu->dtb_compatible = "marvell,xscale";
1447     set_feature(&cpu->env, ARM_FEATURE_V5);
1448     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1449     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1450     cpu->midr = 0x69054112;
1451     cpu->ctr = 0xd172172;
1452     cpu->reset_sctlr = 0x00000078;
1453 }
1454
1455 static void pxa270b1_initfn(Object *obj)
1456 {
1457     ARMCPU *cpu = ARM_CPU(obj);
1458
1459     cpu->dtb_compatible = "marvell,xscale";
1460     set_feature(&cpu->env, ARM_FEATURE_V5);
1461     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1462     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1463     cpu->midr = 0x69054113;
1464     cpu->ctr = 0xd172172;
1465     cpu->reset_sctlr = 0x00000078;
1466 }
1467
1468 static void pxa270c0_initfn(Object *obj)
1469 {
1470     ARMCPU *cpu = ARM_CPU(obj);
1471
1472     cpu->dtb_compatible = "marvell,xscale";
1473     set_feature(&cpu->env, ARM_FEATURE_V5);
1474     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1475     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1476     cpu->midr = 0x69054114;
1477     cpu->ctr = 0xd172172;
1478     cpu->reset_sctlr = 0x00000078;
1479 }
1480
1481 static void pxa270c5_initfn(Object *obj)
1482 {
1483     ARMCPU *cpu = ARM_CPU(obj);
1484
1485     cpu->dtb_compatible = "marvell,xscale";
1486     set_feature(&cpu->env, ARM_FEATURE_V5);
1487     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1488     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1489     cpu->midr = 0x69054117;
1490     cpu->ctr = 0xd172172;
1491     cpu->reset_sctlr = 0x00000078;
1492 }
1493
1494 #ifdef CONFIG_USER_ONLY
1495 static void arm_any_initfn(Object *obj)
1496 {
1497     ARMCPU *cpu = ARM_CPU(obj);
1498     set_feature(&cpu->env, ARM_FEATURE_V8);
1499     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1500     set_feature(&cpu->env, ARM_FEATURE_NEON);
1501     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1502     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1503     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1504     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1505     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1506     set_feature(&cpu->env, ARM_FEATURE_CRC);
1507     cpu->midr = 0xffffffff;
1508 }
1509 #endif
1510
1511 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1512
1513 typedef struct ARMCPUInfo {
1514     const char *name;
1515     void (*initfn)(Object *obj);
1516     void (*class_init)(ObjectClass *oc, void *data);
1517 } ARMCPUInfo;
1518
1519 static const ARMCPUInfo arm_cpus[] = {
1520 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1521     { .name = "arm926",      .initfn = arm926_initfn },
1522     { .name = "arm946",      .initfn = arm946_initfn },
1523     { .name = "arm1026",     .initfn = arm1026_initfn },
1524     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1525      * older core than plain "arm1136". In particular this does not
1526      * have the v6K features.
1527      */
1528     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1529     { .name = "arm1136",     .initfn = arm1136_initfn },
1530     { .name = "arm1176",     .initfn = arm1176_initfn },
1531     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1532     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1533                              .class_init = arm_v7m_class_init },
1534     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1535                              .class_init = arm_v7m_class_init },
1536     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1537     { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
1538     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1539     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1540     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1541     { .name = "ti925t",      .initfn = ti925t_initfn },
1542     { .name = "sa1100",      .initfn = sa1100_initfn },
1543     { .name = "sa1110",      .initfn = sa1110_initfn },
1544     { .name = "pxa250",      .initfn = pxa250_initfn },
1545     { .name = "pxa255",      .initfn = pxa255_initfn },
1546     { .name = "pxa260",      .initfn = pxa260_initfn },
1547     { .name = "pxa261",      .initfn = pxa261_initfn },
1548     { .name = "pxa262",      .initfn = pxa262_initfn },
1549     /* "pxa270" is an alias for "pxa270-a0" */
1550     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1551     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1552     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1553     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1554     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1555     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1556     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1557 #ifdef CONFIG_USER_ONLY
1558     { .name = "any",         .initfn = arm_any_initfn },
1559 #endif
1560 #endif
1561     { .name = NULL }
1562 };
1563
1564 static Property arm_cpu_properties[] = {
1565     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1566     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1567     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1568     DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
1569                         mp_affinity, ARM64_AFFINITY_INVALID),
1570     DEFINE_PROP_END_OF_LIST()
1571 };
1572
1573 #ifdef CONFIG_USER_ONLY
1574 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1575                                     int mmu_idx)
1576 {
1577     ARMCPU *cpu = ARM_CPU(cs);
1578     CPUARMState *env = &cpu->env;
1579
1580     env->exception.vaddress = address;
1581     if (rw == 2) {
1582         cs->exception_index = EXCP_PREFETCH_ABORT;
1583     } else {
1584         cs->exception_index = EXCP_DATA_ABORT;
1585     }
1586     return 1;
1587 }
1588 #endif
1589
1590 static gchar *arm_gdb_arch_name(CPUState *cs)
1591 {
1592     ARMCPU *cpu = ARM_CPU(cs);
1593     CPUARMState *env = &cpu->env;
1594
1595     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1596         return g_strdup("iwmmxt");
1597     }
1598     return g_strdup("arm");
1599 }
1600
1601 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1602 {
1603     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1604     CPUClass *cc = CPU_CLASS(acc);
1605     DeviceClass *dc = DEVICE_CLASS(oc);
1606
1607     acc->parent_realize = dc->realize;
1608     dc->realize = arm_cpu_realizefn;
1609     dc->props = arm_cpu_properties;
1610
1611     acc->parent_reset = cc->reset;
1612     cc->reset = arm_cpu_reset;
1613
1614     cc->class_by_name = arm_cpu_class_by_name;
1615     cc->has_work = arm_cpu_has_work;
1616     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1617     cc->dump_state = arm_cpu_dump_state;
1618     cc->set_pc = arm_cpu_set_pc;
1619     cc->gdb_read_register = arm_cpu_gdb_read_register;
1620     cc->gdb_write_register = arm_cpu_gdb_write_register;
1621 #ifdef CONFIG_USER_ONLY
1622     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1623 #else
1624     cc->do_interrupt = arm_cpu_do_interrupt;
1625     cc->do_unaligned_access = arm_cpu_do_unaligned_access;
1626     cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
1627     cc->asidx_from_attrs = arm_asidx_from_attrs;
1628     cc->vmsd = &vmstate_arm_cpu;
1629     cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
1630     cc->write_elf64_note = arm_cpu_write_elf64_note;
1631     cc->write_elf32_note = arm_cpu_write_elf32_note;
1632 #endif
1633     cc->gdb_num_core_regs = 26;
1634     cc->gdb_core_xml_file = "arm-core.xml";
1635     cc->gdb_arch_name = arm_gdb_arch_name;
1636     cc->gdb_stop_before_watchpoint = true;
1637     cc->debug_excp_handler = arm_debug_excp_handler;
1638     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
1639 #if !defined(CONFIG_USER_ONLY)
1640     cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
1641 #endif
1642
1643     cc->disas_set_info = arm_disas_set_info;
1644 }
1645
1646 static void cpu_register(const ARMCPUInfo *info)
1647 {
1648     TypeInfo type_info = {
1649         .parent = TYPE_ARM_CPU,
1650         .instance_size = sizeof(ARMCPU),
1651         .instance_init = info->initfn,
1652         .class_size = sizeof(ARMCPUClass),
1653         .class_init = info->class_init,
1654     };
1655
1656     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1657     type_register(&type_info);
1658     g_free((void *)type_info.name);
1659 }
1660
1661 static const TypeInfo arm_cpu_type_info = {
1662     .name = TYPE_ARM_CPU,
1663     .parent = TYPE_CPU,
1664     .instance_size = sizeof(ARMCPU),
1665     .instance_init = arm_cpu_initfn,
1666     .instance_post_init = arm_cpu_post_init,
1667     .instance_finalize = arm_cpu_finalizefn,
1668     .abstract = true,
1669     .class_size = sizeof(ARMCPUClass),
1670     .class_init = arm_cpu_class_init,
1671 };
1672
1673 static void arm_cpu_register_types(void)
1674 {
1675     const ARMCPUInfo *info = arm_cpus;
1676
1677     type_register_static(&arm_cpu_type_info);
1678
1679     while (info->name) {
1680         cpu_register(info);
1681         info++;
1682     }
1683 }
1684
1685 type_init(arm_cpu_register_types)