target/arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "target/arm/idau.h"
  23 #include "qemu/error-report.h"
  24 #include "qapi/error.h"
  25 #include "qapi/visitor.h"
  26 #include "cpu.h"
  27 #include "internals.h"
  28 #include "qemu-common.h"
  29 #include "exec/exec-all.h"
  30 #include "hw/qdev-properties.h"
  31 #if !defined(CONFIG_USER_ONLY)
  32 #include "hw/loader.h"
  33 #endif
  34 #include "hw/arm/arm.h"
  35 #include "sysemu/sysemu.h"
  36 #include "sysemu/hw_accel.h"
  37 #include "kvm_arm.h"
  38 #include "disas/capstone.h"
  39 #include "fpu/softfloat.h"
  40
  41 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  42 {
  43     ARMCPU *cpu = ARM_CPU(cs);
  44     CPUARMState *env = &cpu->env;
  45
  46     if (is_a64(env)) {
  47         env->pc = value;
  48         env->thumb = 0;
  49     } else {
  50         env->regs[15] = value & ~1;
  51         env->thumb = value & 1;
  52     }
  53 }
  54
  55 static void arm_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  56 {
  57     ARMCPU *cpu = ARM_CPU(cs);
  58     CPUARMState *env = &cpu->env;
  59
  60     /*
  61      * It's OK to look at env for the current mode here, because it's
  62      * never possible for an AArch64 TB to chain to an AArch32 TB.
  63      */
  64     if (is_a64(env)) {
  65         env->pc = tb->pc;
  66     } else {
  67         env->regs[15] = tb->pc;
  68     }
  69 }
  70
  71 static bool arm_cpu_has_work(CPUState *cs)
  72 {
  73     ARMCPU *cpu = ARM_CPU(cs);
  74
  75     return (cpu->power_state != PSCI_OFF)
  76         && cs->interrupt_request &
  77         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  78          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  79          | CPU_INTERRUPT_EXITTB);
  80 }
  81
  82 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
  83                                  void *opaque)
  84 {
  85     ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
  86
  87     entry->hook = hook;
  88     entry->opaque = opaque;
  89
  90     QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
  91 }
  92
  93 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
  94                                  void *opaque)
  95 {
  96     ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
  97
  98     entry->hook = hook;
  99     entry->opaque = opaque;
 100
 101     QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
 102 }
 103
 104 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
 105 {
 106     /* Reset a single ARMCPRegInfo register */
 107     ARMCPRegInfo *ri = value;
 108     ARMCPU *cpu = opaque;
 109
 110     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
 111         return;
 112     }
 113
 114     if (ri->resetfn) {
 115         ri->resetfn(&cpu->env, ri);
 116         return;
 117     }
 118
 119     /* A zero offset is never possible as it would be regs[0]
 120      * so we use it to indicate that reset is being handled elsewhere.
 121      * This is basically only used for fields in non-core coprocessors
 122      * (like the pxa2xx ones).
 123      */
 124     if (!ri->fieldoffset) {
 125         return;
 126     }
 127
 128     if (cpreg_field_is_64bit(ri)) {
 129         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
 130     } else {
 131         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
 132     }
 133 }
 134
 135 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
 136 {
 137     /* Purely an assertion check: we've already done reset once,
 138      * so now check that running the reset for the cpreg doesn't
 139      * change its value. This traps bugs where two different cpregs
 140      * both try to reset the same state field but to different values.
 141      */
 142     ARMCPRegInfo *ri = value;
 143     ARMCPU *cpu = opaque;
 144     uint64_t oldvalue, newvalue;
 145
 146     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
 147         return;
 148     }
 149
 150     oldvalue = read_raw_cp_reg(&cpu->env, ri);
 151     cp_reg_reset(key, value, opaque);
 152     newvalue = read_raw_cp_reg(&cpu->env, ri);
 153     assert(oldvalue == newvalue);
 154 }
 155
 156 /* CPUClass::reset() */
 157 static void arm_cpu_reset(CPUState *s)
 158 {
 159     ARMCPU *cpu = ARM_CPU(s);
 160     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 161     CPUARMState *env = &cpu->env;
 162
 163     acc->parent_reset(s);
 164
 165     memset(env, 0, offsetof(CPUARMState, end_reset_fields));
 166
 167     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
 168     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 169
 170     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
 171     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->isar.mvfr0;
 172     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->isar.mvfr1;
 173     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->isar.mvfr2;
 174
 175     cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
 176     s->halted = cpu->start_powered_off;
 177
 178     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 179         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 180     }
 181
 182     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 183         /* 64 bit CPUs always start in 64 bit mode */
 184         env->aarch64 = 1;
 185 #if defined(CONFIG_USER_ONLY)
 186         env->pstate = PSTATE_MODE_EL0t;
 187         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 188         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 189         /* Enable all PAC keys.  */
 190         env->cp15.sctlr_el[1] |= (SCTLR_EnIA | SCTLR_EnIB |
 191                                   SCTLR_EnDA | SCTLR_EnDB);
 192         /* Enable all PAC instructions */
 193         env->cp15.hcr_el2 |= HCR_API;
 194         env->cp15.scr_el3 |= SCR_API;
 195         /* and to the FP/Neon instructions */
 196         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 197         /* and to the SVE instructions */
 198         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
 199         env->cp15.cptr_el[3] |= CPTR_EZ;
 200         /* with maximum vector length */
 201         env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
 202         env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
 203         env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
 204         /*
 205          * Enable TBI0 and TBI1.  While the real kernel only enables TBI0,
 206          * turning on both here will produce smaller code and otherwise
 207          * make no difference to the user-level emulation.
 208          */
 209         env->cp15.tcr_el[1].raw_tcr = (3ULL << 37);
 210 #else
 211         /* Reset into the highest available EL */
 212         if (arm_feature(env, ARM_FEATURE_EL3)) {
 213             env->pstate = PSTATE_MODE_EL3h;
 214         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 215             env->pstate = PSTATE_MODE_EL2h;
 216         } else {
 217             env->pstate = PSTATE_MODE_EL1h;
 218         }
 219         env->pc = cpu->rvbar;
 220 #endif
 221     } else {
 222 #if defined(CONFIG_USER_ONLY)
 223         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 224         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 225 #endif
 226     }
 227
 228 #if defined(CONFIG_USER_ONLY)
 229     env->uncached_cpsr = ARM_CPU_MODE_USR;
 230     /* For user mode we must enable access to coprocessors */
 231     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 232     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 233         env->cp15.c15_cpar = 3;
 234     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 235         env->cp15.c15_cpar = 1;
 236     }
 237 #else
 238
 239     /*
 240      * If the highest available EL is EL2, AArch32 will start in Hyp
 241      * mode; otherwise it starts in SVC. Note that if we start in
 242      * AArch64 then these values in the uncached_cpsr will be ignored.
 243      */
 244     if (arm_feature(env, ARM_FEATURE_EL2) &&
 245         !arm_feature(env, ARM_FEATURE_EL3)) {
 246         env->uncached_cpsr = ARM_CPU_MODE_HYP;
 247     } else {
 248         env->uncached_cpsr = ARM_CPU_MODE_SVC;
 249     }
 250     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 251
 252     if (arm_feature(env, ARM_FEATURE_M)) {
 253         uint32_t initial_msp; /* Loaded from 0x0 */
 254         uint32_t initial_pc; /* Loaded from 0x4 */
 255         uint8_t *rom;
 256         uint32_t vecbase;
 257
 258         if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 259             env->v7m.secure = true;
 260         } else {
 261             /* This bit resets to 0 if security is supported, but 1 if
 262              * it is not. The bit is not present in v7M, but we set it
 263              * here so we can avoid having to make checks on it conditional
 264              * on ARM_FEATURE_V8 (we don't let the guest see the bit).
 265              */
 266             env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
 267         }
 268
 269         /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
 270          * that it resets to 1, so QEMU always does that rather than making
 271          * it dependent on CPU model. In v8M it is RES1.
 272          */
 273         env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
 274         env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
 275         if (arm_feature(env, ARM_FEATURE_V8)) {
 276             /* in v8M the NONBASETHRDENA bit [0] is RES1 */
 277             env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
 278             env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
 279         }
 280         if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
 281             env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
 282             env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
 283         }
 284
 285         /* Unlike A/R profile, M profile defines the reset LR value */
 286         env->regs[14] = 0xffffffff;
 287
 288         env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
 289
 290         /* Load the initial SP and PC from offset 0 and 4 in the vector table */
 291         vecbase = env->v7m.vecbase[env->v7m.secure];
 292         rom = rom_ptr(vecbase, 8);
 293         if (rom) {
 294             /* Address zero is covered by ROM which hasn't yet been
 295              * copied into physical memory.
 296              */
 297             initial_msp = ldl_p(rom);
 298             initial_pc = ldl_p(rom + 4);
 299         } else {
 300             /* Address zero not covered by a ROM blob, or the ROM blob
 301              * is in non-modifiable memory and this is a second reset after
 302              * it got copied into memory. In the latter case, rom_ptr
 303              * will return a NULL pointer and we should use ldl_phys instead.
 304              */
 305             initial_msp = ldl_phys(s->as, vecbase);
 306             initial_pc = ldl_phys(s->as, vecbase + 4);
 307         }
 308
 309         env->regs[13] = initial_msp & 0xFFFFFFFC;
 310         env->regs[15] = initial_pc & ~1;
 311         env->thumb = initial_pc & 1;
 312     }
 313
 314     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 315      * executing as AArch32 then check if highvecs are enabled and
 316      * adjust the PC accordingly.
 317      */
 318     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 319         env->regs[15] = 0xFFFF0000;
 320     }
 321
 322     /* M profile requires that reset clears the exclusive monitor;
 323      * A profile does not, but clearing it makes more sense than having it
 324      * set with an exclusive access on address zero.
 325      */
 326     arm_clear_exclusive(env);
 327
 328     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 329 #endif
 330
 331     if (arm_feature(env, ARM_FEATURE_PMSA)) {
 332         if (cpu->pmsav7_dregion > 0) {
 333             if (arm_feature(env, ARM_FEATURE_V8)) {
 334                 memset(env->pmsav8.rbar[M_REG_NS], 0,
 335                        sizeof(*env->pmsav8.rbar[M_REG_NS])
 336                        * cpu->pmsav7_dregion);
 337                 memset(env->pmsav8.rlar[M_REG_NS], 0,
 338                        sizeof(*env->pmsav8.rlar[M_REG_NS])
 339                        * cpu->pmsav7_dregion);
 340                 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 341                     memset(env->pmsav8.rbar[M_REG_S], 0,
 342                            sizeof(*env->pmsav8.rbar[M_REG_S])
 343                            * cpu->pmsav7_dregion);
 344                     memset(env->pmsav8.rlar[M_REG_S], 0,
 345                            sizeof(*env->pmsav8.rlar[M_REG_S])
 346                            * cpu->pmsav7_dregion);
 347                 }
 348             } else if (arm_feature(env, ARM_FEATURE_V7)) {
 349                 memset(env->pmsav7.drbar, 0,
 350                        sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
 351                 memset(env->pmsav7.drsr, 0,
 352                        sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
 353                 memset(env->pmsav7.dracr, 0,
 354                        sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
 355             }
 356         }
 357         env->pmsav7.rnr[M_REG_NS] = 0;
 358         env->pmsav7.rnr[M_REG_S] = 0;
 359         env->pmsav8.mair0[M_REG_NS] = 0;
 360         env->pmsav8.mair0[M_REG_S] = 0;
 361         env->pmsav8.mair1[M_REG_NS] = 0;
 362         env->pmsav8.mair1[M_REG_S] = 0;
 363     }
 364
 365     if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
 366         if (cpu->sau_sregion > 0) {
 367             memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
 368             memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
 369         }
 370         env->sau.rnr = 0;
 371         /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
 372          * the Cortex-M33 does.
 373          */
 374         env->sau.ctrl = 0;
 375     }
 376
 377     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 378     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 379     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 380     set_float_detect_tininess(float_tininess_before_rounding,
 381                               &env->vfp.fp_status);
 382     set_float_detect_tininess(float_tininess_before_rounding,
 383                               &env->vfp.standard_fp_status);
 384     set_float_detect_tininess(float_tininess_before_rounding,
 385                               &env->vfp.fp_status_f16);
 386 #ifndef CONFIG_USER_ONLY
 387     if (kvm_enabled()) {
 388         kvm_arm_reset_vcpu(cpu);
 389     }
 390 #endif
 391
 392     hw_breakpoint_update_all(cpu);
 393     hw_watchpoint_update_all(cpu);
 394 }
 395
 396 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 397 {
 398     CPUClass *cc = CPU_GET_CLASS(cs);
 399     CPUARMState *env = cs->env_ptr;
 400     uint32_t cur_el = arm_current_el(env);
 401     bool secure = arm_is_secure(env);
 402     uint32_t target_el;
 403     uint32_t excp_idx;
 404     bool ret = false;
 405
 406     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 407         excp_idx = EXCP_FIQ;
 408         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 409         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 410             cs->exception_index = excp_idx;
 411             env->exception.target_el = target_el;
 412             cc->do_interrupt(cs);
 413             ret = true;
 414         }
 415     }
 416     if (interrupt_request & CPU_INTERRUPT_HARD) {
 417         excp_idx = EXCP_IRQ;
 418         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 419         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 420             cs->exception_index = excp_idx;
 421             env->exception.target_el = target_el;
 422             cc->do_interrupt(cs);
 423             ret = true;
 424         }
 425     }
 426     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 427         excp_idx = EXCP_VIRQ;
 428         target_el = 1;
 429         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 430             cs->exception_index = excp_idx;
 431             env->exception.target_el = target_el;
 432             cc->do_interrupt(cs);
 433             ret = true;
 434         }
 435     }
 436     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 437         excp_idx = EXCP_VFIQ;
 438         target_el = 1;
 439         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 440             cs->exception_index = excp_idx;
 441             env->exception.target_el = target_el;
 442             cc->do_interrupt(cs);
 443             ret = true;
 444         }
 445     }
 446
 447     return ret;
 448 }
 449
 450 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 451 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 452 {
 453     CPUClass *cc = CPU_GET_CLASS(cs);
 454     ARMCPU *cpu = ARM_CPU(cs);
 455     CPUARMState *env = &cpu->env;
 456     bool ret = false;
 457
 458     /* ARMv7-M interrupt masking works differently than -A or -R.
 459      * There is no FIQ/IRQ distinction. Instead of I and F bits
 460      * masking FIQ and IRQ interrupts, an exception is taken only
 461      * if it is higher priority than the current execution priority
 462      * (which depends on state like BASEPRI, FAULTMASK and the
 463      * currently active exception).
 464      */
 465     if (interrupt_request & CPU_INTERRUPT_HARD
 466         && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
 467         cs->exception_index = EXCP_IRQ;
 468         cc->do_interrupt(cs);
 469         ret = true;
 470     }
 471     return ret;
 472 }
 473 #endif
 474
 475 void arm_cpu_update_virq(ARMCPU *cpu)
 476 {
 477     /*
 478      * Update the interrupt level for VIRQ, which is the logical OR of
 479      * the HCR_EL2.VI bit and the input line level from the GIC.
 480      */
 481     CPUARMState *env = &cpu->env;
 482     CPUState *cs = CPU(cpu);
 483
 484     bool new_state = (env->cp15.hcr_el2 & HCR_VI) ||
 485         (env->irq_line_state & CPU_INTERRUPT_VIRQ);
 486
 487     if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) != 0)) {
 488         if (new_state) {
 489             cpu_interrupt(cs, CPU_INTERRUPT_VIRQ);
 490         } else {
 491             cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ);
 492         }
 493     }
 494 }
 495
 496 void arm_cpu_update_vfiq(ARMCPU *cpu)
 497 {
 498     /*
 499      * Update the interrupt level for VFIQ, which is the logical OR of
 500      * the HCR_EL2.VF bit and the input line level from the GIC.
 501      */
 502     CPUARMState *env = &cpu->env;
 503     CPUState *cs = CPU(cpu);
 504
 505     bool new_state = (env->cp15.hcr_el2 & HCR_VF) ||
 506         (env->irq_line_state & CPU_INTERRUPT_VFIQ);
 507
 508     if (new_state != ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) != 0)) {
 509         if (new_state) {
 510             cpu_interrupt(cs, CPU_INTERRUPT_VFIQ);
 511         } else {
 512             cpu_reset_interrupt(cs, CPU_INTERRUPT_VFIQ);
 513         }
 514     }
 515 }
 516
 517 #ifndef CONFIG_USER_ONLY
 518 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 519 {
 520     ARMCPU *cpu = opaque;
 521     CPUARMState *env = &cpu->env;
 522     CPUState *cs = CPU(cpu);
 523     static const int mask[] = {
 524         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 525         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 526         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 527         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 528     };
 529
 530     if (level) {
 531         env->irq_line_state |= mask[irq];
 532     } else {
 533         env->irq_line_state &= ~mask[irq];
 534     }
 535
 536     switch (irq) {
 537     case ARM_CPU_VIRQ:
 538         assert(arm_feature(env, ARM_FEATURE_EL2));
 539         arm_cpu_update_virq(cpu);
 540         break;
 541     case ARM_CPU_VFIQ:
 542         assert(arm_feature(env, ARM_FEATURE_EL2));
 543         arm_cpu_update_vfiq(cpu);
 544         break;
 545     case ARM_CPU_IRQ:
 546     case ARM_CPU_FIQ:
 547         if (level) {
 548             cpu_interrupt(cs, mask[irq]);
 549         } else {
 550             cpu_reset_interrupt(cs, mask[irq]);
 551         }
 552         break;
 553     default:
 554         g_assert_not_reached();
 555     }
 556 }
 557
 558 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 559 {
 560 #ifdef CONFIG_KVM
 561     ARMCPU *cpu = opaque;
 562     CPUARMState *env = &cpu->env;
 563     CPUState *cs = CPU(cpu);
 564     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 565     uint32_t linestate_bit;
 566
 567     switch (irq) {
 568     case ARM_CPU_IRQ:
 569         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 570         linestate_bit = CPU_INTERRUPT_HARD;
 571         break;
 572     case ARM_CPU_FIQ:
 573         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 574         linestate_bit = CPU_INTERRUPT_FIQ;
 575         break;
 576     default:
 577         g_assert_not_reached();
 578     }
 579
 580     if (level) {
 581         env->irq_line_state |= linestate_bit;
 582     } else {
 583         env->irq_line_state &= ~linestate_bit;
 584     }
 585
 586     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 587     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 588 #endif
 589 }
 590
 591 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
 592 {
 593     ARMCPU *cpu = ARM_CPU(cs);
 594     CPUARMState *env = &cpu->env;
 595
 596     cpu_synchronize_state(cs);
 597     return arm_cpu_data_is_big_endian(env);
 598 }
 599
 600 #endif
 601
 602 static inline void set_feature(CPUARMState *env, int feature)
 603 {
 604     env->features |= 1ULL << feature;
 605 }
 606
 607 static inline void unset_feature(CPUARMState *env, int feature)
 608 {
 609     env->features &= ~(1ULL << feature);
 610 }
 611
 612 static int
 613 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 614 {
 615   return print_insn_arm(pc | 1, info);
 616 }
 617
 618 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 619 {
 620     ARMCPU *ac = ARM_CPU(cpu);
 621     CPUARMState *env = &ac->env;
 622     bool sctlr_b;
 623
 624     if (is_a64(env)) {
 625         /* We might not be compiled with the A64 disassembler
 626          * because it needs a C++ compiler. Leave print_insn
 627          * unset in this case to use the caller default behaviour.
 628          */
 629 #if defined(CONFIG_ARM_A64_DIS)
 630         info->print_insn = print_insn_arm_a64;
 631 #endif
 632         info->cap_arch = CS_ARCH_ARM64;
 633         info->cap_insn_unit = 4;
 634         info->cap_insn_split = 4;
 635     } else {
 636         int cap_mode;
 637         if (env->thumb) {
 638             info->print_insn = print_insn_thumb1;
 639             info->cap_insn_unit = 2;
 640             info->cap_insn_split = 4;
 641             cap_mode = CS_MODE_THUMB;
 642         } else {
 643             info->print_insn = print_insn_arm;
 644             info->cap_insn_unit = 4;
 645             info->cap_insn_split = 4;
 646             cap_mode = CS_MODE_ARM;
 647         }
 648         if (arm_feature(env, ARM_FEATURE_V8)) {
 649             cap_mode |= CS_MODE_V8;
 650         }
 651         if (arm_feature(env, ARM_FEATURE_M)) {
 652             cap_mode |= CS_MODE_MCLASS;
 653         }
 654         info->cap_arch = CS_ARCH_ARM;
 655         info->cap_mode = cap_mode;
 656     }
 657
 658     sctlr_b = arm_sctlr_b(env);
 659     if (bswap_code(sctlr_b)) {
 660 #ifdef TARGET_WORDS_BIGENDIAN
 661         info->endian = BFD_ENDIAN_LITTLE;
 662 #else
 663         info->endian = BFD_ENDIAN_BIG;
 664 #endif
 665     }
 666     info->flags &= ~INSN_ARM_BE32;
 667 #ifndef CONFIG_USER_ONLY
 668     if (sctlr_b) {
 669         info->flags |= INSN_ARM_BE32;
 670     }
 671 #endif
 672 }
 673
 674 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
 675 {
 676     uint32_t Aff1 = idx / clustersz;
 677     uint32_t Aff0 = idx % clustersz;
 678     return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 679 }
 680
 681 static void cpreg_hashtable_data_destroy(gpointer data)
 682 {
 683     /*
 684      * Destroy function for cpu->cp_regs hashtable data entries.
 685      * We must free the name string because it was g_strdup()ed in
 686      * add_cpreg_to_hashtable(). It's OK to cast away the 'const'
 687      * from r->name because we know we definitely allocated it.
 688      */
 689     ARMCPRegInfo *r = data;
 690
 691     g_free((void *)r->name);
 692     g_free(r);
 693 }
 694
 695 static void arm_cpu_initfn(Object *obj)
 696 {
 697     CPUState *cs = CPU(obj);
 698     ARMCPU *cpu = ARM_CPU(obj);
 699
 700     cs->env_ptr = &cpu->env;
 701     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 702                                          g_free, cpreg_hashtable_data_destroy);
 703
 704     QLIST_INIT(&cpu->pre_el_change_hooks);
 705     QLIST_INIT(&cpu->el_change_hooks);
 706
 707 #ifndef CONFIG_USER_ONLY
 708     /* Our inbound IRQ and FIQ lines */
 709     if (kvm_enabled()) {
 710         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 711          * the same interface as non-KVM CPUs.
 712          */
 713         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 714     } else {
 715         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 716     }
 717
 718     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 719                        ARRAY_SIZE(cpu->gt_timer_outputs));
 720
 721     qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
 722                              "gicv3-maintenance-interrupt", 1);
 723     qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
 724                              "pmu-interrupt", 1);
 725 #endif
 726
 727     /* DTB consumers generally don't in fact care what the 'compatible'
 728      * string is, so always provide some string and trust that a hypothetical
 729      * picky DTB consumer will also provide a helpful error message.
 730      */
 731     cpu->dtb_compatible = "qemu,unknown";
 732     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 733     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 734
 735     if (tcg_enabled()) {
 736         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 737     }
 738 }
 739
 740 static Property arm_cpu_reset_cbar_property =
 741             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 742
 743 static Property arm_cpu_reset_hivecs_property =
 744             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 745
 746 static Property arm_cpu_rvbar_property =
 747             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 748
 749 static Property arm_cpu_has_el2_property =
 750             DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
 751
 752 static Property arm_cpu_has_el3_property =
 753             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 754
 755 static Property arm_cpu_cfgend_property =
 756             DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
 757
 758 /* use property name "pmu" to match other archs and virt tools */
 759 static Property arm_cpu_has_pmu_property =
 760             DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
 761
 762 static Property arm_cpu_has_mpu_property =
 763             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 764
 765 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
 766  * because the CPU initfn will have already set cpu->pmsav7_dregion to
 767  * the right value for that particular CPU type, and we don't want
 768  * to override that with an incorrect constant value.
 769  */
 770 static Property arm_cpu_pmsav7_dregion_property =
 771             DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
 772                                            pmsav7_dregion,
 773                                            qdev_prop_uint32, uint32_t);
 774
 775 static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
 776                                void *opaque, Error **errp)
 777 {
 778     ARMCPU *cpu = ARM_CPU(obj);
 779
 780     visit_type_uint32(v, name, &cpu->init_svtor, errp);
 781 }
 782
 783 static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
 784                                void *opaque, Error **errp)
 785 {
 786     ARMCPU *cpu = ARM_CPU(obj);
 787
 788     visit_type_uint32(v, name, &cpu->init_svtor, errp);
 789 }
 790
 791 void arm_cpu_post_init(Object *obj)
 792 {
 793     ARMCPU *cpu = ARM_CPU(obj);
 794
 795     /* M profile implies PMSA. We have to do this here rather than
 796      * in realize with the other feature-implication checks because
 797      * we look at the PMSA bit to see if we should add some properties.
 798      */
 799     if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
 800         set_feature(&cpu->env, ARM_FEATURE_PMSA);
 801     }
 802
 803     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 804         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 805         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 806                                  &error_abort);
 807     }
 808
 809     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 810         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 811                                  &error_abort);
 812     }
 813
 814     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 815         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 816                                  &error_abort);
 817     }
 818
 819     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 820         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 821          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 822          */
 823         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 824                                  &error_abort);
 825
 826 #ifndef CONFIG_USER_ONLY
 827         object_property_add_link(obj, "secure-memory",
 828                                  TYPE_MEMORY_REGION,
 829                                  (Object **)&cpu->secure_memory,
 830                                  qdev_prop_allow_set_link_before_realize,
 831                                  OBJ_PROP_LINK_STRONG,
 832                                  &error_abort);
 833 #endif
 834     }
 835
 836     if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
 837         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
 838                                  &error_abort);
 839     }
 840
 841     if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
 842         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
 843                                  &error_abort);
 844     }
 845
 846     if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
 847         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 848                                  &error_abort);
 849         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 850             qdev_property_add_static(DEVICE(obj),
 851                                      &arm_cpu_pmsav7_dregion_property,
 852                                      &error_abort);
 853         }
 854     }
 855
 856     if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
 857         object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
 858                                  qdev_prop_allow_set_link_before_realize,
 859                                  OBJ_PROP_LINK_STRONG,
 860                                  &error_abort);
 861         /*
 862          * M profile: initial value of the Secure VTOR. We can't just use
 863          * a simple DEFINE_PROP_UINT32 for this because we want to permit
 864          * the property to be set after realize.
 865          */
 866         object_property_add(obj, "init-svtor", "uint32",
 867                             arm_get_init_svtor, arm_set_init_svtor,
 868                             NULL, NULL, &error_abort);
 869     }
 870
 871     qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
 872                              &error_abort);
 873 }
 874
 875 static void arm_cpu_finalizefn(Object *obj)
 876 {
 877     ARMCPU *cpu = ARM_CPU(obj);
 878     ARMELChangeHook *hook, *next;
 879
 880     g_hash_table_destroy(cpu->cp_regs);
 881
 882     QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
 883         QLIST_REMOVE(hook, node);
 884         g_free(hook);
 885     }
 886     QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
 887         QLIST_REMOVE(hook, node);
 888         g_free(hook);
 889     }
 890 #ifndef CONFIG_USER_ONLY
 891     if (cpu->pmu_timer) {
 892         timer_del(cpu->pmu_timer);
 893         timer_deinit(cpu->pmu_timer);
 894         timer_free(cpu->pmu_timer);
 895     }
 896 #endif
 897 }
 898
 899 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 900 {
 901     CPUState *cs = CPU(dev);
 902     ARMCPU *cpu = ARM_CPU(dev);
 903     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 904     CPUARMState *env = &cpu->env;
 905     int pagebits;
 906     Error *local_err = NULL;
 907     bool no_aa32 = false;
 908
 909     /* If we needed to query the host kernel for the CPU features
 910      * then it's possible that might have failed in the initfn, but
 911      * this is the first point where we can report it.
 912      */
 913     if (cpu->host_cpu_probe_failed) {
 914         if (!kvm_enabled()) {
 915             error_setg(errp, "The 'host' CPU type can only be used with KVM");
 916         } else {
 917             error_setg(errp, "Failed to retrieve host CPU features");
 918         }
 919         return;
 920     }
 921
 922 #ifndef CONFIG_USER_ONLY
 923     /* The NVIC and M-profile CPU are two halves of a single piece of
 924      * hardware; trying to use one without the other is a command line
 925      * error and will result in segfaults if not caught here.
 926      */
 927     if (arm_feature(env, ARM_FEATURE_M)) {
 928         if (!env->nvic) {
 929             error_setg(errp, "This board cannot be used with Cortex-M CPUs");
 930             return;
 931         }
 932     } else {
 933         if (env->nvic) {
 934             error_setg(errp, "This board can only be used with Cortex-M CPUs");
 935             return;
 936         }
 937     }
 938
 939     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 940                                            arm_gt_ptimer_cb, cpu);
 941     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 942                                            arm_gt_vtimer_cb, cpu);
 943     cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 944                                           arm_gt_htimer_cb, cpu);
 945     cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 946                                           arm_gt_stimer_cb, cpu);
 947 #endif
 948
 949     cpu_exec_realizefn(cs, &local_err);
 950     if (local_err != NULL) {
 951         error_propagate(errp, local_err);
 952         return;
 953     }
 954
 955     /* Some features automatically imply others: */
 956     if (arm_feature(env, ARM_FEATURE_V8)) {
 957         if (arm_feature(env, ARM_FEATURE_M)) {
 958             set_feature(env, ARM_FEATURE_V7);
 959         } else {
 960             set_feature(env, ARM_FEATURE_V7VE);
 961         }
 962     }
 963
 964     /*
 965      * There exist AArch64 cpus without AArch32 support.  When KVM
 966      * queries ID_ISAR0_EL1 on such a host, the value is UNKNOWN.
 967      * Similarly, we cannot check ID_AA64PFR0 without AArch64 support.
 968      */
 969     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 970         no_aa32 = !cpu_isar_feature(aa64_aa32, cpu);
 971     }
 972
 973     if (arm_feature(env, ARM_FEATURE_V7VE)) {
 974         /* v7 Virtualization Extensions. In real hardware this implies
 975          * EL2 and also the presence of the Security Extensions.
 976          * For QEMU, for backwards-compatibility we implement some
 977          * CPUs or CPU configs which have no actual EL2 or EL3 but do
 978          * include the various other features that V7VE implies.
 979          * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
 980          * Security Extensions is ARM_FEATURE_EL3.
 981          */
 982         assert(no_aa32 || cpu_isar_feature(arm_div, cpu));
 983         set_feature(env, ARM_FEATURE_LPAE);
 984         set_feature(env, ARM_FEATURE_V7);
 985     }
 986     if (arm_feature(env, ARM_FEATURE_V7)) {
 987         set_feature(env, ARM_FEATURE_VAPA);
 988         set_feature(env, ARM_FEATURE_THUMB2);
 989         set_feature(env, ARM_FEATURE_MPIDR);
 990         if (!arm_feature(env, ARM_FEATURE_M)) {
 991             set_feature(env, ARM_FEATURE_V6K);
 992         } else {
 993             set_feature(env, ARM_FEATURE_V6);
 994         }
 995
 996         /* Always define VBAR for V7 CPUs even if it doesn't exist in
 997          * non-EL3 configs. This is needed by some legacy boards.
 998          */
 999         set_feature(env, ARM_FEATURE_VBAR);
1000     }
1001     if (arm_feature(env, ARM_FEATURE_V6K)) {
1002         set_feature(env, ARM_FEATURE_V6);
1003         set_feature(env, ARM_FEATURE_MVFR);
1004     }
1005     if (arm_feature(env, ARM_FEATURE_V6)) {
1006         set_feature(env, ARM_FEATURE_V5);
1007         if (!arm_feature(env, ARM_FEATURE_M)) {
1008             assert(no_aa32 || cpu_isar_feature(jazelle, cpu));
1009             set_feature(env, ARM_FEATURE_AUXCR);
1010         }
1011     }
1012     if (arm_feature(env, ARM_FEATURE_V5)) {
1013         set_feature(env, ARM_FEATURE_V4T);
1014     }
1015     if (arm_feature(env, ARM_FEATURE_VFP4)) {
1016         set_feature(env, ARM_FEATURE_VFP3);
1017     }
1018     if (arm_feature(env, ARM_FEATURE_VFP3)) {
1019         set_feature(env, ARM_FEATURE_VFP);
1020     }
1021     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1022         set_feature(env, ARM_FEATURE_V7MP);
1023         set_feature(env, ARM_FEATURE_PXN);
1024     }
1025     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
1026         set_feature(env, ARM_FEATURE_CBAR);
1027     }
1028     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
1029         !arm_feature(env, ARM_FEATURE_M)) {
1030         set_feature(env, ARM_FEATURE_THUMB_DSP);
1031     }
1032
1033     if (arm_feature(env, ARM_FEATURE_V7) &&
1034         !arm_feature(env, ARM_FEATURE_M) &&
1035         !arm_feature(env, ARM_FEATURE_PMSA)) {
1036         /* v7VMSA drops support for the old ARMv5 tiny pages, so we
1037          * can use 4K pages.
1038          */
1039         pagebits = 12;
1040     } else {
1041         /* For CPUs which might have tiny 1K pages, or which have an
1042          * MPU and might have small region sizes, stick with 1K pages.
1043          */
1044         pagebits = 10;
1045     }
1046     if (!set_preferred_target_page_bits(pagebits)) {
1047         /* This can only ever happen for hotplugging a CPU, or if
1048          * the board code incorrectly creates a CPU which it has
1049          * promised via minimum_page_size that it will not.
1050          */
1051         error_setg(errp, "This CPU requires a smaller page size than the "
1052                    "system is using");
1053         return;
1054     }
1055
1056     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
1057      * We don't support setting cluster ID ([16..23]) (known as Aff2
1058      * in later ARM ARM versions), or any of the higher affinity level fields,
1059      * so these bits always RAZ.
1060      */
1061     if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
1062         cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
1063                                                ARM_DEFAULT_CPUS_PER_CLUSTER);
1064     }
1065
1066     if (cpu->reset_hivecs) {
1067             cpu->reset_sctlr |= (1 << 13);
1068     }
1069
1070     if (cpu->cfgend) {
1071         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
1072             cpu->reset_sctlr |= SCTLR_EE;
1073         } else {
1074             cpu->reset_sctlr |= SCTLR_B;
1075         }
1076     }
1077
1078     if (!cpu->has_el3) {
1079         /* If the has_el3 CPU property is disabled then we need to disable the
1080          * feature.
1081          */
1082         unset_feature(env, ARM_FEATURE_EL3);
1083
1084         /* Disable the security extension feature bits in the processor feature
1085          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
1086          */
1087         cpu->id_pfr1 &= ~0xf0;
1088         cpu->isar.id_aa64pfr0 &= ~0xf000;
1089     }
1090
1091     if (!cpu->has_el2) {
1092         unset_feature(env, ARM_FEATURE_EL2);
1093     }
1094
1095     if (!cpu->has_pmu) {
1096         unset_feature(env, ARM_FEATURE_PMU);
1097     }
1098     if (arm_feature(env, ARM_FEATURE_PMU)) {
1099         pmu_init(cpu);
1100
1101         if (!kvm_enabled()) {
1102             arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
1103             arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
1104         }
1105
1106 #ifndef CONFIG_USER_ONLY
1107         cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, arm_pmu_timer_cb,
1108                 cpu);
1109 #endif
1110     } else {
1111         cpu->id_aa64dfr0 &= ~0xf00;
1112         cpu->id_dfr0 &= ~(0xf << 24);
1113         cpu->pmceid0 = 0;
1114         cpu->pmceid1 = 0;
1115     }
1116
1117     if (!arm_feature(env, ARM_FEATURE_EL2)) {
1118         /* Disable the hypervisor feature bits in the processor feature
1119          * registers if we don't have EL2. These are id_pfr1[15:12] and
1120          * id_aa64pfr0_el1[11:8].
1121          */
1122         cpu->isar.id_aa64pfr0 &= ~0xf00;
1123         cpu->id_pfr1 &= ~0xf000;
1124     }
1125
1126     /* MPU can be configured out of a PMSA CPU either by setting has-mpu
1127      * to false or by setting pmsav7-dregion to 0.
1128      */
1129     if (!cpu->has_mpu) {
1130         cpu->pmsav7_dregion = 0;
1131     }
1132     if (cpu->pmsav7_dregion == 0) {
1133         cpu->has_mpu = false;
1134     }
1135
1136     if (arm_feature(env, ARM_FEATURE_PMSA) &&
1137         arm_feature(env, ARM_FEATURE_V7)) {
1138         uint32_t nr = cpu->pmsav7_dregion;
1139
1140         if (nr > 0xff) {
1141             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
1142             return;
1143         }
1144
1145         if (nr) {
1146             if (arm_feature(env, ARM_FEATURE_V8)) {
1147                 /* PMSAv8 */
1148                 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
1149                 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
1150                 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1151                     env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
1152                     env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
1153                 }
1154             } else {
1155                 env->pmsav7.drbar = g_new0(uint32_t, nr);
1156                 env->pmsav7.drsr = g_new0(uint32_t, nr);
1157                 env->pmsav7.dracr = g_new0(uint32_t, nr);
1158             }
1159         }
1160     }
1161
1162     if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1163         uint32_t nr = cpu->sau_sregion;
1164
1165         if (nr > 0xff) {
1166             error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1167             return;
1168         }
1169
1170         if (nr) {
1171             env->sau.rbar = g_new0(uint32_t, nr);
1172             env->sau.rlar = g_new0(uint32_t, nr);
1173         }
1174     }
1175
1176     if (arm_feature(env, ARM_FEATURE_EL3)) {
1177         set_feature(env, ARM_FEATURE_VBAR);
1178     }
1179
1180     register_cp_regs_for_features(cpu);
1181     arm_cpu_register_gdb_regs_for_features(cpu);
1182
1183     init_cpreg_list(cpu);
1184
1185 #ifndef CONFIG_USER_ONLY
1186     if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1187         cs->num_ases = 2;
1188
1189         if (!cpu->secure_memory) {
1190             cpu->secure_memory = cs->memory;
1191         }
1192         cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1193                                cpu->secure_memory);
1194     } else {
1195         cs->num_ases = 1;
1196     }
1197     cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
1198
1199     /* No core_count specified, default to smp_cpus. */
1200     if (cpu->core_count == -1) {
1201         cpu->core_count = smp_cpus;
1202     }
1203 #endif
1204
1205     qemu_init_vcpu(cs);
1206     cpu_reset(cs);
1207
1208     acc->parent_realize(dev, errp);
1209 }
1210
1211 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1212 {
1213     ObjectClass *oc;
1214     char *typename;
1215     char **cpuname;
1216     const char *cpunamestr;
1217
1218     cpuname = g_strsplit(cpu_model, ",", 1);
1219     cpunamestr = cpuname[0];
1220 #ifdef CONFIG_USER_ONLY
1221     /* For backwards compatibility usermode emulation allows "-cpu any",
1222      * which has the same semantics as "-cpu max".
1223      */
1224     if (!strcmp(cpunamestr, "any")) {
1225         cpunamestr = "max";
1226     }
1227 #endif
1228     typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
1229     oc = object_class_by_name(typename);
1230     g_strfreev(cpuname);
1231     g_free(typename);
1232     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1233         object_class_is_abstract(oc)) {
1234         return NULL;
1235     }
1236     return oc;
1237 }
1238
1239 /* CPU models. These are not needed for the AArch64 linux-user build. */
1240 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1241
1242 static void arm926_initfn(Object *obj)
1243 {
1244     ARMCPU *cpu = ARM_CPU(obj);
1245
1246     cpu->dtb_compatible = "arm,arm926";
1247     set_feature(&cpu->env, ARM_FEATURE_V5);
1248     set_feature(&cpu->env, ARM_FEATURE_VFP);
1249     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1250     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1251     cpu->midr = 0x41069265;
1252     cpu->reset_fpsid = 0x41011090;
1253     cpu->ctr = 0x1dd20d2;
1254     cpu->reset_sctlr = 0x00090078;
1255
1256     /*
1257      * ARMv5 does not have the ID_ISAR registers, but we can still
1258      * set the field to indicate Jazelle support within QEMU.
1259      */
1260     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1261 }
1262
1263 static void arm946_initfn(Object *obj)
1264 {
1265     ARMCPU *cpu = ARM_CPU(obj);
1266
1267     cpu->dtb_compatible = "arm,arm946";
1268     set_feature(&cpu->env, ARM_FEATURE_V5);
1269     set_feature(&cpu->env, ARM_FEATURE_PMSA);
1270     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1271     cpu->midr = 0x41059461;
1272     cpu->ctr = 0x0f004006;
1273     cpu->reset_sctlr = 0x00000078;
1274 }
1275
1276 static void arm1026_initfn(Object *obj)
1277 {
1278     ARMCPU *cpu = ARM_CPU(obj);
1279
1280     cpu->dtb_compatible = "arm,arm1026";
1281     set_feature(&cpu->env, ARM_FEATURE_V5);
1282     set_feature(&cpu->env, ARM_FEATURE_VFP);
1283     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
1284     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1285     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1286     cpu->midr = 0x4106a262;
1287     cpu->reset_fpsid = 0x410110a0;
1288     cpu->ctr = 0x1dd20d2;
1289     cpu->reset_sctlr = 0x00090078;
1290     cpu->reset_auxcr = 1;
1291
1292     /*
1293      * ARMv5 does not have the ID_ISAR registers, but we can still
1294      * set the field to indicate Jazelle support within QEMU.
1295      */
1296     cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
1297
1298     {
1299         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1300         ARMCPRegInfo ifar = {
1301             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1302             .access = PL1_RW,
1303             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
1304             .resetvalue = 0
1305         };
1306         define_one_arm_cp_reg(cpu, &ifar);
1307     }
1308 }
1309
1310 static void arm1136_r2_initfn(Object *obj)
1311 {
1312     ARMCPU *cpu = ARM_CPU(obj);
1313     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1314      * older core than plain "arm1136". In particular this does not
1315      * have the v6K features.
1316      * These ID register values are correct for 1136 but may be wrong
1317      * for 1136_r2 (in particular r0p2 does not actually implement most
1318      * of the ID registers).
1319      */
1320
1321     cpu->dtb_compatible = "arm,arm1136";
1322     set_feature(&cpu->env, ARM_FEATURE_V6);
1323     set_feature(&cpu->env, ARM_FEATURE_VFP);
1324     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1325     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1326     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1327     cpu->midr = 0x4107b362;
1328     cpu->reset_fpsid = 0x410120b4;
1329     cpu->isar.mvfr0 = 0x11111111;
1330     cpu->isar.mvfr1 = 0x00000000;
1331     cpu->ctr = 0x1dd20d2;
1332     cpu->reset_sctlr = 0x00050078;
1333     cpu->id_pfr0 = 0x111;
1334     cpu->id_pfr1 = 0x1;
1335     cpu->id_dfr0 = 0x2;
1336     cpu->id_afr0 = 0x3;
1337     cpu->id_mmfr0 = 0x01130003;
1338     cpu->id_mmfr1 = 0x10030302;
1339     cpu->id_mmfr2 = 0x01222110;
1340     cpu->isar.id_isar0 = 0x00140011;
1341     cpu->isar.id_isar1 = 0x12002111;
1342     cpu->isar.id_isar2 = 0x11231111;
1343     cpu->isar.id_isar3 = 0x01102131;
1344     cpu->isar.id_isar4 = 0x141;
1345     cpu->reset_auxcr = 7;
1346 }
1347
1348 static void arm1136_initfn(Object *obj)
1349 {
1350     ARMCPU *cpu = ARM_CPU(obj);
1351
1352     cpu->dtb_compatible = "arm,arm1136";
1353     set_feature(&cpu->env, ARM_FEATURE_V6K);
1354     set_feature(&cpu->env, ARM_FEATURE_V6);
1355     set_feature(&cpu->env, ARM_FEATURE_VFP);
1356     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1357     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1358     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1359     cpu->midr = 0x4117b363;
1360     cpu->reset_fpsid = 0x410120b4;
1361     cpu->isar.mvfr0 = 0x11111111;
1362     cpu->isar.mvfr1 = 0x00000000;
1363     cpu->ctr = 0x1dd20d2;
1364     cpu->reset_sctlr = 0x00050078;
1365     cpu->id_pfr0 = 0x111;
1366     cpu->id_pfr1 = 0x1;
1367     cpu->id_dfr0 = 0x2;
1368     cpu->id_afr0 = 0x3;
1369     cpu->id_mmfr0 = 0x01130003;
1370     cpu->id_mmfr1 = 0x10030302;
1371     cpu->id_mmfr2 = 0x01222110;
1372     cpu->isar.id_isar0 = 0x00140011;
1373     cpu->isar.id_isar1 = 0x12002111;
1374     cpu->isar.id_isar2 = 0x11231111;
1375     cpu->isar.id_isar3 = 0x01102131;
1376     cpu->isar.id_isar4 = 0x141;
1377     cpu->reset_auxcr = 7;
1378 }
1379
1380 static void arm1176_initfn(Object *obj)
1381 {
1382     ARMCPU *cpu = ARM_CPU(obj);
1383
1384     cpu->dtb_compatible = "arm,arm1176";
1385     set_feature(&cpu->env, ARM_FEATURE_V6K);
1386     set_feature(&cpu->env, ARM_FEATURE_VFP);
1387     set_feature(&cpu->env, ARM_FEATURE_VAPA);
1388     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1389     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1390     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1391     set_feature(&cpu->env, ARM_FEATURE_EL3);
1392     cpu->midr = 0x410fb767;
1393     cpu->reset_fpsid = 0x410120b5;
1394     cpu->isar.mvfr0 = 0x11111111;
1395     cpu->isar.mvfr1 = 0x00000000;
1396     cpu->ctr = 0x1dd20d2;
1397     cpu->reset_sctlr = 0x00050078;
1398     cpu->id_pfr0 = 0x111;
1399     cpu->id_pfr1 = 0x11;
1400     cpu->id_dfr0 = 0x33;
1401     cpu->id_afr0 = 0;
1402     cpu->id_mmfr0 = 0x01130003;
1403     cpu->id_mmfr1 = 0x10030302;
1404     cpu->id_mmfr2 = 0x01222100;
1405     cpu->isar.id_isar0 = 0x0140011;
1406     cpu->isar.id_isar1 = 0x12002111;
1407     cpu->isar.id_isar2 = 0x11231121;
1408     cpu->isar.id_isar3 = 0x01102131;
1409     cpu->isar.id_isar4 = 0x01141;
1410     cpu->reset_auxcr = 7;
1411 }
1412
1413 static void arm11mpcore_initfn(Object *obj)
1414 {
1415     ARMCPU *cpu = ARM_CPU(obj);
1416
1417     cpu->dtb_compatible = "arm,arm11mpcore";
1418     set_feature(&cpu->env, ARM_FEATURE_V6K);
1419     set_feature(&cpu->env, ARM_FEATURE_VFP);
1420     set_feature(&cpu->env, ARM_FEATURE_VAPA);
1421     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
1422     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1423     cpu->midr = 0x410fb022;
1424     cpu->reset_fpsid = 0x410120b4;
1425     cpu->isar.mvfr0 = 0x11111111;
1426     cpu->isar.mvfr1 = 0x00000000;
1427     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
1428     cpu->id_pfr0 = 0x111;
1429     cpu->id_pfr1 = 0x1;
1430     cpu->id_dfr0 = 0;
1431     cpu->id_afr0 = 0x2;
1432     cpu->id_mmfr0 = 0x01100103;
1433     cpu->id_mmfr1 = 0x10020302;
1434     cpu->id_mmfr2 = 0x01222000;
1435     cpu->isar.id_isar0 = 0x00100011;
1436     cpu->isar.id_isar1 = 0x12002111;
1437     cpu->isar.id_isar2 = 0x11221011;
1438     cpu->isar.id_isar3 = 0x01102131;
1439     cpu->isar.id_isar4 = 0x141;
1440     cpu->reset_auxcr = 1;
1441 }
1442
1443 static void cortex_m0_initfn(Object *obj)
1444 {
1445     ARMCPU *cpu = ARM_CPU(obj);
1446     set_feature(&cpu->env, ARM_FEATURE_V6);
1447     set_feature(&cpu->env, ARM_FEATURE_M);
1448
1449     cpu->midr = 0x410cc200;
1450 }
1451
1452 static void cortex_m3_initfn(Object *obj)
1453 {
1454     ARMCPU *cpu = ARM_CPU(obj);
1455     set_feature(&cpu->env, ARM_FEATURE_V7);
1456     set_feature(&cpu->env, ARM_FEATURE_M);
1457     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1458     cpu->midr = 0x410fc231;
1459     cpu->pmsav7_dregion = 8;
1460     cpu->id_pfr0 = 0x00000030;
1461     cpu->id_pfr1 = 0x00000200;
1462     cpu->id_dfr0 = 0x00100000;
1463     cpu->id_afr0 = 0x00000000;
1464     cpu->id_mmfr0 = 0x00000030;
1465     cpu->id_mmfr1 = 0x00000000;
1466     cpu->id_mmfr2 = 0x00000000;
1467     cpu->id_mmfr3 = 0x00000000;
1468     cpu->isar.id_isar0 = 0x01141110;
1469     cpu->isar.id_isar1 = 0x02111000;
1470     cpu->isar.id_isar2 = 0x21112231;
1471     cpu->isar.id_isar3 = 0x01111110;
1472     cpu->isar.id_isar4 = 0x01310102;
1473     cpu->isar.id_isar5 = 0x00000000;
1474     cpu->isar.id_isar6 = 0x00000000;
1475 }
1476
1477 static void cortex_m4_initfn(Object *obj)
1478 {
1479     ARMCPU *cpu = ARM_CPU(obj);
1480
1481     set_feature(&cpu->env, ARM_FEATURE_V7);
1482     set_feature(&cpu->env, ARM_FEATURE_M);
1483     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1484     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1485     cpu->midr = 0x410fc240; /* r0p0 */
1486     cpu->pmsav7_dregion = 8;
1487     cpu->id_pfr0 = 0x00000030;
1488     cpu->id_pfr1 = 0x00000200;
1489     cpu->id_dfr0 = 0x00100000;
1490     cpu->id_afr0 = 0x00000000;
1491     cpu->id_mmfr0 = 0x00000030;
1492     cpu->id_mmfr1 = 0x00000000;
1493     cpu->id_mmfr2 = 0x00000000;
1494     cpu->id_mmfr3 = 0x00000000;
1495     cpu->isar.id_isar0 = 0x01141110;
1496     cpu->isar.id_isar1 = 0x02111000;
1497     cpu->isar.id_isar2 = 0x21112231;
1498     cpu->isar.id_isar3 = 0x01111110;
1499     cpu->isar.id_isar4 = 0x01310102;
1500     cpu->isar.id_isar5 = 0x00000000;
1501     cpu->isar.id_isar6 = 0x00000000;
1502 }
1503
1504 static void cortex_m33_initfn(Object *obj)
1505 {
1506     ARMCPU *cpu = ARM_CPU(obj);
1507
1508     set_feature(&cpu->env, ARM_FEATURE_V8);
1509     set_feature(&cpu->env, ARM_FEATURE_M);
1510     set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1511     set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1512     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1513     cpu->midr = 0x410fd213; /* r0p3 */
1514     cpu->pmsav7_dregion = 16;
1515     cpu->sau_sregion = 8;
1516     cpu->id_pfr0 = 0x00000030;
1517     cpu->id_pfr1 = 0x00000210;
1518     cpu->id_dfr0 = 0x00200000;
1519     cpu->id_afr0 = 0x00000000;
1520     cpu->id_mmfr0 = 0x00101F40;
1521     cpu->id_mmfr1 = 0x00000000;
1522     cpu->id_mmfr2 = 0x01000000;
1523     cpu->id_mmfr3 = 0x00000000;
1524     cpu->isar.id_isar0 = 0x01101110;
1525     cpu->isar.id_isar1 = 0x02212000;
1526     cpu->isar.id_isar2 = 0x20232232;
1527     cpu->isar.id_isar3 = 0x01111131;
1528     cpu->isar.id_isar4 = 0x01310132;
1529     cpu->isar.id_isar5 = 0x00000000;
1530     cpu->isar.id_isar6 = 0x00000000;
1531     cpu->clidr = 0x00000000;
1532     cpu->ctr = 0x8000c000;
1533 }
1534
1535 static void arm_v7m_class_init(ObjectClass *oc, void *data)
1536 {
1537     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1538     CPUClass *cc = CPU_CLASS(oc);
1539
1540     acc->info = data;
1541 #ifndef CONFIG_USER_ONLY
1542     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1543 #endif
1544
1545     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1546 }
1547
1548 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1549     /* Dummy the TCM region regs for the moment */
1550     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1551       .access = PL1_RW, .type = ARM_CP_CONST },
1552     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1553       .access = PL1_RW, .type = ARM_CP_CONST },
1554     { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
1555       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
1556     REGINFO_SENTINEL
1557 };
1558
1559 static void cortex_r5_initfn(Object *obj)
1560 {
1561     ARMCPU *cpu = ARM_CPU(obj);
1562
1563     set_feature(&cpu->env, ARM_FEATURE_V7);
1564     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1565     set_feature(&cpu->env, ARM_FEATURE_PMSA);
1566     cpu->midr = 0x411fc153; /* r1p3 */
1567     cpu->id_pfr0 = 0x0131;
1568     cpu->id_pfr1 = 0x001;
1569     cpu->id_dfr0 = 0x010400;
1570     cpu->id_afr0 = 0x0;
1571     cpu->id_mmfr0 = 0x0210030;
1572     cpu->id_mmfr1 = 0x00000000;
1573     cpu->id_mmfr2 = 0x01200000;
1574     cpu->id_mmfr3 = 0x0211;
1575     cpu->isar.id_isar0 = 0x02101111;
1576     cpu->isar.id_isar1 = 0x13112111;
1577     cpu->isar.id_isar2 = 0x21232141;
1578     cpu->isar.id_isar3 = 0x01112131;
1579     cpu->isar.id_isar4 = 0x0010142;
1580     cpu->isar.id_isar5 = 0x0;
1581     cpu->isar.id_isar6 = 0x0;
1582     cpu->mp_is_up = true;
1583     cpu->pmsav7_dregion = 16;
1584     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1585 }
1586
1587 static void cortex_r5f_initfn(Object *obj)
1588 {
1589     ARMCPU *cpu = ARM_CPU(obj);
1590
1591     cortex_r5_initfn(obj);
1592     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1593 }
1594
1595 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1596     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1597       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1598     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1599       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1600     REGINFO_SENTINEL
1601 };
1602
1603 static void cortex_a8_initfn(Object *obj)
1604 {
1605     ARMCPU *cpu = ARM_CPU(obj);
1606
1607     cpu->dtb_compatible = "arm,cortex-a8";
1608     set_feature(&cpu->env, ARM_FEATURE_V7);
1609     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1610     set_feature(&cpu->env, ARM_FEATURE_NEON);
1611     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1612     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1613     set_feature(&cpu->env, ARM_FEATURE_EL3);
1614     cpu->midr = 0x410fc080;
1615     cpu->reset_fpsid = 0x410330c0;
1616     cpu->isar.mvfr0 = 0x11110222;
1617     cpu->isar.mvfr1 = 0x00011111;
1618     cpu->ctr = 0x82048004;
1619     cpu->reset_sctlr = 0x00c50078;
1620     cpu->id_pfr0 = 0x1031;
1621     cpu->id_pfr1 = 0x11;
1622     cpu->id_dfr0 = 0x400;
1623     cpu->id_afr0 = 0;
1624     cpu->id_mmfr0 = 0x31100003;
1625     cpu->id_mmfr1 = 0x20000000;
1626     cpu->id_mmfr2 = 0x01202000;
1627     cpu->id_mmfr3 = 0x11;
1628     cpu->isar.id_isar0 = 0x00101111;
1629     cpu->isar.id_isar1 = 0x12112111;
1630     cpu->isar.id_isar2 = 0x21232031;
1631     cpu->isar.id_isar3 = 0x11112131;
1632     cpu->isar.id_isar4 = 0x00111142;
1633     cpu->dbgdidr = 0x15141000;
1634     cpu->clidr = (1 << 27) | (2 << 24) | 3;
1635     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1636     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1637     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1638     cpu->reset_auxcr = 2;
1639     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1640 }
1641
1642 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1643     /* power_control should be set to maximum latency. Again,
1644      * default to 0 and set by private hook
1645      */
1646     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1647       .access = PL1_RW, .resetvalue = 0,
1648       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1649     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1650       .access = PL1_RW, .resetvalue = 0,
1651       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1652     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1653       .access = PL1_RW, .resetvalue = 0,
1654       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1655     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1656       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1657     /* TLB lockdown control */
1658     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1659       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1660     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1661       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1662     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1663       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1664     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1665       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1666     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1667       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1668     REGINFO_SENTINEL
1669 };
1670
1671 static void cortex_a9_initfn(Object *obj)
1672 {
1673     ARMCPU *cpu = ARM_CPU(obj);
1674
1675     cpu->dtb_compatible = "arm,cortex-a9";
1676     set_feature(&cpu->env, ARM_FEATURE_V7);
1677     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1678     set_feature(&cpu->env, ARM_FEATURE_NEON);
1679     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1680     set_feature(&cpu->env, ARM_FEATURE_EL3);
1681     /* Note that A9 supports the MP extensions even for
1682      * A9UP and single-core A9MP (which are both different
1683      * and valid configurations; we don't model A9UP).
1684      */
1685     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1686     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1687     cpu->midr = 0x410fc090;
1688     cpu->reset_fpsid = 0x41033090;
1689     cpu->isar.mvfr0 = 0x11110222;
1690     cpu->isar.mvfr1 = 0x01111111;
1691     cpu->ctr = 0x80038003;
1692     cpu->reset_sctlr = 0x00c50078;
1693     cpu->id_pfr0 = 0x1031;
1694     cpu->id_pfr1 = 0x11;
1695     cpu->id_dfr0 = 0x000;
1696     cpu->id_afr0 = 0;
1697     cpu->id_mmfr0 = 0x00100103;
1698     cpu->id_mmfr1 = 0x20000000;
1699     cpu->id_mmfr2 = 0x01230000;
1700     cpu->id_mmfr3 = 0x00002111;
1701     cpu->isar.id_isar0 = 0x00101111;
1702     cpu->isar.id_isar1 = 0x13112111;
1703     cpu->isar.id_isar2 = 0x21232041;
1704     cpu->isar.id_isar3 = 0x11112131;
1705     cpu->isar.id_isar4 = 0x00111142;
1706     cpu->dbgdidr = 0x35141000;
1707     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1708     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1709     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1710     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1711 }
1712
1713 #ifndef CONFIG_USER_ONLY
1714 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1715 {
1716     /* Linux wants the number of processors from here.
1717      * Might as well set the interrupt-controller bit too.
1718      */
1719     return ((smp_cpus - 1) << 24) | (1 << 23);
1720 }
1721 #endif
1722
1723 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1724 #ifndef CONFIG_USER_ONLY
1725     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1726       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1727       .writefn = arm_cp_write_ignore, },
1728 #endif
1729     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1730       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1731     REGINFO_SENTINEL
1732 };
1733
1734 static void cortex_a7_initfn(Object *obj)
1735 {
1736     ARMCPU *cpu = ARM_CPU(obj);
1737
1738     cpu->dtb_compatible = "arm,cortex-a7";
1739     set_feature(&cpu->env, ARM_FEATURE_V7VE);
1740     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1741     set_feature(&cpu->env, ARM_FEATURE_NEON);
1742     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1743     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1744     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1745     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1746     set_feature(&cpu->env, ARM_FEATURE_EL2);
1747     set_feature(&cpu->env, ARM_FEATURE_EL3);
1748     set_feature(&cpu->env, ARM_FEATURE_PMU);
1749     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1750     cpu->midr = 0x410fc075;
1751     cpu->reset_fpsid = 0x41023075;
1752     cpu->isar.mvfr0 = 0x10110222;
1753     cpu->isar.mvfr1 = 0x11111111;
1754     cpu->ctr = 0x84448003;
1755     cpu->reset_sctlr = 0x00c50078;
1756     cpu->id_pfr0 = 0x00001131;
1757     cpu->id_pfr1 = 0x00011011;
1758     cpu->id_dfr0 = 0x02010555;
1759     cpu->id_afr0 = 0x00000000;
1760     cpu->id_mmfr0 = 0x10101105;
1761     cpu->id_mmfr1 = 0x40000000;
1762     cpu->id_mmfr2 = 0x01240000;
1763     cpu->id_mmfr3 = 0x02102211;
1764     /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
1765      * table 4-41 gives 0x02101110, which includes the arm div insns.
1766      */
1767     cpu->isar.id_isar0 = 0x02101110;
1768     cpu->isar.id_isar1 = 0x13112111;
1769     cpu->isar.id_isar2 = 0x21232041;
1770     cpu->isar.id_isar3 = 0x11112131;
1771     cpu->isar.id_isar4 = 0x10011142;
1772     cpu->dbgdidr = 0x3515f005;
1773     cpu->clidr = 0x0a200023;
1774     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1775     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1776     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1777     define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
1778 }
1779
1780 static void cortex_a15_initfn(Object *obj)
1781 {
1782     ARMCPU *cpu = ARM_CPU(obj);
1783
1784     cpu->dtb_compatible = "arm,cortex-a15";
1785     set_feature(&cpu->env, ARM_FEATURE_V7VE);
1786     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1787     set_feature(&cpu->env, ARM_FEATURE_NEON);
1788     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1789     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1790     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1791     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1792     set_feature(&cpu->env, ARM_FEATURE_EL2);
1793     set_feature(&cpu->env, ARM_FEATURE_EL3);
1794     set_feature(&cpu->env, ARM_FEATURE_PMU);
1795     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1796     cpu->midr = 0x412fc0f1;
1797     cpu->reset_fpsid = 0x410430f0;
1798     cpu->isar.mvfr0 = 0x10110222;
1799     cpu->isar.mvfr1 = 0x11111111;
1800     cpu->ctr = 0x8444c004;
1801     cpu->reset_sctlr = 0x00c50078;
1802     cpu->id_pfr0 = 0x00001131;
1803     cpu->id_pfr1 = 0x00011011;
1804     cpu->id_dfr0 = 0x02010555;
1805     cpu->id_afr0 = 0x00000000;
1806     cpu->id_mmfr0 = 0x10201105;
1807     cpu->id_mmfr1 = 0x20000000;
1808     cpu->id_mmfr2 = 0x01240000;
1809     cpu->id_mmfr3 = 0x02102211;
1810     cpu->isar.id_isar0 = 0x02101110;
1811     cpu->isar.id_isar1 = 0x13112111;
1812     cpu->isar.id_isar2 = 0x21232041;
1813     cpu->isar.id_isar3 = 0x11112131;
1814     cpu->isar.id_isar4 = 0x10011142;
1815     cpu->dbgdidr = 0x3515f021;
1816     cpu->clidr = 0x0a200023;
1817     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1818     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1819     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1820     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1821 }
1822
1823 static void ti925t_initfn(Object *obj)
1824 {
1825     ARMCPU *cpu = ARM_CPU(obj);
1826     set_feature(&cpu->env, ARM_FEATURE_V4T);
1827     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1828     cpu->midr = ARM_CPUID_TI925T;
1829     cpu->ctr = 0x5109149;
1830     cpu->reset_sctlr = 0x00000070;
1831 }
1832
1833 static void sa1100_initfn(Object *obj)
1834 {
1835     ARMCPU *cpu = ARM_CPU(obj);
1836
1837     cpu->dtb_compatible = "intel,sa1100";
1838     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1839     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1840     cpu->midr = 0x4401A11B;
1841     cpu->reset_sctlr = 0x00000070;
1842 }
1843
1844 static void sa1110_initfn(Object *obj)
1845 {
1846     ARMCPU *cpu = ARM_CPU(obj);
1847     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1848     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1849     cpu->midr = 0x6901B119;
1850     cpu->reset_sctlr = 0x00000070;
1851 }
1852
1853 static void pxa250_initfn(Object *obj)
1854 {
1855     ARMCPU *cpu = ARM_CPU(obj);
1856
1857     cpu->dtb_compatible = "marvell,xscale";
1858     set_feature(&cpu->env, ARM_FEATURE_V5);
1859     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1860     cpu->midr = 0x69052100;
1861     cpu->ctr = 0xd172172;
1862     cpu->reset_sctlr = 0x00000078;
1863 }
1864
1865 static void pxa255_initfn(Object *obj)
1866 {
1867     ARMCPU *cpu = ARM_CPU(obj);
1868
1869     cpu->dtb_compatible = "marvell,xscale";
1870     set_feature(&cpu->env, ARM_FEATURE_V5);
1871     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1872     cpu->midr = 0x69052d00;
1873     cpu->ctr = 0xd172172;
1874     cpu->reset_sctlr = 0x00000078;
1875 }
1876
1877 static void pxa260_initfn(Object *obj)
1878 {
1879     ARMCPU *cpu = ARM_CPU(obj);
1880
1881     cpu->dtb_compatible = "marvell,xscale";
1882     set_feature(&cpu->env, ARM_FEATURE_V5);
1883     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1884     cpu->midr = 0x69052903;
1885     cpu->ctr = 0xd172172;
1886     cpu->reset_sctlr = 0x00000078;
1887 }
1888
1889 static void pxa261_initfn(Object *obj)
1890 {
1891     ARMCPU *cpu = ARM_CPU(obj);
1892
1893     cpu->dtb_compatible = "marvell,xscale";
1894     set_feature(&cpu->env, ARM_FEATURE_V5);
1895     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1896     cpu->midr = 0x69052d05;
1897     cpu->ctr = 0xd172172;
1898     cpu->reset_sctlr = 0x00000078;
1899 }
1900
1901 static void pxa262_initfn(Object *obj)
1902 {
1903     ARMCPU *cpu = ARM_CPU(obj);
1904
1905     cpu->dtb_compatible = "marvell,xscale";
1906     set_feature(&cpu->env, ARM_FEATURE_V5);
1907     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1908     cpu->midr = 0x69052d06;
1909     cpu->ctr = 0xd172172;
1910     cpu->reset_sctlr = 0x00000078;
1911 }
1912
1913 static void pxa270a0_initfn(Object *obj)
1914 {
1915     ARMCPU *cpu = ARM_CPU(obj);
1916
1917     cpu->dtb_compatible = "marvell,xscale";
1918     set_feature(&cpu->env, ARM_FEATURE_V5);
1919     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1920     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1921     cpu->midr = 0x69054110;
1922     cpu->ctr = 0xd172172;
1923     cpu->reset_sctlr = 0x00000078;
1924 }
1925
1926 static void pxa270a1_initfn(Object *obj)
1927 {
1928     ARMCPU *cpu = ARM_CPU(obj);
1929
1930     cpu->dtb_compatible = "marvell,xscale";
1931     set_feature(&cpu->env, ARM_FEATURE_V5);
1932     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1933     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1934     cpu->midr = 0x69054111;
1935     cpu->ctr = 0xd172172;
1936     cpu->reset_sctlr = 0x00000078;
1937 }
1938
1939 static void pxa270b0_initfn(Object *obj)
1940 {
1941     ARMCPU *cpu = ARM_CPU(obj);
1942
1943     cpu->dtb_compatible = "marvell,xscale";
1944     set_feature(&cpu->env, ARM_FEATURE_V5);
1945     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1946     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1947     cpu->midr = 0x69054112;
1948     cpu->ctr = 0xd172172;
1949     cpu->reset_sctlr = 0x00000078;
1950 }
1951
1952 static void pxa270b1_initfn(Object *obj)
1953 {
1954     ARMCPU *cpu = ARM_CPU(obj);
1955
1956     cpu->dtb_compatible = "marvell,xscale";
1957     set_feature(&cpu->env, ARM_FEATURE_V5);
1958     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1959     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1960     cpu->midr = 0x69054113;
1961     cpu->ctr = 0xd172172;
1962     cpu->reset_sctlr = 0x00000078;
1963 }
1964
1965 static void pxa270c0_initfn(Object *obj)
1966 {
1967     ARMCPU *cpu = ARM_CPU(obj);
1968
1969     cpu->dtb_compatible = "marvell,xscale";
1970     set_feature(&cpu->env, ARM_FEATURE_V5);
1971     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1972     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1973     cpu->midr = 0x69054114;
1974     cpu->ctr = 0xd172172;
1975     cpu->reset_sctlr = 0x00000078;
1976 }
1977
1978 static void pxa270c5_initfn(Object *obj)
1979 {
1980     ARMCPU *cpu = ARM_CPU(obj);
1981
1982     cpu->dtb_compatible = "marvell,xscale";
1983     set_feature(&cpu->env, ARM_FEATURE_V5);
1984     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1985     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1986     cpu->midr = 0x69054117;
1987     cpu->ctr = 0xd172172;
1988     cpu->reset_sctlr = 0x00000078;
1989 }
1990
1991 #ifndef TARGET_AARCH64
1992 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
1993  * otherwise, a CPU with as many features enabled as our emulation supports.
1994  * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1995  * this only needs to handle 32 bits.
1996  */
1997 static void arm_max_initfn(Object *obj)
1998 {
1999     ARMCPU *cpu = ARM_CPU(obj);
2000
2001     if (kvm_enabled()) {
2002         kvm_arm_set_cpu_features_from_host(cpu);
2003     } else {
2004         cortex_a15_initfn(obj);
2005 #ifdef CONFIG_USER_ONLY
2006         /* We don't set these in system emulation mode for the moment,
2007          * since we don't correctly set (all of) the ID registers to
2008          * advertise them.
2009          */
2010         set_feature(&cpu->env, ARM_FEATURE_V8);
2011         {
2012             uint32_t t;
2013
2014             t = cpu->isar.id_isar5;
2015             t = FIELD_DP32(t, ID_ISAR5, AES, 2);
2016             t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
2017             t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
2018             t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
2019             t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
2020             t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
2021             cpu->isar.id_isar5 = t;
2022
2023             t = cpu->isar.id_isar6;
2024             t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
2025             t = FIELD_DP32(t, ID_ISAR6, DP, 1);
2026             t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
2027             t = FIELD_DP32(t, ID_ISAR6, SB, 1);
2028             t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
2029             cpu->isar.id_isar6 = t;
2030
2031             t = cpu->isar.mvfr2;
2032             t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
2033             t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
2034             cpu->isar.mvfr2 = t;
2035
2036             t = cpu->id_mmfr4;
2037             t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
2038             cpu->id_mmfr4 = t;
2039         }
2040 #endif
2041     }
2042 }
2043 #endif
2044
2045 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
2046
2047 struct ARMCPUInfo {
2048     const char *name;
2049     void (*initfn)(Object *obj);
2050     void (*class_init)(ObjectClass *oc, void *data);
2051 };
2052
2053 static const ARMCPUInfo arm_cpus[] = {
2054 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2055     { .name = "arm926",      .initfn = arm926_initfn },
2056     { .name = "arm946",      .initfn = arm946_initfn },
2057     { .name = "arm1026",     .initfn = arm1026_initfn },
2058     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
2059      * older core than plain "arm1136". In particular this does not
2060      * have the v6K features.
2061      */
2062     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
2063     { .name = "arm1136",     .initfn = arm1136_initfn },
2064     { .name = "arm1176",     .initfn = arm1176_initfn },
2065     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
2066     { .name = "cortex-m0",   .initfn = cortex_m0_initfn,
2067                              .class_init = arm_v7m_class_init },
2068     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
2069                              .class_init = arm_v7m_class_init },
2070     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
2071                              .class_init = arm_v7m_class_init },
2072     { .name = "cortex-m33",  .initfn = cortex_m33_initfn,
2073                              .class_init = arm_v7m_class_init },
2074     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
2075     { .name = "cortex-r5f",  .initfn = cortex_r5f_initfn },
2076     { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
2077     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
2078     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
2079     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
2080     { .name = "ti925t",      .initfn = ti925t_initfn },
2081     { .name = "sa1100",      .initfn = sa1100_initfn },
2082     { .name = "sa1110",      .initfn = sa1110_initfn },
2083     { .name = "pxa250",      .initfn = pxa250_initfn },
2084     { .name = "pxa255",      .initfn = pxa255_initfn },
2085     { .name = "pxa260",      .initfn = pxa260_initfn },
2086     { .name = "pxa261",      .initfn = pxa261_initfn },
2087     { .name = "pxa262",      .initfn = pxa262_initfn },
2088     /* "pxa270" is an alias for "pxa270-a0" */
2089     { .name = "pxa270",      .initfn = pxa270a0_initfn },
2090     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
2091     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
2092     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
2093     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
2094     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
2095     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
2096 #ifndef TARGET_AARCH64
2097     { .name = "max",         .initfn = arm_max_initfn },
2098 #endif
2099 #ifdef CONFIG_USER_ONLY
2100     { .name = "any",         .initfn = arm_max_initfn },
2101 #endif
2102 #endif
2103     { .name = NULL }
2104 };
2105
2106 static Property arm_cpu_properties[] = {
2107     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
2108     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
2109     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
2110     DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
2111                         mp_affinity, ARM64_AFFINITY_INVALID),
2112     DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
2113     DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
2114     DEFINE_PROP_END_OF_LIST()
2115 };
2116
2117 #ifdef CONFIG_USER_ONLY
2118 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
2119                                     int rw, int mmu_idx)
2120 {
2121     ARMCPU *cpu = ARM_CPU(cs);
2122     CPUARMState *env = &cpu->env;
2123
2124     env->exception.vaddress = address;
2125     if (rw == 2) {
2126         cs->exception_index = EXCP_PREFETCH_ABORT;
2127     } else {
2128         cs->exception_index = EXCP_DATA_ABORT;
2129     }
2130     return 1;
2131 }
2132 #endif
2133
2134 static gchar *arm_gdb_arch_name(CPUState *cs)
2135 {
2136     ARMCPU *cpu = ARM_CPU(cs);
2137     CPUARMState *env = &cpu->env;
2138
2139     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
2140         return g_strdup("iwmmxt");
2141     }
2142     return g_strdup("arm");
2143 }
2144
2145 static void arm_cpu_class_init(ObjectClass *oc, void *data)
2146 {
2147     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2148     CPUClass *cc = CPU_CLASS(acc);
2149     DeviceClass *dc = DEVICE_CLASS(oc);
2150
2151     device_class_set_parent_realize(dc, arm_cpu_realizefn,
2152                                     &acc->parent_realize);
2153     dc->props = arm_cpu_properties;
2154
2155     acc->parent_reset = cc->reset;
2156     cc->reset = arm_cpu_reset;
2157
2158     cc->class_by_name = arm_cpu_class_by_name;
2159     cc->has_work = arm_cpu_has_work;
2160     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
2161     cc->dump_state = arm_cpu_dump_state;
2162     cc->set_pc = arm_cpu_set_pc;
2163     cc->synchronize_from_tb = arm_cpu_synchronize_from_tb;
2164     cc->gdb_read_register = arm_cpu_gdb_read_register;
2165     cc->gdb_write_register = arm_cpu_gdb_write_register;
2166 #ifdef CONFIG_USER_ONLY
2167     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
2168 #else
2169     cc->do_interrupt = arm_cpu_do_interrupt;
2170     cc->do_unaligned_access = arm_cpu_do_unaligned_access;
2171     cc->do_transaction_failed = arm_cpu_do_transaction_failed;
2172     cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
2173     cc->asidx_from_attrs = arm_asidx_from_attrs;
2174     cc->vmsd = &vmstate_arm_cpu;
2175     cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
2176     cc->write_elf64_note = arm_cpu_write_elf64_note;
2177     cc->write_elf32_note = arm_cpu_write_elf32_note;
2178 #endif
2179     cc->gdb_num_core_regs = 26;
2180     cc->gdb_core_xml_file = "arm-core.xml";
2181     cc->gdb_arch_name = arm_gdb_arch_name;
2182     cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
2183     cc->gdb_stop_before_watchpoint = true;
2184     cc->debug_excp_handler = arm_debug_excp_handler;
2185     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
2186 #if !defined(CONFIG_USER_ONLY)
2187     cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
2188 #endif
2189
2190     cc->disas_set_info = arm_disas_set_info;
2191 #ifdef CONFIG_TCG
2192     cc->tcg_initialize = arm_translate_init;
2193 #endif
2194 }
2195
2196 #ifdef CONFIG_KVM
2197 static void arm_host_initfn(Object *obj)
2198 {
2199     ARMCPU *cpu = ARM_CPU(obj);
2200
2201     kvm_arm_set_cpu_features_from_host(cpu);
2202     arm_cpu_post_init(obj);
2203 }
2204
2205 static const TypeInfo host_arm_cpu_type_info = {
2206     .name = TYPE_ARM_HOST_CPU,
2207 #ifdef TARGET_AARCH64
2208     .parent = TYPE_AARCH64_CPU,
2209 #else
2210     .parent = TYPE_ARM_CPU,
2211 #endif
2212     .instance_init = arm_host_initfn,
2213 };
2214
2215 #endif
2216
2217 static void arm_cpu_instance_init(Object *obj)
2218 {
2219     ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
2220
2221     acc->info->initfn(obj);
2222     arm_cpu_post_init(obj);
2223 }
2224
2225 static void cpu_register_class_init(ObjectClass *oc, void *data)
2226 {
2227     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
2228
2229     acc->info = data;
2230 }
2231
2232 static void cpu_register(const ARMCPUInfo *info)
2233 {
2234     TypeInfo type_info = {
2235         .parent = TYPE_ARM_CPU,
2236         .instance_size = sizeof(ARMCPU),
2237         .instance_init = arm_cpu_instance_init,
2238         .class_size = sizeof(ARMCPUClass),
2239         .class_init = info->class_init ?: cpu_register_class_init,
2240         .class_data = (void *)info,
2241     };
2242
2243     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2244     type_register(&type_info);
2245     g_free((void *)type_info.name);
2246 }
2247
2248 static const TypeInfo arm_cpu_type_info = {
2249     .name = TYPE_ARM_CPU,
2250     .parent = TYPE_CPU,
2251     .instance_size = sizeof(ARMCPU),
2252     .instance_init = arm_cpu_initfn,
2253     .instance_finalize = arm_cpu_finalizefn,
2254     .abstract = true,
2255     .class_size = sizeof(ARMCPUClass),
2256     .class_init = arm_cpu_class_init,
2257 };
2258
2259 static const TypeInfo idau_interface_type_info = {
2260     .name = TYPE_IDAU_INTERFACE,
2261     .parent = TYPE_INTERFACE,
2262     .class_size = sizeof(IDAUInterfaceClass),
2263 };
2264
2265 static void arm_cpu_register_types(void)
2266 {
2267     const ARMCPUInfo *info = arm_cpus;
2268
2269     type_register_static(&arm_cpu_type_info);
2270     type_register_static(&idau_interface_type_info);
2271
2272     while (info->name) {
2273         cpu_register(info);
2274         info++;
2275     }
2276
2277 #ifdef CONFIG_KVM
2278     type_register_static(&host_arm_cpu_type_info);
2279 #endif
2280 }
2281
2282 type_init(arm_cpu_register_types)