target/arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qemu/error-report.h"
  23 #include "qapi/error.h"
  24 #include "cpu.h"
  25 #include "internals.h"
  26 #include "qemu-common.h"
  27 #include "exec/exec-all.h"
  28 #include "hw/qdev-properties.h"
  29 #if !defined(CONFIG_USER_ONLY)
  30 #include "hw/loader.h"
  31 #endif
  32 #include "hw/arm/arm.h"
  33 #include "sysemu/sysemu.h"
  34 #include "sysemu/kvm.h"
  35 #include "kvm_arm.h"
  36
  37 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  38 {
  39     ARMCPU *cpu = ARM_CPU(cs);
  40
  41     cpu->env.regs[15] = value;
  42 }
  43
  44 static bool arm_cpu_has_work(CPUState *cs)
  45 {
  46     ARMCPU *cpu = ARM_CPU(cs);
  47
  48     return !cpu->powered_off
  49         && cs->interrupt_request &
  50         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  51          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  52          | CPU_INTERRUPT_EXITTB);
  53 }
  54
  55 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHook *hook,
  56                                  void *opaque)
  57 {
  58     /* We currently only support registering a single hook function */
  59     assert(!cpu->el_change_hook);
  60     cpu->el_change_hook = hook;
  61     cpu->el_change_hook_opaque = opaque;
  62 }
  63
  64 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  65 {
  66     /* Reset a single ARMCPRegInfo register */
  67     ARMCPRegInfo *ri = value;
  68     ARMCPU *cpu = opaque;
  69
  70     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
  71         return;
  72     }
  73
  74     if (ri->resetfn) {
  75         ri->resetfn(&cpu->env, ri);
  76         return;
  77     }
  78
  79     /* A zero offset is never possible as it would be regs[0]
  80      * so we use it to indicate that reset is being handled elsewhere.
  81      * This is basically only used for fields in non-core coprocessors
  82      * (like the pxa2xx ones).
  83      */
  84     if (!ri->fieldoffset) {
  85         return;
  86     }
  87
  88     if (cpreg_field_is_64bit(ri)) {
  89         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  90     } else {
  91         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  92     }
  93 }
  94
  95 static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
  96 {
  97     /* Purely an assertion check: we've already done reset once,
  98      * so now check that running the reset for the cpreg doesn't
  99      * change its value. This traps bugs where two different cpregs
 100      * both try to reset the same state field but to different values.
 101      */
 102     ARMCPRegInfo *ri = value;
 103     ARMCPU *cpu = opaque;
 104     uint64_t oldvalue, newvalue;
 105
 106     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
 107         return;
 108     }
 109
 110     oldvalue = read_raw_cp_reg(&cpu->env, ri);
 111     cp_reg_reset(key, value, opaque);
 112     newvalue = read_raw_cp_reg(&cpu->env, ri);
 113     assert(oldvalue == newvalue);
 114 }
 115
 116 /* CPUClass::reset() */
 117 static void arm_cpu_reset(CPUState *s)
 118 {
 119     ARMCPU *cpu = ARM_CPU(s);
 120     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
 121     CPUARMState *env = &cpu->env;
 122
 123     acc->parent_reset(s);
 124
 125     memset(env, 0, offsetof(CPUARMState, end_reset_fields));
 126
 127     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
 128     g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
 129
 130     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
 131     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
 132     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
 133     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
 134
 135     cpu->powered_off = cpu->start_powered_off;
 136     s->halted = cpu->start_powered_off;
 137
 138     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 139         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 140     }
 141
 142     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 143         /* 64 bit CPUs always start in 64 bit mode */
 144         env->aarch64 = 1;
 145 #if defined(CONFIG_USER_ONLY)
 146         env->pstate = PSTATE_MODE_EL0t;
 147         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 148         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 149         /* and to the FP/Neon instructions */
 150         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 151 #else
 152         /* Reset into the highest available EL */
 153         if (arm_feature(env, ARM_FEATURE_EL3)) {
 154             env->pstate = PSTATE_MODE_EL3h;
 155         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 156             env->pstate = PSTATE_MODE_EL2h;
 157         } else {
 158             env->pstate = PSTATE_MODE_EL1h;
 159         }
 160         env->pc = cpu->rvbar;
 161 #endif
 162     } else {
 163 #if defined(CONFIG_USER_ONLY)
 164         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 165         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 166 #endif
 167     }
 168
 169 #if defined(CONFIG_USER_ONLY)
 170     env->uncached_cpsr = ARM_CPU_MODE_USR;
 171     /* For user mode we must enable access to coprocessors */
 172     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 173     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 174         env->cp15.c15_cpar = 3;
 175     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 176         env->cp15.c15_cpar = 1;
 177     }
 178 #else
 179     /* SVC mode with interrupts disabled.  */
 180     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 181     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 182     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 183      * clear at reset. Initial SP and PC are loaded from ROM.
 184      */
 185     if (IS_M(env)) {
 186         uint32_t initial_msp; /* Loaded from 0x0 */
 187         uint32_t initial_pc; /* Loaded from 0x4 */
 188         uint8_t *rom;
 189
 190         env->daif &= ~PSTATE_I;
 191         rom = rom_ptr(0);
 192         if (rom) {
 193             /* Address zero is covered by ROM which hasn't yet been
 194              * copied into physical memory.
 195              */
 196             initial_msp = ldl_p(rom);
 197             initial_pc = ldl_p(rom + 4);
 198         } else {
 199             /* Address zero not covered by a ROM blob, or the ROM blob
 200              * is in non-modifiable memory and this is a second reset after
 201              * it got copied into memory. In the latter case, rom_ptr
 202              * will return a NULL pointer and we should use ldl_phys instead.
 203              */
 204             initial_msp = ldl_phys(s->as, 0);
 205             initial_pc = ldl_phys(s->as, 4);
 206         }
 207
 208         env->regs[13] = initial_msp & 0xFFFFFFFC;
 209         env->regs[15] = initial_pc & ~1;
 210         env->thumb = initial_pc & 1;
 211     }
 212
 213     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 214      * executing as AArch32 then check if highvecs are enabled and
 215      * adjust the PC accordingly.
 216      */
 217     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 218         env->regs[15] = 0xFFFF0000;
 219     }
 220
 221     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 222 #endif
 223     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 224     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 225     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 226     set_float_detect_tininess(float_tininess_before_rounding,
 227                               &env->vfp.fp_status);
 228     set_float_detect_tininess(float_tininess_before_rounding,
 229                               &env->vfp.standard_fp_status);
 230 #ifndef CONFIG_USER_ONLY
 231     if (kvm_enabled()) {
 232         kvm_arm_reset_vcpu(cpu);
 233     }
 234 #endif
 235
 236     hw_breakpoint_update_all(cpu);
 237     hw_watchpoint_update_all(cpu);
 238 }
 239
 240 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 241 {
 242     CPUClass *cc = CPU_GET_CLASS(cs);
 243     CPUARMState *env = cs->env_ptr;
 244     uint32_t cur_el = arm_current_el(env);
 245     bool secure = arm_is_secure(env);
 246     uint32_t target_el;
 247     uint32_t excp_idx;
 248     bool ret = false;
 249
 250     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 251         excp_idx = EXCP_FIQ;
 252         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 253         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 254             cs->exception_index = excp_idx;
 255             env->exception.target_el = target_el;
 256             cc->do_interrupt(cs);
 257             ret = true;
 258         }
 259     }
 260     if (interrupt_request & CPU_INTERRUPT_HARD) {
 261         excp_idx = EXCP_IRQ;
 262         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 263         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 264             cs->exception_index = excp_idx;
 265             env->exception.target_el = target_el;
 266             cc->do_interrupt(cs);
 267             ret = true;
 268         }
 269     }
 270     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 271         excp_idx = EXCP_VIRQ;
 272         target_el = 1;
 273         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 274             cs->exception_index = excp_idx;
 275             env->exception.target_el = target_el;
 276             cc->do_interrupt(cs);
 277             ret = true;
 278         }
 279     }
 280     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 281         excp_idx = EXCP_VFIQ;
 282         target_el = 1;
 283         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 284             cs->exception_index = excp_idx;
 285             env->exception.target_el = target_el;
 286             cc->do_interrupt(cs);
 287             ret = true;
 288         }
 289     }
 290
 291     return ret;
 292 }
 293
 294 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 295 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 296 {
 297     CPUClass *cc = CPU_GET_CLASS(cs);
 298     ARMCPU *cpu = ARM_CPU(cs);
 299     CPUARMState *env = &cpu->env;
 300     bool ret = false;
 301
 302
 303     if (interrupt_request & CPU_INTERRUPT_FIQ
 304         && !(env->daif & PSTATE_F)) {
 305         cs->exception_index = EXCP_FIQ;
 306         cc->do_interrupt(cs);
 307         ret = true;
 308     }
 309     /* ARMv7-M interrupt return works by loading a magic value
 310      * into the PC.  On real hardware the load causes the
 311      * return to occur.  The qemu implementation performs the
 312      * jump normally, then does the exception return when the
 313      * CPU tries to execute code at the magic address.
 314      * This will cause the magic PC value to be pushed to
 315      * the stack if an interrupt occurred at the wrong time.
 316      * We avoid this by disabling interrupts when
 317      * pc contains a magic address.
 318      */
 319     if (interrupt_request & CPU_INTERRUPT_HARD
 320         && !(env->daif & PSTATE_I)
 321         && (env->regs[15] < 0xfffffff0)) {
 322         cs->exception_index = EXCP_IRQ;
 323         cc->do_interrupt(cs);
 324         ret = true;
 325     }
 326     return ret;
 327 }
 328 #endif
 329
 330 #ifndef CONFIG_USER_ONLY
 331 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 332 {
 333     ARMCPU *cpu = opaque;
 334     CPUARMState *env = &cpu->env;
 335     CPUState *cs = CPU(cpu);
 336     static const int mask[] = {
 337         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 338         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 339         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 340         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 341     };
 342
 343     switch (irq) {
 344     case ARM_CPU_VIRQ:
 345     case ARM_CPU_VFIQ:
 346         assert(arm_feature(env, ARM_FEATURE_EL2));
 347         /* fall through */
 348     case ARM_CPU_IRQ:
 349     case ARM_CPU_FIQ:
 350         if (level) {
 351             cpu_interrupt(cs, mask[irq]);
 352         } else {
 353             cpu_reset_interrupt(cs, mask[irq]);
 354         }
 355         break;
 356     default:
 357         g_assert_not_reached();
 358     }
 359 }
 360
 361 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 362 {
 363 #ifdef CONFIG_KVM
 364     ARMCPU *cpu = opaque;
 365     CPUState *cs = CPU(cpu);
 366     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 367
 368     switch (irq) {
 369     case ARM_CPU_IRQ:
 370         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 371         break;
 372     case ARM_CPU_FIQ:
 373         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 374         break;
 375     default:
 376         g_assert_not_reached();
 377     }
 378     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 379     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 380 #endif
 381 }
 382
 383 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
 384 {
 385     ARMCPU *cpu = ARM_CPU(cs);
 386     CPUARMState *env = &cpu->env;
 387
 388     cpu_synchronize_state(cs);
 389     return arm_cpu_data_is_big_endian(env);
 390 }
 391
 392 #endif
 393
 394 static inline void set_feature(CPUARMState *env, int feature)
 395 {
 396     env->features |= 1ULL << feature;
 397 }
 398
 399 static inline void unset_feature(CPUARMState *env, int feature)
 400 {
 401     env->features &= ~(1ULL << feature);
 402 }
 403
 404 static int
 405 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 406 {
 407   return print_insn_arm(pc | 1, info);
 408 }
 409
 410 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 411 {
 412     ARMCPU *ac = ARM_CPU(cpu);
 413     CPUARMState *env = &ac->env;
 414
 415     if (is_a64(env)) {
 416         /* We might not be compiled with the A64 disassembler
 417          * because it needs a C++ compiler. Leave print_insn
 418          * unset in this case to use the caller default behaviour.
 419          */
 420 #if defined(CONFIG_ARM_A64_DIS)
 421         info->print_insn = print_insn_arm_a64;
 422 #endif
 423     } else if (env->thumb) {
 424         info->print_insn = print_insn_thumb1;
 425     } else {
 426         info->print_insn = print_insn_arm;
 427     }
 428     if (bswap_code(arm_sctlr_b(env))) {
 429 #ifdef TARGET_WORDS_BIGENDIAN
 430         info->endian = BFD_ENDIAN_LITTLE;
 431 #else
 432         info->endian = BFD_ENDIAN_BIG;
 433 #endif
 434     }
 435 }
 436
 437 static void arm_cpu_initfn(Object *obj)
 438 {
 439     CPUState *cs = CPU(obj);
 440     ARMCPU *cpu = ARM_CPU(obj);
 441     static bool inited;
 442
 443     cs->env_ptr = &cpu->env;
 444     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 445                                          g_free, g_free);
 446
 447 #ifndef CONFIG_USER_ONLY
 448     /* Our inbound IRQ and FIQ lines */
 449     if (kvm_enabled()) {
 450         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 451          * the same interface as non-KVM CPUs.
 452          */
 453         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 454     } else {
 455         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 456     }
 457
 458     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 459                                                 arm_gt_ptimer_cb, cpu);
 460     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 461                                                 arm_gt_vtimer_cb, cpu);
 462     cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 463                                                 arm_gt_htimer_cb, cpu);
 464     cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 465                                                 arm_gt_stimer_cb, cpu);
 466     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 467                        ARRAY_SIZE(cpu->gt_timer_outputs));
 468 #endif
 469
 470     /* DTB consumers generally don't in fact care what the 'compatible'
 471      * string is, so always provide some string and trust that a hypothetical
 472      * picky DTB consumer will also provide a helpful error message.
 473      */
 474     cpu->dtb_compatible = "qemu,unknown";
 475     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 476     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 477
 478     if (tcg_enabled()) {
 479         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 480         if (!inited) {
 481             inited = true;
 482             arm_translate_init();
 483         }
 484     }
 485 }
 486
 487 static Property arm_cpu_reset_cbar_property =
 488             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 489
 490 static Property arm_cpu_reset_hivecs_property =
 491             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 492
 493 static Property arm_cpu_rvbar_property =
 494             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 495
 496 static Property arm_cpu_has_el3_property =
 497             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 498
 499 /* use property name "pmu" to match other archs and virt tools */
 500 static Property arm_cpu_has_pmu_property =
 501             DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
 502
 503 static Property arm_cpu_has_mpu_property =
 504             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 505
 506 static Property arm_cpu_pmsav7_dregion_property =
 507             DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
 508
 509 static void arm_cpu_post_init(Object *obj)
 510 {
 511     ARMCPU *cpu = ARM_CPU(obj);
 512
 513     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 514         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 515         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 516                                  &error_abort);
 517     }
 518
 519     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 520         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 521                                  &error_abort);
 522     }
 523
 524     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 525         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 526                                  &error_abort);
 527     }
 528
 529     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 530         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 531          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 532          */
 533         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 534                                  &error_abort);
 535
 536 #ifndef CONFIG_USER_ONLY
 537         object_property_add_link(obj, "secure-memory",
 538                                  TYPE_MEMORY_REGION,
 539                                  (Object **)&cpu->secure_memory,
 540                                  qdev_prop_allow_set_link_before_realize,
 541                                  OBJ_PROP_LINK_UNREF_ON_RELEASE,
 542                                  &error_abort);
 543 #endif
 544     }
 545
 546     if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
 547         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
 548                                  &error_abort);
 549     }
 550
 551     if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
 552         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 553                                  &error_abort);
 554         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 555             qdev_property_add_static(DEVICE(obj),
 556                                      &arm_cpu_pmsav7_dregion_property,
 557                                      &error_abort);
 558         }
 559     }
 560
 561 }
 562
 563 static void arm_cpu_finalizefn(Object *obj)
 564 {
 565     ARMCPU *cpu = ARM_CPU(obj);
 566     g_hash_table_destroy(cpu->cp_regs);
 567 }
 568
 569 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 570 {
 571     CPUState *cs = CPU(dev);
 572     ARMCPU *cpu = ARM_CPU(dev);
 573     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 574     CPUARMState *env = &cpu->env;
 575     int pagebits;
 576     Error *local_err = NULL;
 577
 578     cpu_exec_realizefn(cs, &local_err);
 579     if (local_err != NULL) {
 580         error_propagate(errp, local_err);
 581         return;
 582     }
 583
 584     /* Some features automatically imply others: */
 585     if (arm_feature(env, ARM_FEATURE_V8)) {
 586         set_feature(env, ARM_FEATURE_V7);
 587         set_feature(env, ARM_FEATURE_ARM_DIV);
 588         set_feature(env, ARM_FEATURE_LPAE);
 589     }
 590     if (arm_feature(env, ARM_FEATURE_V7)) {
 591         set_feature(env, ARM_FEATURE_VAPA);
 592         set_feature(env, ARM_FEATURE_THUMB2);
 593         set_feature(env, ARM_FEATURE_MPIDR);
 594         if (!arm_feature(env, ARM_FEATURE_M)) {
 595             set_feature(env, ARM_FEATURE_V6K);
 596         } else {
 597             set_feature(env, ARM_FEATURE_V6);
 598         }
 599
 600         /* Always define VBAR for V7 CPUs even if it doesn't exist in
 601          * non-EL3 configs. This is needed by some legacy boards.
 602          */
 603         set_feature(env, ARM_FEATURE_VBAR);
 604     }
 605     if (arm_feature(env, ARM_FEATURE_V6K)) {
 606         set_feature(env, ARM_FEATURE_V6);
 607         set_feature(env, ARM_FEATURE_MVFR);
 608     }
 609     if (arm_feature(env, ARM_FEATURE_V6)) {
 610         set_feature(env, ARM_FEATURE_V5);
 611         if (!arm_feature(env, ARM_FEATURE_M)) {
 612             set_feature(env, ARM_FEATURE_AUXCR);
 613         }
 614     }
 615     if (arm_feature(env, ARM_FEATURE_V5)) {
 616         set_feature(env, ARM_FEATURE_V4T);
 617     }
 618     if (arm_feature(env, ARM_FEATURE_M)) {
 619         set_feature(env, ARM_FEATURE_THUMB_DIV);
 620     }
 621     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 622         set_feature(env, ARM_FEATURE_THUMB_DIV);
 623     }
 624     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 625         set_feature(env, ARM_FEATURE_VFP3);
 626         set_feature(env, ARM_FEATURE_VFP_FP16);
 627     }
 628     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 629         set_feature(env, ARM_FEATURE_VFP);
 630     }
 631     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 632         set_feature(env, ARM_FEATURE_V7MP);
 633         set_feature(env, ARM_FEATURE_PXN);
 634     }
 635     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 636         set_feature(env, ARM_FEATURE_CBAR);
 637     }
 638     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 639         !arm_feature(env, ARM_FEATURE_M)) {
 640         set_feature(env, ARM_FEATURE_THUMB_DSP);
 641     }
 642
 643     if (arm_feature(env, ARM_FEATURE_V7) &&
 644         !arm_feature(env, ARM_FEATURE_M) &&
 645         !arm_feature(env, ARM_FEATURE_MPU)) {
 646         /* v7VMSA drops support for the old ARMv5 tiny pages, so we
 647          * can use 4K pages.
 648          */
 649         pagebits = 12;
 650     } else {
 651         /* For CPUs which might have tiny 1K pages, or which have an
 652          * MPU and might have small region sizes, stick with 1K pages.
 653          */
 654         pagebits = 10;
 655     }
 656     if (!set_preferred_target_page_bits(pagebits)) {
 657         /* This can only ever happen for hotplugging a CPU, or if
 658          * the board code incorrectly creates a CPU which it has
 659          * promised via minimum_page_size that it will not.
 660          */
 661         error_setg(errp, "This CPU requires a smaller page size than the "
 662                    "system is using");
 663         return;
 664     }
 665
 666     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
 667      * We don't support setting cluster ID ([16..23]) (known as Aff2
 668      * in later ARM ARM versions), or any of the higher affinity level fields,
 669      * so these bits always RAZ.
 670      */
 671     if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
 672         uint32_t Aff1 = cs->cpu_index / ARM_DEFAULT_CPUS_PER_CLUSTER;
 673         uint32_t Aff0 = cs->cpu_index % ARM_DEFAULT_CPUS_PER_CLUSTER;
 674         cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
 675     }
 676
 677     if (cpu->reset_hivecs) {
 678             cpu->reset_sctlr |= (1 << 13);
 679     }
 680
 681     if (!cpu->has_el3) {
 682         /* If the has_el3 CPU property is disabled then we need to disable the
 683          * feature.
 684          */
 685         unset_feature(env, ARM_FEATURE_EL3);
 686
 687         /* Disable the security extension feature bits in the processor feature
 688          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 689          */
 690         cpu->id_pfr1 &= ~0xf0;
 691         cpu->id_aa64pfr0 &= ~0xf000;
 692     }
 693
 694     if (!cpu->has_pmu || !kvm_enabled()) {
 695         cpu->has_pmu = false;
 696         unset_feature(env, ARM_FEATURE_PMU);
 697     }
 698
 699     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 700         /* Disable the hypervisor feature bits in the processor feature
 701          * registers if we don't have EL2. These are id_pfr1[15:12] and
 702          * id_aa64pfr0_el1[11:8].
 703          */
 704         cpu->id_aa64pfr0 &= ~0xf00;
 705         cpu->id_pfr1 &= ~0xf000;
 706     }
 707
 708     if (!cpu->has_mpu) {
 709         unset_feature(env, ARM_FEATURE_MPU);
 710     }
 711
 712     if (arm_feature(env, ARM_FEATURE_MPU) &&
 713         arm_feature(env, ARM_FEATURE_V7)) {
 714         uint32_t nr = cpu->pmsav7_dregion;
 715
 716         if (nr > 0xff) {
 717             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
 718             return;
 719         }
 720
 721         if (nr) {
 722             env->pmsav7.drbar = g_new0(uint32_t, nr);
 723             env->pmsav7.drsr = g_new0(uint32_t, nr);
 724             env->pmsav7.dracr = g_new0(uint32_t, nr);
 725         }
 726     }
 727
 728     if (arm_feature(env, ARM_FEATURE_EL3)) {
 729         set_feature(env, ARM_FEATURE_VBAR);
 730     }
 731
 732     register_cp_regs_for_features(cpu);
 733     arm_cpu_register_gdb_regs_for_features(cpu);
 734
 735     init_cpreg_list(cpu);
 736
 737 #ifndef CONFIG_USER_ONLY
 738     if (cpu->has_el3) {
 739         cs->num_ases = 2;
 740     } else {
 741         cs->num_ases = 1;
 742     }
 743
 744     if (cpu->has_el3) {
 745         AddressSpace *as;
 746
 747         if (!cpu->secure_memory) {
 748             cpu->secure_memory = cs->memory;
 749         }
 750         as = address_space_init_shareable(cpu->secure_memory,
 751                                           "cpu-secure-memory");
 752         cpu_address_space_init(cs, as, ARMASIdx_S);
 753     }
 754     cpu_address_space_init(cs,
 755                            address_space_init_shareable(cs->memory,
 756                                                         "cpu-memory"),
 757                            ARMASIdx_NS);
 758 #endif
 759
 760     qemu_init_vcpu(cs);
 761     cpu_reset(cs);
 762
 763     acc->parent_realize(dev, errp);
 764 }
 765
 766 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 767 {
 768     ObjectClass *oc;
 769     char *typename;
 770     char **cpuname;
 771
 772     if (!cpu_model) {
 773         return NULL;
 774     }
 775
 776     cpuname = g_strsplit(cpu_model, ",", 1);
 777     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
 778     oc = object_class_by_name(typename);
 779     g_strfreev(cpuname);
 780     g_free(typename);
 781     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 782         object_class_is_abstract(oc)) {
 783         return NULL;
 784     }
 785     return oc;
 786 }
 787
 788 /* CPU models. These are not needed for the AArch64 linux-user build. */
 789 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 790
 791 static void arm926_initfn(Object *obj)
 792 {
 793     ARMCPU *cpu = ARM_CPU(obj);
 794
 795     cpu->dtb_compatible = "arm,arm926";
 796     set_feature(&cpu->env, ARM_FEATURE_V5);
 797     set_feature(&cpu->env, ARM_FEATURE_VFP);
 798     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 799     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 800     cpu->midr = 0x41069265;
 801     cpu->reset_fpsid = 0x41011090;
 802     cpu->ctr = 0x1dd20d2;
 803     cpu->reset_sctlr = 0x00090078;
 804 }
 805
 806 static void arm946_initfn(Object *obj)
 807 {
 808     ARMCPU *cpu = ARM_CPU(obj);
 809
 810     cpu->dtb_compatible = "arm,arm946";
 811     set_feature(&cpu->env, ARM_FEATURE_V5);
 812     set_feature(&cpu->env, ARM_FEATURE_MPU);
 813     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 814     cpu->midr = 0x41059461;
 815     cpu->ctr = 0x0f004006;
 816     cpu->reset_sctlr = 0x00000078;
 817 }
 818
 819 static void arm1026_initfn(Object *obj)
 820 {
 821     ARMCPU *cpu = ARM_CPU(obj);
 822
 823     cpu->dtb_compatible = "arm,arm1026";
 824     set_feature(&cpu->env, ARM_FEATURE_V5);
 825     set_feature(&cpu->env, ARM_FEATURE_VFP);
 826     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 827     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 828     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 829     cpu->midr = 0x4106a262;
 830     cpu->reset_fpsid = 0x410110a0;
 831     cpu->ctr = 0x1dd20d2;
 832     cpu->reset_sctlr = 0x00090078;
 833     cpu->reset_auxcr = 1;
 834     {
 835         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 836         ARMCPRegInfo ifar = {
 837             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 838             .access = PL1_RW,
 839             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 840             .resetvalue = 0
 841         };
 842         define_one_arm_cp_reg(cpu, &ifar);
 843     }
 844 }
 845
 846 static void arm1136_r2_initfn(Object *obj)
 847 {
 848     ARMCPU *cpu = ARM_CPU(obj);
 849     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 850      * older core than plain "arm1136". In particular this does not
 851      * have the v6K features.
 852      * These ID register values are correct for 1136 but may be wrong
 853      * for 1136_r2 (in particular r0p2 does not actually implement most
 854      * of the ID registers).
 855      */
 856
 857     cpu->dtb_compatible = "arm,arm1136";
 858     set_feature(&cpu->env, ARM_FEATURE_V6);
 859     set_feature(&cpu->env, ARM_FEATURE_VFP);
 860     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 861     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 862     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 863     cpu->midr = 0x4107b362;
 864     cpu->reset_fpsid = 0x410120b4;
 865     cpu->mvfr0 = 0x11111111;
 866     cpu->mvfr1 = 0x00000000;
 867     cpu->ctr = 0x1dd20d2;
 868     cpu->reset_sctlr = 0x00050078;
 869     cpu->id_pfr0 = 0x111;
 870     cpu->id_pfr1 = 0x1;
 871     cpu->id_dfr0 = 0x2;
 872     cpu->id_afr0 = 0x3;
 873     cpu->id_mmfr0 = 0x01130003;
 874     cpu->id_mmfr1 = 0x10030302;
 875     cpu->id_mmfr2 = 0x01222110;
 876     cpu->id_isar0 = 0x00140011;
 877     cpu->id_isar1 = 0x12002111;
 878     cpu->id_isar2 = 0x11231111;
 879     cpu->id_isar3 = 0x01102131;
 880     cpu->id_isar4 = 0x141;
 881     cpu->reset_auxcr = 7;
 882 }
 883
 884 static void arm1136_initfn(Object *obj)
 885 {
 886     ARMCPU *cpu = ARM_CPU(obj);
 887
 888     cpu->dtb_compatible = "arm,arm1136";
 889     set_feature(&cpu->env, ARM_FEATURE_V6K);
 890     set_feature(&cpu->env, ARM_FEATURE_V6);
 891     set_feature(&cpu->env, ARM_FEATURE_VFP);
 892     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 893     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 894     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 895     cpu->midr = 0x4117b363;
 896     cpu->reset_fpsid = 0x410120b4;
 897     cpu->mvfr0 = 0x11111111;
 898     cpu->mvfr1 = 0x00000000;
 899     cpu->ctr = 0x1dd20d2;
 900     cpu->reset_sctlr = 0x00050078;
 901     cpu->id_pfr0 = 0x111;
 902     cpu->id_pfr1 = 0x1;
 903     cpu->id_dfr0 = 0x2;
 904     cpu->id_afr0 = 0x3;
 905     cpu->id_mmfr0 = 0x01130003;
 906     cpu->id_mmfr1 = 0x10030302;
 907     cpu->id_mmfr2 = 0x01222110;
 908     cpu->id_isar0 = 0x00140011;
 909     cpu->id_isar1 = 0x12002111;
 910     cpu->id_isar2 = 0x11231111;
 911     cpu->id_isar3 = 0x01102131;
 912     cpu->id_isar4 = 0x141;
 913     cpu->reset_auxcr = 7;
 914 }
 915
 916 static void arm1176_initfn(Object *obj)
 917 {
 918     ARMCPU *cpu = ARM_CPU(obj);
 919
 920     cpu->dtb_compatible = "arm,arm1176";
 921     set_feature(&cpu->env, ARM_FEATURE_V6K);
 922     set_feature(&cpu->env, ARM_FEATURE_VFP);
 923     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 924     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 925     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 926     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 927     set_feature(&cpu->env, ARM_FEATURE_EL3);
 928     cpu->midr = 0x410fb767;
 929     cpu->reset_fpsid = 0x410120b5;
 930     cpu->mvfr0 = 0x11111111;
 931     cpu->mvfr1 = 0x00000000;
 932     cpu->ctr = 0x1dd20d2;
 933     cpu->reset_sctlr = 0x00050078;
 934     cpu->id_pfr0 = 0x111;
 935     cpu->id_pfr1 = 0x11;
 936     cpu->id_dfr0 = 0x33;
 937     cpu->id_afr0 = 0;
 938     cpu->id_mmfr0 = 0x01130003;
 939     cpu->id_mmfr1 = 0x10030302;
 940     cpu->id_mmfr2 = 0x01222100;
 941     cpu->id_isar0 = 0x0140011;
 942     cpu->id_isar1 = 0x12002111;
 943     cpu->id_isar2 = 0x11231121;
 944     cpu->id_isar3 = 0x01102131;
 945     cpu->id_isar4 = 0x01141;
 946     cpu->reset_auxcr = 7;
 947 }
 948
 949 static void arm11mpcore_initfn(Object *obj)
 950 {
 951     ARMCPU *cpu = ARM_CPU(obj);
 952
 953     cpu->dtb_compatible = "arm,arm11mpcore";
 954     set_feature(&cpu->env, ARM_FEATURE_V6K);
 955     set_feature(&cpu->env, ARM_FEATURE_VFP);
 956     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 957     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 958     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 959     cpu->midr = 0x410fb022;
 960     cpu->reset_fpsid = 0x410120b4;
 961     cpu->mvfr0 = 0x11111111;
 962     cpu->mvfr1 = 0x00000000;
 963     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 964     cpu->id_pfr0 = 0x111;
 965     cpu->id_pfr1 = 0x1;
 966     cpu->id_dfr0 = 0;
 967     cpu->id_afr0 = 0x2;
 968     cpu->id_mmfr0 = 0x01100103;
 969     cpu->id_mmfr1 = 0x10020302;
 970     cpu->id_mmfr2 = 0x01222000;
 971     cpu->id_isar0 = 0x00100011;
 972     cpu->id_isar1 = 0x12002111;
 973     cpu->id_isar2 = 0x11221011;
 974     cpu->id_isar3 = 0x01102131;
 975     cpu->id_isar4 = 0x141;
 976     cpu->reset_auxcr = 1;
 977 }
 978
 979 static void cortex_m3_initfn(Object *obj)
 980 {
 981     ARMCPU *cpu = ARM_CPU(obj);
 982     set_feature(&cpu->env, ARM_FEATURE_V7);
 983     set_feature(&cpu->env, ARM_FEATURE_M);
 984     cpu->midr = 0x410fc231;
 985 }
 986
 987 static void cortex_m4_initfn(Object *obj)
 988 {
 989     ARMCPU *cpu = ARM_CPU(obj);
 990
 991     set_feature(&cpu->env, ARM_FEATURE_V7);
 992     set_feature(&cpu->env, ARM_FEATURE_M);
 993     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 994     cpu->midr = 0x410fc240; /* r0p0 */
 995 }
 996 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 997 {
 998     CPUClass *cc = CPU_CLASS(oc);
 999
1000 #ifndef CONFIG_USER_ONLY
1001     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1002 #endif
1003
1004     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1005 }
1006
1007 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1008     /* Dummy the TCM region regs for the moment */
1009     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1010       .access = PL1_RW, .type = ARM_CP_CONST },
1011     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1012       .access = PL1_RW, .type = ARM_CP_CONST },
1013     REGINFO_SENTINEL
1014 };
1015
1016 static void cortex_r5_initfn(Object *obj)
1017 {
1018     ARMCPU *cpu = ARM_CPU(obj);
1019
1020     set_feature(&cpu->env, ARM_FEATURE_V7);
1021     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
1022     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1023     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1024     set_feature(&cpu->env, ARM_FEATURE_MPU);
1025     cpu->midr = 0x411fc153; /* r1p3 */
1026     cpu->id_pfr0 = 0x0131;
1027     cpu->id_pfr1 = 0x001;
1028     cpu->id_dfr0 = 0x010400;
1029     cpu->id_afr0 = 0x0;
1030     cpu->id_mmfr0 = 0x0210030;
1031     cpu->id_mmfr1 = 0x00000000;
1032     cpu->id_mmfr2 = 0x01200000;
1033     cpu->id_mmfr3 = 0x0211;
1034     cpu->id_isar0 = 0x2101111;
1035     cpu->id_isar1 = 0x13112111;
1036     cpu->id_isar2 = 0x21232141;
1037     cpu->id_isar3 = 0x01112131;
1038     cpu->id_isar4 = 0x0010142;
1039     cpu->id_isar5 = 0x0;
1040     cpu->mp_is_up = true;
1041     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1042 }
1043
1044 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1045     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1046       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1047     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1048       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1049     REGINFO_SENTINEL
1050 };
1051
1052 static void cortex_a8_initfn(Object *obj)
1053 {
1054     ARMCPU *cpu = ARM_CPU(obj);
1055
1056     cpu->dtb_compatible = "arm,cortex-a8";
1057     set_feature(&cpu->env, ARM_FEATURE_V7);
1058     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1059     set_feature(&cpu->env, ARM_FEATURE_NEON);
1060     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1061     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1062     set_feature(&cpu->env, ARM_FEATURE_EL3);
1063     cpu->midr = 0x410fc080;
1064     cpu->reset_fpsid = 0x410330c0;
1065     cpu->mvfr0 = 0x11110222;
1066     cpu->mvfr1 = 0x00011111;
1067     cpu->ctr = 0x82048004;
1068     cpu->reset_sctlr = 0x00c50078;
1069     cpu->id_pfr0 = 0x1031;
1070     cpu->id_pfr1 = 0x11;
1071     cpu->id_dfr0 = 0x400;
1072     cpu->id_afr0 = 0;
1073     cpu->id_mmfr0 = 0x31100003;
1074     cpu->id_mmfr1 = 0x20000000;
1075     cpu->id_mmfr2 = 0x01202000;
1076     cpu->id_mmfr3 = 0x11;
1077     cpu->id_isar0 = 0x00101111;
1078     cpu->id_isar1 = 0x12112111;
1079     cpu->id_isar2 = 0x21232031;
1080     cpu->id_isar3 = 0x11112131;
1081     cpu->id_isar4 = 0x00111142;
1082     cpu->dbgdidr = 0x15141000;
1083     cpu->clidr = (1 << 27) | (2 << 24) | 3;
1084     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1085     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1086     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1087     cpu->reset_auxcr = 2;
1088     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1089 }
1090
1091 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1092     /* power_control should be set to maximum latency. Again,
1093      * default to 0 and set by private hook
1094      */
1095     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1096       .access = PL1_RW, .resetvalue = 0,
1097       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1098     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1099       .access = PL1_RW, .resetvalue = 0,
1100       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1101     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1102       .access = PL1_RW, .resetvalue = 0,
1103       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1104     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1105       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1106     /* TLB lockdown control */
1107     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1108       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1109     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1110       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1111     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1112       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1113     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1114       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1115     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1116       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1117     REGINFO_SENTINEL
1118 };
1119
1120 static void cortex_a9_initfn(Object *obj)
1121 {
1122     ARMCPU *cpu = ARM_CPU(obj);
1123
1124     cpu->dtb_compatible = "arm,cortex-a9";
1125     set_feature(&cpu->env, ARM_FEATURE_V7);
1126     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1127     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1128     set_feature(&cpu->env, ARM_FEATURE_NEON);
1129     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1130     set_feature(&cpu->env, ARM_FEATURE_EL3);
1131     /* Note that A9 supports the MP extensions even for
1132      * A9UP and single-core A9MP (which are both different
1133      * and valid configurations; we don't model A9UP).
1134      */
1135     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1136     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1137     cpu->midr = 0x410fc090;
1138     cpu->reset_fpsid = 0x41033090;
1139     cpu->mvfr0 = 0x11110222;
1140     cpu->mvfr1 = 0x01111111;
1141     cpu->ctr = 0x80038003;
1142     cpu->reset_sctlr = 0x00c50078;
1143     cpu->id_pfr0 = 0x1031;
1144     cpu->id_pfr1 = 0x11;
1145     cpu->id_dfr0 = 0x000;
1146     cpu->id_afr0 = 0;
1147     cpu->id_mmfr0 = 0x00100103;
1148     cpu->id_mmfr1 = 0x20000000;
1149     cpu->id_mmfr2 = 0x01230000;
1150     cpu->id_mmfr3 = 0x00002111;
1151     cpu->id_isar0 = 0x00101111;
1152     cpu->id_isar1 = 0x13112111;
1153     cpu->id_isar2 = 0x21232041;
1154     cpu->id_isar3 = 0x11112131;
1155     cpu->id_isar4 = 0x00111142;
1156     cpu->dbgdidr = 0x35141000;
1157     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1158     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1159     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1160     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1161 }
1162
1163 #ifndef CONFIG_USER_ONLY
1164 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1165 {
1166     /* Linux wants the number of processors from here.
1167      * Might as well set the interrupt-controller bit too.
1168      */
1169     return ((smp_cpus - 1) << 24) | (1 << 23);
1170 }
1171 #endif
1172
1173 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1174 #ifndef CONFIG_USER_ONLY
1175     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1176       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1177       .writefn = arm_cp_write_ignore, },
1178 #endif
1179     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1180       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1181     REGINFO_SENTINEL
1182 };
1183
1184 static void cortex_a7_initfn(Object *obj)
1185 {
1186     ARMCPU *cpu = ARM_CPU(obj);
1187
1188     cpu->dtb_compatible = "arm,cortex-a7";
1189     set_feature(&cpu->env, ARM_FEATURE_V7);
1190     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1191     set_feature(&cpu->env, ARM_FEATURE_NEON);
1192     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1193     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1194     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1195     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1196     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1197     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1198     set_feature(&cpu->env, ARM_FEATURE_EL3);
1199     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1200     cpu->midr = 0x410fc075;
1201     cpu->reset_fpsid = 0x41023075;
1202     cpu->mvfr0 = 0x10110222;
1203     cpu->mvfr1 = 0x11111111;
1204     cpu->ctr = 0x84448003;
1205     cpu->reset_sctlr = 0x00c50078;
1206     cpu->id_pfr0 = 0x00001131;
1207     cpu->id_pfr1 = 0x00011011;
1208     cpu->id_dfr0 = 0x02010555;
1209     cpu->pmceid0 = 0x00000000;
1210     cpu->pmceid1 = 0x00000000;
1211     cpu->id_afr0 = 0x00000000;
1212     cpu->id_mmfr0 = 0x10101105;
1213     cpu->id_mmfr1 = 0x40000000;
1214     cpu->id_mmfr2 = 0x01240000;
1215     cpu->id_mmfr3 = 0x02102211;
1216     cpu->id_isar0 = 0x01101110;
1217     cpu->id_isar1 = 0x13112111;
1218     cpu->id_isar2 = 0x21232041;
1219     cpu->id_isar3 = 0x11112131;
1220     cpu->id_isar4 = 0x10011142;
1221     cpu->dbgdidr = 0x3515f005;
1222     cpu->clidr = 0x0a200023;
1223     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1224     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1225     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1226     define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
1227 }
1228
1229 static void cortex_a15_initfn(Object *obj)
1230 {
1231     ARMCPU *cpu = ARM_CPU(obj);
1232
1233     cpu->dtb_compatible = "arm,cortex-a15";
1234     set_feature(&cpu->env, ARM_FEATURE_V7);
1235     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1236     set_feature(&cpu->env, ARM_FEATURE_NEON);
1237     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1238     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1239     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1240     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1241     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1242     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1243     set_feature(&cpu->env, ARM_FEATURE_EL3);
1244     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1245     cpu->midr = 0x412fc0f1;
1246     cpu->reset_fpsid = 0x410430f0;
1247     cpu->mvfr0 = 0x10110222;
1248     cpu->mvfr1 = 0x11111111;
1249     cpu->ctr = 0x8444c004;
1250     cpu->reset_sctlr = 0x00c50078;
1251     cpu->id_pfr0 = 0x00001131;
1252     cpu->id_pfr1 = 0x00011011;
1253     cpu->id_dfr0 = 0x02010555;
1254     cpu->pmceid0 = 0x0000000;
1255     cpu->pmceid1 = 0x00000000;
1256     cpu->id_afr0 = 0x00000000;
1257     cpu->id_mmfr0 = 0x10201105;
1258     cpu->id_mmfr1 = 0x20000000;
1259     cpu->id_mmfr2 = 0x01240000;
1260     cpu->id_mmfr3 = 0x02102211;
1261     cpu->id_isar0 = 0x02101110;
1262     cpu->id_isar1 = 0x13112111;
1263     cpu->id_isar2 = 0x21232041;
1264     cpu->id_isar3 = 0x11112131;
1265     cpu->id_isar4 = 0x10011142;
1266     cpu->dbgdidr = 0x3515f021;
1267     cpu->clidr = 0x0a200023;
1268     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1269     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1270     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1271     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1272 }
1273
1274 static void ti925t_initfn(Object *obj)
1275 {
1276     ARMCPU *cpu = ARM_CPU(obj);
1277     set_feature(&cpu->env, ARM_FEATURE_V4T);
1278     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1279     cpu->midr = ARM_CPUID_TI925T;
1280     cpu->ctr = 0x5109149;
1281     cpu->reset_sctlr = 0x00000070;
1282 }
1283
1284 static void sa1100_initfn(Object *obj)
1285 {
1286     ARMCPU *cpu = ARM_CPU(obj);
1287
1288     cpu->dtb_compatible = "intel,sa1100";
1289     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1290     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1291     cpu->midr = 0x4401A11B;
1292     cpu->reset_sctlr = 0x00000070;
1293 }
1294
1295 static void sa1110_initfn(Object *obj)
1296 {
1297     ARMCPU *cpu = ARM_CPU(obj);
1298     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1299     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1300     cpu->midr = 0x6901B119;
1301     cpu->reset_sctlr = 0x00000070;
1302 }
1303
1304 static void pxa250_initfn(Object *obj)
1305 {
1306     ARMCPU *cpu = ARM_CPU(obj);
1307
1308     cpu->dtb_compatible = "marvell,xscale";
1309     set_feature(&cpu->env, ARM_FEATURE_V5);
1310     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1311     cpu->midr = 0x69052100;
1312     cpu->ctr = 0xd172172;
1313     cpu->reset_sctlr = 0x00000078;
1314 }
1315
1316 static void pxa255_initfn(Object *obj)
1317 {
1318     ARMCPU *cpu = ARM_CPU(obj);
1319
1320     cpu->dtb_compatible = "marvell,xscale";
1321     set_feature(&cpu->env, ARM_FEATURE_V5);
1322     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1323     cpu->midr = 0x69052d00;
1324     cpu->ctr = 0xd172172;
1325     cpu->reset_sctlr = 0x00000078;
1326 }
1327
1328 static void pxa260_initfn(Object *obj)
1329 {
1330     ARMCPU *cpu = ARM_CPU(obj);
1331
1332     cpu->dtb_compatible = "marvell,xscale";
1333     set_feature(&cpu->env, ARM_FEATURE_V5);
1334     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1335     cpu->midr = 0x69052903;
1336     cpu->ctr = 0xd172172;
1337     cpu->reset_sctlr = 0x00000078;
1338 }
1339
1340 static void pxa261_initfn(Object *obj)
1341 {
1342     ARMCPU *cpu = ARM_CPU(obj);
1343
1344     cpu->dtb_compatible = "marvell,xscale";
1345     set_feature(&cpu->env, ARM_FEATURE_V5);
1346     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1347     cpu->midr = 0x69052d05;
1348     cpu->ctr = 0xd172172;
1349     cpu->reset_sctlr = 0x00000078;
1350 }
1351
1352 static void pxa262_initfn(Object *obj)
1353 {
1354     ARMCPU *cpu = ARM_CPU(obj);
1355
1356     cpu->dtb_compatible = "marvell,xscale";
1357     set_feature(&cpu->env, ARM_FEATURE_V5);
1358     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1359     cpu->midr = 0x69052d06;
1360     cpu->ctr = 0xd172172;
1361     cpu->reset_sctlr = 0x00000078;
1362 }
1363
1364 static void pxa270a0_initfn(Object *obj)
1365 {
1366     ARMCPU *cpu = ARM_CPU(obj);
1367
1368     cpu->dtb_compatible = "marvell,xscale";
1369     set_feature(&cpu->env, ARM_FEATURE_V5);
1370     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1371     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1372     cpu->midr = 0x69054110;
1373     cpu->ctr = 0xd172172;
1374     cpu->reset_sctlr = 0x00000078;
1375 }
1376
1377 static void pxa270a1_initfn(Object *obj)
1378 {
1379     ARMCPU *cpu = ARM_CPU(obj);
1380
1381     cpu->dtb_compatible = "marvell,xscale";
1382     set_feature(&cpu->env, ARM_FEATURE_V5);
1383     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1384     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1385     cpu->midr = 0x69054111;
1386     cpu->ctr = 0xd172172;
1387     cpu->reset_sctlr = 0x00000078;
1388 }
1389
1390 static void pxa270b0_initfn(Object *obj)
1391 {
1392     ARMCPU *cpu = ARM_CPU(obj);
1393
1394     cpu->dtb_compatible = "marvell,xscale";
1395     set_feature(&cpu->env, ARM_FEATURE_V5);
1396     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1397     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1398     cpu->midr = 0x69054112;
1399     cpu->ctr = 0xd172172;
1400     cpu->reset_sctlr = 0x00000078;
1401 }
1402
1403 static void pxa270b1_initfn(Object *obj)
1404 {
1405     ARMCPU *cpu = ARM_CPU(obj);
1406
1407     cpu->dtb_compatible = "marvell,xscale";
1408     set_feature(&cpu->env, ARM_FEATURE_V5);
1409     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1410     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1411     cpu->midr = 0x69054113;
1412     cpu->ctr = 0xd172172;
1413     cpu->reset_sctlr = 0x00000078;
1414 }
1415
1416 static void pxa270c0_initfn(Object *obj)
1417 {
1418     ARMCPU *cpu = ARM_CPU(obj);
1419
1420     cpu->dtb_compatible = "marvell,xscale";
1421     set_feature(&cpu->env, ARM_FEATURE_V5);
1422     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1423     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1424     cpu->midr = 0x69054114;
1425     cpu->ctr = 0xd172172;
1426     cpu->reset_sctlr = 0x00000078;
1427 }
1428
1429 static void pxa270c5_initfn(Object *obj)
1430 {
1431     ARMCPU *cpu = ARM_CPU(obj);
1432
1433     cpu->dtb_compatible = "marvell,xscale";
1434     set_feature(&cpu->env, ARM_FEATURE_V5);
1435     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1436     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1437     cpu->midr = 0x69054117;
1438     cpu->ctr = 0xd172172;
1439     cpu->reset_sctlr = 0x00000078;
1440 }
1441
1442 #ifdef CONFIG_USER_ONLY
1443 static void arm_any_initfn(Object *obj)
1444 {
1445     ARMCPU *cpu = ARM_CPU(obj);
1446     set_feature(&cpu->env, ARM_FEATURE_V8);
1447     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1448     set_feature(&cpu->env, ARM_FEATURE_NEON);
1449     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1450     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1451     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1452     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1453     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1454     set_feature(&cpu->env, ARM_FEATURE_CRC);
1455     cpu->midr = 0xffffffff;
1456 }
1457 #endif
1458
1459 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1460
1461 typedef struct ARMCPUInfo {
1462     const char *name;
1463     void (*initfn)(Object *obj);
1464     void (*class_init)(ObjectClass *oc, void *data);
1465 } ARMCPUInfo;
1466
1467 static const ARMCPUInfo arm_cpus[] = {
1468 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1469     { .name = "arm926",      .initfn = arm926_initfn },
1470     { .name = "arm946",      .initfn = arm946_initfn },
1471     { .name = "arm1026",     .initfn = arm1026_initfn },
1472     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1473      * older core than plain "arm1136". In particular this does not
1474      * have the v6K features.
1475      */
1476     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1477     { .name = "arm1136",     .initfn = arm1136_initfn },
1478     { .name = "arm1176",     .initfn = arm1176_initfn },
1479     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1480     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1481                              .class_init = arm_v7m_class_init },
1482     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1483                              .class_init = arm_v7m_class_init },
1484     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1485     { .name = "cortex-a7",   .initfn = cortex_a7_initfn },
1486     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1487     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1488     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1489     { .name = "ti925t",      .initfn = ti925t_initfn },
1490     { .name = "sa1100",      .initfn = sa1100_initfn },
1491     { .name = "sa1110",      .initfn = sa1110_initfn },
1492     { .name = "pxa250",      .initfn = pxa250_initfn },
1493     { .name = "pxa255",      .initfn = pxa255_initfn },
1494     { .name = "pxa260",      .initfn = pxa260_initfn },
1495     { .name = "pxa261",      .initfn = pxa261_initfn },
1496     { .name = "pxa262",      .initfn = pxa262_initfn },
1497     /* "pxa270" is an alias for "pxa270-a0" */
1498     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1499     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1500     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1501     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1502     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1503     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1504     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1505 #ifdef CONFIG_USER_ONLY
1506     { .name = "any",         .initfn = arm_any_initfn },
1507 #endif
1508 #endif
1509     { .name = NULL }
1510 };
1511
1512 static Property arm_cpu_properties[] = {
1513     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1514     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1515     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1516     DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
1517                         mp_affinity, ARM64_AFFINITY_INVALID),
1518     DEFINE_PROP_END_OF_LIST()
1519 };
1520
1521 #ifdef CONFIG_USER_ONLY
1522 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1523                                     int mmu_idx)
1524 {
1525     ARMCPU *cpu = ARM_CPU(cs);
1526     CPUARMState *env = &cpu->env;
1527
1528     env->exception.vaddress = address;
1529     if (rw == 2) {
1530         cs->exception_index = EXCP_PREFETCH_ABORT;
1531     } else {
1532         cs->exception_index = EXCP_DATA_ABORT;
1533     }
1534     return 1;
1535 }
1536 #endif
1537
1538 static gchar *arm_gdb_arch_name(CPUState *cs)
1539 {
1540     ARMCPU *cpu = ARM_CPU(cs);
1541     CPUARMState *env = &cpu->env;
1542
1543     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1544         return g_strdup("iwmmxt");
1545     }
1546     return g_strdup("arm");
1547 }
1548
1549 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1550 {
1551     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1552     CPUClass *cc = CPU_CLASS(acc);
1553     DeviceClass *dc = DEVICE_CLASS(oc);
1554
1555     acc->parent_realize = dc->realize;
1556     dc->realize = arm_cpu_realizefn;
1557     dc->props = arm_cpu_properties;
1558
1559     acc->parent_reset = cc->reset;
1560     cc->reset = arm_cpu_reset;
1561
1562     cc->class_by_name = arm_cpu_class_by_name;
1563     cc->has_work = arm_cpu_has_work;
1564     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1565     cc->dump_state = arm_cpu_dump_state;
1566     cc->set_pc = arm_cpu_set_pc;
1567     cc->gdb_read_register = arm_cpu_gdb_read_register;
1568     cc->gdb_write_register = arm_cpu_gdb_write_register;
1569 #ifdef CONFIG_USER_ONLY
1570     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1571 #else
1572     cc->do_interrupt = arm_cpu_do_interrupt;
1573     cc->do_unaligned_access = arm_cpu_do_unaligned_access;
1574     cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
1575     cc->asidx_from_attrs = arm_asidx_from_attrs;
1576     cc->vmsd = &vmstate_arm_cpu;
1577     cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
1578     cc->write_elf64_note = arm_cpu_write_elf64_note;
1579     cc->write_elf32_note = arm_cpu_write_elf32_note;
1580 #endif
1581     cc->gdb_num_core_regs = 26;
1582     cc->gdb_core_xml_file = "arm-core.xml";
1583     cc->gdb_arch_name = arm_gdb_arch_name;
1584     cc->gdb_stop_before_watchpoint = true;
1585     cc->debug_excp_handler = arm_debug_excp_handler;
1586     cc->debug_check_watchpoint = arm_debug_check_watchpoint;
1587
1588     cc->disas_set_info = arm_disas_set_info;
1589 }
1590
1591 static void cpu_register(const ARMCPUInfo *info)
1592 {
1593     TypeInfo type_info = {
1594         .parent = TYPE_ARM_CPU,
1595         .instance_size = sizeof(ARMCPU),
1596         .instance_init = info->initfn,
1597         .class_size = sizeof(ARMCPUClass),
1598         .class_init = info->class_init,
1599     };
1600
1601     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1602     type_register(&type_info);
1603     g_free((void *)type_info.name);
1604 }
1605
1606 static const TypeInfo arm_cpu_type_info = {
1607     .name = TYPE_ARM_CPU,
1608     .parent = TYPE_CPU,
1609     .instance_size = sizeof(ARMCPU),
1610     .instance_init = arm_cpu_initfn,
1611     .instance_post_init = arm_cpu_post_init,
1612     .instance_finalize = arm_cpu_finalizefn,
1613     .abstract = true,
1614     .class_size = sizeof(ARMCPUClass),
1615     .class_init = arm_cpu_class_init,
1616 };
1617
1618 static void arm_cpu_register_types(void)
1619 {
1620     const ARMCPUInfo *info = arm_cpus;
1621
1622     type_register_static(&arm_cpu_type_info);
1623
1624     while (info->name) {
1625         cpu_register(info);
1626         info++;
1627     }
1628 }
1629
1630 type_init(arm_cpu_register_types)