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cb9c377f PB |
1 | #ifndef HW_QXL_H |
2 | #define HW_QXL_H 1 | |
3 | ||
a19cbfb3 GH |
4 | #include "qemu-common.h" |
5 | ||
28ecbaee | 6 | #include "ui/console.h" |
83c9f4ca PB |
7 | #include "hw/hw.h" |
8 | #include "hw/pci/pci.h" | |
47b43a1f | 9 | #include "vga_int.h" |
1de7afc9 | 10 | #include "qemu/thread.h" |
a19cbfb3 GH |
11 | |
12 | #include "ui/qemu-spice.h" | |
13 | #include "ui/spice-display.h" | |
14 | ||
15 | enum qxl_mode { | |
16 | QXL_MODE_UNDEFINED, | |
17 | QXL_MODE_VGA, | |
18 | QXL_MODE_COMPAT, /* spice 0.4.x */ | |
19 | QXL_MODE_NATIVE, | |
20 | }; | |
21 | ||
6f2b175a GH |
22 | #ifndef QXL_VRAM64_RANGE_INDEX |
23 | #define QXL_VRAM64_RANGE_INDEX 4 | |
24 | #endif | |
25 | ||
5ff4e36c AL |
26 | #define QXL_UNDEFINED_IO UINT32_MAX |
27 | ||
81fb6f15 AL |
28 | #define QXL_NUM_DIRTY_RECTS 64 |
29 | ||
9efc2d8d GH |
30 | #define QXL_PAGE_BITS 12 |
31 | #define QXL_PAGE_SIZE (1 << QXL_PAGE_BITS); | |
32 | ||
a19cbfb3 GH |
33 | typedef struct PCIQXLDevice { |
34 | PCIDevice pci; | |
848696bf | 35 | PortioList vga_port_list; |
a19cbfb3 GH |
36 | SimpleSpiceDisplay ssd; |
37 | int id; | |
38 | uint32_t debug; | |
39 | uint32_t guestdebug; | |
40 | uint32_t cmdlog; | |
087e6a42 AL |
41 | |
42 | uint32_t guest_bug; | |
43 | ||
a19cbfb3 GH |
44 | enum qxl_mode mode; |
45 | uint32_t cmdflags; | |
46 | int generation; | |
47 | uint32_t revision; | |
48 | ||
49 | int32_t num_memslots; | |
a19cbfb3 | 50 | |
5ff4e36c AL |
51 | uint32_t current_async; |
52 | QemuMutex async_lock; | |
53 | ||
a19cbfb3 GH |
54 | struct guest_slots { |
55 | QXLMemSlot slot; | |
56 | void *ptr; | |
57 | uint64_t size; | |
58 | uint64_t delta; | |
59 | uint32_t active; | |
60 | } guest_slots[NUM_MEMSLOTS]; | |
61 | ||
62 | struct guest_primary { | |
63 | QXLSurfaceCreate surface; | |
64 | uint32_t commands; | |
65 | uint32_t resized; | |
0e2487bd GH |
66 | int32_t qxl_stride; |
67 | uint32_t abs_stride; | |
a19cbfb3 GH |
68 | uint32_t bits_pp; |
69 | uint32_t bytes_pp; | |
4c19ebb5 | 70 | uint8_t *data; |
a19cbfb3 GH |
71 | } guest_primary; |
72 | ||
73 | struct surfaces { | |
ddd8fdc7 | 74 | QXLPHYSICAL *cmds; |
a19cbfb3 GH |
75 | uint32_t count; |
76 | uint32_t max; | |
77 | } guest_surfaces; | |
78 | QXLPHYSICAL guest_cursor; | |
79 | ||
020af1c4 AL |
80 | QXLPHYSICAL guest_monitors_config; |
81 | ||
14898cf6 GH |
82 | QemuMutex track_lock; |
83 | ||
a19cbfb3 | 84 | /* thread signaling */ |
4a46c99c | 85 | QEMUBH *update_irq; |
a19cbfb3 GH |
86 | |
87 | /* ram pci bar */ | |
88 | QXLRam *ram; | |
89 | VGACommonState vga; | |
90 | uint32_t num_free_res; | |
91 | QXLReleaseInfo *last_release; | |
92 | uint32_t last_release_offset; | |
93 | uint32_t oom_running; | |
13d1fd44 | 94 | uint32_t vgamem_size; |
a19cbfb3 GH |
95 | |
96 | /* rom pci bar */ | |
97 | QXLRom shadow_rom; | |
98 | QXLRom *rom; | |
99 | QXLModes *modes; | |
100 | uint32_t rom_size; | |
b1950430 | 101 | MemoryRegion rom_bar; |
a19cbfb3 GH |
102 | |
103 | /* vram pci bar */ | |
104 | uint32_t vram_size; | |
b1950430 | 105 | MemoryRegion vram_bar; |
6f2b175a GH |
106 | uint32_t vram32_size; |
107 | MemoryRegion vram32_bar; | |
a19cbfb3 GH |
108 | |
109 | /* io bar */ | |
b1950430 | 110 | MemoryRegion io_bar; |
017438ee GH |
111 | |
112 | /* user-friendly properties (in megabytes) */ | |
113 | uint32_t ram_size_mb; | |
114 | uint32_t vram_size_mb; | |
6f2b175a | 115 | uint32_t vram32_size_mb; |
13d1fd44 | 116 | uint32_t vgamem_size_mb; |
81fb6f15 AL |
117 | |
118 | /* qxl_render_update state */ | |
119 | int render_update_cookie_num; | |
120 | int num_dirty_rects; | |
121 | QXLRect dirty[QXL_NUM_DIRTY_RECTS]; | |
122 | QEMUBH *update_area_bh; | |
a19cbfb3 GH |
123 | } PCIQXLDevice; |
124 | ||
125 | #define PANIC_ON(x) if ((x)) { \ | |
126 | printf("%s: PANIC %s failed\n", __FUNCTION__, #x); \ | |
2bce0400 | 127 | abort(); \ |
a19cbfb3 GH |
128 | } |
129 | ||
130 | #define dprint(_qxl, _level, _fmt, ...) \ | |
131 | do { \ | |
132 | if (_qxl->debug >= _level) { \ | |
133 | fprintf(stderr, "qxl-%d: ", _qxl->id); \ | |
134 | fprintf(stderr, _fmt, ## __VA_ARGS__); \ | |
135 | } \ | |
136 | } while (0) | |
137 | ||
020af1c4 | 138 | #define QXL_DEFAULT_REVISION QXL_REVISION_STABLE_V12 |
9197a7c8 | 139 | |
a19cbfb3 GH |
140 | /* qxl.c */ |
141 | void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL phys, int group_id); | |
0a530548 AL |
142 | void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...) |
143 | GCC_FMT_ATTR(2, 3); | |
a19cbfb3 | 144 | |
aee32bf3 GH |
145 | void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id, |
146 | struct QXLRect *area, struct QXLRect *dirty_rects, | |
147 | uint32_t num_dirty_rects, | |
5ff4e36c | 148 | uint32_t clear_dirty_region, |
2e1a98c9 | 149 | qxl_async_io async, QXLCookie *cookie); |
aee32bf3 GH |
150 | void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext, |
151 | uint32_t count); | |
152 | void qxl_spice_oom(PCIQXLDevice *qxl); | |
153 | void qxl_spice_reset_memslots(PCIQXLDevice *qxl); | |
aee32bf3 GH |
154 | void qxl_spice_reset_image_cache(PCIQXLDevice *qxl); |
155 | void qxl_spice_reset_cursor(PCIQXLDevice *qxl); | |
156 | ||
a19cbfb3 | 157 | /* qxl-logger.c */ |
fae2afb1 AL |
158 | int qxl_log_cmd_cursor(PCIQXLDevice *qxl, QXLCursorCmd *cmd, int group_id); |
159 | int qxl_log_command(PCIQXLDevice *qxl, const char *ring, QXLCommandExt *ext); | |
a19cbfb3 GH |
160 | |
161 | /* qxl-render.c */ | |
162 | void qxl_render_resize(PCIQXLDevice *qxl); | |
163 | void qxl_render_update(PCIQXLDevice *qxl); | |
fae2afb1 | 164 | int qxl_render_cursor(PCIQXLDevice *qxl, QXLCommandExt *ext); |
81fb6f15 AL |
165 | void qxl_render_update_area_done(PCIQXLDevice *qxl, QXLCookie *cookie); |
166 | void qxl_render_update_area_bh(void *opaque); | |
cb9c377f PB |
167 | |
168 | #endif |