[qemu.git] / target-cris / op_helper.c

/*
 *  CRIS helper routines
 *
 *  Copyright (c) 2007 AXIS Communications
 *  Written by Edgar E. Iglesias
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "mmu.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "exec/cpu_ldst.h"

//#define CRIS_OP_HELPER_DEBUG


#ifdef CRIS_OP_HELPER_DEBUG
#define D(x) x
#define D_LOG(...) qemu_log(__VA_ARGS__)
#else
#define D(x)
#define D_LOG(...) do { } while (0)
#endif

#if !defined(CONFIG_USER_ONLY)
/* Try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
              uintptr_t retaddr)
{
    CRISCPU *cpu = CRIS_CPU(cs);
    CPUCRISState *env = &cpu->env;
    int ret;

    D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
          env->pc, env->pregs[PR_EDA], (void *)retaddr);
    ret = cris_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            if (cpu_restore_state(cs, retaddr)) {
		/* Evaluate flags after retranslation.  */
                helper_top_evaluate_flags(env);
            }
        }
        cpu_loop_exit(cs);
    }
}

#endif

void helper_raise_exception(CPUCRISState *env, uint32_t index)
{
    CPUState *cs = CPU(cris_env_get_cpu(env));

    cs->exception_index = index;
    cpu_loop_exit(cs);
}

void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
{
#if !defined(CONFIG_USER_ONLY)
	pid &= 0xff;
	if (pid != (env->pregs[PR_PID] & 0xff))
		cris_mmu_flush_pid(env, env->pregs[PR_PID]);
#endif
}

void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
    CRISCPU *cpu = cris_env_get_cpu(env);
    CPUState *cs = CPU(cpu);

    tlb_flush_page(cs, env->pregs[PR_SPC]);
    tlb_flush_page(cs, new_spc);
#endif
}

void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
{
	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
}

/* Used by the tlb decoder.  */
#define EXTRACT_FIELD(src, start, end) \
	    (((src) >> start) & ((1 << (end - start + 1)) - 1))

void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
{
#if !defined(CONFIG_USER_ONLY)
    CRISCPU *cpu = cris_env_get_cpu(env);
#endif
	uint32_t srs;
	srs = env->pregs[PR_SRS];
	srs &= 3;
	env->sregs[srs][sreg] = env->regs[reg];

#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2) {
		if (sreg == 6) {
			/* Writes to tlb-hi write to mm_cause as a side 
			   effect.  */
			env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
			env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
		}
		else if (sreg == 5) {
			uint32_t set;
			uint32_t idx;
			uint32_t lo, hi;
			uint32_t vaddr;
			int tlb_v;

			idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
			set >>= 4;
			set &= 3;

			idx &= 15;
			/* We've just made a write to tlb_lo.  */
			lo = env->sregs[SFR_RW_MM_TLB_LO];
			/* Writes are done via r_mm_cause.  */
			hi = env->sregs[SFR_R_MM_CAUSE];

			vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
					      13, 31);
			vaddr <<= TARGET_PAGE_BITS;
			tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
					    3, 3);
			env->tlbsets[srs - 1][set][idx].lo = lo;
			env->tlbsets[srs - 1][set][idx].hi = hi;

			D_LOG("tlb flush vaddr=%x v=%d pc=%x\n", 
				  vaddr, tlb_v, env->pc);
			if (tlb_v) {
                tlb_flush_page(CPU(cpu), vaddr);
			}
		}
	}
#endif
}

void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
{
	uint32_t srs;
	env->pregs[PR_SRS] &= 3;
	srs = env->pregs[PR_SRS];
	
#if !defined(CONFIG_USER_ONLY)
	if (srs == 1 || srs == 2)
	{
		uint32_t set;
		uint32_t idx;
		uint32_t lo, hi;

		idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
		set >>= 4;
		set &= 3;
		idx &= 15;

		/* Update the mirror regs.  */
		hi = env->tlbsets[srs - 1][set][idx].hi;
		lo = env->tlbsets[srs - 1][set][idx].lo;
		env->sregs[SFR_RW_MM_TLB_HI] = hi;
		env->sregs[SFR_RW_MM_TLB_LO] = lo;
	}
#endif
	env->regs[reg] = env->sregs[srs][sreg];
}

static void cris_ccs_rshift(CPUCRISState *env)
{
	uint32_t ccs;

	/* Apply the ccs shift.  */
	ccs = env->pregs[PR_CCS];
	ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
	if (ccs & U_FLAG)
	{
		/* Enter user mode.  */
		env->ksp = env->regs[R_SP];
		env->regs[R_SP] = env->pregs[PR_USP];
	}

	env->pregs[PR_CCS] = ccs;
}

void helper_rfe(CPUCRISState *env)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* RFE sets the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;
}

void helper_rfn(CPUCRISState *env)
{
	int rflag = env->pregs[PR_CCS] & R_FLAG;

	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n", 
		 env->pregs[PR_ERP], env->pregs[PR_PID],
		 env->pregs[PR_CCS],
		 env->btarget);

	cris_ccs_rshift(env);

	/* Set the P_FLAG only if the R_FLAG is not set.  */
	if (!rflag)
		env->pregs[PR_CCS] |= P_FLAG;

	/* Always set the M flag.  */
	env->pregs[PR_CCS] |= M_FLAG_V32;
}

uint32_t helper_lz(uint32_t t0)
{
	return clz32(t0);
}

uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
{
	/* FIXME: clean this up.  */

	/* des ref:
	   The N flag is set according to the selected bit in the dest reg.
	   The Z flag is set if the selected bit and all bits to the right are
	   zero.
	   The X flag is cleared.
	   Other flags are left untouched.
	   The destination reg is not affected.*/
	unsigned int fz, sbit, bset, mask, masked_t0;

	sbit = t1 & 31;
	bset = !!(t0 & (1 << sbit));
	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	masked_t0 = t0 & mask;
	fz = !(masked_t0 | bset);

	/* Clear the X, N and Z flags.  */
	ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
	if (env->pregs[PR_VR] < 32)
		ccs &= ~(V_FLAG | C_FLAG);
	/* Set the N and Z flags accordingly.  */
	ccs |= (bset << 3) | (fz << 2);
	return ccs;
}

static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
                                                uint32_t flags, uint32_t ccs)
{
	unsigned int x, z, mask;

	/* Extended arithmetics, leave the z flag alone.  */
	x = env->cc_x;
	mask = env->cc_mask | X_FLAG;
        if (x) {
		z = flags & Z_FLAG;
		mask = mask & ~z;
	}
	flags &= mask;

	/* all insn clear the x-flag except setf or clrf.  */
	ccs &= ~mask;
	ccs |= flags;
	return ccs;
}

uint32_t helper_evaluate_flags_muls(CPUCRISState *env,
                                    uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	int64_t tmp;
	int dneg;

	dneg = ((int32_t)res) < 0;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp < 0)
		flags |= N_FLAG;
	if ((dneg && mof != -1)
	    || (!dneg && mof != 0))
		flags |= V_FLAG;
        return evaluate_flags_writeback(env, flags, ccs);
}

uint32_t helper_evaluate_flags_mulu(CPUCRISState *env,
                                    uint32_t ccs, uint32_t res, uint32_t mof)
{
	uint32_t flags = 0;
	uint64_t tmp;

	tmp = mof;
	tmp <<= 32;
	tmp |= res;
	if (tmp == 0)
		flags |= Z_FLAG;
	else if (tmp >> 63)
		flags |= N_FLAG;
	if (mof)
		flags |= V_FLAG;

        return evaluate_flags_writeback(env, flags, ccs);
}

uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
				   uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= R_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= R_FLAG;
	}

        return evaluate_flags_writeback(env, flags, ccs);
}

uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = src & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

        return evaluate_flags_writeback(env, flags, ccs);
}

uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
				     uint32_t src, uint32_t dst, uint32_t res)
{
	uint32_t flags = 0;

	src = (~src) & 0x80000000;
	dst = dst & 0x80000000;

	if ((res & 0x80000000L) != 0L)
	{
		flags |= N_FLAG;
		if (!src && !dst)
			flags |= V_FLAG;
		else if (src & dst)
			flags |= C_FLAG;
	}
	else
	{
		if (res == 0L)
			flags |= Z_FLAG;
		if (src & dst) 
			flags |= V_FLAG;
		if (dst | src) 
			flags |= C_FLAG;
	}

	flags ^= C_FLAG;
        return evaluate_flags_writeback(env, flags, ccs);
}

uint32_t helper_evaluate_flags_move_4(CPUCRISState *env,
                                      uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int32_t)res < 0)
		flags |= N_FLAG;
	else if (res == 0L)
		flags |= Z_FLAG;

        return evaluate_flags_writeback(env, flags, ccs);
}
uint32_t helper_evaluate_flags_move_2(CPUCRISState *env,
                                      uint32_t ccs, uint32_t res)
{
	uint32_t flags = 0;

	if ((int16_t)res < 0L)
		flags |= N_FLAG;
	else if (res == 0)
		flags |= Z_FLAG;

        return evaluate_flags_writeback(env, flags, ccs);
}

/* TODO: This is expensive. We could split things up and only evaluate part of
   CCR on a need to know basis. For now, we simply re-evaluate everything.  */
void helper_evaluate_flags(CPUCRISState *env)
{
	uint32_t src, dst, res;
	uint32_t flags = 0;

	src = env->cc_src;
	dst = env->cc_dest;
	res = env->cc_result;

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		src = ~src;

	/* Now, evaluate the flags. This stuff is based on
	   Per Zander's CRISv10 simulator.  */
	switch (env->cc_size)
	{
		case 1:
			if ((res & 0x80L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80L) == 0L)
				    && ((dst & 0x80L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80L) != 0L)
					 && ((dst & 0x80L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x80L) != 0L)
				    && ((dst & 0x80L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x80L) != 0L
				    || (src & 0x80L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 2:
			if ((res & 0x8000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x8000L) == 0L)
				    && ((dst & 0x8000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x8000L) != 0L)
					 && ((dst & 0x8000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if ((res & 0xFFFFL) == 0L)
				{
					flags |= Z_FLAG;
				}
				if (((src & 0x8000L) != 0L)
				    && ((dst & 0x8000L) != 0L))
				{
					flags |= V_FLAG;
				}
				if ((dst & 0x8000L) != 0L
				    || (src & 0x8000L) != 0L)
				{
					flags |= C_FLAG;
				}
			}
			break;
		case 4:
			if ((res & 0x80000000L) != 0L)
			{
				flags |= N_FLAG;
				if (((src & 0x80000000L) == 0L)
				    && ((dst & 0x80000000L) == 0L))
				{
					flags |= V_FLAG;
				}
				else if (((src & 0x80000000L) != 0L) &&
					 ((dst & 0x80000000L) != 0L))
				{
					flags |= C_FLAG;
				}
			}
			else
			{
				if (res == 0L)
					flags |= Z_FLAG;
				if (((src & 0x80000000L) != 0L)
				    && ((dst & 0x80000000L) != 0L))
					flags |= V_FLAG;
				if ((dst & 0x80000000L) != 0L
				    || (src & 0x80000000L) != 0L)
					flags |= C_FLAG;
			}
			break;
		default:
			break;
	}

	if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
		flags ^= C_FLAG;

        env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
                                                      env->pregs[PR_CCS]);
}

void helper_top_evaluate_flags(CPUCRISState *env)
{
	switch (env->cc_op)
	{
		case CC_OP_MCP:
                        env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
					env->pregs[PR_CCS], env->cc_src,
					env->cc_dest, env->cc_result);
			break;
		case CC_OP_MULS:
                        env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MULU:
                        env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
					env->pregs[PR_CCS], env->cc_result,
					env->pregs[PR_MOF]);
			break;
		case CC_OP_MOVE:
		case CC_OP_AND:
		case CC_OP_OR:
		case CC_OP_XOR:
		case CC_OP_ASR:
		case CC_OP_LSR:
		case CC_OP_LSL:
		switch (env->cc_size)
		{
			case 4:
				env->pregs[PR_CCS] =
                                        helper_evaluate_flags_move_4(env,
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			case 2:
				env->pregs[PR_CCS] =
                                        helper_evaluate_flags_move_2(env,
							env->pregs[PR_CCS],
							env->cc_result);
				break;
			default:
                                helper_evaluate_flags(env);
				break;
		}
		break;
		case CC_OP_FLAGS:
			/* live.  */
			break;
		case CC_OP_SUB:
		case CC_OP_CMP:
			if (env->cc_size == 4)
				env->pregs[PR_CCS] =
                                        helper_evaluate_flags_sub_4(env,
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
			else
                                helper_evaluate_flags(env);
			break;
		default:
		{
			switch (env->cc_size)
			{
			case 4:
				env->pregs[PR_CCS] =
                                        helper_evaluate_flags_alu_4(env,
						env->pregs[PR_CCS],
						env->cc_src, env->cc_dest,
						env->cc_result);
				break;
			default:
                                helper_evaluate_flags(env);
				break;
			}
		}
		break;
	}
}
Commit	Line	Data
81fdc5f8 TS	1	/*
	2	* CRIS helper routines
	3	*
	4	* Copyright (c) 2007 AXIS Communications
	5	* Written by Edgar E. Iglesias
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
81fdc5f8 TS	19	*/
81fdc5f8 TS	20
3e457172	21	#include "cpu.h"
786c02f1	22	#include "mmu.h"
2ef6175a	23	#include "exec/helper-proto.h"
1de7afc9	24	#include "qemu/host-utils.h"
f08b6170	25	#include "exec/cpu_ldst.h"
81fdc5f8	26
d12d51d5 AL	27	//#define CRIS_OP_HELPER_DEBUG
	28
	29
	30	#ifdef CRIS_OP_HELPER_DEBUG
	31	#define D(x) x
3f668b6c	32	#define D_LOG(...) qemu_log(__VA_ARGS__)
d12d51d5	33	#else
e2eef170	34	#define D(x)
d12d51d5 AL	35	#define D_LOG(...) do { } while (0)
d12d51d5 AL	36	#endif
e2eef170 PB	37
e2eef170 PB	38	#if !defined(CONFIG_USER_ONLY)
81fdc5f8 TS	39	/* Try to fill the TLB and return an exception if error. If retaddr is
	40	NULL, it means that the function was called in C code (i.e. not
	41	from generated code or from helper.c) */
d5a11fef	42	void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
20503968	43	uintptr_t retaddr)
81fdc5f8	44	{
d5a11fef AF	45	CRISCPU *cpu = CRIS_CPU(cs);
d5a11fef AF	46	CPUCRISState *env = &cpu->env;
81fdc5f8 TS	47	int ret;
81fdc5f8 TS	48
20503968	49	D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
ff057ccb	50	env->pc, env->pregs[PR_EDA], (void *)retaddr);
d5a11fef	51	ret = cris_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
551bd27f	52	if (unlikely(ret)) {
81fdc5f8 TS	53	if (retaddr) {
81fdc5f8 TS	54	/* now we have a real cpu fault */
3f38f309	55	if (cpu_restore_state(cs, retaddr)) {
30abcfc7	56	/* Evaluate flags after retranslation. */
febc9920	57	helper_top_evaluate_flags(env);
81fdc5f8 TS	58	}
81fdc5f8 TS	59	}
5638d180	60	cpu_loop_exit(cs);
81fdc5f8	61	}
81fdc5f8 TS	62	}
81fdc5f8 TS	63
e2eef170 PB	64	#endif
e2eef170 PB	65
febc9920	66	void helper_raise_exception(CPUCRISState *env, uint32_t index)
786c02f1	67	{
27103424 AF	68	CPUState *cs = CPU(cris_env_get_cpu(env));
	69
	70	cs->exception_index = index;
5638d180	71	cpu_loop_exit(cs);
786c02f1 EI	72	}
786c02f1 EI	73
febc9920	74	void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
cf1d97f0 EI	75	{
cf1d97f0 EI	76	#if !defined(CONFIG_USER_ONLY)
28de16da EI	77	pid &= 0xff;
	78	if (pid != (env->pregs[PR_PID] & 0xff))
	79	cris_mmu_flush_pid(env, env->pregs[PR_PID]);
cf1d97f0 EI	80	#endif
	81	}
	82
febc9920	83	void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
a1aebcb8 EI	84	{
a1aebcb8 EI	85	#if !defined(CONFIG_USER_ONLY)
31b030d4 AF	86	CRISCPU *cpu = cris_env_get_cpu(env);
	87	CPUState *cs = CPU(cpu);
	88
	89	tlb_flush_page(cs, env->pregs[PR_SPC]);
	90	tlb_flush_page(cs, new_spc);
a1aebcb8 EI	91	#endif
	92	}
	93
30abcfc7	94	void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
b41f7df0	95	{
93fcfe39	96	qemu_log("%s: a0=%x a1=%x\n", __func__, a0, a1);
b41f7df0 EI	97	}
b41f7df0 EI	98
cf1d97f0 EI	99	/* Used by the tlb decoder. */
	100	#define EXTRACT_FIELD(src, start, end) \
	101	(((src) >> start) & ((1 << (end - start + 1)) - 1))
	102
febc9920	103	void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
dceaf394	104	{
31b030d4 AF	105	#if !defined(CONFIG_USER_ONLY)
	106	CRISCPU *cpu = cris_env_get_cpu(env);
	107	#endif
dceaf394 EI	108	uint32_t srs;
	109	srs = env->pregs[PR_SRS];
	110	srs &= 3;
	111	env->sregs[srs][sreg] = env->regs[reg];
	112
	113	#if !defined(CONFIG_USER_ONLY)
	114	if (srs == 1 \|\| srs == 2) {
	115	if (sreg == 6) {
	116	/* Writes to tlb-hi write to mm_cause as a side
	117	effect. */
6913ba56 EI	118	env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
6913ba56 EI	119	env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
dceaf394 EI	120	}
	121	else if (sreg == 5) {
	122	uint32_t set;
	123	uint32_t idx;
	124	uint32_t lo, hi;
	125	uint32_t vaddr;
cf1d97f0	126	int tlb_v;
dceaf394 EI	127
	128	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	129	set >>= 4;
	130	set &= 3;
	131
	132	idx &= 15;
	133	/* We've just made a write to tlb_lo. */
	134	lo = env->sregs[SFR_RW_MM_TLB_LO];
	135	/* Writes are done via r_mm_cause. */
	136	hi = env->sregs[SFR_R_MM_CAUSE];
cf1d97f0 EI	137
	138	vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
	139	13, 31);
	140	vaddr <<= TARGET_PAGE_BITS;
	141	tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
	142	3, 3);
dceaf394 EI	143	env->tlbsets[srs - 1][set][idx].lo = lo;
dceaf394 EI	144	env->tlbsets[srs - 1][set][idx].hi = hi;
cf1d97f0	145
d12d51d5 AL	146	D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
d12d51d5 AL	147	vaddr, tlb_v, env->pc);
3e18c6bf	148	if (tlb_v) {
31b030d4	149	tlb_flush_page(CPU(cpu), vaddr);
3e18c6bf	150	}
dceaf394 EI	151	}
	152	}
	153	#endif
	154	}
	155
febc9920	156	void helper_movl_reg_sreg(CPUCRISState *env, uint32_t reg, uint32_t sreg)
dceaf394 EI	157	{
	158	uint32_t srs;
	159	env->pregs[PR_SRS] &= 3;
	160	srs = env->pregs[PR_SRS];
	161
	162	#if !defined(CONFIG_USER_ONLY)
	163	if (srs == 1 \|\| srs == 2)
	164	{
	165	uint32_t set;
	166	uint32_t idx;
	167	uint32_t lo, hi;
	168
	169	idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
	170	set >>= 4;
	171	set &= 3;
	172	idx &= 15;
	173
	174	/* Update the mirror regs. */
	175	hi = env->tlbsets[srs - 1][set][idx].hi;
	176	lo = env->tlbsets[srs - 1][set][idx].lo;
	177	env->sregs[SFR_RW_MM_TLB_HI] = hi;
	178	env->sregs[SFR_RW_MM_TLB_LO] = lo;
	179	}
	180	#endif
	181	env->regs[reg] = env->sregs[srs][sreg];
dceaf394 EI	182	}
dceaf394 EI	183
a1170bfd	184	static void cris_ccs_rshift(CPUCRISState *env)
dceaf394 EI	185	{
	186	uint32_t ccs;
	187
	188	/* Apply the ccs shift. */
	189	ccs = env->pregs[PR_CCS];
	190	ccs = (ccs & 0xc0000000) \| ((ccs & 0x0fffffff) >> 10);
	191	if (ccs & U_FLAG)
	192	{
	193	/* Enter user mode. */
	194	env->ksp = env->regs[R_SP];
	195	env->regs[R_SP] = env->pregs[PR_USP];
	196	}
	197
	198	env->pregs[PR_CCS] = ccs;
	199	}
	200
febc9920	201	void helper_rfe(CPUCRISState *env)
b41f7df0	202	{
bf443337 EI	203	int rflag = env->pregs[PR_CCS] & R_FLAG;
bf443337 EI	204
d12d51d5	205	D_LOG("rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
b41f7df0 EI	206	env->pregs[PR_ERP], env->pregs[PR_PID],
b41f7df0 EI	207	env->pregs[PR_CCS],
d12d51d5	208	env->btarget);
dceaf394 EI	209
	210	cris_ccs_rshift(env);
	211
	212	/* RFE sets the P_FLAG only if the R_FLAG is not set. */
bf443337	213	if (!rflag)
dceaf394	214	env->pregs[PR_CCS] \|= P_FLAG;
b41f7df0 EI	215	}
b41f7df0 EI	216
febc9920	217	void helper_rfn(CPUCRISState *env)
5bf8f1ab EI	218	{
	219	int rflag = env->pregs[PR_CCS] & R_FLAG;
	220
d12d51d5	221	D_LOG("rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
5bf8f1ab EI	222	env->pregs[PR_ERP], env->pregs[PR_PID],
5bf8f1ab EI	223	env->pregs[PR_CCS],
d12d51d5	224	env->btarget);
5bf8f1ab EI	225
	226	cris_ccs_rshift(env);
	227
	228	/* Set the P_FLAG only if the R_FLAG is not set. */
	229	if (!rflag)
	230	env->pregs[PR_CCS] \|= P_FLAG;
	231
8219314b LP	232	/* Always set the M flag. */
8219314b LP	233	env->pregs[PR_CCS] \|= M_FLAG_V32;
5bf8f1ab EI	234	}
5bf8f1ab EI	235
c38ac98d EI	236	uint32_t helper_lz(uint32_t t0)
	237	{
	238	return clz32(t0);
	239	}
	240
febc9920	241	uint32_t helper_btst(CPUCRISState *env, uint32_t t0, uint32_t t1, uint32_t ccs)
abd5c94e EI	242	{
	243	/* FIXME: clean this up. */
	244
	245	/* des ref:
	246	The N flag is set according to the selected bit in the dest reg.
	247	The Z flag is set if the selected bit and all bits to the right are
	248	zero.
	249	The X flag is cleared.
	250	Other flags are left untouched.
	251	The destination reg is not affected.*/
	252	unsigned int fz, sbit, bset, mask, masked_t0;
	253
	254	sbit = t1 & 31;
	255	bset = !!(t0 & (1 << sbit));
	256	mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
	257	masked_t0 = t0 & mask;
	258	fz = !(masked_t0 \| bset);
	259
	260	/* Clear the X, N and Z flags. */
	261	ccs = ccs & ~(X_FLAG \| N_FLAG \| Z_FLAG);
95475216 EI	262	if (env->pregs[PR_VR] < 32)
95475216 EI	263	ccs &= ~(V_FLAG \| C_FLAG);
abd5c94e EI	264	/* Set the N and Z flags accordingly. */
	265	ccs \|= (bset << 3) \| (fz << 2);
	266	return ccs;
	267	}
	268
febc9920 AJ	269	static inline uint32_t evaluate_flags_writeback(CPUCRISState *env,
febc9920 AJ	270	uint32_t flags, uint32_t ccs)
b41f7df0	271	{
a8cf66bb	272	unsigned int x, z, mask;
b41f7df0 EI	273
b41f7df0 EI	274	/* Extended arithmetics, leave the z flag alone. */
30abcfc7	275	x = env->cc_x;
a8cf66bb EI	276	mask = env->cc_mask \| X_FLAG;
	277	if (x) {
	278	z = flags & Z_FLAG;
	279	mask = mask & ~z;
	280	}
	281	flags &= mask;
b41f7df0 EI	282
b41f7df0 EI	283	/* all insn clear the x-flag except setf or clrf. */
6231868b EI	284	ccs &= ~mask;
	285	ccs \|= flags;
	286	return ccs;
b41f7df0 EI	287	}
b41f7df0 EI	288
febc9920 AJ	289	uint32_t helper_evaluate_flags_muls(CPUCRISState *env,
febc9920 AJ	290	uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	291	{
b41f7df0	292	uint32_t flags = 0;
dceaf394	293	int64_t tmp;
b41f7df0 EI	294	int dneg;
b41f7df0 EI	295
b41f7df0 EI	296	dneg = ((int32_t)res) < 0;
b41f7df0 EI	297
dceaf394 EI	298	tmp = mof;
	299	tmp <<= 32;
	300	tmp \|= res;
b41f7df0 EI	301	if (tmp == 0)
	302	flags \|= Z_FLAG;
	303	else if (tmp < 0)
	304	flags \|= N_FLAG;
	305	if ((dneg && mof != -1)
	306	\|\| (!dneg && mof != 0))
	307	flags \|= V_FLAG;
febc9920	308	return evaluate_flags_writeback(env, flags, ccs);
b41f7df0 EI	309	}
b41f7df0 EI	310
febc9920 AJ	311	uint32_t helper_evaluate_flags_mulu(CPUCRISState *env,
febc9920 AJ	312	uint32_t ccs, uint32_t res, uint32_t mof)
b41f7df0	313	{
b41f7df0	314	uint32_t flags = 0;
dceaf394	315	uint64_t tmp;
b41f7df0	316
dceaf394 EI	317	tmp = mof;
	318	tmp <<= 32;
	319	tmp \|= res;
b41f7df0 EI	320	if (tmp == 0)
	321	flags \|= Z_FLAG;
	322	else if (tmp >> 63)
	323	flags \|= N_FLAG;
	324	if (mof)
	325	flags \|= V_FLAG;
	326
febc9920	327	return evaluate_flags_writeback(env, flags, ccs);
b41f7df0 EI	328	}
b41f7df0 EI	329
febc9920	330	uint32_t helper_evaluate_flags_mcp(CPUCRISState *env, uint32_t ccs,
6231868b	331	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	332	{
b41f7df0 EI	333	uint32_t flags = 0;
b41f7df0 EI	334
6231868b EI	335	src = src & 0x80000000;
6231868b EI	336	dst = dst & 0x80000000;
b41f7df0 EI	337
	338	if ((res & 0x80000000L) != 0L)
	339	{
	340	flags \|= N_FLAG;
a8cf66bb	341	if (!src && !dst)
b41f7df0	342	flags \|= V_FLAG;
a8cf66bb	343	else if (src & dst)
b41f7df0	344	flags \|= R_FLAG;
b41f7df0 EI	345	}
	346	else
	347	{
	348	if (res == 0L)
	349	flags \|= Z_FLAG;
a8cf66bb	350	if (src & dst)
b41f7df0	351	flags \|= V_FLAG;
a8cf66bb	352	if (dst \| src)
b41f7df0 EI	353	flags \|= R_FLAG;
	354	}
	355
febc9920	356	return evaluate_flags_writeback(env, flags, ccs);
b41f7df0 EI	357	}
b41f7df0 EI	358
febc9920	359	uint32_t helper_evaluate_flags_alu_4(CPUCRISState *env, uint32_t ccs,
6231868b	360	uint32_t src, uint32_t dst, uint32_t res)
b41f7df0	361	{
b41f7df0 EI	362	uint32_t flags = 0;
b41f7df0 EI	363
6231868b EI	364	src = src & 0x80000000;
6231868b EI	365	dst = dst & 0x80000000;
30abcfc7	366
a8cf66bb	367	if ((res & 0x80000000L) != 0L)
30abcfc7	368	{
a8cf66bb EI	369	flags \|= N_FLAG;
	370	if (!src && !dst)
	371	flags \|= V_FLAG;
	372	else if (src & dst)
	373	flags \|= C_FLAG;
	374	}
	375	else
	376	{
	377	if (res == 0L)
	378	flags \|= Z_FLAG;
	379	if (src & dst)
	380	flags \|= V_FLAG;
	381	if (dst \| src)
	382	flags \|= C_FLAG;
30abcfc7 EI	383	}
30abcfc7 EI	384
febc9920	385	return evaluate_flags_writeback(env, flags, ccs);
a8cf66bb EI	386	}
a8cf66bb EI	387
febc9920	388	uint32_t helper_evaluate_flags_sub_4(CPUCRISState *env, uint32_t ccs,
6231868b	389	uint32_t src, uint32_t dst, uint32_t res)
a8cf66bb	390	{
a8cf66bb EI	391	uint32_t flags = 0;
a8cf66bb EI	392
6231868b EI	393	src = (~src) & 0x80000000;
6231868b EI	394	dst = dst & 0x80000000;
b41f7df0 EI	395
	396	if ((res & 0x80000000L) != 0L)
	397	{
	398	flags \|= N_FLAG;
a8cf66bb	399	if (!src && !dst)
b41f7df0	400	flags \|= V_FLAG;
a8cf66bb	401	else if (src & dst)
b41f7df0	402	flags \|= C_FLAG;
b41f7df0 EI	403	}
	404	else
	405	{
	406	if (res == 0L)
	407	flags \|= Z_FLAG;
a8cf66bb	408	if (src & dst)
b41f7df0	409	flags \|= V_FLAG;
a8cf66bb	410	if (dst \| src)
b41f7df0 EI	411	flags \|= C_FLAG;
	412	}
	413
a8cf66bb	414	flags ^= C_FLAG;
febc9920	415	return evaluate_flags_writeback(env, flags, ccs);
b41f7df0 EI	416	}
b41f7df0 EI	417
febc9920 AJ	418	uint32_t helper_evaluate_flags_move_4(CPUCRISState *env,
febc9920 AJ	419	uint32_t ccs, uint32_t res)
b41f7df0	420	{
b41f7df0 EI	421	uint32_t flags = 0;
b41f7df0 EI	422
b41f7df0 EI	423	if ((int32_t)res < 0)
	424	flags \|= N_FLAG;
	425	else if (res == 0L)
	426	flags \|= Z_FLAG;
	427
febc9920	428	return evaluate_flags_writeback(env, flags, ccs);
b41f7df0	429	}
febc9920 AJ	430	uint32_t helper_evaluate_flags_move_2(CPUCRISState *env,
febc9920 AJ	431	uint32_t ccs, uint32_t res)
b41f7df0	432	{
b41f7df0	433	uint32_t flags = 0;
b41f7df0 EI	434
	435	if ((int16_t)res < 0L)
	436	flags \|= N_FLAG;
	437	else if (res == 0)
	438	flags \|= Z_FLAG;
	439
febc9920	440	return evaluate_flags_writeback(env, flags, ccs);
b41f7df0 EI	441	}
	442
	443	/* TODO: This is expensive. We could split things up and only evaluate part of
	444	CCR on a need to know basis. For now, we simply re-evaluate everything. */
febc9920	445	void helper_evaluate_flags(CPUCRISState *env)
b41f7df0	446	{
6231868b	447	uint32_t src, dst, res;
b41f7df0 EI	448	uint32_t flags = 0;
	449
	450	src = env->cc_src;
	451	dst = env->cc_dest;
	452	res = env->cc_result;
	453
30abcfc7 EI	454	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
30abcfc7 EI	455	src = ~src;
b41f7df0 EI	456
	457	/* Now, evaluate the flags. This stuff is based on
	458	Per Zander's CRISv10 simulator. */
	459	switch (env->cc_size)
	460	{
	461	case 1:
	462	if ((res & 0x80L) != 0L)
	463	{
	464	flags \|= N_FLAG;
	465	if (((src & 0x80L) == 0L)
	466	&& ((dst & 0x80L) == 0L))
	467	{
	468	flags \|= V_FLAG;
	469	}
	470	else if (((src & 0x80L) != 0L)
	471	&& ((dst & 0x80L) != 0L))
	472	{
	473	flags \|= C_FLAG;
	474	}
	475	}
	476	else
	477	{
	478	if ((res & 0xFFL) == 0L)
	479	{
	480	flags \|= Z_FLAG;
	481	}
	482	if (((src & 0x80L) != 0L)
	483	&& ((dst & 0x80L) != 0L))
	484	{
	485	flags \|= V_FLAG;
	486	}
	487	if ((dst & 0x80L) != 0L
	488	\|\| (src & 0x80L) != 0L)
	489	{
	490	flags \|= C_FLAG;
	491	}
	492	}
	493	break;
	494	case 2:
	495	if ((res & 0x8000L) != 0L)
	496	{
	497	flags \|= N_FLAG;
	498	if (((src & 0x8000L) == 0L)
	499	&& ((dst & 0x8000L) == 0L))
	500	{
	501	flags \|= V_FLAG;
	502	}
	503	else if (((src & 0x8000L) != 0L)
	504	&& ((dst & 0x8000L) != 0L))
	505	{
	506	flags \|= C_FLAG;
	507	}
	508	}
	509	else
	510	{
	511	if ((res & 0xFFFFL) == 0L)
	512	{
	513	flags \|= Z_FLAG;
	514	}
	515	if (((src & 0x8000L) != 0L)
	516	&& ((dst & 0x8000L) != 0L))
	517	{
	518	flags \|= V_FLAG;
	519	}
520	if ((dst & 0x8000L) != 0L
521	\|\| (src & 0x8000L) != 0L)
522	{
523	flags \|= C_FLAG;
524	}
525	}
526	break;
527	case 4:
528	if ((res & 0x80000000L) != 0L)
529	{
530	flags \|= N_FLAG;
531	if (((src & 0x80000000L) == 0L)
532	&& ((dst & 0x80000000L) == 0L))
533	{
534	flags \|= V_FLAG;
535	}
536	else if (((src & 0x80000000L) != 0L) &&
537	((dst & 0x80000000L) != 0L))
538	{
539	flags \|= C_FLAG;
540	}
541	}
542	else
543	{
544	if (res == 0L)
545	flags \|= Z_FLAG;
546	if (((src & 0x80000000L) != 0L)
547	&& ((dst & 0x80000000L) != 0L))
548	flags \|= V_FLAG;
549	if ((dst & 0x80000000L) != 0L
550	\|\| (src & 0x80000000L) != 0L)
551	flags \|= C_FLAG;
552	}
553	break;
554	default:
555	break;
556	}
557
6231868b	558	if (env->cc_op == CC_OP_SUB \|\| env->cc_op == CC_OP_CMP)
b41f7df0	559	flags ^= C_FLAG;
6231868b	560
febc9920 AJ	561	env->pregs[PR_CCS] = evaluate_flags_writeback(env, flags,
febc9920 AJ	562	env->pregs[PR_CCS]);
b41f7df0	563	}
30abcfc7	564
febc9920	565	void helper_top_evaluate_flags(CPUCRISState *env)
30abcfc7 EI	566	{
	567	switch (env->cc_op)
	568	{
	569	case CC_OP_MCP:
febc9920	570	env->pregs[PR_CCS] = helper_evaluate_flags_mcp(env,
6231868b EI	571	env->pregs[PR_CCS], env->cc_src,
6231868b EI	572	env->cc_dest, env->cc_result);
30abcfc7 EI	573	break;
30abcfc7 EI	574	case CC_OP_MULS:
febc9920	575	env->pregs[PR_CCS] = helper_evaluate_flags_muls(env,
6231868b EI	576	env->pregs[PR_CCS], env->cc_result,
6231868b EI	577	env->pregs[PR_MOF]);
30abcfc7 EI	578	break;
30abcfc7 EI	579	case CC_OP_MULU:
febc9920	580	env->pregs[PR_CCS] = helper_evaluate_flags_mulu(env,
6231868b EI	581	env->pregs[PR_CCS], env->cc_result,
6231868b EI	582	env->pregs[PR_MOF]);
30abcfc7 EI	583	break;
	584	case CC_OP_MOVE:
	585	case CC_OP_AND:
	586	case CC_OP_OR:
	587	case CC_OP_XOR:
	588	case CC_OP_ASR:
	589	case CC_OP_LSR:
	590	case CC_OP_LSL:
6231868b EI	591	switch (env->cc_size)
	592	{
	593	case 4:
	594	env->pregs[PR_CCS] =
febc9920	595	helper_evaluate_flags_move_4(env,
6231868b EI	596	env->pregs[PR_CCS],
	597	env->cc_result);
	598	break;
	599	case 2:
	600	env->pregs[PR_CCS] =
febc9920	601	helper_evaluate_flags_move_2(env,
6231868b EI	602	env->pregs[PR_CCS],
	603	env->cc_result);
	604	break;
	605	default:
febc9920	606	helper_evaluate_flags(env);
6231868b EI	607	break;
	608	}
	609	break;
30abcfc7 EI	610	case CC_OP_FLAGS:
	611	/* live. */
	612	break;
a8cf66bb EI	613	case CC_OP_SUB:
	614	case CC_OP_CMP:
	615	if (env->cc_size == 4)
6231868b	616	env->pregs[PR_CCS] =
febc9920	617	helper_evaluate_flags_sub_4(env,
6231868b EI	618	env->pregs[PR_CCS],
	619	env->cc_src, env->cc_dest,
	620	env->cc_result);
a8cf66bb	621	else
febc9920	622	helper_evaluate_flags(env);
a8cf66bb	623	break;
30abcfc7 EI	624	default:
	625	{
	626	switch (env->cc_size)
	627	{
6231868b EI	628	case 4:
6231868b EI	629	env->pregs[PR_CCS] =
febc9920	630	helper_evaluate_flags_alu_4(env,
6231868b EI	631	env->pregs[PR_CCS],
	632	env->cc_src, env->cc_dest,
	633	env->cc_result);
	634	break;
	635	default:
febc9920	636	helper_evaluate_flags(env);
6231868b	637	break;
30abcfc7 EI	638	}
	639	}
	640	break;
	641	}
	642	}