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CRIS: bound operates directly on regs, no need to allocate temp destination.
[qemu.git] / target-cris / op_helper.c
CommitLineData
81fdc5f8
TS
1/*
2 * CRIS helper routines
3 *
4 * Copyright (c) 2007 AXIS Communications
5 * Written by Edgar E. Iglesias
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
fad6cb1a 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
81fdc5f8
TS
20 */
21
22#include <assert.h>
23#include "exec.h"
786c02f1 24#include "mmu.h"
30abcfc7 25#include "helper.h"
81fdc5f8 26
e2eef170
PB
27#define D(x)
28
29#if !defined(CONFIG_USER_ONLY)
30
81fdc5f8 31#define MMUSUFFIX _mmu
81fdc5f8
TS
32
33#define SHIFT 0
34#include "softmmu_template.h"
35
36#define SHIFT 1
37#include "softmmu_template.h"
38
39#define SHIFT 2
40#include "softmmu_template.h"
41
42#define SHIFT 3
43#include "softmmu_template.h"
44
45/* Try to fill the TLB and return an exception if error. If retaddr is
46 NULL, it means that the function was called in C code (i.e. not
47 from generated code or from helper.c) */
48/* XXX: fix it to restore all registers */
6ebbf390 49void tlb_fill (target_ulong addr, int is_write, int mmu_idx, void *retaddr)
81fdc5f8
TS
50{
51 TranslationBlock *tb;
52 CPUState *saved_env;
44f8625d 53 unsigned long pc;
81fdc5f8
TS
54 int ret;
55
56 /* XXX: hack to restore env in all cases, even if not called from
57 generated code */
58 saved_env = env;
59 env = cpu_single_env;
b41f7df0 60
ef29a70d
EI
61 D(fprintf(logfile, "%s pc=%x tpc=%x ra=%x\n", __func__,
62 env->pc, env->debug1, retaddr));
6ebbf390 63 ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx, 1);
551bd27f 64 if (unlikely(ret)) {
81fdc5f8
TS
65 if (retaddr) {
66 /* now we have a real cpu fault */
44f8625d 67 pc = (unsigned long)retaddr;
81fdc5f8
TS
68 tb = tb_find_pc(pc);
69 if (tb) {
70 /* the PC is inside the translated code. It means that we have
71 a virtual CPU fault */
72 cpu_restore_state(tb, env, pc, NULL);
30abcfc7
EI
73
74 /* Evaluate flags after retranslation. */
75 helper_top_evaluate_flags();
81fdc5f8
TS
76 }
77 }
78 cpu_loop_exit();
79 }
80 env = saved_env;
81}
82
e2eef170
PB
83#endif
84
dceaf394 85void helper_raise_exception(uint32_t index)
786c02f1 86{
dceaf394
EI
87 env->exception_index = index;
88 cpu_loop_exit();
786c02f1
EI
89}
90
cf1d97f0
EI
91void helper_tlb_flush_pid(uint32_t pid)
92{
93#if !defined(CONFIG_USER_ONLY)
28de16da
EI
94 pid &= 0xff;
95 if (pid != (env->pregs[PR_PID] & 0xff))
96 cris_mmu_flush_pid(env, env->pregs[PR_PID]);
cf1d97f0
EI
97#endif
98}
99
a1aebcb8
EI
100void helper_spc_write(uint32_t new_spc)
101{
102#if !defined(CONFIG_USER_ONLY)
103 tlb_flush_page(env, env->pregs[PR_SPC]);
104 tlb_flush_page(env, new_spc);
105#endif
106}
107
30abcfc7 108void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
b41f7df0
EI
109{
110 (fprintf(logfile, "%s: a0=%x a1=%x\n", __func__, a0, a1));
111}
112
cf1d97f0
EI
113/* Used by the tlb decoder. */
114#define EXTRACT_FIELD(src, start, end) \
115 (((src) >> start) & ((1 << (end - start + 1)) - 1))
116
dceaf394
EI
117void helper_movl_sreg_reg (uint32_t sreg, uint32_t reg)
118{
119 uint32_t srs;
120 srs = env->pregs[PR_SRS];
121 srs &= 3;
122 env->sregs[srs][sreg] = env->regs[reg];
123
124#if !defined(CONFIG_USER_ONLY)
125 if (srs == 1 || srs == 2) {
126 if (sreg == 6) {
127 /* Writes to tlb-hi write to mm_cause as a side
128 effect. */
6913ba56
EI
129 env->sregs[SFR_RW_MM_TLB_HI] = env->regs[reg];
130 env->sregs[SFR_R_MM_CAUSE] = env->regs[reg];
dceaf394
EI
131 }
132 else if (sreg == 5) {
133 uint32_t set;
134 uint32_t idx;
135 uint32_t lo, hi;
136 uint32_t vaddr;
cf1d97f0 137 int tlb_v;
dceaf394
EI
138
139 idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
140 set >>= 4;
141 set &= 3;
142
143 idx &= 15;
144 /* We've just made a write to tlb_lo. */
145 lo = env->sregs[SFR_RW_MM_TLB_LO];
146 /* Writes are done via r_mm_cause. */
147 hi = env->sregs[SFR_R_MM_CAUSE];
cf1d97f0
EI
148
149 vaddr = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].hi,
150 13, 31);
151 vaddr <<= TARGET_PAGE_BITS;
152 tlb_v = EXTRACT_FIELD(env->tlbsets[srs-1][set][idx].lo,
153 3, 3);
dceaf394
EI
154 env->tlbsets[srs - 1][set][idx].lo = lo;
155 env->tlbsets[srs - 1][set][idx].hi = hi;
cf1d97f0
EI
156
157 D(fprintf(logfile,
158 "tlb flush vaddr=%x v=%d pc=%x\n",
159 vaddr, tlb_v, env->pc));
160 tlb_flush_page(env, vaddr);
dceaf394
EI
161 }
162 }
163#endif
164}
165
166void helper_movl_reg_sreg (uint32_t reg, uint32_t sreg)
167{
168 uint32_t srs;
169 env->pregs[PR_SRS] &= 3;
170 srs = env->pregs[PR_SRS];
171
172#if !defined(CONFIG_USER_ONLY)
173 if (srs == 1 || srs == 2)
174 {
175 uint32_t set;
176 uint32_t idx;
177 uint32_t lo, hi;
178
179 idx = set = env->sregs[SFR_RW_MM_TLB_SEL];
180 set >>= 4;
181 set &= 3;
182 idx &= 15;
183
184 /* Update the mirror regs. */
185 hi = env->tlbsets[srs - 1][set][idx].hi;
186 lo = env->tlbsets[srs - 1][set][idx].lo;
187 env->sregs[SFR_RW_MM_TLB_HI] = hi;
188 env->sregs[SFR_RW_MM_TLB_LO] = lo;
189 }
190#endif
191 env->regs[reg] = env->sregs[srs][sreg];
dceaf394
EI
192}
193
194static void cris_ccs_rshift(CPUState *env)
195{
196 uint32_t ccs;
197
198 /* Apply the ccs shift. */
199 ccs = env->pregs[PR_CCS];
200 ccs = (ccs & 0xc0000000) | ((ccs & 0x0fffffff) >> 10);
201 if (ccs & U_FLAG)
202 {
203 /* Enter user mode. */
204 env->ksp = env->regs[R_SP];
205 env->regs[R_SP] = env->pregs[PR_USP];
206 }
207
208 env->pregs[PR_CCS] = ccs;
209}
210
b41f7df0
EI
211void helper_rfe(void)
212{
bf443337
EI
213 int rflag = env->pregs[PR_CCS] & R_FLAG;
214
b41f7df0
EI
215 D(fprintf(logfile, "rfe: erp=%x pid=%x ccs=%x btarget=%x\n",
216 env->pregs[PR_ERP], env->pregs[PR_PID],
217 env->pregs[PR_CCS],
218 env->btarget));
dceaf394
EI
219
220 cris_ccs_rshift(env);
221
222 /* RFE sets the P_FLAG only if the R_FLAG is not set. */
bf443337 223 if (!rflag)
dceaf394 224 env->pregs[PR_CCS] |= P_FLAG;
b41f7df0
EI
225}
226
5bf8f1ab
EI
227void helper_rfn(void)
228{
229 int rflag = env->pregs[PR_CCS] & R_FLAG;
230
231 D(fprintf(logfile, "rfn: erp=%x pid=%x ccs=%x btarget=%x\n",
232 env->pregs[PR_ERP], env->pregs[PR_PID],
233 env->pregs[PR_CCS],
234 env->btarget));
235
236 cris_ccs_rshift(env);
237
238 /* Set the P_FLAG only if the R_FLAG is not set. */
239 if (!rflag)
240 env->pregs[PR_CCS] |= P_FLAG;
241
242 /* Always set the M flag. */
243 env->pregs[PR_CCS] |= M_FLAG;
244}
245
abd5c94e
EI
246uint32_t helper_btst(uint32_t t0, uint32_t t1, uint32_t ccs)
247{
248 /* FIXME: clean this up. */
249
250 /* des ref:
251 The N flag is set according to the selected bit in the dest reg.
252 The Z flag is set if the selected bit and all bits to the right are
253 zero.
254 The X flag is cleared.
255 Other flags are left untouched.
256 The destination reg is not affected.*/
257 unsigned int fz, sbit, bset, mask, masked_t0;
258
259 sbit = t1 & 31;
260 bset = !!(t0 & (1 << sbit));
261 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
262 masked_t0 = t0 & mask;
263 fz = !(masked_t0 | bset);
264
265 /* Clear the X, N and Z flags. */
266 ccs = ccs & ~(X_FLAG | N_FLAG | Z_FLAG);
267 /* Set the N and Z flags accordingly. */
268 ccs |= (bset << 3) | (fz << 2);
269 return ccs;
270}
271
b41f7df0
EI
272static void evaluate_flags_writeback(uint32_t flags)
273{
a8cf66bb 274 unsigned int x, z, mask;
b41f7df0
EI
275
276 /* Extended arithmetics, leave the z flag alone. */
30abcfc7 277 x = env->cc_x;
a8cf66bb
EI
278 mask = env->cc_mask | X_FLAG;
279 if (x) {
280 z = flags & Z_FLAG;
281 mask = mask & ~z;
282 }
283 flags &= mask;
b41f7df0
EI
284
285 /* all insn clear the x-flag except setf or clrf. */
a8cf66bb 286 env->pregs[PR_CCS] &= ~mask;
b41f7df0 287 env->pregs[PR_CCS] |= flags;
b41f7df0
EI
288}
289
290void helper_evaluate_flags_muls(void)
291{
292 uint32_t src;
293 uint32_t dst;
294 uint32_t res;
295 uint32_t flags = 0;
dceaf394 296 int64_t tmp;
b41f7df0
EI
297 int32_t mof;
298 int dneg;
299
300 src = env->cc_src;
301 dst = env->cc_dest;
302 res = env->cc_result;
303
b41f7df0
EI
304 dneg = ((int32_t)res) < 0;
305
dceaf394
EI
306 mof = env->pregs[PR_MOF];
307 tmp = mof;
308 tmp <<= 32;
309 tmp |= res;
b41f7df0
EI
310 if (tmp == 0)
311 flags |= Z_FLAG;
312 else if (tmp < 0)
313 flags |= N_FLAG;
314 if ((dneg && mof != -1)
315 || (!dneg && mof != 0))
316 flags |= V_FLAG;
317 evaluate_flags_writeback(flags);
318}
319
320void helper_evaluate_flags_mulu(void)
321{
322 uint32_t src;
323 uint32_t dst;
324 uint32_t res;
325 uint32_t flags = 0;
dceaf394 326 uint64_t tmp;
b41f7df0
EI
327 uint32_t mof;
328
329 src = env->cc_src;
330 dst = env->cc_dest;
331 res = env->cc_result;
332
dceaf394
EI
333 mof = env->pregs[PR_MOF];
334 tmp = mof;
335 tmp <<= 32;
336 tmp |= res;
b41f7df0
EI
337 if (tmp == 0)
338 flags |= Z_FLAG;
339 else if (tmp >> 63)
340 flags |= N_FLAG;
341 if (mof)
342 flags |= V_FLAG;
343
344 evaluate_flags_writeback(flags);
345}
346
347void helper_evaluate_flags_mcp(void)
348{
349 uint32_t src;
350 uint32_t dst;
351 uint32_t res;
352 uint32_t flags = 0;
353
a8cf66bb
EI
354 src = env->cc_src & 0x80000000;
355 dst = env->cc_dest & 0x80000000;
b41f7df0
EI
356 res = env->cc_result;
357
358 if ((res & 0x80000000L) != 0L)
359 {
360 flags |= N_FLAG;
a8cf66bb 361 if (!src && !dst)
b41f7df0 362 flags |= V_FLAG;
a8cf66bb 363 else if (src & dst)
b41f7df0 364 flags |= R_FLAG;
b41f7df0
EI
365 }
366 else
367 {
368 if (res == 0L)
369 flags |= Z_FLAG;
a8cf66bb 370 if (src & dst)
b41f7df0 371 flags |= V_FLAG;
a8cf66bb 372 if (dst | src)
b41f7df0
EI
373 flags |= R_FLAG;
374 }
375
376 evaluate_flags_writeback(flags);
377}
378
379void helper_evaluate_flags_alu_4(void)
380{
381 uint32_t src;
382 uint32_t dst;
383 uint32_t res;
384 uint32_t flags = 0;
385
a8cf66bb
EI
386 src = env->cc_src & 0x80000000;
387 dst = env->cc_dest & 0x80000000;
388 res = env->cc_result;
30abcfc7 389
a8cf66bb 390 if ((res & 0x80000000L) != 0L)
30abcfc7 391 {
a8cf66bb
EI
392 flags |= N_FLAG;
393 if (!src && !dst)
394 flags |= V_FLAG;
395 else if (src & dst)
396 flags |= C_FLAG;
397 }
398 else
399 {
400 if (res == 0L)
401 flags |= Z_FLAG;
402 if (src & dst)
403 flags |= V_FLAG;
404 if (dst | src)
405 flags |= C_FLAG;
30abcfc7
EI
406 }
407
a8cf66bb
EI
408 evaluate_flags_writeback(flags);
409}
410
411void helper_evaluate_flags_sub_4(void)
412{
413 uint32_t src;
414 uint32_t dst;
415 uint32_t res;
416 uint32_t flags = 0;
417
418 src = (~env->cc_src) & 0x80000000;
419 dst = env->cc_dest & 0x80000000;
420 res = env->cc_result;
b41f7df0
EI
421
422 if ((res & 0x80000000L) != 0L)
423 {
424 flags |= N_FLAG;
a8cf66bb 425 if (!src && !dst)
b41f7df0 426 flags |= V_FLAG;
a8cf66bb 427 else if (src & dst)
b41f7df0 428 flags |= C_FLAG;
b41f7df0
EI
429 }
430 else
431 {
432 if (res == 0L)
433 flags |= Z_FLAG;
a8cf66bb 434 if (src & dst)
b41f7df0 435 flags |= V_FLAG;
a8cf66bb 436 if (dst | src)
b41f7df0
EI
437 flags |= C_FLAG;
438 }
439
a8cf66bb 440 flags ^= C_FLAG;
b41f7df0
EI
441 evaluate_flags_writeback(flags);
442}
443
444void helper_evaluate_flags_move_4 (void)
445{
b41f7df0
EI
446 uint32_t res;
447 uint32_t flags = 0;
448
b41f7df0
EI
449 res = env->cc_result;
450
451 if ((int32_t)res < 0)
452 flags |= N_FLAG;
453 else if (res == 0L)
454 flags |= Z_FLAG;
455
456 evaluate_flags_writeback(flags);
457}
458void helper_evaluate_flags_move_2 (void)
459{
460 uint32_t src;
461 uint32_t flags = 0;
462 uint16_t res;
463
464 src = env->cc_src;
465 res = env->cc_result;
466
467 if ((int16_t)res < 0L)
468 flags |= N_FLAG;
469 else if (res == 0)
470 flags |= Z_FLAG;
471
472 evaluate_flags_writeback(flags);
473}
474
475/* TODO: This is expensive. We could split things up and only evaluate part of
476 CCR on a need to know basis. For now, we simply re-evaluate everything. */
477void helper_evaluate_flags (void)
478{
479 uint32_t src;
480 uint32_t dst;
481 uint32_t res;
482 uint32_t flags = 0;
483
484 src = env->cc_src;
485 dst = env->cc_dest;
486 res = env->cc_result;
487
30abcfc7
EI
488 if (env->cc_op == CC_OP_SUB || env->cc_op == CC_OP_CMP)
489 src = ~src;
b41f7df0
EI
490
491 /* Now, evaluate the flags. This stuff is based on
492 Per Zander's CRISv10 simulator. */
493 switch (env->cc_size)
494 {
495 case 1:
496 if ((res & 0x80L) != 0L)
497 {
498 flags |= N_FLAG;
499 if (((src & 0x80L) == 0L)
500 && ((dst & 0x80L) == 0L))
501 {
502 flags |= V_FLAG;
503 }
504 else if (((src & 0x80L) != 0L)
505 && ((dst & 0x80L) != 0L))
506 {
507 flags |= C_FLAG;
508 }
509 }
510 else
511 {
512 if ((res & 0xFFL) == 0L)
513 {
514 flags |= Z_FLAG;
515 }
516 if (((src & 0x80L) != 0L)
517 && ((dst & 0x80L) != 0L))
518 {
519 flags |= V_FLAG;
520 }
521 if ((dst & 0x80L) != 0L
522 || (src & 0x80L) != 0L)
523 {
524 flags |= C_FLAG;
525 }
526 }
527 break;
528 case 2:
529 if ((res & 0x8000L) != 0L)
530 {
531 flags |= N_FLAG;
532 if (((src & 0x8000L) == 0L)
533 && ((dst & 0x8000L) == 0L))
534 {
535 flags |= V_FLAG;
536 }
537 else if (((src & 0x8000L) != 0L)
538 && ((dst & 0x8000L) != 0L))
539 {
540 flags |= C_FLAG;
541 }
542 }
543 else
544 {
545 if ((res & 0xFFFFL) == 0L)
546 {
547 flags |= Z_FLAG;
548 }
549 if (((src & 0x8000L) != 0L)
550 && ((dst & 0x8000L) != 0L))
551 {
552 flags |= V_FLAG;
553 }
554 if ((dst & 0x8000L) != 0L
555 || (src & 0x8000L) != 0L)
556 {
557 flags |= C_FLAG;
558 }
559 }
560 break;
561 case 4:
562 if ((res & 0x80000000L) != 0L)
563 {
564 flags |= N_FLAG;
565 if (((src & 0x80000000L) == 0L)
566 && ((dst & 0x80000000L) == 0L))
567 {
568 flags |= V_FLAG;
569 }
570 else if (((src & 0x80000000L) != 0L) &&
571 ((dst & 0x80000000L) != 0L))
572 {
573 flags |= C_FLAG;
574 }
575 }
576 else
577 {
578 if (res == 0L)
579 flags |= Z_FLAG;
580 if (((src & 0x80000000L) != 0L)
581 && ((dst & 0x80000000L) != 0L))
582 flags |= V_FLAG;
583 if ((dst & 0x80000000L) != 0L
584 || (src & 0x80000000L) != 0L)
585 flags |= C_FLAG;
586 }
587 break;
588 default:
589 break;
590 }
591
592 if (env->cc_op == CC_OP_SUB
593 || env->cc_op == CC_OP_CMP) {
594 flags ^= C_FLAG;
595 }
596 evaluate_flags_writeback(flags);
597}
30abcfc7
EI
598
599void helper_top_evaluate_flags(void)
600{
601 switch (env->cc_op)
602 {
603 case CC_OP_MCP:
604 helper_evaluate_flags_mcp();
605 break;
606 case CC_OP_MULS:
607 helper_evaluate_flags_muls();
608 break;
609 case CC_OP_MULU:
610 helper_evaluate_flags_mulu();
611 break;
612 case CC_OP_MOVE:
613 case CC_OP_AND:
614 case CC_OP_OR:
615 case CC_OP_XOR:
616 case CC_OP_ASR:
617 case CC_OP_LSR:
618 case CC_OP_LSL:
619 switch (env->cc_size)
620 {
621 case 4:
622 helper_evaluate_flags_move_4();
623 break;
624 case 2:
625 helper_evaluate_flags_move_2();
626 break;
627 default:
628 helper_evaluate_flags();
629 break;
630 }
631 break;
632 case CC_OP_FLAGS:
633 /* live. */
634 break;
a8cf66bb
EI
635 case CC_OP_SUB:
636 case CC_OP_CMP:
637 if (env->cc_size == 4)
638 helper_evaluate_flags_sub_4();
639 else
640 helper_evaluate_flags();
641 break;
30abcfc7
EI
642 default:
643 {
644 switch (env->cc_size)
645 {
646 case 4:
647 helper_evaluate_flags_alu_4();
648 break;
649 default:
650 helper_evaluate_flags();
651 break;
652 }
653 }
654 break;
655 }
656}
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