[qemu.git] / hw / wdt_i6300esb.c

/*
 * Virtual hardware watchdog.
 *
 * Copyright (C) 2009 Red Hat Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * By Richard W.M. Jones ([email protected]).
 */

#include <inttypes.h>

#include "qemu-common.h"
#include "qemu-timer.h"
#include "watchdog.h"
#include "hw.h"
#include "pci.h"

/*#define I6300ESB_DEBUG 1*/

#ifdef I6300ESB_DEBUG
#define i6300esb_debug(fs,...) \
    fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
#else
#define i6300esb_debug(fs,...)
#endif

/* PCI configuration registers */
#define ESB_CONFIG_REG  0x60            /* Config register                   */
#define ESB_LOCK_REG    0x68            /* WDT lock register                 */

/* Memory mapped registers (offset from base address) */
#define ESB_TIMER1_REG  0x00            /* Timer1 value after each reset     */
#define ESB_TIMER2_REG  0x04            /* Timer2 value after each reset     */
#define ESB_GINTSR_REG  0x08            /* General Interrupt Status Register */
#define ESB_RELOAD_REG  0x0c            /* Reload register                   */

/* Lock register bits */
#define ESB_WDT_FUNC    (0x01 << 2)   /* Watchdog functionality            */
#define ESB_WDT_ENABLE  (0x01 << 1)   /* Enable WDT                        */
#define ESB_WDT_LOCK    (0x01 << 0)   /* Lock (nowayout)                   */

/* Config register bits */
#define ESB_WDT_REBOOT  (0x01 << 5)   /* Enable reboot on timeout          */
#define ESB_WDT_FREQ    (0x01 << 2)   /* Decrement frequency               */
#define ESB_WDT_INTTYPE (0x11 << 0)   /* Interrupt type on timer1 timeout  */

/* Reload register bits */
#define ESB_WDT_RELOAD  (0x01 << 8)    /* prevent timeout                   */

/* Magic constants */
#define ESB_UNLOCK1     0x80            /* Step 1 to unlock reset registers  */
#define ESB_UNLOCK2     0x86            /* Step 2 to unlock reset registers  */

/* Device state. */
struct I6300State {
    PCIDevice dev;

    int reboot_enabled;         /* "Reboot" on timer expiry.  The real action
                                 * performed depends on the -watchdog-action
                                 * param passed on QEMU command line.
                                 */
    int clock_scale;            /* Clock scale. */
#define CLOCK_SCALE_1KHZ 0
#define CLOCK_SCALE_1MHZ 1

    int int_type;               /* Interrupt type generated. */
#define INT_TYPE_IRQ 0          /* APIC 1, INT 10 */
#define INT_TYPE_SMI 2
#define INT_TYPE_DISABLED 3

    int free_run;               /* If true, reload timer on expiry. */
    int locked;                 /* If true, enabled field cannot be changed. */
    int enabled;                /* If true, watchdog is enabled. */

    QEMUTimer *timer;           /* The actual watchdog timer. */

    uint32_t timer1_preload;    /* Values preloaded into timer1, timer2. */
    uint32_t timer2_preload;
    int stage;                  /* Stage (1 or 2). */

    int unlock_state;           /* Guest writes 0x80, 0x86 to unlock the
                                 * registers, and we transition through
                                 * states 0 -> 1 -> 2 when this happens.
                                 */

    int previous_reboot_flag;   /* If the watchdog caused the previous
                                 * reboot, this flag will be set.
                                 */
};

typedef struct I6300State I6300State;

/* This function is called when the watchdog has either been enabled
 * (hence it starts counting down) or has been keep-alived.
 */
static void i6300esb_restart_timer(I6300State *d, int stage)
{
    int64_t timeout;

    if (!d->enabled)
        return;

    d->stage = stage;

    if (d->stage <= 1)
        timeout = d->timer1_preload;
    else
        timeout = d->timer2_preload;

    if (d->clock_scale == CLOCK_SCALE_1KHZ)
        timeout <<= 15;
    else
        timeout <<= 5;

    /* Get the timeout in units of ticks_per_sec. */
    timeout = get_ticks_per_sec() * timeout / 33000000;

    i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);

    qemu_mod_timer(d->timer, qemu_get_clock_ns(vm_clock) + timeout);
}

/* This is called when the guest disables the watchdog. */
static void i6300esb_disable_timer(I6300State *d)
{
    i6300esb_debug("timer disabled\n");

    qemu_del_timer(d->timer);
}

static void i6300esb_reset(DeviceState *dev)
{
    PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev);
    I6300State *d = DO_UPCAST(I6300State, dev, pdev);

    i6300esb_debug("I6300State = %p\n", d);

    i6300esb_disable_timer(d);

    /* NB: Don't change d->previous_reboot_flag in this function. */

    d->reboot_enabled = 1;
    d->clock_scale = CLOCK_SCALE_1KHZ;
    d->int_type = INT_TYPE_IRQ;
    d->free_run = 0;
    d->locked = 0;
    d->enabled = 0;
    d->timer1_preload = 0xfffff;
    d->timer2_preload = 0xfffff;
    d->stage = 1;
    d->unlock_state = 0;
}

/* This function is called when the watchdog expires.  Note that
 * the hardware has two timers, and so expiry happens in two stages.
 * If d->stage == 1 then we perform the first stage action (usually,
 * sending an interrupt) and then restart the timer again for the
 * second stage.  If the second stage expires then the watchdog
 * really has run out.
 */
static void i6300esb_timer_expired(void *vp)
{
    I6300State *d = vp;

    i6300esb_debug("stage %d\n", d->stage);

    if (d->stage == 1) {
        /* What to do at the end of stage 1? */
        switch (d->int_type) {
        case INT_TYPE_IRQ:
            fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
            break;
        case INT_TYPE_SMI:
            fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
            break;
        }

        /* Start the second stage. */
        i6300esb_restart_timer(d, 2);
    } else {
        /* Second stage expired, reboot for real. */
        if (d->reboot_enabled) {
            d->previous_reboot_flag = 1;
            watchdog_perform_action(); /* This reboots, exits, etc */
            i6300esb_reset(&d->dev.qdev);
        }

        /* In "free running mode" we start stage 1 again. */
        if (d->free_run)
            i6300esb_restart_timer(d, 1);
    }
}

static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
                                  uint32_t data, int len)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    int old;

    i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);

    if (addr == ESB_CONFIG_REG && len == 2) {
        d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
        d->clock_scale =
            (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
        d->int_type = (data & ESB_WDT_INTTYPE);
    } else if (addr == ESB_LOCK_REG && len == 1) {
        if (!d->locked) {
            d->locked = (data & ESB_WDT_LOCK) != 0;
            d->free_run = (data & ESB_WDT_FUNC) != 0;
            old = d->enabled;
            d->enabled = (data & ESB_WDT_ENABLE) != 0;
            if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
                i6300esb_restart_timer(d, 1);
            else if (!d->enabled)
                i6300esb_disable_timer(d);
        }
    } else {
        pci_default_write_config(dev, addr, data, len);
    }
}

static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    uint32_t data;

    i6300esb_debug ("addr = %x, len = %d\n", addr, len);

    if (addr == ESB_CONFIG_REG && len == 2) {
        data =
            (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
            (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
            d->int_type;
        return data;
    } else if (addr == ESB_LOCK_REG && len == 1) {
        data =
            (d->free_run ? ESB_WDT_FUNC : 0) |
            (d->locked ? ESB_WDT_LOCK : 0) |
            (d->enabled ? ESB_WDT_ENABLE : 0);
        return data;
    } else {
        return pci_default_read_config(dev, addr, len);
    }
}

static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr)
{
    i6300esb_debug ("addr = %x\n", (int) addr);

    return 0;
}

static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr)
{
    uint32_t data = 0;
    I6300State *d = vp;

    i6300esb_debug("addr = %x\n", (int) addr);

    if (addr == 0xc) {
        /* The previous reboot flag is really bit 9, but there is
         * a bug in the Linux driver where it thinks it's bit 12.
         * Set both.
         */
        data = d->previous_reboot_flag ? 0x1200 : 0;
    }

    return data;
}

static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr)
{
    i6300esb_debug("addr = %x\n", (int) addr);

    return 0;
}

static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val)
{
    I6300State *d = vp;

    i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
}

static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val)
{
    I6300State *d = vp;

    i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
    else {
        if (d->unlock_state == 2) {
            if (addr == 0xc) {
                if ((val & 0x100) != 0)
                    /* This is the "ping" from the userspace watchdog in
                     * the guest ...
                     */
                    i6300esb_restart_timer(d, 1);

                /* Setting bit 9 resets the previous reboot flag.
                 * There's a bug in the Linux driver where it sets
                 * bit 12 instead.
                 */
                if ((val & 0x200) != 0 || (val & 0x1000) != 0) {
                    d->previous_reboot_flag = 0;
                }
            }

            d->unlock_state = 0;
        }
    }
}

static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
{
    I6300State *d = vp;

    i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
    else {
        if (d->unlock_state == 2) {
            if (addr == 0)
                d->timer1_preload = val & 0xfffff;
            else if (addr == 4)
                d->timer2_preload = val & 0xfffff;

            d->unlock_state = 0;
        }
    }
}

static const VMStateDescription vmstate_i6300esb = {
    .name = "i6300esb_wdt",
    .version_id = sizeof(I6300State),
    .minimum_version_id = sizeof(I6300State),
    .minimum_version_id_old = sizeof(I6300State),
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, I6300State),
        VMSTATE_INT32(reboot_enabled, I6300State),
        VMSTATE_INT32(clock_scale, I6300State),
        VMSTATE_INT32(int_type, I6300State),
        VMSTATE_INT32(free_run, I6300State),
        VMSTATE_INT32(locked, I6300State),
        VMSTATE_INT32(enabled, I6300State),
        VMSTATE_TIMER(timer, I6300State),
        VMSTATE_UINT32(timer1_preload, I6300State),
        VMSTATE_UINT32(timer2_preload, I6300State),
        VMSTATE_INT32(stage, I6300State),
        VMSTATE_INT32(unlock_state, I6300State),
        VMSTATE_INT32(previous_reboot_flag, I6300State),
        VMSTATE_END_OF_LIST()
    }
};

static int i6300esb_init(PCIDevice *dev)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    int io_mem;
    static CPUReadMemoryFunc * const mem_read[3] = {
        i6300esb_mem_readb,
        i6300esb_mem_readw,
        i6300esb_mem_readl,
    };
    static CPUWriteMemoryFunc * const mem_write[3] = {
        i6300esb_mem_writeb,
        i6300esb_mem_writew,
        i6300esb_mem_writel,
    };

    i6300esb_debug("I6300State = %p\n", d);

    d->timer = qemu_new_timer_ns(vm_clock, i6300esb_timer_expired, d);
    d->previous_reboot_flag = 0;

    io_mem = cpu_register_io_memory(mem_read, mem_write, d,
                                    DEVICE_NATIVE_ENDIAN);
    pci_register_bar_simple(&d->dev, 0, 0x10, 0, io_mem);
    /* qemu_register_coalesced_mmio (addr, 0x10); ? */

    return 0;
}

static WatchdogTimerModel model = {
    .wdt_name = "i6300esb",
    .wdt_description = "Intel 6300ESB",
};

static PCIDeviceInfo i6300esb_info = {
    .qdev.name    = "i6300esb",
    .qdev.size    = sizeof(I6300State),
    .qdev.vmsd    = &vmstate_i6300esb,
    .qdev.reset   = i6300esb_reset,
    .config_read  = i6300esb_config_read,
    .config_write = i6300esb_config_write,
    .init         = i6300esb_init,
    .vendor_id    = PCI_VENDOR_ID_INTEL,
    .device_id    = PCI_DEVICE_ID_INTEL_ESB_9,
    .class_id     = PCI_CLASS_SYSTEM_OTHER,
};

static void i6300esb_register_devices(void)
{
    watchdog_add_model(&model);
    pci_qdev_register(&i6300esb_info);
}

device_init(i6300esb_register_devices);
Commit	Line	Data
9dd986cc RJ	1	/*
	2	* Virtual hardware watchdog.
	3	*
	4	* Copyright (C) 2009 Red Hat Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
8167ee88	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
9dd986cc RJ	18	*
	19	* By Richard W.M. Jones ([email protected]).
	20	*/
	21
	22	#include <inttypes.h>
	23
	24	#include "qemu-common.h"
	25	#include "qemu-timer.h"
	26	#include "watchdog.h"
	27	#include "hw.h"
9dd986cc RJ	28	#include "pci.h"
	29
	30	/#define I6300ESB_DEBUG 1/
	31
	32	#ifdef I6300ESB_DEBUG
	33	#define i6300esb_debug(fs,...) \
	34	fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
	35	#else
	36	#define i6300esb_debug(fs,...)
	37	#endif
	38
9dd986cc RJ	39	/* PCI configuration registers */
	40	#define ESB_CONFIG_REG 0x60 /* Config register */
	41	#define ESB_LOCK_REG 0x68 /* WDT lock register */
	42
	43	/* Memory mapped registers (offset from base address) */
	44	#define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */
	45	#define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */
	46	#define ESB_GINTSR_REG 0x08 /* General Interrupt Status Register */
	47	#define ESB_RELOAD_REG 0x0c /* Reload register */
	48
	49	/* Lock register bits */
	50	#define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
	51	#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
	52	#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
	53
	54	/* Config register bits */
	55	#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
	56	#define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
	57	#define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */
	58
	59	/* Reload register bits */
	60	#define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
	61
	62	/* Magic constants */
	63	#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
	64	#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
	65
	66	/* Device state. */
	67	struct I6300State {
9d472d51	68	PCIDevice dev;
9dd986cc RJ	69
	70	int reboot_enabled; /* "Reboot" on timer expiry. The real action
	71	* performed depends on the -watchdog-action
	72	* param passed on QEMU command line.
	73	*/
	74	int clock_scale; /* Clock scale. */
	75	#define CLOCK_SCALE_1KHZ 0
	76	#define CLOCK_SCALE_1MHZ 1
	77
	78	int int_type; /* Interrupt type generated. */
	79	#define INT_TYPE_IRQ 0 /* APIC 1, INT 10 */
	80	#define INT_TYPE_SMI 2
	81	#define INT_TYPE_DISABLED 3
	82
	83	int free_run; /* If true, reload timer on expiry. */
	84	int locked; /* If true, enabled field cannot be changed. */
	85	int enabled; /* If true, watchdog is enabled. */
	86
	87	QEMUTimer timer; / The actual watchdog timer. */
	88
	89	uint32_t timer1_preload; /* Values preloaded into timer1, timer2. */
	90	uint32_t timer2_preload;
	91	int stage; /* Stage (1 or 2). */
	92
	93	int unlock_state; /* Guest writes 0x80, 0x86 to unlock the
	94	* registers, and we transition through
	95	* states 0 -> 1 -> 2 when this happens.
	96	*/
	97
	98	int previous_reboot_flag; /* If the watchdog caused the previous
	99	* reboot, this flag will be set.
	100	*/
	101	};
	102
	103	typedef struct I6300State I6300State;
	104
	105	/* This function is called when the watchdog has either been enabled
	106	* (hence it starts counting down) or has been keep-alived.
	107	*/
	108	static void i6300esb_restart_timer(I6300State *d, int stage)
	109	{
	110	int64_t timeout;
	111
	112	if (!d->enabled)
	113	return;
	114
	115	d->stage = stage;
	116
	117	if (d->stage <= 1)
	118	timeout = d->timer1_preload;
	119	else
	120	timeout = d->timer2_preload;
	121
	122	if (d->clock_scale == CLOCK_SCALE_1KHZ)
	123	timeout <<= 15;
	124	else
	125	timeout <<= 5;
	126
	127	/* Get the timeout in units of ticks_per_sec. */
6ee093c9	128	timeout = get_ticks_per_sec() * timeout / 33000000;
9dd986cc RJ	129
	130	i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
	131
74475455	132	qemu_mod_timer(d->timer, qemu_get_clock_ns(vm_clock) + timeout);
9dd986cc RJ	133	}
	134
	135	/* This is called when the guest disables the watchdog. */
	136	static void i6300esb_disable_timer(I6300State *d)
	137	{
	138	i6300esb_debug("timer disabled\n");
	139
	140	qemu_del_timer(d->timer);
	141	}
	142
fa82e9c3	143	static void i6300esb_reset(DeviceState *dev)
9dd986cc	144	{
fa82e9c3 BK	145	PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev);
	146	I6300State *d = DO_UPCAST(I6300State, dev, pdev);
	147
	148	i6300esb_debug("I6300State = %p\n", d);
	149
9dd986cc	150	i6300esb_disable_timer(d);
fa82e9c3	151
36888c63 RJ	152	/* NB: Don't change d->previous_reboot_flag in this function. */
36888c63 RJ	153
fa82e9c3 BK	154	d->reboot_enabled = 1;
	155	d->clock_scale = CLOCK_SCALE_1KHZ;
	156	d->int_type = INT_TYPE_IRQ;
	157	d->free_run = 0;
	158	d->locked = 0;
	159	d->enabled = 0;
	160	d->timer1_preload = 0xfffff;
	161	d->timer2_preload = 0xfffff;
	162	d->stage = 1;
	163	d->unlock_state = 0;
9dd986cc RJ	164	}
	165
	166	/* This function is called when the watchdog expires. Note that
	167	* the hardware has two timers, and so expiry happens in two stages.
	168	* If d->stage == 1 then we perform the first stage action (usually,
	169	* sending an interrupt) and then restart the timer again for the
	170	* second stage. If the second stage expires then the watchdog
	171	* really has run out.
	172	*/
	173	static void i6300esb_timer_expired(void *vp)
	174	{
4f423e81	175	I6300State *d = vp;
9dd986cc RJ	176
	177	i6300esb_debug("stage %d\n", d->stage);
	178
	179	if (d->stage == 1) {
	180	/* What to do at the end of stage 1? */
	181	switch (d->int_type) {
	182	case INT_TYPE_IRQ:
	183	fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
	184	break;
	185	case INT_TYPE_SMI:
	186	fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
	187	break;
	188	}
	189
	190	/* Start the second stage. */
	191	i6300esb_restart_timer(d, 2);
	192	} else {
	193	/* Second stage expired, reboot for real. */
	194	if (d->reboot_enabled) {
	195	d->previous_reboot_flag = 1;
	196	watchdog_perform_action(); /* This reboots, exits, etc */
36888c63	197	i6300esb_reset(&d->dev.qdev);
9dd986cc RJ	198	}
	199
	200	/* In "free running mode" we start stage 1 again. */
	201	if (d->free_run)
	202	i6300esb_restart_timer(d, 1);
	203	}
	204	}
	205
	206	static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
	207	uint32_t data, int len)
	208	{
d03f09cc	209	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc RJ	210	int old;
	211
	212	i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
	213
	214	if (addr == ESB_CONFIG_REG && len == 2) {
	215	d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
	216	d->clock_scale =
	217	(data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
	218	d->int_type = (data & ESB_WDT_INTTYPE);
	219	} else if (addr == ESB_LOCK_REG && len == 1) {
	220	if (!d->locked) {
	221	d->locked = (data & ESB_WDT_LOCK) != 0;
	222	d->free_run = (data & ESB_WDT_FUNC) != 0;
	223	old = d->enabled;
	224	d->enabled = (data & ESB_WDT_ENABLE) != 0;
	225	if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
	226	i6300esb_restart_timer(d, 1);
	227	else if (!d->enabled)
	228	i6300esb_disable_timer(d);
	229	}
	230	} else {
	231	pci_default_write_config(dev, addr, data, len);
	232	}
	233	}
	234
	235	static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
	236	{
d03f09cc	237	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc RJ	238	uint32_t data;
	239
	240	i6300esb_debug ("addr = %x, len = %d\n", addr, len);
	241
	242	if (addr == ESB_CONFIG_REG && len == 2) {
	243	data =
	244	(d->reboot_enabled ? 0 : ESB_WDT_REBOOT) \|
	245	(d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) \|
	246	d->int_type;
	247	return data;
	248	} else if (addr == ESB_LOCK_REG && len == 1) {
	249	data =
	250	(d->free_run ? ESB_WDT_FUNC : 0) \|
	251	(d->locked ? ESB_WDT_LOCK : 0) \|
	252	(d->enabled ? ESB_WDT_ENABLE : 0);
	253	return data;
	254	} else {
	255	return pci_default_read_config(dev, addr, len);
	256	}
	257	}
	258
c227f099	259	static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr)
9dd986cc RJ	260	{
	261	i6300esb_debug ("addr = %x\n", (int) addr);
	262
	263	return 0;
	264	}
	265
c227f099	266	static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr)
9dd986cc RJ	267	{
9dd986cc RJ	268	uint32_t data = 0;
4f423e81	269	I6300State *d = vp;
9dd986cc RJ	270
	271	i6300esb_debug("addr = %x\n", (int) addr);
	272
	273	if (addr == 0xc) {
	274	/* The previous reboot flag is really bit 9, but there is
	275	* a bug in the Linux driver where it thinks it's bit 12.
	276	* Set both.
	277	*/
	278	data = d->previous_reboot_flag ? 0x1200 : 0;
	279	}
	280
	281	return data;
	282	}
	283
c227f099	284	static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr)
9dd986cc RJ	285	{
	286	i6300esb_debug("addr = %x\n", (int) addr);
	287
	288	return 0;
	289	}
	290
c227f099	291	static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val)
9dd986cc	292	{
4f423e81	293	I6300State *d = vp;
9dd986cc RJ	294
	295	i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
	296
	297	if (addr == 0xc && val == 0x80)
	298	d->unlock_state = 1;
	299	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	300	d->unlock_state = 2;
	301	}
	302
c227f099	303	static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val)
9dd986cc	304	{
4f423e81	305	I6300State *d = vp;
9dd986cc RJ	306
	307	i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
	308
	309	if (addr == 0xc && val == 0x80)
	310	d->unlock_state = 1;
	311	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	312	d->unlock_state = 2;
	313	else {
	314	if (d->unlock_state == 2) {
	315	if (addr == 0xc) {
	316	if ((val & 0x100) != 0)
	317	/* This is the "ping" from the userspace watchdog in
	318	* the guest ...
	319	*/
	320	i6300esb_restart_timer(d, 1);
	321
	322	/* Setting bit 9 resets the previous reboot flag.
	323	* There's a bug in the Linux driver where it sets
	324	* bit 12 instead.
	325	*/
	326	if ((val & 0x200) != 0 \|\| (val & 0x1000) != 0) {
	327	d->previous_reboot_flag = 0;
	328	}
	329	}
	330
	331	d->unlock_state = 0;
	332	}
	333	}
	334	}
	335
c227f099	336	static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
9dd986cc	337	{
4f423e81	338	I6300State *d = vp;
9dd986cc RJ	339
	340	i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);
	341
	342	if (addr == 0xc && val == 0x80)
	343	d->unlock_state = 1;
	344	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	345	d->unlock_state = 2;
	346	else {
	347	if (d->unlock_state == 2) {
	348	if (addr == 0)
	349	d->timer1_preload = val & 0xfffff;
	350	else if (addr == 4)
	351	d->timer2_preload = val & 0xfffff;
	352
	353	d->unlock_state = 0;
	354	}
	355	}
	356	}
	357
95c90a0e JQ	358	static const VMStateDescription vmstate_i6300esb = {
	359	.name = "i6300esb_wdt",
	360	.version_id = sizeof(I6300State),
	361	.minimum_version_id = sizeof(I6300State),
	362	.minimum_version_id_old = sizeof(I6300State),
	363	.fields = (VMStateField []) {
	364	VMSTATE_PCI_DEVICE(dev, I6300State),
	365	VMSTATE_INT32(reboot_enabled, I6300State),
	366	VMSTATE_INT32(clock_scale, I6300State),
	367	VMSTATE_INT32(int_type, I6300State),
	368	VMSTATE_INT32(free_run, I6300State),
	369	VMSTATE_INT32(locked, I6300State),
	370	VMSTATE_INT32(enabled, I6300State),
	371	VMSTATE_TIMER(timer, I6300State),
	372	VMSTATE_UINT32(timer1_preload, I6300State),
	373	VMSTATE_UINT32(timer2_preload, I6300State),
	374	VMSTATE_INT32(stage, I6300State),
	375	VMSTATE_INT32(unlock_state, I6300State),
	376	VMSTATE_INT32(previous_reboot_flag, I6300State),
	377	VMSTATE_END_OF_LIST()
	378	}
	379	};
9dd986cc	380
81a322d4	381	static int i6300esb_init(PCIDevice *dev)
9dd986cc	382	{
d03f09cc	383	I6300State *d = DO_UPCAST(I6300State, dev, dev);
22f3647b AK	384	int io_mem;
	385	static CPUReadMemoryFunc * const mem_read[3] = {
	386	i6300esb_mem_readb,
	387	i6300esb_mem_readw,
	388	i6300esb_mem_readl,
	389	};
	390	static CPUWriteMemoryFunc * const mem_write[3] = {
	391	i6300esb_mem_writeb,
	392	i6300esb_mem_writew,
	393	i6300esb_mem_writel,
	394	};
9dd986cc	395
fa82e9c3 BK	396	i6300esb_debug("I6300State = %p\n", d);
fa82e9c3 BK	397
74475455	398	d->timer = qemu_new_timer_ns(vm_clock, i6300esb_timer_expired, d);
36888c63	399	d->previous_reboot_flag = 0;
9dd986cc	400
22f3647b AK	401	io_mem = cpu_register_io_memory(mem_read, mem_write, d,
	402	DEVICE_NATIVE_ENDIAN);
	403	pci_register_bar_simple(&d->dev, 0, 0x10, 0, io_mem);
	404	/* qemu_register_coalesced_mmio (addr, 0x10); ? */
9dd986cc	405
81a322d4	406	return 0;
9dd986cc RJ	407	}
	408
	409	static WatchdogTimerModel model = {
	410	.wdt_name = "i6300esb",
	411	.wdt_description = "Intel 6300ESB",
9dd986cc RJ	412	};
9dd986cc RJ	413
09aaa160 MA	414	static PCIDeviceInfo i6300esb_info = {
	415	.qdev.name = "i6300esb",
	416	.qdev.size = sizeof(I6300State),
be73cfe2	417	.qdev.vmsd = &vmstate_i6300esb,
fa82e9c3	418	.qdev.reset = i6300esb_reset,
09aaa160 MA	419	.config_read = i6300esb_config_read,
	420	.config_write = i6300esb_config_write,
	421	.init = i6300esb_init,
24b856ca IY	422	.vendor_id = PCI_VENDOR_ID_INTEL,
	423	.device_id = PCI_DEVICE_ID_INTEL_ESB_9,
	424	.class_id = PCI_CLASS_SYSTEM_OTHER,
09aaa160 MA	425	};
	426
	427	static void i6300esb_register_devices(void)
9dd986cc RJ	428	{
9dd986cc RJ	429	watchdog_add_model(&model);
09aaa160	430	pci_qdev_register(&i6300esb_info);
9dd986cc	431	}
09aaa160 MA	432
09aaa160 MA	433	device_init(i6300esb_register_devices);