[qemu.git] / hw / wdt_i6300esb.c

/*
 * Virtual hardware watchdog.
 *
 * Copyright (C) 2009 Red Hat Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * By Richard W.M. Jones ([email protected]).
 */

#include <inttypes.h>

#include "qemu-common.h"
#include "qemu-timer.h"
#include "watchdog.h"
#include "hw.h"
#include "pci.h"

/*#define I6300ESB_DEBUG 1*/

#ifdef I6300ESB_DEBUG
#define i6300esb_debug(fs,...) \
    fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
#else
#define i6300esb_debug(fs,...)
#endif

/* PCI configuration registers */
#define ESB_CONFIG_REG  0x60            /* Config register                   */
#define ESB_LOCK_REG    0x68            /* WDT lock register                 */

/* Memory mapped registers (offset from base address) */
#define ESB_TIMER1_REG  0x00            /* Timer1 value after each reset     */
#define ESB_TIMER2_REG  0x04            /* Timer2 value after each reset     */
#define ESB_GINTSR_REG  0x08            /* General Interrupt Status Register */
#define ESB_RELOAD_REG  0x0c            /* Reload register                   */

/* Lock register bits */
#define ESB_WDT_FUNC    (0x01 << 2)   /* Watchdog functionality            */
#define ESB_WDT_ENABLE  (0x01 << 1)   /* Enable WDT                        */
#define ESB_WDT_LOCK    (0x01 << 0)   /* Lock (nowayout)                   */

/* Config register bits */
#define ESB_WDT_REBOOT  (0x01 << 5)   /* Enable reboot on timeout          */
#define ESB_WDT_FREQ    (0x01 << 2)   /* Decrement frequency               */
#define ESB_WDT_INTTYPE (0x11 << 0)   /* Interrupt type on timer1 timeout  */

/* Reload register bits */
#define ESB_WDT_RELOAD  (0x01 << 8)    /* prevent timeout                   */

/* Magic constants */
#define ESB_UNLOCK1     0x80            /* Step 1 to unlock reset registers  */
#define ESB_UNLOCK2     0x86            /* Step 2 to unlock reset registers  */

/* Device state. */
struct I6300State {
    PCIDevice dev;

    int reboot_enabled;         /* "Reboot" on timer expiry.  The real action
                                 * performed depends on the -watchdog-action
                                 * param passed on QEMU command line.
                                 */
    int clock_scale;            /* Clock scale. */
#define CLOCK_SCALE_1KHZ 0
#define CLOCK_SCALE_1MHZ 1

    int int_type;               /* Interrupt type generated. */
#define INT_TYPE_IRQ 0          /* APIC 1, INT 10 */
#define INT_TYPE_SMI 2
#define INT_TYPE_DISABLED 3

    int free_run;               /* If true, reload timer on expiry. */
    int locked;                 /* If true, enabled field cannot be changed. */
    int enabled;                /* If true, watchdog is enabled. */

    QEMUTimer *timer;           /* The actual watchdog timer. */

    uint32_t timer1_preload;    /* Values preloaded into timer1, timer2. */
    uint32_t timer2_preload;
    int stage;                  /* Stage (1 or 2). */

    int unlock_state;           /* Guest writes 0x80, 0x86 to unlock the
                                 * registers, and we transition through
                                 * states 0 -> 1 -> 2 when this happens.
                                 */

    int previous_reboot_flag;   /* If the watchdog caused the previous
                                 * reboot, this flag will be set.
                                 */
};

typedef struct I6300State I6300State;

/* This function is called when the watchdog has either been enabled
 * (hence it starts counting down) or has been keep-alived.
 */
static void i6300esb_restart_timer(I6300State *d, int stage)
{
    int64_t timeout;

    if (!d->enabled)
        return;

    d->stage = stage;

    if (d->stage <= 1)
        timeout = d->timer1_preload;
    else
        timeout = d->timer2_preload;

    if (d->clock_scale == CLOCK_SCALE_1KHZ)
        timeout <<= 15;
    else
        timeout <<= 5;

    /* Get the timeout in units of ticks_per_sec. */
    timeout = get_ticks_per_sec() * timeout / 33000000;

    i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);

    qemu_mod_timer(d->timer, qemu_get_clock(vm_clock) + timeout);
}

/* This is called when the guest disables the watchdog. */
static void i6300esb_disable_timer(I6300State *d)
{
    i6300esb_debug("timer disabled\n");

    qemu_del_timer(d->timer);
}

static void i6300esb_reset(DeviceState *dev)
{
    PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev);
    I6300State *d = DO_UPCAST(I6300State, dev, pdev);

    i6300esb_debug("I6300State = %p\n", d);

    i6300esb_disable_timer(d);

    d->reboot_enabled = 1;
    d->clock_scale = CLOCK_SCALE_1KHZ;
    d->int_type = INT_TYPE_IRQ;
    d->free_run = 0;
    d->locked = 0;
    d->enabled = 0;
    d->timer1_preload = 0xfffff;
    d->timer2_preload = 0xfffff;
    d->stage = 1;
    d->unlock_state = 0;
    d->previous_reboot_flag = 0;
}

/* This function is called when the watchdog expires.  Note that
 * the hardware has two timers, and so expiry happens in two stages.
 * If d->stage == 1 then we perform the first stage action (usually,
 * sending an interrupt) and then restart the timer again for the
 * second stage.  If the second stage expires then the watchdog
 * really has run out.
 */
static void i6300esb_timer_expired(void *vp)
{
    I6300State *d = vp;

    i6300esb_debug("stage %d\n", d->stage);

    if (d->stage == 1) {
        /* What to do at the end of stage 1? */
        switch (d->int_type) {
        case INT_TYPE_IRQ:
            fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
            break;
        case INT_TYPE_SMI:
            fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
            break;
        }

        /* Start the second stage. */
        i6300esb_restart_timer(d, 2);
    } else {
        /* Second stage expired, reboot for real. */
        if (d->reboot_enabled) {
            d->previous_reboot_flag = 1;
            watchdog_perform_action(); /* This reboots, exits, etc */
        }

        /* In "free running mode" we start stage 1 again. */
        if (d->free_run)
            i6300esb_restart_timer(d, 1);
    }
}

static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
                                  uint32_t data, int len)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    int old;

    i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);

    if (addr == ESB_CONFIG_REG && len == 2) {
        d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
        d->clock_scale =
            (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
        d->int_type = (data & ESB_WDT_INTTYPE);
    } else if (addr == ESB_LOCK_REG && len == 1) {
        if (!d->locked) {
            d->locked = (data & ESB_WDT_LOCK) != 0;
            d->free_run = (data & ESB_WDT_FUNC) != 0;
            old = d->enabled;
            d->enabled = (data & ESB_WDT_ENABLE) != 0;
            if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
                i6300esb_restart_timer(d, 1);
            else if (!d->enabled)
                i6300esb_disable_timer(d);
        }
    } else {
        pci_default_write_config(dev, addr, data, len);
    }
}

static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    uint32_t data;

    i6300esb_debug ("addr = %x, len = %d\n", addr, len);

    if (addr == ESB_CONFIG_REG && len == 2) {
        data =
            (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
            (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
            d->int_type;
        return data;
    } else if (addr == ESB_LOCK_REG && len == 1) {
        data =
            (d->free_run ? ESB_WDT_FUNC : 0) |
            (d->locked ? ESB_WDT_LOCK : 0) |
            (d->enabled ? ESB_WDT_ENABLE : 0);
        return data;
    } else {
        return pci_default_read_config(dev, addr, len);
    }
}

static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr)
{
    i6300esb_debug ("addr = %x\n", (int) addr);

    return 0;
}

static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr)
{
    uint32_t data = 0;
    I6300State *d = vp;

    i6300esb_debug("addr = %x\n", (int) addr);

    if (addr == 0xc) {
        /* The previous reboot flag is really bit 9, but there is
         * a bug in the Linux driver where it thinks it's bit 12.
         * Set both.
         */
        data = d->previous_reboot_flag ? 0x1200 : 0;
    }

    return data;
}

static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr)
{
    i6300esb_debug("addr = %x\n", (int) addr);

    return 0;
}

static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val)
{
    I6300State *d = vp;

    i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
}

static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val)
{
    I6300State *d = vp;

    i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
    else {
        if (d->unlock_state == 2) {
            if (addr == 0xc) {
                if ((val & 0x100) != 0)
                    /* This is the "ping" from the userspace watchdog in
                     * the guest ...
                     */
                    i6300esb_restart_timer(d, 1);

                /* Setting bit 9 resets the previous reboot flag.
                 * There's a bug in the Linux driver where it sets
                 * bit 12 instead.
                 */
                if ((val & 0x200) != 0 || (val & 0x1000) != 0) {
                    d->previous_reboot_flag = 0;
                }
            }

            d->unlock_state = 0;
        }
    }
}

static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
{
    I6300State *d = vp;

    i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
    else {
        if (d->unlock_state == 2) {
            if (addr == 0)
                d->timer1_preload = val & 0xfffff;
            else if (addr == 4)
                d->timer2_preload = val & 0xfffff;

            d->unlock_state = 0;
        }
    }
}

static void i6300esb_map(PCIDevice *dev, int region_num,
                         pcibus_t addr, pcibus_t size, int type)
{
    static CPUReadMemoryFunc * const mem_read[3] = {
        i6300esb_mem_readb,
        i6300esb_mem_readw,
        i6300esb_mem_readl,
    };
    static CPUWriteMemoryFunc * const mem_write[3] = {
        i6300esb_mem_writeb,
        i6300esb_mem_writew,
        i6300esb_mem_writel,
    };
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    int io_mem;

    i6300esb_debug("addr = %"FMT_PCIBUS", size = %"FMT_PCIBUS", type = %d\n",
                   addr, size, type);

    io_mem = cpu_register_io_memory(mem_read, mem_write, d,
                                    DEVICE_NATIVE_ENDIAN);
    cpu_register_physical_memory (addr, 0x10, io_mem);
    /* qemu_register_coalesced_mmio (addr, 0x10); ? */
}

static const VMStateDescription vmstate_i6300esb = {
    .name = "i6300esb_wdt",
    .version_id = sizeof(I6300State),
    .minimum_version_id = sizeof(I6300State),
    .minimum_version_id_old = sizeof(I6300State),
    .fields      = (VMStateField []) {
        VMSTATE_PCI_DEVICE(dev, I6300State),
        VMSTATE_INT32(reboot_enabled, I6300State),
        VMSTATE_INT32(clock_scale, I6300State),
        VMSTATE_INT32(int_type, I6300State),
        VMSTATE_INT32(free_run, I6300State),
        VMSTATE_INT32(locked, I6300State),
        VMSTATE_INT32(enabled, I6300State),
        VMSTATE_TIMER(timer, I6300State),
        VMSTATE_UINT32(timer1_preload, I6300State),
        VMSTATE_UINT32(timer2_preload, I6300State),
        VMSTATE_INT32(stage, I6300State),
        VMSTATE_INT32(unlock_state, I6300State),
        VMSTATE_INT32(previous_reboot_flag, I6300State),
        VMSTATE_END_OF_LIST()
    }
};

static int i6300esb_init(PCIDevice *dev)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    uint8_t *pci_conf;

    i6300esb_debug("I6300State = %p\n", d);

    d->timer = qemu_new_timer(vm_clock, i6300esb_timer_expired, d);

    pci_conf = d->dev.config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_ESB_9);
    pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER);

    pci_register_bar(&d->dev, 0, 0x10,
                            PCI_BASE_ADDRESS_SPACE_MEMORY, i6300esb_map);

    return 0;
}

static WatchdogTimerModel model = {
    .wdt_name = "i6300esb",
    .wdt_description = "Intel 6300ESB",
};

static PCIDeviceInfo i6300esb_info = {
    .qdev.name    = "i6300esb",
    .qdev.size    = sizeof(I6300State),
    .qdev.vmsd    = &vmstate_i6300esb,
    .qdev.reset   = i6300esb_reset,
    .config_read  = i6300esb_config_read,
    .config_write = i6300esb_config_write,
    .init         = i6300esb_init,
};

static void i6300esb_register_devices(void)
{
    watchdog_add_model(&model);
    pci_qdev_register(&i6300esb_info);
}

device_init(i6300esb_register_devices);
Commit	Line	Data
9dd986cc RJ	1	/*
	2	* Virtual hardware watchdog.
	3	*
	4	* Copyright (C) 2009 Red Hat Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
8167ee88	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
9dd986cc RJ	18	*
	19	* By Richard W.M. Jones ([email protected]).
	20	*/
	21
	22	#include <inttypes.h>
	23
	24	#include "qemu-common.h"
	25	#include "qemu-timer.h"
	26	#include "watchdog.h"
	27	#include "hw.h"
9dd986cc RJ	28	#include "pci.h"
	29
	30	/#define I6300ESB_DEBUG 1/
	31
	32	#ifdef I6300ESB_DEBUG
	33	#define i6300esb_debug(fs,...) \
	34	fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
	35	#else
	36	#define i6300esb_debug(fs,...)
	37	#endif
	38
9dd986cc RJ	39	/* PCI configuration registers */
	40	#define ESB_CONFIG_REG 0x60 /* Config register */
	41	#define ESB_LOCK_REG 0x68 /* WDT lock register */
	42
	43	/* Memory mapped registers (offset from base address) */
	44	#define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */
	45	#define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */
	46	#define ESB_GINTSR_REG 0x08 /* General Interrupt Status Register */
	47	#define ESB_RELOAD_REG 0x0c /* Reload register */
	48
	49	/* Lock register bits */
	50	#define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
	51	#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
	52	#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
	53
	54	/* Config register bits */
	55	#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
	56	#define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
	57	#define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */
	58
	59	/* Reload register bits */
	60	#define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
	61
	62	/* Magic constants */
	63	#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
	64	#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
	65
	66	/* Device state. */
	67	struct I6300State {
9d472d51	68	PCIDevice dev;
9dd986cc RJ	69
	70	int reboot_enabled; /* "Reboot" on timer expiry. The real action
	71	* performed depends on the -watchdog-action
	72	* param passed on QEMU command line.
	73	*/
	74	int clock_scale; /* Clock scale. */
	75	#define CLOCK_SCALE_1KHZ 0
	76	#define CLOCK_SCALE_1MHZ 1
	77
	78	int int_type; /* Interrupt type generated. */
	79	#define INT_TYPE_IRQ 0 /* APIC 1, INT 10 */
	80	#define INT_TYPE_SMI 2
	81	#define INT_TYPE_DISABLED 3
	82
	83	int free_run; /* If true, reload timer on expiry. */
	84	int locked; /* If true, enabled field cannot be changed. */
	85	int enabled; /* If true, watchdog is enabled. */
	86
	87	QEMUTimer timer; / The actual watchdog timer. */
	88
	89	uint32_t timer1_preload; /* Values preloaded into timer1, timer2. */
	90	uint32_t timer2_preload;
	91	int stage; /* Stage (1 or 2). */
	92
	93	int unlock_state; /* Guest writes 0x80, 0x86 to unlock the
	94	* registers, and we transition through
	95	* states 0 -> 1 -> 2 when this happens.
	96	*/
	97
	98	int previous_reboot_flag; /* If the watchdog caused the previous
	99	* reboot, this flag will be set.
	100	*/
	101	};
	102
	103	typedef struct I6300State I6300State;
	104
	105	/* This function is called when the watchdog has either been enabled
	106	* (hence it starts counting down) or has been keep-alived.
	107	*/
	108	static void i6300esb_restart_timer(I6300State *d, int stage)
	109	{
	110	int64_t timeout;
	111
	112	if (!d->enabled)
	113	return;
	114
	115	d->stage = stage;
	116
	117	if (d->stage <= 1)
	118	timeout = d->timer1_preload;
	119	else
	120	timeout = d->timer2_preload;
	121
	122	if (d->clock_scale == CLOCK_SCALE_1KHZ)
	123	timeout <<= 15;
	124	else
	125	timeout <<= 5;
	126
	127	/* Get the timeout in units of ticks_per_sec. */
6ee093c9	128	timeout = get_ticks_per_sec() * timeout / 33000000;
9dd986cc RJ	129
	130	i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
	131
	132	qemu_mod_timer(d->timer, qemu_get_clock(vm_clock) + timeout);
	133	}
	134
	135	/* This is called when the guest disables the watchdog. */
	136	static void i6300esb_disable_timer(I6300State *d)
	137	{
	138	i6300esb_debug("timer disabled\n");
	139
	140	qemu_del_timer(d->timer);
	141	}
	142
fa82e9c3	143	static void i6300esb_reset(DeviceState *dev)
9dd986cc	144	{
fa82e9c3 BK	145	PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, dev);
	146	I6300State *d = DO_UPCAST(I6300State, dev, pdev);
	147
	148	i6300esb_debug("I6300State = %p\n", d);
	149
9dd986cc	150	i6300esb_disable_timer(d);
fa82e9c3 BK	151
	152	d->reboot_enabled = 1;
	153	d->clock_scale = CLOCK_SCALE_1KHZ;
	154	d->int_type = INT_TYPE_IRQ;
	155	d->free_run = 0;
	156	d->locked = 0;
	157	d->enabled = 0;
	158	d->timer1_preload = 0xfffff;
	159	d->timer2_preload = 0xfffff;
	160	d->stage = 1;
	161	d->unlock_state = 0;
	162	d->previous_reboot_flag = 0;
9dd986cc RJ	163	}
	164
	165	/* This function is called when the watchdog expires. Note that
	166	* the hardware has two timers, and so expiry happens in two stages.
	167	* If d->stage == 1 then we perform the first stage action (usually,
	168	* sending an interrupt) and then restart the timer again for the
	169	* second stage. If the second stage expires then the watchdog
	170	* really has run out.
	171	*/
	172	static void i6300esb_timer_expired(void *vp)
	173	{
4f423e81	174	I6300State *d = vp;
9dd986cc RJ	175
	176	i6300esb_debug("stage %d\n", d->stage);
	177
	178	if (d->stage == 1) {
	179	/* What to do at the end of stage 1? */
	180	switch (d->int_type) {
	181	case INT_TYPE_IRQ:
	182	fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
	183	break;
	184	case INT_TYPE_SMI:
	185	fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
	186	break;
	187	}
	188
	189	/* Start the second stage. */
	190	i6300esb_restart_timer(d, 2);
	191	} else {
	192	/* Second stage expired, reboot for real. */
	193	if (d->reboot_enabled) {
	194	d->previous_reboot_flag = 1;
	195	watchdog_perform_action(); /* This reboots, exits, etc */
9dd986cc RJ	196	}
	197
	198	/* In "free running mode" we start stage 1 again. */
	199	if (d->free_run)
	200	i6300esb_restart_timer(d, 1);
	201	}
	202	}
	203
	204	static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
	205	uint32_t data, int len)
	206	{
d03f09cc	207	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc RJ	208	int old;
	209
	210	i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
	211
	212	if (addr == ESB_CONFIG_REG && len == 2) {
	213	d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
	214	d->clock_scale =
	215	(data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
	216	d->int_type = (data & ESB_WDT_INTTYPE);
	217	} else if (addr == ESB_LOCK_REG && len == 1) {
	218	if (!d->locked) {
	219	d->locked = (data & ESB_WDT_LOCK) != 0;
	220	d->free_run = (data & ESB_WDT_FUNC) != 0;
	221	old = d->enabled;
	222	d->enabled = (data & ESB_WDT_ENABLE) != 0;
	223	if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
	224	i6300esb_restart_timer(d, 1);
	225	else if (!d->enabled)
	226	i6300esb_disable_timer(d);
	227	}
	228	} else {
	229	pci_default_write_config(dev, addr, data, len);
	230	}
	231	}
	232
	233	static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
	234	{
d03f09cc	235	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc RJ	236	uint32_t data;
	237
	238	i6300esb_debug ("addr = %x, len = %d\n", addr, len);
	239
	240	if (addr == ESB_CONFIG_REG && len == 2) {
	241	data =
	242	(d->reboot_enabled ? 0 : ESB_WDT_REBOOT) \|
	243	(d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) \|
	244	d->int_type;
	245	return data;
	246	} else if (addr == ESB_LOCK_REG && len == 1) {
	247	data =
	248	(d->free_run ? ESB_WDT_FUNC : 0) \|
	249	(d->locked ? ESB_WDT_LOCK : 0) \|
	250	(d->enabled ? ESB_WDT_ENABLE : 0);
	251	return data;
	252	} else {
	253	return pci_default_read_config(dev, addr, len);
	254	}
	255	}
	256
c227f099	257	static uint32_t i6300esb_mem_readb(void *vp, target_phys_addr_t addr)
9dd986cc RJ	258	{
	259	i6300esb_debug ("addr = %x\n", (int) addr);
	260
	261	return 0;
	262	}
	263
c227f099	264	static uint32_t i6300esb_mem_readw(void *vp, target_phys_addr_t addr)
9dd986cc RJ	265	{
9dd986cc RJ	266	uint32_t data = 0;
4f423e81	267	I6300State *d = vp;
9dd986cc RJ	268
	269	i6300esb_debug("addr = %x\n", (int) addr);
	270
	271	if (addr == 0xc) {
	272	/* The previous reboot flag is really bit 9, but there is
	273	* a bug in the Linux driver where it thinks it's bit 12.
	274	* Set both.
	275	*/
	276	data = d->previous_reboot_flag ? 0x1200 : 0;
	277	}
	278
	279	return data;
	280	}
	281
c227f099	282	static uint32_t i6300esb_mem_readl(void *vp, target_phys_addr_t addr)
9dd986cc RJ	283	{
	284	i6300esb_debug("addr = %x\n", (int) addr);
	285
	286	return 0;
	287	}
	288
c227f099	289	static void i6300esb_mem_writeb(void *vp, target_phys_addr_t addr, uint32_t val)
9dd986cc	290	{
4f423e81	291	I6300State *d = vp;
9dd986cc RJ	292
	293	i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
	294
	295	if (addr == 0xc && val == 0x80)
	296	d->unlock_state = 1;
	297	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	298	d->unlock_state = 2;
	299	}
	300
c227f099	301	static void i6300esb_mem_writew(void *vp, target_phys_addr_t addr, uint32_t val)
9dd986cc	302	{
4f423e81	303	I6300State *d = vp;
9dd986cc RJ	304
	305	i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
	306
	307	if (addr == 0xc && val == 0x80)
	308	d->unlock_state = 1;
	309	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	310	d->unlock_state = 2;
	311	else {
	312	if (d->unlock_state == 2) {
	313	if (addr == 0xc) {
	314	if ((val & 0x100) != 0)
	315	/* This is the "ping" from the userspace watchdog in
	316	* the guest ...
	317	*/
	318	i6300esb_restart_timer(d, 1);
	319
	320	/* Setting bit 9 resets the previous reboot flag.
	321	* There's a bug in the Linux driver where it sets
	322	* bit 12 instead.
	323	*/
	324	if ((val & 0x200) != 0 \|\| (val & 0x1000) != 0) {
	325	d->previous_reboot_flag = 0;
	326	}
	327	}
	328
	329	d->unlock_state = 0;
	330	}
	331	}
	332	}
	333
c227f099	334	static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val)
9dd986cc	335	{
4f423e81	336	I6300State *d = vp;
9dd986cc RJ	337
	338	i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);
	339
	340	if (addr == 0xc && val == 0x80)
	341	d->unlock_state = 1;
	342	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	343	d->unlock_state = 2;
	344	else {
	345	if (d->unlock_state == 2) {
	346	if (addr == 0)
	347	d->timer1_preload = val & 0xfffff;
	348	else if (addr == 4)
	349	d->timer2_preload = val & 0xfffff;
	350
	351	d->unlock_state = 0;
	352	}
	353	}
	354	}
	355
	356	static void i6300esb_map(PCIDevice *dev, int region_num,
6e355d90	357	pcibus_t addr, pcibus_t size, int type)
9dd986cc	358	{
d60efc6b	359	static CPUReadMemoryFunc * const mem_read[3] = {
9dd986cc RJ	360	i6300esb_mem_readb,
	361	i6300esb_mem_readw,
	362	i6300esb_mem_readl,
	363	};
d60efc6b	364	static CPUWriteMemoryFunc * const mem_write[3] = {
9dd986cc RJ	365	i6300esb_mem_writeb,
	366	i6300esb_mem_writew,
	367	i6300esb_mem_writel,
	368	};
d03f09cc	369	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc RJ	370	int io_mem;
9dd986cc RJ	371
89e8b13c IY	372	i6300esb_debug("addr = %"FMT_PCIBUS", size = %"FMT_PCIBUS", type = %d\n",
89e8b13c IY	373	addr, size, type);
9dd986cc	374
2507c12a AG	375	io_mem = cpu_register_io_memory(mem_read, mem_write, d,
2507c12a AG	376	DEVICE_NATIVE_ENDIAN);
9dd986cc RJ	377	cpu_register_physical_memory (addr, 0x10, io_mem);
	378	/* qemu_register_coalesced_mmio (addr, 0x10); ? */
	379	}
	380
95c90a0e JQ	381	static const VMStateDescription vmstate_i6300esb = {
	382	.name = "i6300esb_wdt",
	383	.version_id = sizeof(I6300State),
	384	.minimum_version_id = sizeof(I6300State),
	385	.minimum_version_id_old = sizeof(I6300State),
	386	.fields = (VMStateField []) {
	387	VMSTATE_PCI_DEVICE(dev, I6300State),
	388	VMSTATE_INT32(reboot_enabled, I6300State),
	389	VMSTATE_INT32(clock_scale, I6300State),
	390	VMSTATE_INT32(int_type, I6300State),
	391	VMSTATE_INT32(free_run, I6300State),
	392	VMSTATE_INT32(locked, I6300State),
	393	VMSTATE_INT32(enabled, I6300State),
	394	VMSTATE_TIMER(timer, I6300State),
	395	VMSTATE_UINT32(timer1_preload, I6300State),
	396	VMSTATE_UINT32(timer2_preload, I6300State),
	397	VMSTATE_INT32(stage, I6300State),
	398	VMSTATE_INT32(unlock_state, I6300State),
	399	VMSTATE_INT32(previous_reboot_flag, I6300State),
	400	VMSTATE_END_OF_LIST()
	401	}
	402	};
9dd986cc	403
81a322d4	404	static int i6300esb_init(PCIDevice *dev)
9dd986cc	405	{
d03f09cc	406	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc RJ	407	uint8_t *pci_conf;
9dd986cc RJ	408
fa82e9c3 BK	409	i6300esb_debug("I6300State = %p\n", d);
fa82e9c3 BK	410
9dd986cc	411	d->timer = qemu_new_timer(vm_clock, i6300esb_timer_expired, d);
9dd986cc RJ	412
	413	pci_conf = d->dev.config;
	414	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
	415	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_ESB_9);
	416	pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER);
9dd986cc	417
28c2c264	418	pci_register_bar(&d->dev, 0, 0x10,
0392a017	419	PCI_BASE_ADDRESS_SPACE_MEMORY, i6300esb_map);
9dd986cc	420
81a322d4	421	return 0;
9dd986cc RJ	422	}
	423
	424	static WatchdogTimerModel model = {
	425	.wdt_name = "i6300esb",
	426	.wdt_description = "Intel 6300ESB",
9dd986cc RJ	427	};
9dd986cc RJ	428
09aaa160 MA	429	static PCIDeviceInfo i6300esb_info = {
	430	.qdev.name = "i6300esb",
	431	.qdev.size = sizeof(I6300State),
be73cfe2	432	.qdev.vmsd = &vmstate_i6300esb,
fa82e9c3	433	.qdev.reset = i6300esb_reset,
09aaa160 MA	434	.config_read = i6300esb_config_read,
	435	.config_write = i6300esb_config_write,
	436	.init = i6300esb_init,
	437	};
	438
	439	static void i6300esb_register_devices(void)
9dd986cc RJ	440	{
9dd986cc RJ	441	watchdog_add_model(&model);
09aaa160	442	pci_qdev_register(&i6300esb_info);
9dd986cc	443	}
09aaa160 MA	444
09aaa160 MA	445	device_init(i6300esb_register_devices);