[qemu.git] / hw / wdt_i6300esb.c

/*
 * Virtual hardware watchdog.
 *
 * Copyright (C) 2009 Red Hat Inc.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, see <http://www.gnu.org/licenses/>.
 *
 * By Richard W.M. Jones ([email protected]).
 */

#include <inttypes.h>

#include "qemu-common.h"
#include "qemu-timer.h"
#include "watchdog.h"
#include "hw.h"
#include "pci.h"

/*#define I6300ESB_DEBUG 1*/

#ifdef I6300ESB_DEBUG
#define i6300esb_debug(fs,...) \
    fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
#else
#define i6300esb_debug(fs,...)
#endif

#ifndef PCI_DEVICE_ID_INTEL_ESB_9
#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
#endif

/* PCI configuration registers */
#define ESB_CONFIG_REG  0x60            /* Config register                   */
#define ESB_LOCK_REG    0x68            /* WDT lock register                 */

/* Memory mapped registers (offset from base address) */
#define ESB_TIMER1_REG  0x00            /* Timer1 value after each reset     */
#define ESB_TIMER2_REG  0x04            /* Timer2 value after each reset     */
#define ESB_GINTSR_REG  0x08            /* General Interrupt Status Register */
#define ESB_RELOAD_REG  0x0c            /* Reload register                   */

/* Lock register bits */
#define ESB_WDT_FUNC    (0x01 << 2)   /* Watchdog functionality            */
#define ESB_WDT_ENABLE  (0x01 << 1)   /* Enable WDT                        */
#define ESB_WDT_LOCK    (0x01 << 0)   /* Lock (nowayout)                   */

/* Config register bits */
#define ESB_WDT_REBOOT  (0x01 << 5)   /* Enable reboot on timeout          */
#define ESB_WDT_FREQ    (0x01 << 2)   /* Decrement frequency               */
#define ESB_WDT_INTTYPE (0x11 << 0)   /* Interrupt type on timer1 timeout  */

/* Reload register bits */
#define ESB_WDT_RELOAD  (0x01 << 8)    /* prevent timeout                   */

/* Magic constants */
#define ESB_UNLOCK1     0x80            /* Step 1 to unlock reset registers  */
#define ESB_UNLOCK2     0x86            /* Step 2 to unlock reset registers  */

/* Device state. */
struct I6300State {
    PCIDevice dev;

    int reboot_enabled;         /* "Reboot" on timer expiry.  The real action
                                 * performed depends on the -watchdog-action
                                 * param passed on QEMU command line.
                                 */
    int clock_scale;            /* Clock scale. */
#define CLOCK_SCALE_1KHZ 0
#define CLOCK_SCALE_1MHZ 1

    int int_type;               /* Interrupt type generated. */
#define INT_TYPE_IRQ 0          /* APIC 1, INT 10 */
#define INT_TYPE_SMI 2
#define INT_TYPE_DISABLED 3

    int free_run;               /* If true, reload timer on expiry. */
    int locked;                 /* If true, enabled field cannot be changed. */
    int enabled;                /* If true, watchdog is enabled. */

    QEMUTimer *timer;           /* The actual watchdog timer. */

    uint32_t timer1_preload;    /* Values preloaded into timer1, timer2. */
    uint32_t timer2_preload;
    int stage;                  /* Stage (1 or 2). */

    int unlock_state;           /* Guest writes 0x80, 0x86 to unlock the
                                 * registers, and we transition through
                                 * states 0 -> 1 -> 2 when this happens.
                                 */

    int previous_reboot_flag;   /* If the watchdog caused the previous
                                 * reboot, this flag will be set.
                                 */
};

typedef struct I6300State I6300State;

/* This function is called when the watchdog has either been enabled
 * (hence it starts counting down) or has been keep-alived.
 */
static void i6300esb_restart_timer(I6300State *d, int stage)
{
    int64_t timeout;

    if (!d->enabled)
        return;

    d->stage = stage;

    if (d->stage <= 1)
        timeout = d->timer1_preload;
    else
        timeout = d->timer2_preload;

    if (d->clock_scale == CLOCK_SCALE_1KHZ)
        timeout <<= 15;
    else
        timeout <<= 5;

    /* Get the timeout in units of ticks_per_sec. */
    timeout = get_ticks_per_sec() * timeout / 33000000;

    i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);

    qemu_mod_timer(d->timer, qemu_get_clock(vm_clock) + timeout);
}

/* This is called when the guest disables the watchdog. */
static void i6300esb_disable_timer(I6300State *d)
{
    i6300esb_debug("timer disabled\n");

    qemu_del_timer(d->timer);
}

static void i6300esb_reset(I6300State *d)
{
    /* XXX We should probably reset other parts of the state here,
     * but we should also reset our state on general machine reset
     * too.  For now just disable the timer so it doesn't fire
     * again after the reboot.
     */
    i6300esb_disable_timer(d);
}

/* This function is called when the watchdog expires.  Note that
 * the hardware has two timers, and so expiry happens in two stages.
 * If d->stage == 1 then we perform the first stage action (usually,
 * sending an interrupt) and then restart the timer again for the
 * second stage.  If the second stage expires then the watchdog
 * really has run out.
 */
static void i6300esb_timer_expired(void *vp)
{
    I6300State *d = (I6300State *) vp;

    i6300esb_debug("stage %d\n", d->stage);

    if (d->stage == 1) {
        /* What to do at the end of stage 1? */
        switch (d->int_type) {
        case INT_TYPE_IRQ:
            fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
            break;
        case INT_TYPE_SMI:
            fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
            break;
        }

        /* Start the second stage. */
        i6300esb_restart_timer(d, 2);
    } else {
        /* Second stage expired, reboot for real. */
        if (d->reboot_enabled) {
            d->previous_reboot_flag = 1;
            watchdog_perform_action(); /* This reboots, exits, etc */
            i6300esb_reset(d);
        }

        /* In "free running mode" we start stage 1 again. */
        if (d->free_run)
            i6300esb_restart_timer(d, 1);
    }
}

static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
                                  uint32_t data, int len)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    int old;

    i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);

    if (addr == ESB_CONFIG_REG && len == 2) {
        d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
        d->clock_scale =
            (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
        d->int_type = (data & ESB_WDT_INTTYPE);
    } else if (addr == ESB_LOCK_REG && len == 1) {
        if (!d->locked) {
            d->locked = (data & ESB_WDT_LOCK) != 0;
            d->free_run = (data & ESB_WDT_FUNC) != 0;
            old = d->enabled;
            d->enabled = (data & ESB_WDT_ENABLE) != 0;
            if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
                i6300esb_restart_timer(d, 1);
            else if (!d->enabled)
                i6300esb_disable_timer(d);
        }
    } else {
        pci_default_write_config(dev, addr, data, len);
    }
}

static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    uint32_t data;

    i6300esb_debug ("addr = %x, len = %d\n", addr, len);

    if (addr == ESB_CONFIG_REG && len == 2) {
        data =
            (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) |
            (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) |
            d->int_type;
        return data;
    } else if (addr == ESB_LOCK_REG && len == 1) {
        data =
            (d->free_run ? ESB_WDT_FUNC : 0) |
            (d->locked ? ESB_WDT_LOCK : 0) |
            (d->enabled ? ESB_WDT_ENABLE : 0);
        return data;
    } else {
        return pci_default_read_config(dev, addr, len);
    }
}

static uint32_t i6300esb_mem_readb(void *vp, a_target_phys_addr addr)
{
    i6300esb_debug ("addr = %x\n", (int) addr);

    return 0;
}

static uint32_t i6300esb_mem_readw(void *vp, a_target_phys_addr addr)
{
    uint32_t data = 0;
    I6300State *d = (I6300State *) vp;

    i6300esb_debug("addr = %x\n", (int) addr);

    if (addr == 0xc) {
        /* The previous reboot flag is really bit 9, but there is
         * a bug in the Linux driver where it thinks it's bit 12.
         * Set both.
         */
        data = d->previous_reboot_flag ? 0x1200 : 0;
    }

    return data;
}

static uint32_t i6300esb_mem_readl(void *vp, a_target_phys_addr addr)
{
    i6300esb_debug("addr = %x\n", (int) addr);

    return 0;
}

static void i6300esb_mem_writeb(void *vp, a_target_phys_addr addr, uint32_t val)
{
    I6300State *d = (I6300State *) vp;

    i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
}

static void i6300esb_mem_writew(void *vp, a_target_phys_addr addr, uint32_t val)
{
    I6300State *d = (I6300State *) vp;

    i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
    else {
        if (d->unlock_state == 2) {
            if (addr == 0xc) {
                if ((val & 0x100) != 0)
                    /* This is the "ping" from the userspace watchdog in
                     * the guest ...
                     */
                    i6300esb_restart_timer(d, 1);

                /* Setting bit 9 resets the previous reboot flag.
                 * There's a bug in the Linux driver where it sets
                 * bit 12 instead.
                 */
                if ((val & 0x200) != 0 || (val & 0x1000) != 0) {
                    d->previous_reboot_flag = 0;
                }
            }

            d->unlock_state = 0;
        }
    }
}

static void i6300esb_mem_writel(void *vp, a_target_phys_addr addr, uint32_t val)
{
    I6300State *d = (I6300State *) vp;

    i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);

    if (addr == 0xc && val == 0x80)
        d->unlock_state = 1;
    else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
        d->unlock_state = 2;
    else {
        if (d->unlock_state == 2) {
            if (addr == 0)
                d->timer1_preload = val & 0xfffff;
            else if (addr == 4)
                d->timer2_preload = val & 0xfffff;

            d->unlock_state = 0;
        }
    }
}

static void i6300esb_map(PCIDevice *dev, int region_num,
                         uint32_t addr, uint32_t size, int type)
{
    static CPUReadMemoryFunc * const mem_read[3] = {
        i6300esb_mem_readb,
        i6300esb_mem_readw,
        i6300esb_mem_readl,
    };
    static CPUWriteMemoryFunc * const mem_write[3] = {
        i6300esb_mem_writeb,
        i6300esb_mem_writew,
        i6300esb_mem_writel,
    };
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    int io_mem;

    i6300esb_debug("addr = %x, size = %x, type = %d\n", addr, size, type);

    io_mem = cpu_register_io_memory(mem_read, mem_write, d);
    cpu_register_physical_memory (addr, 0x10, io_mem);
    /* qemu_register_coalesced_mmio (addr, 0x10); ? */
}

static void i6300esb_save(QEMUFile *f, void *vp)
{
    I6300State *d = (I6300State *) vp;

    pci_device_save(&d->dev, f);
    qemu_put_be32(f, d->reboot_enabled);
    qemu_put_be32(f, d->clock_scale);
    qemu_put_be32(f, d->int_type);
    qemu_put_be32(f, d->free_run);
    qemu_put_be32(f, d->locked);
    qemu_put_be32(f, d->enabled);
    qemu_put_timer(f, d->timer);
    qemu_put_be32(f, d->timer1_preload);
    qemu_put_be32(f, d->timer2_preload);
    qemu_put_be32(f, d->stage);
    qemu_put_be32(f, d->unlock_state);
    qemu_put_be32(f, d->previous_reboot_flag);
}

static int i6300esb_load(QEMUFile *f, void *vp, int version)
{
    I6300State *d = (I6300State *) vp;

    if (version != sizeof (I6300State))
        return -EINVAL;

    pci_device_load(&d->dev, f);
    d->reboot_enabled = qemu_get_be32(f);
    d->clock_scale = qemu_get_be32(f);
    d->int_type = qemu_get_be32(f);
    d->free_run = qemu_get_be32(f);
    d->locked = qemu_get_be32(f);
    d->enabled = qemu_get_be32(f);
    qemu_get_timer(f, d->timer);
    d->timer1_preload = qemu_get_be32(f);
    d->timer2_preload = qemu_get_be32(f);
    d->stage = qemu_get_be32(f);
    d->unlock_state = qemu_get_be32(f);
    d->previous_reboot_flag = qemu_get_be32(f);

    return 0;
}

static int i6300esb_init(PCIDevice *dev)
{
    I6300State *d = DO_UPCAST(I6300State, dev, dev);
    uint8_t *pci_conf;

    d->reboot_enabled = 1;
    d->clock_scale = CLOCK_SCALE_1KHZ;
    d->int_type = INT_TYPE_IRQ;
    d->free_run = 0;
    d->locked = 0;
    d->enabled = 0;
    d->timer = qemu_new_timer(vm_clock, i6300esb_timer_expired, d);
    d->timer1_preload = 0xfffff;
    d->timer2_preload = 0xfffff;
    d->stage = 1;
    d->unlock_state = 0;
    d->previous_reboot_flag = 0;

    pci_conf = d->dev.config;
    pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
    pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_ESB_9);
    pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER);
    pci_conf[0x0e] = 0x00;

    pci_register_bar(&d->dev, 0, 0x10,
                            PCI_ADDRESS_SPACE_MEM, i6300esb_map);

    register_savevm("i6300esb_wdt", -1, sizeof(I6300State),
                     i6300esb_save, i6300esb_load, d);

    return 0;
}

static WatchdogTimerModel model = {
    .wdt_name = "i6300esb",
    .wdt_description = "Intel 6300ESB",
};

static PCIDeviceInfo i6300esb_info = {
    .qdev.name    = "i6300esb",
    .qdev.size    = sizeof(I6300State),
    .config_read  = i6300esb_config_read,
    .config_write = i6300esb_config_write,
    .init         = i6300esb_init,
};

static void i6300esb_register_devices(void)
{
    watchdog_add_model(&model);
    pci_qdev_register(&i6300esb_info);
}

device_init(i6300esb_register_devices);
Commit	Line	Data
9dd986cc RJ	1	/*
	2	* Virtual hardware watchdog.
	3	*
	4	* Copyright (C) 2009 Red Hat Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
8167ee88	17	* along with this program; if not, see <http://www.gnu.org/licenses/>.
9dd986cc RJ	18	*
	19	* By Richard W.M. Jones ([email protected]).
	20	*/
	21
	22	#include <inttypes.h>
	23
	24	#include "qemu-common.h"
	25	#include "qemu-timer.h"
	26	#include "watchdog.h"
	27	#include "hw.h"
9dd986cc RJ	28	#include "pci.h"
	29
	30	/#define I6300ESB_DEBUG 1/
	31
	32	#ifdef I6300ESB_DEBUG
	33	#define i6300esb_debug(fs,...) \
	34	fprintf(stderr,"i6300esb: %s: "fs,__func__,##__VA_ARGS__)
	35	#else
	36	#define i6300esb_debug(fs,...)
	37	#endif
	38
	39	#ifndef PCI_DEVICE_ID_INTEL_ESB_9
	40	#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
	41	#endif
	42
	43	/* PCI configuration registers */
	44	#define ESB_CONFIG_REG 0x60 /* Config register */
	45	#define ESB_LOCK_REG 0x68 /* WDT lock register */
	46
	47	/* Memory mapped registers (offset from base address) */
	48	#define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */
	49	#define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */
	50	#define ESB_GINTSR_REG 0x08 /* General Interrupt Status Register */
	51	#define ESB_RELOAD_REG 0x0c /* Reload register */
	52
	53	/* Lock register bits */
	54	#define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
	55	#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
	56	#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
	57
	58	/* Config register bits */
	59	#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
	60	#define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
	61	#define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */
	62
	63	/* Reload register bits */
	64	#define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
	65
	66	/* Magic constants */
	67	#define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
	68	#define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
	69
	70	/* Device state. */
	71	struct I6300State {
9d472d51	72	PCIDevice dev;
9dd986cc RJ	73
	74	int reboot_enabled; /* "Reboot" on timer expiry. The real action
	75	* performed depends on the -watchdog-action
	76	* param passed on QEMU command line.
	77	*/
	78	int clock_scale; /* Clock scale. */
	79	#define CLOCK_SCALE_1KHZ 0
	80	#define CLOCK_SCALE_1MHZ 1
	81
	82	int int_type; /* Interrupt type generated. */
	83	#define INT_TYPE_IRQ 0 /* APIC 1, INT 10 */
	84	#define INT_TYPE_SMI 2
	85	#define INT_TYPE_DISABLED 3
	86
	87	int free_run; /* If true, reload timer on expiry. */
	88	int locked; /* If true, enabled field cannot be changed. */
	89	int enabled; /* If true, watchdog is enabled. */
	90
	91	QEMUTimer timer; / The actual watchdog timer. */
	92
	93	uint32_t timer1_preload; /* Values preloaded into timer1, timer2. */
	94	uint32_t timer2_preload;
	95	int stage; /* Stage (1 or 2). */
	96
	97	int unlock_state; /* Guest writes 0x80, 0x86 to unlock the
	98	* registers, and we transition through
	99	* states 0 -> 1 -> 2 when this happens.
	100	*/
	101
	102	int previous_reboot_flag; /* If the watchdog caused the previous
	103	* reboot, this flag will be set.
	104	*/
	105	};
	106
	107	typedef struct I6300State I6300State;
	108
	109	/* This function is called when the watchdog has either been enabled
	110	* (hence it starts counting down) or has been keep-alived.
	111	*/
	112	static void i6300esb_restart_timer(I6300State *d, int stage)
	113	{
	114	int64_t timeout;
	115
	116	if (!d->enabled)
	117	return;
	118
	119	d->stage = stage;
	120
	121	if (d->stage <= 1)
	122	timeout = d->timer1_preload;
	123	else
	124	timeout = d->timer2_preload;
	125
	126	if (d->clock_scale == CLOCK_SCALE_1KHZ)
	127	timeout <<= 15;
	128	else
	129	timeout <<= 5;
	130
	131	/* Get the timeout in units of ticks_per_sec. */
6ee093c9	132	timeout = get_ticks_per_sec() * timeout / 33000000;
9dd986cc RJ	133
	134	i6300esb_debug("stage %d, timeout %" PRIi64 "\n", d->stage, timeout);
	135
	136	qemu_mod_timer(d->timer, qemu_get_clock(vm_clock) + timeout);
	137	}
	138
	139	/* This is called when the guest disables the watchdog. */
	140	static void i6300esb_disable_timer(I6300State *d)
	141	{
	142	i6300esb_debug("timer disabled\n");
	143
	144	qemu_del_timer(d->timer);
	145	}
	146
	147	static void i6300esb_reset(I6300State *d)
	148	{
	149	/* XXX We should probably reset other parts of the state here,
	150	* but we should also reset our state on general machine reset
	151	* too. For now just disable the timer so it doesn't fire
	152	* again after the reboot.
	153	*/
	154	i6300esb_disable_timer(d);
	155	}
	156
	157	/* This function is called when the watchdog expires. Note that
	158	* the hardware has two timers, and so expiry happens in two stages.
	159	* If d->stage == 1 then we perform the first stage action (usually,
	160	* sending an interrupt) and then restart the timer again for the
	161	* second stage. If the second stage expires then the watchdog
	162	* really has run out.
	163	*/
	164	static void i6300esb_timer_expired(void *vp)
	165	{
	166	I6300State d = (I6300State ) vp;
	167
	168	i6300esb_debug("stage %d\n", d->stage);
	169
	170	if (d->stage == 1) {
	171	/* What to do at the end of stage 1? */
	172	switch (d->int_type) {
	173	case INT_TYPE_IRQ:
	174	fprintf(stderr, "i6300esb_timer_expired: I would send APIC 1 INT 10 here if I knew how (XXX)\n");
	175	break;
	176	case INT_TYPE_SMI:
	177	fprintf(stderr, "i6300esb_timer_expired: I would send SMI here if I knew how (XXX)\n");
	178	break;
	179	}
	180
	181	/* Start the second stage. */
	182	i6300esb_restart_timer(d, 2);
	183	} else {
	184	/* Second stage expired, reboot for real. */
	185	if (d->reboot_enabled) {
	186	d->previous_reboot_flag = 1;
	187	watchdog_perform_action(); /* This reboots, exits, etc */
	188	i6300esb_reset(d);
	189	}
	190
	191	/* In "free running mode" we start stage 1 again. */
	192	if (d->free_run)
	193	i6300esb_restart_timer(d, 1);
	194	}
	195	}
	196
197	static void i6300esb_config_write(PCIDevice *dev, uint32_t addr,
198	uint32_t data, int len)
199	{
d03f09cc	200	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc RJ	201	int old;
	202
	203	i6300esb_debug("addr = %x, data = %x, len = %d\n", addr, data, len);
	204
	205	if (addr == ESB_CONFIG_REG && len == 2) {
	206	d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0;
	207	d->clock_scale =
	208	(data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ;
	209	d->int_type = (data & ESB_WDT_INTTYPE);
	210	} else if (addr == ESB_LOCK_REG && len == 1) {
	211	if (!d->locked) {
	212	d->locked = (data & ESB_WDT_LOCK) != 0;
	213	d->free_run = (data & ESB_WDT_FUNC) != 0;
	214	old = d->enabled;
	215	d->enabled = (data & ESB_WDT_ENABLE) != 0;
	216	if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */
	217	i6300esb_restart_timer(d, 1);
	218	else if (!d->enabled)
	219	i6300esb_disable_timer(d);
	220	}
	221	} else {
	222	pci_default_write_config(dev, addr, data, len);
	223	}
	224	}
	225
	226	static uint32_t i6300esb_config_read(PCIDevice *dev, uint32_t addr, int len)
	227	{
d03f09cc	228	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc RJ	229	uint32_t data;
	230
	231	i6300esb_debug ("addr = %x, len = %d\n", addr, len);
	232
	233	if (addr == ESB_CONFIG_REG && len == 2) {
	234	data =
	235	(d->reboot_enabled ? 0 : ESB_WDT_REBOOT) \|
	236	(d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) \|
	237	d->int_type;
	238	return data;
	239	} else if (addr == ESB_LOCK_REG && len == 1) {
	240	data =
	241	(d->free_run ? ESB_WDT_FUNC : 0) \|
	242	(d->locked ? ESB_WDT_LOCK : 0) \|
	243	(d->enabled ? ESB_WDT_ENABLE : 0);
	244	return data;
	245	} else {
	246	return pci_default_read_config(dev, addr, len);
	247	}
	248	}
	249
99a0949b	250	static uint32_t i6300esb_mem_readb(void *vp, a_target_phys_addr addr)
9dd986cc RJ	251	{
	252	i6300esb_debug ("addr = %x\n", (int) addr);
	253
	254	return 0;
	255	}
	256
99a0949b	257	static uint32_t i6300esb_mem_readw(void *vp, a_target_phys_addr addr)
9dd986cc RJ	258	{
	259	uint32_t data = 0;
	260	I6300State d = (I6300State ) vp;
	261
	262	i6300esb_debug("addr = %x\n", (int) addr);
	263
	264	if (addr == 0xc) {
	265	/* The previous reboot flag is really bit 9, but there is
	266	* a bug in the Linux driver where it thinks it's bit 12.
	267	* Set both.
	268	*/
	269	data = d->previous_reboot_flag ? 0x1200 : 0;
	270	}
	271
	272	return data;
	273	}
	274
99a0949b	275	static uint32_t i6300esb_mem_readl(void *vp, a_target_phys_addr addr)
9dd986cc RJ	276	{
	277	i6300esb_debug("addr = %x\n", (int) addr);
	278
	279	return 0;
	280	}
	281
99a0949b	282	static void i6300esb_mem_writeb(void *vp, a_target_phys_addr addr, uint32_t val)
9dd986cc RJ	283	{
	284	I6300State d = (I6300State ) vp;
	285
	286	i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
	287
	288	if (addr == 0xc && val == 0x80)
	289	d->unlock_state = 1;
	290	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	291	d->unlock_state = 2;
	292	}
	293
99a0949b	294	static void i6300esb_mem_writew(void *vp, a_target_phys_addr addr, uint32_t val)
9dd986cc RJ	295	{
	296	I6300State d = (I6300State ) vp;
	297
	298	i6300esb_debug("addr = %x, val = %x\n", (int) addr, val);
	299
	300	if (addr == 0xc && val == 0x80)
	301	d->unlock_state = 1;
	302	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	303	d->unlock_state = 2;
	304	else {
	305	if (d->unlock_state == 2) {
	306	if (addr == 0xc) {
	307	if ((val & 0x100) != 0)
	308	/* This is the "ping" from the userspace watchdog in
	309	* the guest ...
	310	*/
	311	i6300esb_restart_timer(d, 1);
	312
	313	/* Setting bit 9 resets the previous reboot flag.
	314	* There's a bug in the Linux driver where it sets
	315	* bit 12 instead.
	316	*/
	317	if ((val & 0x200) != 0 \|\| (val & 0x1000) != 0) {
	318	d->previous_reboot_flag = 0;
	319	}
	320	}
	321
	322	d->unlock_state = 0;
	323	}
	324	}
	325	}
	326
99a0949b	327	static void i6300esb_mem_writel(void *vp, a_target_phys_addr addr, uint32_t val)
9dd986cc RJ	328	{
	329	I6300State d = (I6300State ) vp;
	330
	331	i6300esb_debug ("addr = %x, val = %x\n", (int) addr, val);
	332
	333	if (addr == 0xc && val == 0x80)
	334	d->unlock_state = 1;
	335	else if (addr == 0xc && val == 0x86 && d->unlock_state == 1)
	336	d->unlock_state = 2;
	337	else {
	338	if (d->unlock_state == 2) {
	339	if (addr == 0)
	340	d->timer1_preload = val & 0xfffff;
	341	else if (addr == 4)
	342	d->timer2_preload = val & 0xfffff;
	343
	344	d->unlock_state = 0;
	345	}
	346	}
	347	}
	348
	349	static void i6300esb_map(PCIDevice *dev, int region_num,
	350	uint32_t addr, uint32_t size, int type)
	351	{
d60efc6b	352	static CPUReadMemoryFunc * const mem_read[3] = {
9dd986cc RJ	353	i6300esb_mem_readb,
	354	i6300esb_mem_readw,
	355	i6300esb_mem_readl,
	356	};
d60efc6b	357	static CPUWriteMemoryFunc * const mem_write[3] = {
9dd986cc RJ	358	i6300esb_mem_writeb,
	359	i6300esb_mem_writew,
	360	i6300esb_mem_writel,
	361	};
d03f09cc	362	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc RJ	363	int io_mem;
	364
	365	i6300esb_debug("addr = %x, size = %x, type = %d\n", addr, size, type);
	366
1eed09cb	367	io_mem = cpu_register_io_memory(mem_read, mem_write, d);
9dd986cc RJ	368	cpu_register_physical_memory (addr, 0x10, io_mem);
	369	/* qemu_register_coalesced_mmio (addr, 0x10); ? */
	370	}
	371
	372	static void i6300esb_save(QEMUFile f, void vp)
	373	{
	374	I6300State d = (I6300State ) vp;
	375
	376	pci_device_save(&d->dev, f);
	377	qemu_put_be32(f, d->reboot_enabled);
	378	qemu_put_be32(f, d->clock_scale);
	379	qemu_put_be32(f, d->int_type);
	380	qemu_put_be32(f, d->free_run);
	381	qemu_put_be32(f, d->locked);
	382	qemu_put_be32(f, d->enabled);
	383	qemu_put_timer(f, d->timer);
	384	qemu_put_be32(f, d->timer1_preload);
	385	qemu_put_be32(f, d->timer2_preload);
	386	qemu_put_be32(f, d->stage);
	387	qemu_put_be32(f, d->unlock_state);
	388	qemu_put_be32(f, d->previous_reboot_flag);
	389	}
	390
	391	static int i6300esb_load(QEMUFile f, void vp, int version)
	392	{
	393	I6300State d = (I6300State ) vp;
	394
	395	if (version != sizeof (I6300State))
	396	return -EINVAL;
	397
	398	pci_device_load(&d->dev, f);
	399	d->reboot_enabled = qemu_get_be32(f);
	400	d->clock_scale = qemu_get_be32(f);
	401	d->int_type = qemu_get_be32(f);
	402	d->free_run = qemu_get_be32(f);
	403	d->locked = qemu_get_be32(f);
	404	d->enabled = qemu_get_be32(f);
	405	qemu_get_timer(f, d->timer);
	406	d->timer1_preload = qemu_get_be32(f);
	407	d->timer2_preload = qemu_get_be32(f);
	408	d->stage = qemu_get_be32(f);
	409	d->unlock_state = qemu_get_be32(f);
	410	d->previous_reboot_flag = qemu_get_be32(f);
	411
	412	return 0;
	413	}
	414
81a322d4	415	static int i6300esb_init(PCIDevice *dev)
9dd986cc	416	{
d03f09cc	417	I6300State *d = DO_UPCAST(I6300State, dev, dev);
9dd986cc RJ	418	uint8_t *pci_conf;
9dd986cc RJ	419
9dd986cc RJ	420	d->reboot_enabled = 1;
	421	d->clock_scale = CLOCK_SCALE_1KHZ;
	422	d->int_type = INT_TYPE_IRQ;
	423	d->free_run = 0;
	424	d->locked = 0;
	425	d->enabled = 0;
	426	d->timer = qemu_new_timer(vm_clock, i6300esb_timer_expired, d);
	427	d->timer1_preload = 0xfffff;
	428	d->timer2_preload = 0xfffff;
	429	d->stage = 1;
	430	d->unlock_state = 0;
	431	d->previous_reboot_flag = 0;
	432
	433	pci_conf = d->dev.config;
	434	pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
	435	pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_ESB_9);
	436	pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER);
	437	pci_conf[0x0e] = 0x00;
	438
28c2c264	439	pci_register_bar(&d->dev, 0, 0x10,
9dd986cc RJ	440	PCI_ADDRESS_SPACE_MEM, i6300esb_map);
	441
	442	register_savevm("i6300esb_wdt", -1, sizeof(I6300State),
	443	i6300esb_save, i6300esb_load, d);
81a322d4 GH	444
81a322d4 GH	445	return 0;
9dd986cc RJ	446	}
	447
	448	static WatchdogTimerModel model = {
	449	.wdt_name = "i6300esb",
	450	.wdt_description = "Intel 6300ESB",
9dd986cc RJ	451	};
9dd986cc RJ	452
09aaa160 MA	453	static PCIDeviceInfo i6300esb_info = {
	454	.qdev.name = "i6300esb",
	455	.qdev.size = sizeof(I6300State),
	456	.config_read = i6300esb_config_read,
	457	.config_write = i6300esb_config_write,
	458	.init = i6300esb_init,
	459	};
	460
	461	static void i6300esb_register_devices(void)
9dd986cc RJ	462	{
9dd986cc RJ	463	watchdog_add_model(&model);
09aaa160	464	pci_qdev_register(&i6300esb_info);
9dd986cc	465	}
09aaa160 MA	466
09aaa160 MA	467	device_init(i6300esb_register_devices);