[qemu.git] / hw / ppc / mac_oldworld.c


/*
 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
 *
 * Copyright (c) 2004-2007 Fabrice Bellard
 * Copyright (c) 2007 Jocelyn Mayer
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "hw/hw.h"
#include "hw/ppc/ppc.h"
#include "mac.h"
#include "hw/input/adb.h"
#include "hw/timer/m48t59.h"
#include "sysemu/sysemu.h"
#include "net/net.h"
#include "hw/isa/isa.h"
#include "hw/pci/pci.h"
#include "hw/boards.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/char/escc.h"
#include "hw/ide.h"
#include "hw/loader.h"
#include "elf.h"
#include "qemu/error-report.h"
#include "sysemu/kvm.h"
#include "kvm_ppc.h"
#include "sysemu/block-backend.h"
#include "exec/address-spaces.h"

#define MAX_IDE_BUS 2
#define CFG_ADDR 0xf0000510
#define TBFREQ 16600000UL
#define CLOCKFREQ 266000000UL
#define BUSFREQ 66000000UL

static void fw_cfg_boot_set(void *opaque, const char *boot_device,
                            Error **errp)
{
    fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
}

static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
{
    return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}

static hwaddr round_page(hwaddr addr)
{
    return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
}

static void ppc_heathrow_reset(void *opaque)
{
    PowerPCCPU *cpu = opaque;

    cpu_reset(CPU(cpu));
}

static void ppc_heathrow_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *kernel_filename = machine->kernel_filename;
    const char *kernel_cmdline = machine->kernel_cmdline;
    const char *initrd_filename = machine->initrd_filename;
    const char *boot_device = machine->boot_order;
    MemoryRegion *sysmem = get_system_memory();
    PowerPCCPU *cpu = NULL;
    CPUPPCState *env = NULL;
    char *filename;
    qemu_irq *pic, **heathrow_irqs;
    int linux_boot, i;
    MemoryRegion *ram = g_new(MemoryRegion, 1);
    MemoryRegion *bios = g_new(MemoryRegion, 1);
    MemoryRegion *isa = g_new(MemoryRegion, 1);
    uint32_t kernel_base, initrd_base, cmdline_base = 0;
    int32_t kernel_size, initrd_size;
    PCIBus *pci_bus;
    PCIDevice *macio;
    MACIOIDEState *macio_ide;
    DeviceState *dev;
    BusState *adb_bus;
    int bios_size;
    MemoryRegion *pic_mem;
    MemoryRegion *escc_mem, *escc_bar = g_new(MemoryRegion, 1);
    uint16_t ppc_boot_device;
    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
    void *fw_cfg;
    uint64_t tbfreq;

    linux_boot = (kernel_filename != NULL);

    /* init CPUs */
    if (machine->cpu_model == NULL)
        machine->cpu_model = "G3";
    for (i = 0; i < smp_cpus; i++) {
        cpu = cpu_ppc_init(machine->cpu_model);
        if (cpu == NULL) {
            fprintf(stderr, "Unable to find PowerPC CPU definition\n");
            exit(1);
        }
        env = &cpu->env;

        /* Set time-base frequency to 16.6 Mhz */
        cpu_ppc_tb_init(env,  TBFREQ);
        qemu_register_reset(ppc_heathrow_reset, cpu);
    }

    /* allocate RAM */
    if (ram_size > (2047 << 20)) {
        fprintf(stderr,
                "qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
                ((unsigned int)ram_size / (1 << 20)));
        exit(1);
    }

    memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram",
                                         ram_size);
    memory_region_add_subregion(sysmem, 0, ram);

    /* allocate and load BIOS */
    memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
                           &error_fatal);
    vmstate_register_ram_global(bios);

    if (bios_name == NULL)
        bios_name = PROM_FILENAME;
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
    memory_region_set_readonly(bios, true);
    memory_region_add_subregion(sysmem, PROM_ADDR, bios);

    /* Load OpenBIOS (ELF) */
    if (filename) {
        bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
                             1, PPC_ELF_MACHINE, 0);
        g_free(filename);
    } else {
        bios_size = -1;
    }
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
        error_report("could not load PowerPC bios '%s'", bios_name);
        exit(1);
    }

    if (linux_boot) {
        uint64_t lowaddr = 0;
        int bswap_needed;

#ifdef BSWAP_NEEDED
        bswap_needed = 1;
#else
        bswap_needed = 0;
#endif
        kernel_base = KERNEL_LOAD_ADDR;
        kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
                               NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 0);
        if (kernel_size < 0)
            kernel_size = load_aout(kernel_filename, kernel_base,
                                    ram_size - kernel_base, bswap_needed,
                                    TARGET_PAGE_SIZE);
        if (kernel_size < 0)
            kernel_size = load_image_targphys(kernel_filename,
                                              kernel_base,
                                              ram_size - kernel_base);
        if (kernel_size < 0) {
            error_report("could not load kernel '%s'", kernel_filename);
            exit(1);
        }
        /* load initrd */
        if (initrd_filename) {
            initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
                                              ram_size - initrd_base);
            if (initrd_size < 0) {
                error_report("could not load initial ram disk '%s'",
                             initrd_filename);
                exit(1);
            }
            cmdline_base = round_page(initrd_base + initrd_size);
        } else {
            initrd_base = 0;
            initrd_size = 0;
            cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
        }
        ppc_boot_device = 'm';
    } else {
        kernel_base = 0;
        kernel_size = 0;
        initrd_base = 0;
        initrd_size = 0;
        ppc_boot_device = '\0';
        for (i = 0; boot_device[i] != '\0'; i++) {
            /* TOFIX: for now, the second IDE channel is not properly
             *        used by OHW. The Mac floppy disk are not emulated.
             *        For now, OHW cannot boot from the network.
             */
#if 0
            if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
                ppc_boot_device = boot_device[i];
                break;
            }
#else
            if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
                ppc_boot_device = boot_device[i];
                break;
            }
#endif
        }
        if (ppc_boot_device == '\0') {
            fprintf(stderr, "No valid boot device for G3 Beige machine\n");
            exit(1);
        }
    }

    /* Register 2 MB of ISA IO space */
    memory_region_init_alias(isa, NULL, "isa_mmio",
                             get_system_io(), 0, 0x00200000);
    memory_region_add_subregion(sysmem, 0xfe000000, isa);

    /* XXX: we register only 1 output pin for heathrow PIC */
    heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
    heathrow_irqs[0] =
        g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
    /* Connect the heathrow PIC outputs to the 6xx bus */
    for (i = 0; i < smp_cpus; i++) {
        switch (PPC_INPUT(env)) {
        case PPC_FLAGS_INPUT_6xx:
            heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
            heathrow_irqs[i][0] =
                ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
            break;
        default:
            error_report("Bus model not supported on OldWorld Mac machine");
            exit(1);
        }
    }

    /* Timebase Frequency */
    if (kvm_enabled()) {
        tbfreq = kvmppc_get_tbfreq();
    } else {
        tbfreq = TBFREQ;
    }

    /* init basic PC hardware */
    if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
        error_report("Only 6xx bus is supported on heathrow machine");
        exit(1);
    }
    pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);
    pci_bus = pci_grackle_init(0xfec00000, pic,
                               get_system_memory(),
                               get_system_io());
    pci_vga_init(pci_bus);

    escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
                               serial_hds[1], ESCC_CLOCK, 4);
    memory_region_init_alias(escc_bar, NULL, "escc-bar",
                             escc_mem, 0, memory_region_size(escc_mem));

    for(i = 0; i < nb_nics; i++)
        pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);


    ide_drive_get(hd, ARRAY_SIZE(hd));

    macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO);
    dev = DEVICE(macio);
    qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
    qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */
    qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */
    qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */
    qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */
    qdev_prop_set_uint64(dev, "frequency", tbfreq);
    macio_init(macio, pic_mem, escc_bar);

    macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
                                                        "ide[0]"));
    macio_ide_init_drives(macio_ide, hd);

    macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
                                                        "ide[1]"));
    macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);

    dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
    adb_bus = qdev_get_child_bus(dev, "adb.0");
    dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
    qdev_init_nofail(dev);
    dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
    qdev_init_nofail(dev);

    if (usb_enabled()) {
        pci_create_simple(pci_bus, -1, "pci-ohci");
    }

    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
        graphic_depth = 15;

    /* No PCI init: the BIOS will do it */

    fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
    fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
    fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
    if (kernel_cmdline) {
        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
    } else {
        fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
    }
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
    fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);

    fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
    fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
    fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);

    fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
    if (kvm_enabled()) {
#ifdef CONFIG_KVM
        uint8_t *hypercall;

        hypercall = g_malloc(16);
        kvmppc_get_hypercall(env, hypercall, 16);
        fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
        fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
#endif
    }
    fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
    /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
    fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
    fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);

    qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}

static int heathrow_kvm_type(const char *arg)
{
    /* Always force PR KVM */
    return 2;
}

static void heathrow_machine_init(MachineClass *mc)
{
    mc->desc = "Heathrow based PowerMAC";
    mc->init = ppc_heathrow_init;
    mc->max_cpus = MAX_CPUS;
#ifndef TARGET_PPC64
    mc->is_default = 1;
#endif
    /* TOFIX "cad" when Mac floppy is implemented */
    mc->default_boot_order = "cd";
    mc->kvm_type = heathrow_kvm_type;
}

DEFINE_MACHINE("g3beige", heathrow_machine_init)
Commit	Line	Data
ae0bfb79	1
3cbee15b	2	/*
4d7ca41e	3	* QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
3cbee15b JM	4	*
	5	* Copyright (c) 2004-2007 Fabrice Bellard
	6	* Copyright (c) 2007 Jocelyn Mayer
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
0d75590d	26	#include "qemu/osdep.h"
baec1910	27	#include "hw/hw.h"
0d09e41a	28	#include "hw/ppc/ppc.h"
baec1910	29	#include "mac.h"
0d09e41a PB	30	#include "hw/input/adb.h"
0d09e41a PB	31	#include "hw/timer/m48t59.h"
9c17d615	32	#include "sysemu/sysemu.h"
1422e32d	33	#include "net/net.h"
0d09e41a	34	#include "hw/isa/isa.h"
baec1910 AF	35	#include "hw/pci/pci.h"
baec1910 AF	36	#include "hw/boards.h"
0d09e41a PB	37	#include "hw/nvram/fw_cfg.h"
0d09e41a PB	38	#include "hw/char/escc.h"
baec1910 AF	39	#include "hw/ide.h"
baec1910 AF	40	#include "hw/loader.h"
ca20cf32	41	#include "elf.h"
c525436e	42	#include "qemu/error-report.h"
9c17d615	43	#include "sysemu/kvm.h"
dc333cd6	44	#include "kvm_ppc.h"
4be74634	45	#include "sysemu/block-backend.h"
022c62cb	46	#include "exec/address-spaces.h"
3cbee15b	47
e4bcb14c	48	#define MAX_IDE_BUS 2
271dd5e0	49	#define CFG_ADDR 0xf0000510
536d8cda	50	#define TBFREQ 16600000UL
9d1c1283 BZ	51	#define CLOCKFREQ 266000000UL
9d1c1283 BZ	52	#define BUSFREQ 66000000UL
271dd5e0	53
ddcd5531 GA	54	static void fw_cfg_boot_set(void opaque, const char boot_device,
ddcd5531 GA	55	Error **errp)
513f789f	56	{
48779e50	57	fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
513f789f BS	58	}
513f789f BS	59
409dbce5 AJ	60	static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
	61	{
	62	return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
	63	}
	64
a8170e5e	65	static hwaddr round_page(hwaddr addr)
b9e17a34 AG	66	{
	67	return (addr + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
	68	}
	69
1bba0dc9 AF	70	static void ppc_heathrow_reset(void *opaque)
1bba0dc9 AF	71	{
cd79664f	72	PowerPCCPU *cpu = opaque;
1bba0dc9	73
cd79664f	74	cpu_reset(CPU(cpu));
1bba0dc9 AF	75	}
1bba0dc9 AF	76
3ef96221	77	static void ppc_heathrow_init(MachineState *machine)
3cbee15b	78	{
3ef96221	79	ram_addr_t ram_size = machine->ram_size;
3ef96221 MA	80	const char *kernel_filename = machine->kernel_filename;
	81	const char *kernel_cmdline = machine->kernel_cmdline;
	82	const char *initrd_filename = machine->initrd_filename;
	83	const char *boot_device = machine->boot_order;
c92bb2c7	84	MemoryRegion *sysmem = get_system_memory();
72c33dd7	85	PowerPCCPU *cpu = NULL;
e2684c0b	86	CPUPPCState *env = NULL;
5cea8590	87	char *filename;
3cbee15b	88	qemu_irq pic, *heathrow_irqs;
3cbee15b	89	int linux_boot, i;
c92bb2c7 AK	90	MemoryRegion *ram = g_new(MemoryRegion, 1);
c92bb2c7 AK	91	MemoryRegion *bios = g_new(MemoryRegion, 1);
7d52857e	92	MemoryRegion *isa = g_new(MemoryRegion, 1);
b9e17a34	93	uint32_t kernel_base, initrd_base, cmdline_base = 0;
7373048c	94	int32_t kernel_size, initrd_size;
3cbee15b	95	PCIBus *pci_bus;
d037834a	96	PCIDevice *macio;
07a7484e AF	97	MACIOIDEState *macio_ide;
07a7484e AF	98	DeviceState *dev;
293c867d	99	BusState *adb_bus;
ae0bfb79	100	int bios_size;
45fa67fb	101	MemoryRegion *pic_mem;
07a7484e	102	MemoryRegion escc_mem, escc_bar = g_new(MemoryRegion, 1);
513f789f	103	uint16_t ppc_boot_device;
f455e98c	104	DriveInfo hd[MAX_IDE_BUS MAX_IDE_DEVS];
271dd5e0	105	void *fw_cfg;
caae6c96	106	uint64_t tbfreq;
3cbee15b JM	107
	108	linux_boot = (kernel_filename != NULL);
	109
	110	/* init CPUs */
19fb2c36 BR	111	if (machine->cpu_model == NULL)
19fb2c36 BR	112	machine->cpu_model = "G3";
3cbee15b	113	for (i = 0; i < smp_cpus; i++) {
19fb2c36	114	cpu = cpu_ppc_init(machine->cpu_model);
72c33dd7	115	if (cpu == NULL) {
aaed909a FB	116	fprintf(stderr, "Unable to find PowerPC CPU definition\n");
	117	exit(1);
	118	}
72c33dd7 AF	119	env = &cpu->env;
72c33dd7 AF	120
b0fb43d8	121	/* Set time-base frequency to 16.6 Mhz */
536d8cda	122	cpu_ppc_tb_init(env, TBFREQ);
cd79664f	123	qemu_register_reset(ppc_heathrow_reset, cpu);
3cbee15b JM	124	}
	125
	126	/* allocate RAM */
6b4079f8 AJ	127	if (ram_size > (2047 << 20)) {
	128	fprintf(stderr,
	129	"qemu: Too much memory for this machine: %d MB, maximum 2047 MB\n",
	130	((unsigned int)ram_size / (1 << 20)));
	131	exit(1);
	132	}
	133
e938ba0c SP	134	memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram",
e938ba0c SP	135	ram_size);
c92bb2c7	136	memory_region_add_subregion(sysmem, 0, ram);
a748ab6d	137
3cbee15b	138	/* allocate and load BIOS */
49946538	139	memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
f8ed85ac	140	&error_fatal);
e206ad48 HT	141	vmstate_register_ram_global(bios);
e206ad48 HT	142
3cbee15b	143	if (bios_name == NULL)
992e5acd	144	bios_name = PROM_FILENAME;
5cea8590	145	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
c92bb2c7 AK	146	memory_region_set_readonly(bios, true);
c92bb2c7 AK	147	memory_region_add_subregion(sysmem, PROM_ADDR, bios);
992e5acd BS	148
992e5acd BS	149	/* Load OpenBIOS (ELF) */
5cea8590	150	if (filename) {
409dbce5	151	bios_size = load_elf(filename, 0, NULL, NULL, NULL, NULL,
4ecd4d16	152	1, PPC_ELF_MACHINE, 0);
7267c094	153	g_free(filename);
5cea8590 PB	154	} else {
	155	bios_size = -1;
	156	}
3cbee15b	157	if (bios_size < 0 \|\| bios_size > BIOS_SIZE) {
c525436e	158	error_report("could not load PowerPC bios '%s'", bios_name);
3cbee15b JM	159	exit(1);
3cbee15b JM	160	}
3cbee15b	161
3cbee15b	162	if (linux_boot) {
36bee1e3	163	uint64_t lowaddr = 0;
ca20cf32 BS	164	int bswap_needed;
	165
	166	#ifdef BSWAP_NEEDED
	167	bswap_needed = 1;
	168	#else
	169	bswap_needed = 0;
	170	#endif
3cbee15b	171	kernel_base = KERNEL_LOAD_ADDR;
409dbce5	172	kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
4ecd4d16	173	NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 0);
52f163b7 BS	174	if (kernel_size < 0)
52f163b7 BS	175	kernel_size = load_aout(kernel_filename, kernel_base,
ca20cf32 BS	176	ram_size - kernel_base, bswap_needed,
ca20cf32 BS	177	TARGET_PAGE_SIZE);
52f163b7 BS	178	if (kernel_size < 0)
	179	kernel_size = load_image_targphys(kernel_filename,
	180	kernel_base,
	181	ram_size - kernel_base);
3cbee15b	182	if (kernel_size < 0) {
c525436e	183	error_report("could not load kernel '%s'", kernel_filename);
3cbee15b JM	184	exit(1);
	185	}
	186	/* load initrd */
	187	if (initrd_filename) {
b9e17a34	188	initrd_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
dcac9679 PB	189	initrd_size = load_image_targphys(initrd_filename, initrd_base,
dcac9679 PB	190	ram_size - initrd_base);
3cbee15b	191	if (initrd_size < 0) {
c525436e MA	192	error_report("could not load initial ram disk '%s'",
c525436e MA	193	initrd_filename);
3cbee15b JM	194	exit(1);
3cbee15b JM	195	}
b9e17a34	196	cmdline_base = round_page(initrd_base + initrd_size);
3cbee15b JM	197	} else {
	198	initrd_base = 0;
	199	initrd_size = 0;
b9e17a34	200	cmdline_base = round_page(kernel_base + kernel_size + KERNEL_GAP);
3cbee15b	201	}
6ac0e82d	202	ppc_boot_device = 'm';
3cbee15b JM	203	} else {
	204	kernel_base = 0;
	205	kernel_size = 0;
	206	initrd_base = 0;
	207	initrd_size = 0;
28c5af54	208	ppc_boot_device = '\0';
0d913fdb	209	for (i = 0; boot_device[i] != '\0'; i++) {
28c5af54	210	/* TOFIX: for now, the second IDE channel is not properly
0d913fdb	211	* used by OHW. The Mac floppy disk are not emulated.
28c5af54 JM	212	* For now, OHW cannot boot from the network.
	213	*/
	214	#if 0
0d913fdb JM	215	if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
0d913fdb JM	216	ppc_boot_device = boot_device[i];
28c5af54	217	break;
0d913fdb	218	}
28c5af54	219	#else
0d913fdb JM	220	if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
0d913fdb JM	221	ppc_boot_device = boot_device[i];
28c5af54	222	break;
0d913fdb	223	}
28c5af54 JM	224	#endif
	225	}
	226	if (ppc_boot_device == '\0') {
8a901def	227	fprintf(stderr, "No valid boot device for G3 Beige machine\n");
28c5af54 JM	228	exit(1);
28c5af54 JM	229	}
3cbee15b JM	230	}
3cbee15b JM	231
3cbee15b	232	/* Register 2 MB of ISA IO space */
7d52857e PB	233	memory_region_init_alias(isa, NULL, "isa_mmio",
	234	get_system_io(), 0, 0x00200000);
	235	memory_region_add_subregion(sysmem, 0xfe000000, isa);
3cbee15b JM	236
3cbee15b JM	237	/* XXX: we register only 1 output pin for heathrow PIC */
7267c094	238	heathrow_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
3cbee15b	239	heathrow_irqs[0] =
7267c094	240	g_malloc0(smp_cpus * sizeof(qemu_irq) * 1);
3cbee15b JM	241	/* Connect the heathrow PIC outputs to the 6xx bus */
	242	for (i = 0; i < smp_cpus; i++) {
	243	switch (PPC_INPUT(env)) {
	244	case PPC_FLAGS_INPUT_6xx:
	245	heathrow_irqs[i] = heathrow_irqs[0] + (i * 1);
	246	heathrow_irqs[i][0] =
	247	((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
	248	break;
	249	default:
c525436e MA	250	error_report("Bus model not supported on OldWorld Mac machine");
c525436e MA	251	exit(1);
3cbee15b JM	252	}
	253	}
	254
caae6c96 AG	255	/* Timebase Frequency */
	256	if (kvm_enabled()) {
	257	tbfreq = kvmppc_get_tbfreq();
	258	} else {
	259	tbfreq = TBFREQ;
	260	}
	261
3cbee15b JM	262	/* init basic PC hardware */
3cbee15b JM	263	if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
c525436e MA	264	error_report("Only 6xx bus is supported on heathrow machine");
c525436e MA	265	exit(1);
3cbee15b	266	}
23c5e4ca	267	pic = heathrow_pic_init(&pic_mem, 1, heathrow_irqs);
aee97b84 AK	268	pci_bus = pci_grackle_init(0xfec00000, pic,
	269	get_system_memory(),
	270	get_system_io());
3e20ad3a	271	pci_vga_init(pci_bus);
aae9366a	272
b39491a8	273	escc_mem = escc_init(0, pic[0x0f], pic[0x10], serial_hds[0],
7fa9ae1a	274	serial_hds[1], ESCC_CLOCK, 4);
2c9b15ca	275	memory_region_init_alias(escc_bar, NULL, "escc-bar",
5b15f275	276	escc_mem, 0, memory_region_size(escc_mem));
aae9366a	277
cb457d76	278	for(i = 0; i < nb_nics; i++)
29b358f9	279	pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
0d913fdb	280
e4bcb14c	281
d8f94e1b	282	ide_drive_get(hd, ARRAY_SIZE(hd));
bd4524ed	283
d037834a	284	macio = pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO);
07a7484e	285	dev = DEVICE(macio);
45fa67fb	286	qdev_connect_gpio_out(dev, 0, pic[0x12]); /* CUDA */
14eefd0e AG	287	qdev_connect_gpio_out(dev, 1, pic[0x0D]); /* IDE-0 */
	288	qdev_connect_gpio_out(dev, 2, pic[0x02]); /* IDE-0 DMA */
	289	qdev_connect_gpio_out(dev, 3, pic[0x0E]); /* IDE-1 */
	290	qdev_connect_gpio_out(dev, 4, pic[0x03]); /* IDE-1 DMA */
b981289c	291	qdev_prop_set_uint64(dev, "frequency", tbfreq);
45fa67fb	292	macio_init(macio, pic_mem, escc_bar);
07a7484e	293
07a7484e	294	macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
14eefd0e	295	"ide[0]"));
07a7484e AF	296	macio_ide_init_drives(macio_ide, hd);
07a7484e AF	297
14eefd0e AG	298	macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
	299	"ide[1]"));
	300	macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
3cbee15b	301
293c867d AF	302	dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
	303	adb_bus = qdev_get_child_bus(dev, "adb.0");
	304	dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
2e4a7c9c	305	qdev_init_nofail(dev);
293c867d	306	dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
2e4a7c9c	307	qdev_init_nofail(dev);
45fa67fb	308
de77a243	309	if (usb_enabled()) {
afb9a60e	310	pci_create_simple(pci_bus, -1, "pci-ohci");
3cbee15b JM	311	}
	312
	313	if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
	314	graphic_depth = 15;
	315
3cbee15b JM	316	/* No PCI init: the BIOS will do it */
3cbee15b JM	317
66708822	318	fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
70db9222	319	fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
271dd5e0 BS	320	fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
271dd5e0 BS	321	fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
513f789f BS	322	fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
	323	fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
	324	if (kernel_cmdline) {
b9e17a34 AG	325	fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
b9e17a34 AG	326	pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
513f789f BS	327	} else {
	328	fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
	329	}
	330	fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
	331	fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
	332	fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
7f1aec5f LV	333
	334	fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
	335	fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
	336	fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
	337
45024f09	338	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
dc333cd6 AG	339	if (kvm_enabled()) {
dc333cd6 AG	340	#ifdef CONFIG_KVM
45024f09 AG	341	uint8_t *hypercall;
45024f09 AG	342
7267c094	343	hypercall = g_malloc(16);
45024f09 AG	344	kvmppc_get_hypercall(env, hypercall, 16);
	345	fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
	346	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
dc333cd6	347	#endif
dc333cd6	348	}
caae6c96	349	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
a1014f25	350	/* Mac OS X requires a "known good" clock-frequency value; pass it one. */
9d1c1283 BZ	351	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
9d1c1283 BZ	352	fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
dc333cd6	353
513f789f	354	qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
3cbee15b JM	355	}
3cbee15b JM	356
277c7a4d AG	357	static int heathrow_kvm_type(const char *arg)
	358	{
	359	/* Always force PR KVM */
	360	return 2;
	361	}
	362
e264d29d EH	363	static void heathrow_machine_init(MachineClass *mc)
	364	{
	365	mc->desc = "Heathrow based PowerMAC";
	366	mc->init = ppc_heathrow_init;
	367	mc->max_cpus = MAX_CPUS;
46214a27	368	#ifndef TARGET_PPC64
e264d29d	369	mc->is_default = 1;
46214a27	370	#endif
f309ae85	371	/* TOFIX "cad" when Mac floppy is implemented */
e264d29d EH	372	mc->default_boot_order = "cd";
e264d29d EH	373	mc->kvm_type = heathrow_kvm_type;
f80f9ec9 AL	374	}
f80f9ec9 AL	375
e264d29d	376	DEFINE_MACHINE("g3beige", heathrow_machine_init)